CN112929133A

CN112929133A - Channel processing device and method based on field programmable logic gate array

Info

Publication number: CN112929133A
Application number: CN202110504395.9A
Authority: CN
Inventors: 余兆基; 符永逸; 卢会群
Original assignee: Guangzhou Huiruisitong Technology Co Ltd
Current assignee: Guangzhou Huiruisitong Technology Co Ltd
Priority date: 2021-05-10
Filing date: 2021-05-10
Publication date: 2021-06-08
Anticipated expiration: 2041-05-10
Also published as: CN112929133B

Abstract

The application relates to a channel processing device and method based on field programmable gate array, which relates to the technical field of mobile communication, and the device comprises: a channel control module and a data link module; the output end of the channel control module is connected with the input end of the data link module; the channel control module is used for outputting user parameter information, user code block data and a symbol mapping address to the data link module according to the interrupt enabling signal; the bit level processing submodule in the data link module is used for carrying out bit level processing on the user code block data based on the user parameter information to obtain scrambled data; and a symbol level processing submodule in the data link module is used for carrying out symbol level processing on the scrambled data by combining the symbol mapping address based on the user parameter information to obtain a mapping address distribution result. The method and the device finish data processing of the whole PDSCH channel, so that the whole designed link has high throughput and high transmission speed.

Description

Channel processing device and method based on field programmable logic gate array

Technical Field

The present invention relates to the Field of mobile communications technologies, and in particular, to a Field Programmable Gate Array (FPGA) based channel processing apparatus and method.

Background

With the rapid development of mobile communication technology, high-capacity data transmission puts higher demands on communication resources, computing resources, and storage resources. For example, after the mobile communication technology has been developed for a long time, a New Radio (NR) protocol of a fifth generation mobile communication technology (5G) has proposed the requirements of high data rate, low cost, low delay, high system capacity and large-scale device connection; and the small base station is a miniaturized and low-power base station device, and has limitations on the scale and power consumption of the device. A Physical Downlink Shared Channel (PDSCH) is used as one of the Physical channels of an Evolved Universal Terrestrial Radio Access (E-UTRA) entity to carry main user data, and the data throughput, processing speed and carrying platform of the PDSCH all need to be improved to meet the requirements of the current 5G NR small base station.

Disclosure of Invention

The related PDSCH implementation scheme mainly realizes physical layer bit level data processing based on FPGA hardware loading, and actually only serves as an accelerator to perform bit level processing of a data coding part, but symbol level processing such as modulation symbol and resource grid mapping is not performed to complete the processing process of the whole link data, so that the specification requirement of a 5G NR small base station cannot be met.

In view of this, the present application provides a channel processing apparatus and method based on a field programmable gate array, so as to meet the specification requirement of a 5G NR small base station.

In a first aspect, an embodiment of the present application provides a field programmable gate array-based channel processing apparatus, including: the device comprises a channel control module and a data link module, wherein the output end of the channel control module is connected with the input end of the data link module;

the channel control module is used for outputting user parameter information, user code block data and symbol mapping addresses to the data link module according to an interrupt enabling signal;

the data link module comprises a bit-level processing sub-module and a symbol-level processing sub-module;

the bit-level processing submodule is used for carrying out bit-level processing on the user code block data based on the user parameter information to obtain scrambled data;

and the symbol level processing submodule is used for carrying out symbol level processing on the scrambled data by combining the symbol mapping address based on the user parameter information to obtain a mapping address distribution result.

Optionally, the user parameter information includes user parameters output by the channel control module after the read parameter information is sorted and analyzed according to the interrupt enable signal, the user code block data includes code block data generated by the channel control module after code block segmentation operation is performed on the read user data, the symbol mapping address includes a symbol mapping address obtained by the channel control module after the read resource grid mapping address is allocated and processed, and the channel control module includes a bus interface analysis submodule; the bus interface analysis submodule is used for receiving an effective indication signal and transmission data output by an upper layer module through a bus interface, and storing the transmission data into a corresponding memory based on the effective indication signal, wherein the transmission data comprises the parameter information, the resource grid mapping address and the user data.

Optionally, the memory includes a parameter memory, a data memory and an address memory connected to the bus analysis submodule; the parameter memory is used for storing the parameter information; the data memory is used for storing the user data; the address memory is used for storing the resource grid mapping address.

Optionally, the channel control module further includes: a parameter control submodule, a data control submodule and an address control submodule;

the parameter control submodule is connected with the parameter memory and used for receiving the interrupt enabling signal through the bus interface, reading the parameter memory based on the interrupt enabling signal, sorting and analyzing the read parameter information and outputting corresponding user parameters and control information signals;

the data control submodule is connected with the data memory and is used for carrying out information analysis after receiving a control information signal output by the parameter control submodule and reading user data from the data memory according to information instruction obtained by analysis so as to carry out code block segmentation operation on the read user data and generate corresponding code block data;

the address control submodule is connected with the address memory and is used for carrying out information analysis after receiving a control information signal output by the parameter control submodule, reading a resource grid mapping address from the address memory according to information instruction obtained by analysis, and carrying out allocation processing on the read resource grid mapping address to obtain a corresponding symbol mapping address.

Optionally, the channel control module is specifically configured to output user parameter information, user code block data, and a symbol mapping address to the data link module through three independent links respectively; a first output end of the channel control module is connected with a first input end of the bit-level processing submodule and a first input end of the symbol-level processing submodule respectively so as to output the user parameter information to the bit-level processing submodule and the symbol-level processing submodule respectively; a second output end of the channel control module is connected with a second input end of the bit-level processing submodule so as to output the user code block data to the bit-level processing submodule; a third output end of the channel control module is connected with a third input end of the symbol level processing submodule so as to output the symbol mapping address to the symbol level processing submodule; and the output end of the bit-level processing submodule is connected with the second input end of the symbol-level processing submodule so as to output the scrambled data to the symbol-level processing submodule.

Optionally, the bit-level processing sub-module includes: the device comprises a check bit adding unit, a coding unit, a code block cascading unit and a data scrambling unit;

the input end of the check bit adding unit is connected with the output end of the channel control module, and the check bit adding unit is used for adding cyclic redundancy check codes to the user code block data based on the user parameter information to obtain first code block data and outputting the first code block data to the encoding unit;

the input end of the coding unit is connected with the output end of the check bit adding unit, and the coding unit is used for coding the first code block data based on the user parameter information and performing rate matching on target code block data generated after coding to obtain second code block data;

the code block cascading unit is connected with the output end of the encoding unit and used for restoring the second code block data output by the encoding unit into transmission block data based on the user parameter information;

the data scrambling unit is connected with the output end of the code block cascading unit and used for scrambling the data of the transmission block based on the user parameter information to obtain scrambled data.

Optionally, the symbol-level processing sub-module includes: the device comprises a symbol modulation unit, a power adjustment unit, a layer mapping port mapping unit, a beam forming unit, a compression unit and a mapping address allocation unit;

the input end of the symbol modulation unit is connected with the input end of the symbol level processing submodule, and the symbol modulation unit is used for modulating the scrambled data based on the user parameter information to obtain symbol level data corresponding to the scrambled data;

the input end of the power adjusting unit is connected with the output end of the symbol modulating unit, and the symbol modulating unit is used for carrying out power adjusting operation on the symbol level data based on the user parameter information to obtain symbol data after power adjustment;

the input end of the layer mapping port mapping unit is connected with the output end of the power adjusting unit, and the layer mapping port mapping unit is used for performing layer mapping and port mapping processing on the symbol data after power adjustment based on the user parameter information to obtain mapping data;

the input end of the beam forming unit is connected with the output end of the layer mapping port mapping unit, and the beam forming unit is used for carrying out beam forming processing on the basis of the user parameter information and the mapping data to obtain beam forming symbol data;

the input end of the compression unit is connected with the output end of the beam forming unit, and the compression unit is used for compressing the beam forming symbol data based on the user parameter information to obtain compressed symbol data;

the mapping address allocation unit is connected with the output end of the compression unit and is used for carrying out combined allocation on the compressed symbol data based on the user parameter information and in combination with the symbol mapping address to obtain a mapping address allocation result.

Optionally, the encoding unit includes: an encoding subunit and a rate matching subunit;

the coding subunit is connected with the check bit adding unit and is used for coding the first code block data after receiving the first code block data to obtain the target code block data;

and the rate matching subunit is connected with the output end of the coding subunit and is used for performing rate matching on the target code block data to obtain second code block data corresponding to the target code block data.

Optionally, the encoding subunit includes an allocation selector and at least two encoders, and the rate matching subunit includes an output selector and at least two rate matchers; the number of the encoders is the same as that of the rate matchers;

the input end of the distribution selector is connected with the output end of the check bit adding unit, and the distribution selector is used for sequentially distributing the received first code block data to the idle encoders according to a preset strategy so as to obtain target code block data;

the input ends of the at least two encoders are connected with the output end of the distribution selector, and the at least two encoders are used for performing parallel encoding processing on the target code block data based on the user parameter information;

the input ends of the at least two rate matchers are correspondingly connected with the output ends of the at least two encoders one by one, and the at least two rate matchers are used for performing parallel rate matching processing on the coded target code block data based on the user parameter information;

the input end of the output selector is connected with the output ends of the at least two rate matchers, and is used for sequentially transmitting the second code block data after rate matching processing to the bit level processing submodule based on the user parameter information.

Optionally, the bit-level processing sub-module further includes: the pseudo-random number generating unit is connected with the data scrambling unit;

the pseudo-random number generation unit is used for outputting a pseudo-random number sequence to the data scrambling unit;

the data scrambling unit is specifically configured to perform bit-level xor on the transport block data according to the pseudo random number sequence to complete the scrambling operation.

In a second aspect, an embodiment of the present application provides a channel processing method based on a field programmable gate array, which is applied to the channel processing apparatus based on the field programmable gate array according to any one of the first aspects, where the channel processing apparatus includes a channel control module and a data link module connected to the channel control module, and the channel processing method includes:

according to the interrupt enabling signal, outputting user parameter information, user code block data and a symbol mapping address to a data link module through a channel control module;

based on the user parameter information, carrying out bit-level processing on the user code block data through a bit-level processing submodule in the data link module to obtain scrambled data;

and based on the user parameter information, combining the symbol mapping address, and performing symbol-level processing on the scrambled data through a symbol-level processing submodule in the data link module to obtain a mapping address allocation result.

Optionally, the user parameter information includes user parameters output by the channel control module after sorting and analyzing the read parameter information according to the interrupt enable signal, the user code block data includes code block data generated by the channel control module after performing code block segmentation operation on the read user data, the symbol mapping address includes a symbol mapping address obtained by the channel control module after performing allocation processing on the read resource grid mapping address, and the channel processing method further includes:

receiving a valid indication signal and transmission data output by an upper layer module through a bus interface, wherein the transmission data comprise the parameter information, the resource grid mapping address and the user data;

and respectively storing the parameter information, the resource grid mapping address and the user data into corresponding memories through a bus interface analysis submodule in the channel control module based on the effective indication signal.

Optionally, the outputting, by the channel control module, the user parameter information, the user code block data, and the symbol mapping address to the data link module according to the interrupt enable signal includes:

receiving the interrupt enable signal through the bus interface;

based on the interrupt enabling signal, reading operation is carried out through a parameter control submodule in the channel control module so as to sort and analyze the read parameter information and output corresponding user parameters and control information signals;

based on the control information signal output by the parameter control submodule, performing information analysis by a data control submodule in the channel control module, and reading user data according to the information instruction obtained by analysis so as to perform code block segmentation operation on the read user data and generate corresponding code block data;

and performing information analysis through an address control submodule in the channel control module according to a control information signal output by the parameter control submodule, reading a resource grid mapping address according to information instruction obtained by analysis, and performing allocation processing on the read resource grid mapping address to obtain a corresponding symbol mapping address.

Optionally, the channel control module outputs the user parameter information, the user code block data, and the symbol mapping address to the data link module through three independent links.

The embodiment of the application outputs the user parameter information, the user code block data and the symbol mapping address to the data link module through the channel control module according to the interrupt enabling signal, so as to perform symbol mapping subsequently, so that a bit level processing submodule in the data link module can perform bit level processing on user code block data based on user parameter information to obtain scrambled data, and then the symbol level processing submodule in the data link module is used for performing symbol level processing on the scrambled data by combining the symbol mapping address to realize symbol level data operation, obtain a mapping address allocation result and complete data processing of the whole PDSCH channel, the resource grid mapping part behind the PDSCH can be directly subjected to mapping processing, the whole designed link has the characteristics of high throughput, high transmission speed, low maintenance cost and the like, and the requirements of a 5G NR small base station are met.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1 is a block diagram of a channel processing apparatus based on a field programmable gate array according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of an FPGA-based channel processing apparatus according to an example of the present application;

fig. 3 is a schematic diagram illustrating a design principle of a channel control module according to an example of the present application;

fig. 4 is a schematic flowchart of a channel processing method based on an FPGA according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In actual processing, the PDSCH is a Downlink physical Channel carrying a large amount of user data, and its main function is mainly to carry data of a Downlink Shared Channel (DSCH) Channel by means of coding and modulation. The relevance of the existing PDSCH implementation scheme and the current 5G NR small base station is not particularly strong, and the requirement of the 5G NR small base station cannot be met.

Aiming at the specification requirements of a 5G NR protocol and a small base station, the embodiment of the application provides a channel processing device and a channel processing method based on a field programmable logic gate array (FPGA), so that the advantages of the customizability of an FPGA and highly integrated hardware resources are utilized to realize the signal processing of a PDSCH channel and complete the data processing of the whole PDSCH channel, the whole designed link has the characteristics of large throughput, high transmission speed, low maintenance cost and the like, and the requirements of the 5G NR small base station are met.

Fig. 1 is a block diagram of a channel processing apparatus based on a field programmable gate array according to an embodiment of the present disclosure. The field programmable gate array-based channel processing apparatus provided by the present application may specifically include: a channel control module 110 and a data link module 120. In a specific implementation, as shown in fig. 1, an output terminal of the channel control module 110 is connected to an input terminal of the data link module 120. The channel control module 110 is configured to output user parameter information, user code block data, and symbol mapping address to the data link module 120 according to an interrupt enable signal. The data link module 120 may perform bit-level processing on user code block data based on the received user parameter information, and may perform symbol-level processing on scrambled data obtained after the bit-level processing in combination with a symbol mapping address to obtain a mapping address allocation result, thereby completing data processing of the entire PDSCH channel, so that a resource grid mapping part behind the PDSCH may be directly subjected to mapping processing.

Specifically, the data link module 120 in the embodiment of the present application may include a bit-level processing sub-module 121 and a symbol-level processing sub-module 122; the bit-level processing sub-module 121 is configured to perform bit-level processing on the user code block data based on the user parameter information to obtain scrambled data; the symbol level processing sub-module 122 is configured to perform symbol level processing on the scrambled data in combination with the symbol mapping address based on the user parameter information, so as to obtain a mapping address allocation result.

It can be seen that the channel processing apparatus based on the fpga in the embodiment of the present application can output the user parameter information, the user code block data and the symbol mapping address to the data link module 120 according to the interrupt enable signal through the channel control module 110, the bit level processing submodule 121 in the data link module 120 performs bit level processing on user code block data based on user parameter information to obtain scrambled data, and then the symbol level processing submodule 122 in the data link module 120 performs symbol level processing on the scrambled data by combining symbol mapping addresses to obtain mapping address allocation results, so as to complete data processing of the whole PDSCH channel, so that the resource grid mapping part behind the PDSCH can be directly subjected to mapping processing, therefore, the whole designed link has high throughput, high transmission speed and low maintenance cost, and meets the requirement of a 5G NR small base station.

In actual Processing, the channel Processing apparatus based on the fpga provided in this embodiment may be developed and implemented by three major parts, and the first part may be a channel control module 110 that obtains upper layer user parameter information and user data provided by an upper layer processor through a bus interface, where the upper layer processor may be a Digital Signal Processor (DSP), a Central Processing Unit (CPU), an ARM processor (Advanced RISC Machine), and the like, which is not limited herein. The upper layer processor is used for realizing data processing of a Media Access Control (MAC) layer and above. As shown in fig. 2, the channel control module 110 may be a PDSCH control module that acquires upper layer user parameter information and user data provided by an upper layer processor through a Peripheral Component Interconnect Express (PCIE) interface; the second part may be a bit-level processing sub-module in the data link module 120 to perform bit-level processing on the received user code block data based on the user parameter information; the third part may be a symbol level processing submodule in the data link module 120, so as to perform symbol level processing on scrambled data output by the symbol level processing submodule based on the user parameter information in combination with the symbol mapping address, and complete data processing of the whole PDSCH channel, so that the resource grid mapping part behind the PDSCH can be directly subjected to mapping processing, and the requirement of a 5G NR small base station is met. It should be noted that, the upper layer processor may provide the upper layer user parameter information and the user data to the interface through the upper layer processor, and the upper layer processor may include: PCIE interface module PCIE _ TOP/SRIO _ TOP which is externally and externally connected with the upper processor in the PDSCH overall design and protocol related parameter allocation and arrangement module PDU _ DISTRIBUTION which is externally and externally connected with the PDSCH overall design, wherein SRIO (Serial RapidIO) and PCIE are both interface standards, and PDU (protocol Data Unit) is a protocol Data unit.

Specifically, when the Media Access Control (MAC) layer and above is implemented based on a DSP and an Advanced reduced instruction set machine (ARM), the channel Control module 110 of the first part may receive, through a bus interface, user parameter information, user data, a resource grid mapping address, and an interrupt enable signal transmitted from an upper processor. Specifically, the channel control module 110 may receive and store data into corresponding Random Access Memories (RAMs) according to three types of user parameter information, user data, or resource grid mapping addresses. When the upper processor provides the interrupt enable signal, the channel control module 110 may start to read the user information parameters from the RAM for analysis based on the interrupt enable signal, and may perform code block segmentation on the user data and output the user data to the second user data processing link portion (i.e., the bit level processing sub-module 121 in the data link module 120) for further processing; the resource grid mapping address can be allocated to the processed data at each symbol level for the subsequent symbol mapping.

On the basis of the foregoing embodiment, optionally, in this embodiment of the present application, the user parameter information output by the channel control module 110 to the data link module 120 may include a user parameter output by the channel control module 110 after performing sorting and analysis on the read parameter information according to the interrupt enable signal; the user code block data output to the data link module 120 may include code block data generated by the channel control module 110 performing a code block segmentation operation on the read user data; the symbol mapping address output to the data link module 120 may include a symbol mapping address obtained by the channel control module 110 performing allocation processing on the read resource grid mapping address. Further, the channel control module 110 provided in the embodiment of the present application may include a bus interface analysis sub-module. The bus interface analysis submodule is used for receiving an effective indication signal and transmission data output by an upper layer module through a bus interface, and storing the transmission data into a corresponding memory based on the effective indication signal, wherein the transmission data comprises the parameter information, the resource grid mapping address and the user data. Wherein, the valid indication signal output by the upper layer module may include: the upper processor outputs effective indication signals through a bus interface; the valid indication signal may be used to indicate a data valid indication, such as when the valid indication signal is pulled high, indicating that the data is valid.

Specifically, the bus interface analysis submodule in this embodiment may determine that the upper layer data, the data valid indication signal, and the data address, which are processed by the upper layer processor and transmitted by the bus interface, are received. As shown in fig. 3, when the valid indication signal is pulled high, the data and the data address are received as valid data to the channel control module 110, and may be stored in the corresponding storage space according to the data type and the data address, that is, the transmission data is stored in the corresponding memory. The upper layer data (i.e., transmission data) processed by the upper layer processor includes parameter information, user data, and a resource grid mapping address input to the channel control module 110.

Further, the memory in the embodiment of the present application may include a parameter memory, a data memory, an address memory, and the like connected to the bus analysis submodule. Wherein the parameter memory may be configured to store the parameter information; the data store may be for storing the user data; the address memory may be used to store the resource grid mapping address.

As an example of the present invention, after the bus interface analysis submodule obtains data from the PCIE interface, the bus interface analysis submodule may analyze the data. Specifically, after receiving the transmission data, the bus interface analysis submodule may decode a data address of the transmission data based on the valid indication signal, determine the input data type and the storage address, and then store the received transmission data in the corresponding memory according to the data type and the address, as shown in fig. 3, the bus interface analysis submodule may store the received parameter information in the corresponding parameter memory, store the received resource grid mapping address in the corresponding address memory, and store the received user data in the corresponding data memory. Subsequently, the channel control module 110 may wait for the PCIE interface to output a raised interrupt enable signal, so as to instruct the PDSCH channel to start operating when the interrupt enable signal is raised, for example, read the user information parameters from the memory for analysis, configure the user information parameters obtained by analysis into the user data processing link portion (i.e., the bit-level processing sub-module 121 and the symbol-level processing sub-module 122 in the data link module 120), perform code block segmentation on the user data and output the user data to the user data processing link portion (i.e., the bit-level processing sub-module 121 in the data link module 120) for further processing, and allocate a resource mesh mapping address to the processed data at each symbol level for subsequent symbol mapping.

In an optional embodiment of the present application, the channel control module 110 may further include: parameter control submodule, data control submodule and address control submodule. The parameter control submodule is connected with the parameter memory and used for receiving the interrupt enabling signal through the bus interface, reading the parameter memory based on the interrupt enabling signal, sorting and analyzing the read parameter information, and outputting corresponding user parameter and control information signals, for example, outputting corresponding control information signals to the data control submodule and the address control submodule so that the data control submodule and the address control submodule start to work. The data control submodule is connected with the data storage, and is configured to perform information analysis after receiving a control information signal output by the parameter control submodule, and read user data from the data storage according to information instruction obtained through analysis, so as to perform code block segmentation operation on the read user data, generate corresponding code block data, and transmit the code block data to the data link module 120 as user code block data, so as to directly output the data after code block segmentation to the data link module 120 for further processing. The address control submodule is connected with the address memory and is used for carrying out information analysis after receiving a control information signal output by the parameter control submodule, reading a resource grid mapping address from the address memory according to information instruction obtained by analysis, and carrying out allocation processing on the read resource grid mapping address to obtain a corresponding symbol mapping address.

For example, in combination with the above example, when receiving an interrupt enable signal that PCIE outputs a pull-up, the parameter control sub-module may start working first, and as shown in fig. 3, the parameter control sub-module may perform a value reading operation on a memory that stores user parameter information, that is, perform a reading operation on the parameter memory, and analyze and sort the read parameter information. Subsequently, the parameter control sub-module may output the user parameter as user parameter information to the data link module 120 according to the processing result, and may transmit control information signals of the data control sub-module and the address control sub-module to corresponding functional sub-modules inside the channel control module 110, so that the functional sub-modules start to operate.

Specifically, after receiving the control information signal output by the parameter control sub-module, the data control sub-module may start to analyze information based on the control information signal, and may read out the channel user data from the data memory based on the rule of protocol code block segmentation according to the information instruction obtained by the analysis, that is, read out the user data from the data memory, to complete two operations of reading out data and code block segmentation, for example, perform a code block segmentation operation on the read user data, and transmit the code block data generated after code block segmentation as the user code block data to the data link module 120, so as to directly output the user data after code block segmentation to the data link portion of the PDSCH. The user code block data may represent user data generated after code block segmentation.

In addition, the address control sub-module after receiving the control information signal may start to analyze the information, may then read out the resource grid mapping address in the mapping address memory according to the information indication, that is, read the resource grid mapping address from the address memory according to the information indication obtained by the analysis, and may perform allocation processing on the read resource grid mapping address to allocate the mapping address to the processed data at each symbol level to obtain a corresponding symbol mapping address, and may then transmit the symbol mapping address to the data link module 120, that is, output the symbol mapping address to the data link portion of the PDSCH, so as to perform symbol mapping subsequently.

Further, the channel control module 110 in this embodiment is specifically configured to output the user parameter information, the user code block data, and the symbol mapping address to the data link module 120 through three independent links. Specifically, the first output end of the channel control module 110 is respectively connected to the first input end of the bit-level processing sub-module 121 and the first input end of the symbol-level processing sub-module 122, so that the channel control module 110 can output the user parameter information to the bit-level processing sub-module 121 and the symbol-level processing sub-module 122 of the data link module through an independent link corresponding to the first output end; a second output end of the channel control module 110 is connected to a second input end of the bit-level processing submodule 121, so that the channel control module 110 can output the user code block data to the bit-level processing submodule 121 of the data link module 120 through an independent link corresponding to the second output end; and, a third output terminal of the channel control module 110 may be connected to a third input terminal of the symbol-level processing submodule 122, so that the channel control module may output a symbol mapping address to the symbol-level processing submodule 122 of the data link module 120 through an independent link corresponding to the third output terminal. In addition, the output terminal of the bit-level processing sub-module 121 may be connected to the second input terminal of the symbol-level processing sub-module 122 to output the scrambled data to the symbol-level processing sub-module, so that the symbol-level processing sub-module 122 may perform symbol-level processing on the scrambled data output by the bit-level processing sub-module based on the user parameter information in combination with the symbol mapping address, thereby completing data processing of the whole PDSCH channel.

Therefore, the channel control module in the embodiment of the application outputs the user parameter information, the user code block data and the symbol mapping address to the data link module through three independent links, so that the three types of data, namely the user parameter information, the user code block data and the symbol mapping address, are uniformly configured in the data link module, and each unit in the data link module can be configured with the parameter of each unit in advance according to the user parameter information and the symbol mapping address, so that the data processing efficiency is improved.

In the actual processing, after receiving the Code Block data transmitted by the first part, the bit-level processing sub-module 121 of the data link module 120 of the second part may add Cyclic Redundancy Check (CRC) codes to the Code Block data, for example, add Transport Block (TB) CRC and Code Block (CB) CRC to the Code Block data, and then transmit the data to the encoding unit to process the Code Block data, so as to implement LDPC encoding and rate matching, further process the Code Block data output after the encoding unit matches the encoding, and perform symbol-level processing in combination with a symbol mapping address, so as to complete a complete flow of the PDSCH user data processing link.

Optionally, the bit-level processing sub-module 121 in the embodiment of the present application may specifically include: the device comprises a check bit adding unit, a coding unit, a code block cascading unit and a data scrambling unit. The input end of the check bit adding unit is connected to the output end of the channel control module 110, and the check bit adding unit is configured to add a cyclic redundancy check code to the user code block data based on the user parameter information to obtain first code block data, and output the first code block data to the encoding unit; the input end of the coding unit is connected with the output end of the check bit adding unit, and the coding unit is used for coding the first code block data based on the user parameter information and performing rate matching on target code block data generated after coding to obtain second code block data; the code block cascading unit is connected with the output end of the encoding unit and used for restoring second code block data output by the encoding unit into transmission block data based on the user parameter information; the data scrambling unit is connected with the output end of the code block cascading unit, and the data scrambling unit is used for scrambling the data of the transmission block based on the user parameter information to obtain scrambled data. The scrambled data may then be transmitted to a symbol level processing sub-module 122 for symbol level processing of the scrambled data by the symbol level processing sub-module 122 based on the user parameter information in combination with the symbol mapping address to obtain a mapping address assignment result.

Specifically, after receiving the user parameter information and the user data provided by the channel control module 110, the data link module 120 may determine the type of the user data based on the user parameter information, and may perform TB-CRC and CB-CRC addition on the received data after the code block segmentation, as shown in fig. 2, perform cyclic redundancy check code addition on the received user code block data through a check bit addition unit to add CRC check bits on the user code block data, so as to form first code block data. For example, the check bit adding unit may perform cyclic redundancy check code addition on the user code block data according to a check algorithm such as CRC16, CRC24A, CRC24B, or the like to complete CRC check bit addition. The first code block data may then be output to an encoding unit to transmit the CRC-added code block data to the encoding unit for LDPC encoding. The first code block data may represent code block data after CRC is added, and may refer to code block data before coding generated after CRC is added.

In the actual processing, in order to meet the low-delay requirement of the 3GPP standard and increase the rate, a four-core processing mode may be adopted, and the encoding unit is set according to the parameters configured by the control module at the previous stage, so that the data is subjected to rate matching on the completed target code block data after being encoded by the LDPC of the encoding unit, and the second code block data obtained after the rate matching may be transmitted to the code block concatenation unit for corresponding data processing, so as to restore the second code block data to the transmission block data. The target block data may refer to code block data generated after encoding. It should be noted that 3GPP is a specification of a communication protocol.

Further, the encoding unit in the embodiment of the present application may include: an encoding subunit and a rate matching subunit; the input end of the coding subunit is connected with the output end of the check bit adding unit, and the coding subunit is configured to code the first code block data after receiving the first code block data, so as to obtain the target code block data; the input end of the rate matching subunit is connected with the output end of the coding subunit, and the rate matching subunit is used for performing rate matching on the target code block data to obtain second code block data corresponding to the target code block data. Specifically, in the process that the check bit adding unit transmits the first code block data to which the CRC is added to the external coding unit for coding, the coding subunits in the coding unit may perform multiple groups of code block parallel processing in the form of multiple cores, and may perform distribution of the code block data through a selector (MUX) to improve the link processing rate.

Optionally, the encoding subunit in this embodiment of the present application may include an allocation selector and at least two encoders, and the rate matching subunit includes an output selector and at least two rate matchers; the number of the encoders is the same as that of the rate matchers; the input end of the distribution selector is connected with the output end of the check bit adding unit, and the distribution selector is used for sequentially distributing the received first code block data to the idle encoders according to a preset strategy so as to obtain target code block data; the input ends of the at least two encoders are connected with the output end of the distribution selector, and the at least two encoders are used for performing parallel encoding processing on the target code block data based on the user parameter information; the input ends of the at least two rate matchers are correspondingly connected with the output ends of the at least two encoders one by one, and the at least two rate matchers are used for performing parallel rate matching processing on the coded target code block data based on the user parameter information; the input end of the output selector is connected with the output ends of the at least two rate matchers, and is used for sequentially transmitting the second code block data after rate matching processing to the bit level processing submodule based on the user parameter information.

Specifically, in the case that the encoding subunit includes an allocation selector and a parity check code LDPC encoder, the allocation selector may be connected to an output end of the check bit adding unit, and the allocation selector may sequentially allocate, according to an order of receiving the first code block data, the received first code block data to an idle LDPC encoder for encoding processing, so as to generate corresponding target code block data. In actual processing, one LDPC encoder may include one encoding core, and the processing time of encoding by one encoding core is relatively long, so that the encoding subunit in this embodiment of the present application may be provided with a plurality of LDPC encoders, so as to make the time equal by a plurality of encoding cores, for example, make the time equal by four encoding cores, implement parallel processing of encoding, and improve the encoding efficiency. Specifically, in the process of transmitting code block data one by one, the encoding subunit in the encoding unit may receive the transmitted code block data through the allocation selector, and sequentially output the code block data to the LDPC encoder based on the received code block data, that is, output one first code block data to the LDPC encoder in a pipelined manner, and perform parallel encoding on the transmitted first code block data through the encoding core in the LDPC encoder. For example, after a first code block data transmission, if the coding core of a first LDPC encoder is operational, the assignment selector may transmit the first code block data to the coding core of a second LDPC encoder for processing; after the next first code block data is transmitted, the coding core of the second LDPC coder and the coding core of the first LDPC coder work, and at the moment, the distribution selector can transmit the next first code block data to the coding core of the idle third LDPC coder for coding, so that parallel processing among a plurality of coding cores is realized, and coding processing efficiency is improved.

As an example of the present application, when transmitting the code block data to which the CRC is added to the encoding unit for LDPC encoding, an encoding subunit in the encoding unit may receive the first code block data to which the CRC is added through an allocation selector, and may allocate the received first code block data according to a preset policy to sequentially allocate the received first code block data to idle LDPC encoders, so that multiple groups of code block parallel processing may be performed by multiple LDPC encoders in the form of multiple (multiple LDPC encoding) cores. For example, as shown in fig. 2, a parity encoder LDPC _ ENCODE in the encoding subunit performs multiple groups of code block parallel processing in the form of four LDPC encoding cores, and outputs four target code block data to the rate matching subunit, so that the rate matching subunit performs rate matching on the target code block data subjected to LDPC encoding, and the process may specifically include puncturing, i.e., removing the first 2 × z columns of bits, bit selection and bit interleaving, so as to input the processed data to the second part for corresponding data processing after the above operations are completed.

In the actual processing, similar to LDPC coding, the rate matching of the rate matching subunit corresponds to the coding of the coding subunit, or a multi-core parallel processing design may be adopted, so that code block data may be transmitted to the corresponding rate matching core for processing after LDPC coding, and after data processing is completed by a plurality of rate matching cores, the data may be sequentially input back to the data link module 120 of the PDSCH through the selector again, so as to perform the operations of code block concatenation, scrambling, modulation, layer mapping, port mapping, power modulation, a-law compression, and mapping address allocation, thereby completing the complete flow of the PDSCH user data processing link.

Specifically, the input end of the rate matcher is connected with the output end of the LDPC encoder in a one-to-one correspondence manner. Each rate matcher, after receiving target block data output by the LDPC encoder, may perform rate matching processing on the received target block data based on the user parameter information. Therefore, when the rate matching subunit includes at least two rate matchers, the target encoded data generated after the encoding process can be subjected to parallel rate matching processing by the cores of the at least two rate matchers, that is, the target encoded data generated after the encoding process can be subjected to parallel rate matching processing by at least two (rate matching) cores, so that parallel rate matching processing in the form of multiple (multiple rate matching) cores can be realized. As shown in fig. 2, the Rate matching subunit may perform parallel Rate matching processing on four target block data output by the parity coding unit LDPC _ ENCODE in the form of four Rate matching cores through the Rate matcher Rate _ Match, and output corresponding four second block data to the output selector, so that the output selector may sequentially transmit the Rate-matched second block data to the code block concatenation unit of the bit-level processing sub-module 121 based on the user parameter information, so as to sequentially transmit the second block data back to the code block concatenation unit for further data processing.

In an alternative embodiment, the coding unit may be a separate module, and the called method may be adopted to call the coding unit, so as to facilitate separate modification of the coding unit. Specifically, the parity adding unit in the bit-level processing sub-module 121 may transmit the first code block data generated after the parity addition to the external encoding module to be encoded by the external encoding module after the parity addition is performed on the received user code block data based on the user parameter information. After receiving the first code block data, the encoding module may encode the first code block data based on the user parameter information, perform rate matching encoding on target code block data generated after encoding, generate second code block data, and output the second code block data to a code block concatenation unit in the bit-level processing submodule 121, so as to sequentially transmit the second code block data to the bit-level processing submodule 121 for further data processing. As can be seen, the encoding module in this embodiment of the application may input the processed second code block data back to the data link module 120, so as to perform the operations of code block concatenation, scrambling, modulation, layer mapping, port mapping, power modulation, a-law compression, and mapping address allocation through the bit-level processing submodule 121 and the symbol-level processing submodule 122 of the data link module 120, thereby completing the complete process of the PDSCH user data processing link.

For example, the output selector may sequentially transmit the received target block data to the code block concatenation unit PDSCH _ CAS of the bit-level processing submodule in the order in which the target block data is received, based on the user parameter information. After receiving the second code block data, the code block concatenation unit PDSCH _ CAS may perform code block concatenation processing on the second code block data, that is, perform code block level processing on data returned after coding and rate matching to remove padding bits between code blocks, concatenate bit data between code blocks to restore to transport block data, and may transmit the transport block data to the data scrambling unit PDSCH _ SCRAM, so as to facilitate symbol level processing behind a channel. Wherein the transport block data may represent data restored to the transport block.

Specifically, after receiving the transport block data, the data scrambling unit PDSCH _ SCRAM may perform a scrambling operation on the transport block data, for example, may perform bit-level xor on the received transport block data and a pre-configured generated pseudo random number sequence to complete the scrambling operation, so as to obtain scrambled data. Further, the bit-level processing sub-module 121 in the embodiment of the present application may further include: the pseudo-random number generating unit is connected with the data scrambling unit; the pseudo-random number generating unit is used for outputting a pseudo-random number sequence to the data scrambling unit; the data scrambling unit is specifically configured to perform bit-level xor on the transport block data according to the pseudo random number sequence to complete the scrambling operation.

Optionally, the symbol level processing sub-module 122 in the embodiment of the present application includes: the device comprises a symbol modulation unit, a power adjustment unit, a layer mapping port mapping unit, a beam forming unit, a compression unit and a mapping address allocation unit. The input end of the symbol modulation unit is connected with the input end of the symbol level processing submodule, and the symbol modulation unit is used for modulating the scrambled data based on the user parameter information to obtain symbol level data corresponding to the scrambled data; the input end of the power adjusting unit is connected with the output end of the symbol modulating unit, and the symbol modulating unit is used for carrying out power adjusting operation on the symbol level data based on the user parameter information to obtain symbol data after power adjustment; the input end of the layer mapping port mapping unit is connected with the output end of the power adjusting unit, and the layer mapping port mapping unit is used for performing layer mapping and port mapping processing on the symbol data after power adjustment based on the user parameter information to obtain mapping data; the input end of the beam forming unit is connected with the output end of the layer mapping port mapping unit, and the beam forming unit is used for carrying out beam forming processing on the basis of the user parameter information and the mapping data to obtain beam forming symbol data; the input end of the compression unit is connected with the output end of the beam forming unit, and the compression unit is used for compressing the beam forming symbol data based on the user parameter information to obtain compressed symbol data; the mapping address allocation unit is connected with the output end of the compression unit and is used for carrying out combined allocation on the compressed symbol data based on the user parameter information and in combination with the symbol mapping address to obtain a mapping address allocation result.

The input end of the symbol level processing submodule 122 includes a first input end, a second input end and a third input end, and the input end of the symbol modulation unit includes a first sub-input end correspondingly connected to the first input end of the symbol level processing submodule 122, a second sub-input end correspondingly connected to the second input end of the symbol level processing submodule 122 and a third sub-input end correspondingly connected to the third input end of the symbol level processing submodule 122. In actual processing, the symbol modulation unit may receive, through the first sub-input terminal, user parameter information output by the channel control module, receive, through the third sub-input terminal, a symbol mapping address output by the channel control module, and receive, through the second sub-input terminal, scrambled data output by the bit-level processing sub-module, so as to perform, based on the user parameter information, symbol-level processing on the scrambled data in combination with the symbol mapping address.

For example, as shown in fig. 2, after receiving the transport block data, the data scrambling unit PDSCH _ SCRAM may perform bit-level xor on the transport block data and the pseudo random number sequence output by the pseudo random number generation unit PN to complete the scrambling operation, and may transmit the scrambled data obtained after the scrambling operation is completed to the symbol modulation unit PDSCH _ MOD, so that the symbol modulation unit PDSCH _ MOD may modulate the scrambled data. Specifically, after receiving the scrambled data output by the data scrambling unit PDSCH _ SCRAM, the symbol modulation unit PDSCH _ MOD may modulate the scrambled data according to a modulation order indication provided by the control module based on the parameter information, for example, perform one of QPSK, 16QAM, 64QAM, and 256QAM on the data to convert the data from a bit level to a symbol level, so as to obtain symbol level data, and then transmit the symbol level data to the power adjustment unit PDSCH _ POW _ ADJ, so as to perform a power adjustment operation on the symbol level data through the power adjustment unit PDSCH _ POW _ ADJ.

After receiving the symbol-level data, the power adjustment unit PDSCH _ POW _ ADJ may perform power adjustment operation on the symbol-level data based on the power factor and user parameter information given by the channel control module 110 according to the performance and protocol requirements of the FPGA to obtain power-adjusted symbol data, and may transmit the power-adjusted symbol data to the LAYER mapping port mapping unit PDSCH _ LAYER _ MAP, so that the power-adjusted symbol data may be mapped according to the LAYER mapping number and port mapping finger given by the control module.

Specifically, after receiving the symbol data with adjusted power, the LAYER mapping port mapping unit PDSCH _ LAYER _ MAP may perform LAYER mapping and port mapping processing on the symbol data with adjusted power according to the LAYER mapping number and the port mapping indication output by the channel control module 110 to obtain mapping data, and may transmit the mapping data to the beamforming unit PDSCH _ DBF to perform beamforming processing on the data after LAYER mapping is completed. The power-adjusted symbol data may include layer-mapped data.

Specifically, after the layer mapping is completed, in this example, the beamforming unit PDSCH _ DBF may perform beamforming processing on the symbol data after power adjustment to obtain beamforming symbol data. For example, after receiving the power-adjusted symbol data, the beamforming unit PDSCH _ DBF may perform matrix operation on the rate-adjusted symbol data and a preset corresponding beamforming matrix data beam based on the user parameter information, so as to perform matrix operation on the data subjected to layer mapping and port mapping and the corresponding beamforming matrix data to obtain a new numerical value, which is used as beamforming symbol data and transmitted to the compression unit PDSCH _ ALCP.

After receiving the beamforming symbol data, the compressing unit PDSCH _ ALCP may perform a-law compression on the beamforming symbol data based on the user parameter information, so as to perform a-law compression on the mapped symbol data, reduce the data amount by one order of magnitude, obtain the compressed symbol data, and transmit the compressed symbol data to the mapping address allocating unit PDSCH _ ADDR _ MAP for combined allocation, so as to facilitate transmission of subsequent data. For example, after receiving the compressed symbol data output by the compression unit PDSCH _ ALCP, the mapping address allocation unit PDSCH _ ADDR _ MAP may perform combined allocation on the symbol mapping address and the compressed symbol data, so as to perform combined allocation on the mapping address of the DSP that has completed resource grid mapping processing and the processed symbol data, and obtain a mapping address allocation result, so that the resource grid mapping part behind the PDSCH may directly perform mapping processing, and does not need to perform complex operations such as mapping address interleaving on an FPGA, and thus the whole designed link has the characteristics of large throughput, high transmission speed, low maintenance cost, and the like, and meets the requirements of a 5G NR small base station.

As can be seen, the FPGA-based channel processing apparatus in this example utilizes the advantages of customizability and highly integrated hardware resources of the FPGA to meet the specification requirements of the 5G NR protocol and the small base station, and implements PDSCH design of the 5G NR small base station under a design architecture based on a pipeline and parallel processing. Therefore, on the basis of ensuring the scale of the device, the method can process larger data volume without reducing or even improving the processing speed, and can process data accurate to the bit level, so that the whole design link has the characteristics of large throughput, high transmission speed, low maintenance cost and the like.

In summary, the channel processing device provided in the embodiment of the present application implements PDSCH channel signal processing based on the FPGA as a platform, and implements parallel processing of multiple data by designing digital circuits on the FPGA, thereby improving channel data throughput; the data pipeline processing can be realized by designing a digital circuit based on the FPGA so as to improve the hardware running speed by utilizing a reasonable circuit design framework, thereby reducing the hardware cost in the aspect of performance requirement; and the design of digital circuits can be realized based on FPGA, so that the data processing precision can be flexibly converted, and not only can the data operation of bit level be realized, but also the data operation of symbol level can be carried out.

In addition, the embodiment of the application has certain advantages in the design and implementation of the channel, the construction of the architecture and the range of the functions. Specifically, the field programmable gate array-based channel processing apparatus provided in the embodiment of the present application can complete data processing of the entire PDSCH channel only by providing relevant parameters, transport block data, and resource grid mapping addresses, so as to more perfectly implement PDSCH, and the channel is subjected to parameter receiving, analysis, and channel control by the channel control module 110, so that two actions of data receiving, storing, and enabling the channel module can be separated from each other, it is ensured that data storage and module operation can be performed simultaneously without mutual interference, and the processing speed and stability of channel design are improved.

Further, the channel control module 110 in this embodiment of the present application may use three memory spaces to correspond to a three-memory control architecture, so as to ensure that parameters, data, and mapping addresses are independent from each other, and may work in a near-parallel state, thereby improving the channel design processing speed and stability.

On the basis of the foregoing embodiment, an embodiment of the present application may further provide a channel processing method based on a field programmable logic gate array, which is applied to any one of the above device embodiments in the channel processing device based on a field programmable logic gate array, so that the channel processing device based on a field programmable logic gate array may perform information data processing and carrying of a physical layer based on upper layer user parameter information and user data provided by a DSP, complete data processing of a whole PDSCH channel, and make a whole designed link have a large throughput, a fast transmission speed, and a low maintenance cost, and meet the requirements of a 5G NR small base station.

Referring to fig. 4, a flowchart of a channel processing method based on a field programmable gate array according to an embodiment of the present application is shown. The channel processing method based on the field programmable gate array provided in the embodiment of the present application may be applied to a channel processing device based on the field programmable gate array, where the channel processing device may include a data link module in which a channel control module is connected to the channel control module, as shown in fig. 4, and the channel processing method may specifically include the following steps:

step 410, outputting user parameter information, user code block data and symbol mapping address to the data link module through the channel control module according to the interrupt enable signal;

step 420, based on the user parameter information, performing bit-level processing on the user code block data by a bit-level processing submodule in the data link module to obtain scrambled data;

and 430, performing symbol-level processing on the scrambled data through a symbol-level processing submodule in the data link module based on the user parameter information and in combination with the symbol mapping address to obtain a mapping address allocation result.

The user parameter information comprises user parameters which are output after the channel control module sorts and analyzes the read parameter information according to the interrupt enabling signal, the user code block data comprises code block data which are generated after the channel control module performs code block segmentation operation on the read user data, and the symbol mapping address comprises a symbol mapping address which is obtained after the channel control module performs allocation processing on the read resource grid mapping address.

On the basis of the foregoing embodiment, the channel processing method provided in this application further includes: receiving a valid indication signal and transmission data output by an upper layer module through a bus interface, wherein the transmission data comprise the parameter information, the resource grid mapping address and the user data; and respectively storing the parameter information, the resource grid mapping address and the user data into corresponding memories through a bus interface analysis submodule in the channel control module based on the effective indication signal.

Optionally, the outputting, by the channel control module, the user parameter information, the user code block data, and the symbol mapping address to the data link module according to the interrupt enable signal includes: receiving the interrupt enable signal through the bus interface; based on the interrupt enabling signal, reading operation is carried out through a parameter control submodule in the channel control module so as to sort and analyze the read parameter information and output corresponding user parameters and control information signals; based on the control information signal output by the parameter control submodule, performing information analysis by a data control submodule in the channel control module, and reading user data according to the information instruction obtained by analysis so as to perform code block segmentation operation on the read user data and generate corresponding code block data; and performing information analysis through an address control submodule in the channel control module according to a control information signal output by the parameter control submodule, reading a resource grid mapping address according to information instruction obtained by analysis, and performing allocation processing on the read resource grid mapping address to obtain a corresponding symbol mapping address.

Further, in this embodiment, the channel control module outputs the user parameter information, the user code block data, and the symbol mapping address to the data link module through three independent links. Specifically, the step of outputting the user parameter information, the user code block data, and the symbol mapping address to the data link module through the channel control module may specifically include the following steps:

substep 4101, outputting the user parameter information to the bit-level processing submodule and the symbol-level processing submodule respectively through a first output end of the channel control module;

sub-step 4102, outputting the user code block data to the bit-level processing sub-module through a second output terminal of the channel control module;

sub-step 4103, outputting said symbol mapped address to said symbol level processing submodule via a third output terminal of said channel control module.

Further, the processing sub-module at the bit level includes: in the embodiments of the present application, based on the user parameter information, the bit-level processing sub-module in the data link module performs bit-level processing on the user code block data to obtain scrambled data under the conditions of the check bit adding unit, the encoding unit, the code block cascading unit, and the data scrambling unit, which may specifically include the following sub-steps:

substep 4201, based on the user parameter information, performing cyclic redundancy check (crc) code addition on the user code block data by a check bit adding unit in the bit level processing sub-module to obtain first code block data, and outputting the first code block data to a coding unit;

substep 4202, encoding, by the encoding unit, the first code block data based on the user parameter information, and performing rate matching on target code block data generated after encoding to obtain second code block data;

substep 4203, restoring, by the code block concatenation unit, the second code block data output by the encoding unit to transport block data based on the user parameter information;

sub-step 4204, performing, by the data scrambling unit, a scrambling operation on the transport block data based on the user parameter information to obtain scrambled data.

Optionally, the symbol level processing sub-module in the embodiment of the present application includes: the device comprises a symbol modulation unit, a power adjustment unit, a layer mapping port mapping unit, a beam forming unit, a compression unit and a mapping address allocation unit. In step 430, based on the user parameter information, in combination with the symbol mapping address, the symbol-level processing sub-module in the data link module performs symbol-level processing on the scrambled data to obtain a mapping address allocation result, which may specifically include the following sub-steps:

substep 4301, modulating the scrambled data based on the user parameter information by the symbol modulation unit to obtain symbol level data corresponding to the scrambled data;

substep 4302, performing power adjustment operation on the symbol level data based on the user parameter information through the symbol modulation unit to obtain symbol data after power adjustment;

substep 4303, performing layer mapping and port mapping processing on the symbol data after power adjustment based on the user parameter information through the layer mapping port mapping unit to obtain mapping data;

substep 4304, performing beamforming processing based on the user parameter information and the mapping data through the beamforming unit to obtain beamforming symbol data;

substep 4305, compressing the beamforming symbol data based on the user parameter information by the compression unit to obtain compressed symbol data;

substep 4306, performing combined allocation on the compressed symbol data based on the user parameter information and combined with the symbol mapping address through the mapping address allocation unit to obtain the mapping address allocation result.

Optionally, the encoding unit in the present application includes: an encoding subunit and a rate matching subunit; the encoding unit may encode the first code block data based on the user parameter information, and perform rate matching on target code block data generated after encoding to obtain second code block data, and the method specifically includes: after the coding subunit receives the first code block data, coding the received first code block data to obtain the target code block data; and performing rate matching on the target code block data through the rate matching subunit to obtain second code block data corresponding to the target code block data.

Optionally, the encoding subunit includes an allocation selector and at least two encoders, and the rate matching subunit includes an output selector and at least two rate matchers; the number of the encoders is the same as the number of the rate matchers. The above receiving, by the encoding subunit, the first code block data, and encoding the received first code block data to obtain the target code block data may specifically include: and sequentially distributing the received first code block data to the idle encoders according to a preset strategy through a distribution selector to obtain target code block data. The at least two encoders are connected with the output end of the distribution selector, and the at least two encoders are used for carrying out parallel encoding processing on the target code block data based on the user parameter information.

Further, in this embodiment of the present application, the input ends of at least two rate matchers are connected to the output ends of the at least two encoders in a one-to-one correspondence; the performing rate matching on the target block data by the rate matching subunit may specifically include: and performing parallel rate matching processing on the coded target code block data through the at least two rate matchers based on the user parameter information. The output selector is connected with the output end of the rate matcher and is used for sequentially transmitting the second code block data subjected to rate matching processing to the bit level processing submodule based on the user parameter information.

Optionally, the bit-level processing sub-module further includes: and the pseudo-random number generating unit is connected with the data scrambling unit. The above-mentioned performing bit-level processing on the user code block data by using a bit-level processing submodule in the data link module to obtain scrambled data, further includes: and outputting a pseudo-random number sequence to the data scrambling unit through the pseudo-random number generating unit so that the data scrambling unit performs bit-level exclusive OR on the transport block data according to the pseudo-random number sequence to complete the scrambling operation. The data scrambling unit is specifically configured to perform bit-level xor on transport block data according to the pseudo-random number sequence to complete the scrambling operation.

It can be seen that, in the channel processing method provided in this embodiment of the application, the channel control module in the channel processing device based on the fpga can output the user parameter information, the user code block data, and the symbol mapping address to the data link module according to the interrupt enable signal, so that the bit-level processing submodule in the data link module can perform bit-level processing on the user code block data based on the user parameter information to obtain scrambled data, and then the symbol-level processing submodule in the data link module performs symbol-level processing on the scrambled data based on the user parameter information and the symbol mapping address to implement symbol-level data operation and obtain a mapping address allocation result, thereby completing data processing of the whole PDSCH channel, so that the resource grid mapping part behind the PDSCH can be directly subjected to mapping processing, and thus the whole designed link has a large throughput, The transmission speed is fast, the maintenance cost is low, and the like, and the requirements of the 5G NR small base station are met.

For example, under the condition that the protocol MAC layer and the above are realized based on the DSP and the ARM, the PCIE interface may acquire pre-parameter information and data provided by the DSP, so as to perform information data processing and carrying of the physical layer based on the acquired pre-value parameter information and data and the channel processing method provided in the embodiment of the present application, thereby developing a channel processing apparatus based on the field programmable logic gate array strictly according to the 3GPP related protocol by using the programmability of the FPGA and the accurate processing capability at the bit level, and ensuring that the channel processing apparatus satisfies the characteristics of the 5G NR, such as high data rate, low cost, low delay, high system capacity, and large-scale equipment.

It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the illustrated order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments of the present invention.

In this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A field programmable gate array based channel processing apparatus, comprising: a channel control module and a data link module,

the output end of the channel control module is connected with the input end of the data link module;

2. The FPGA-based channel processing device as claimed in claim 1, wherein the user parameter information includes user parameters that are output by the channel control module after the read parameter information is sorted and analyzed according to the interrupt enable signal, the user code block data includes code block data generated by the channel control module after the channel control module performs a code block segmentation operation on the read user data, the symbol mapping address includes a symbol mapping address obtained by the channel control module after the channel control module allocates the read resource grid mapping address, and the channel control module includes a bus interface analysis submodule;

the bus interface analysis submodule is used for receiving an effective indication signal and transmission data output by an upper layer module through a bus interface, and storing the transmission data into a corresponding memory based on the effective indication signal, wherein the transmission data comprises the parameter information, the resource grid mapping address and the user data.

3. The FPGA-based channel processing device as claimed in claim 2, wherein the memory comprises a parameter memory, a data memory and an address memory connected to the bus analysis submodule;

the parameter memory is used for storing the parameter information;

the data memory is used for storing the user data;

the address memory is used for storing the resource grid mapping address.

4. The FPGA-based channel processing apparatus of claim 3, wherein the channel control module further comprises: a parameter control submodule, a data control submodule and an address control submodule;

5. The fpga-based channel processing apparatus of claim 1, wherein the channel control module is specifically configured to output user parameter information, user code block data, and symbol mapping addresses to the data link module through three independent links, respectively;

a first output end of the channel control module is connected with a first input end of the bit-level processing submodule and a first input end of the symbol-level processing submodule respectively so as to output the user parameter information to the bit-level processing submodule and the symbol-level processing submodule respectively; a second output end of the channel control module is connected with a second input end of the bit-level processing submodule so as to output the user code block data to the bit-level processing submodule; a third output end of the channel control module is connected with a third input end of the symbol level processing submodule so as to output the symbol mapping address to the symbol level processing submodule;

and the output end of the bit-level processing submodule is connected with the second input end of the symbol-level processing submodule so as to output the scrambled data to the symbol-level processing submodule.

6. The FPGA-based channel processing apparatus of claim 1, wherein the bit-level processing submodule comprises: the device comprises a check bit adding unit, a coding unit, a code block cascading unit and a data scrambling unit;

the code block cascading unit is connected with the output end of the encoding unit and used for restoring second code block data output by the encoding unit into transmission block data based on the user parameter information;

the data scrambling unit is connected with the output end of the code block cascading unit, and the data scrambling unit is used for scrambling the data of the transmission block based on the user parameter information to obtain scrambled data.

7. The FPGA-based channel processing device of claim 1, wherein the symbol-level processing submodule comprises: the device comprises a symbol modulation unit, a power adjustment unit, a layer mapping port mapping unit, a beam forming unit, a compression unit and a mapping address allocation unit;

8. The FPGA-based channel processing apparatus of claim 6, wherein the encoding unit comprises: an encoding subunit and a rate matching subunit;

the input end of the coding subunit is connected with the output end of the check bit adding unit, and the coding subunit is configured to code the first code block data after receiving the first code block data, so as to obtain the target code block data;

the input end of the rate matching subunit is connected with the output end of the coding subunit, and the rate matching subunit is used for performing rate matching on the target code block data to obtain second code block data corresponding to the target code block data.

9. The FPGA-based channel processing apparatus as claimed in claim 8, wherein the coding sub-unit comprises an allocation selector and at least two encoders, and the rate matching sub-unit comprises an output selector and at least two rate matchers; the number of the encoders is the same as that of the rate matchers;

10. The FPGA-based channel processing apparatus of claim 6, wherein the bit-level processing submodule further comprises: the pseudo-random number generating unit is connected with the data scrambling unit;

11. A channel processing method based on field programmable gate array is applied to a channel processing device based on field programmable gate array, the channel processing device comprises a channel control module and a data link module connected with the channel control module, the channel processing method comprises the following steps:

12. The channel processing method according to claim 11, wherein the user parameter information includes user parameters that are output by the channel control module after the read parameter information is sorted and analyzed according to the interrupt enable signal, the user code block data includes code block data generated by the channel control module after performing code block segmentation operation on the read user data, the symbol mapping address includes a symbol mapping address obtained by the channel control module after allocating the read resource grid mapping address, and the channel processing method further includes:

13. The fpga-based channel processing method of claim 12, wherein said outputting user parameter information, user code block data and symbol mapping address to the data link module through the channel control module according to the interrupt enable signal comprises:

receiving the interrupt enable signal through the bus interface;

14. The fpga-based channel processing method of claim 11, wherein said channel control module outputs user parameter information, user code block data, and symbol mapping addresses to said data link module through three independent links, respectively.