CN112912900A - Photoelectric computing system - Google Patents
Photoelectric computing system Download PDFInfo
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- CN112912900A CN112912900A CN202080005363.8A CN202080005363A CN112912900A CN 112912900 A CN112912900 A CN 112912900A CN 202080005363 A CN202080005363 A CN 202080005363A CN 112912900 A CN112912900 A CN 112912900A
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- 230000003287 optical effect Effects 0.000 claims abstract description 2435
- 230000005693 optoelectronics Effects 0.000 claims abstract description 135
- 230000010076 replication Effects 0.000 claims abstract description 61
- 238000009826 distribution Methods 0.000 claims abstract description 58
- 239000004065 semiconductor Substances 0.000 claims abstract description 45
- 239000013598 vector Substances 0.000 description 1355
- 239000011159 matrix material Substances 0.000 description 855
- 238000013528 artificial neural network Methods 0.000 description 749
- 230000000875 corresponding effect Effects 0.000 description 270
- 239000010410 layer Substances 0.000 description 250
- 238000000034 method Methods 0.000 description 234
- 238000012545 processing Methods 0.000 description 230
- 238000006243 chemical reaction Methods 0.000 description 166
- 238000003860 storage Methods 0.000 description 145
- 230000009466 transformation Effects 0.000 description 119
- 238000001514 detection method Methods 0.000 description 112
- 238000004364 calculation method Methods 0.000 description 105
- 238000004260 weight control Methods 0.000 description 100
- 239000000758 substrate Substances 0.000 description 98
- 210000004027 cell Anatomy 0.000 description 91
- 238000004891 communication Methods 0.000 description 84
- 230000006870 function Effects 0.000 description 81
- 238000010586 diagram Methods 0.000 description 74
- 230000008569 process Effects 0.000 description 65
- 239000004020 conductor Substances 0.000 description 42
- 238000012546 transfer Methods 0.000 description 35
- 230000002596 correlated effect Effects 0.000 description 32
- 230000010363 phase shift Effects 0.000 description 30
- 238000013461 design Methods 0.000 description 29
- 239000013307 optical fiber Substances 0.000 description 28
- 230000001427 coherent effect Effects 0.000 description 27
- 238000010521 absorption reaction Methods 0.000 description 26
- 230000002829 reductive effect Effects 0.000 description 25
- 230000008878 coupling Effects 0.000 description 24
- 238000010168 coupling process Methods 0.000 description 24
- 238000005859 coupling reaction Methods 0.000 description 24
- 239000000463 material Substances 0.000 description 22
- 206010028980 Neoplasm Diseases 0.000 description 20
- 239000003990 capacitor Substances 0.000 description 20
- 239000002131 composite material Substances 0.000 description 17
- 201000010099 disease Diseases 0.000 description 17
- 208000037265 diseases, disorders, signs and symptoms Diseases 0.000 description 17
- 201000011510 cancer Diseases 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 230000008901 benefit Effects 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 238000004590 computer program Methods 0.000 description 13
- 230000007246 mechanism Effects 0.000 description 13
- 238000005086 pumping Methods 0.000 description 13
- 238000013500 data storage Methods 0.000 description 12
- 210000001519 tissue Anatomy 0.000 description 12
- 230000005540 biological transmission Effects 0.000 description 11
- 230000008859 change Effects 0.000 description 11
- 230000001902 propagating effect Effects 0.000 description 11
- 108090000623 proteins and genes Proteins 0.000 description 11
- 238000004088 simulation Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 10
- 210000002569 neuron Anatomy 0.000 description 10
- 230000036961 partial effect Effects 0.000 description 10
- 238000012549 training Methods 0.000 description 10
- 238000004422 calculation algorithm Methods 0.000 description 9
- 230000000306 recurrent effect Effects 0.000 description 9
- 241000894006 Bacteria Species 0.000 description 8
- 230000004913 activation Effects 0.000 description 8
- 230000010354 integration Effects 0.000 description 8
- 238000010801 machine learning Methods 0.000 description 8
- 238000012015 optical character recognition Methods 0.000 description 8
- 238000013459 approach Methods 0.000 description 7
- 230000007423 decrease Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 239000000835 fiber Substances 0.000 description 7
- 230000000644 propagated effect Effects 0.000 description 7
- 238000000844 transformation Methods 0.000 description 7
- 238000000354 decomposition reaction Methods 0.000 description 6
- 230000001066 destructive effect Effects 0.000 description 6
- 230000005672 electromagnetic field Effects 0.000 description 6
- 230000014509 gene expression Effects 0.000 description 6
- 238000005457 optimization Methods 0.000 description 6
- 230000009467 reduction Effects 0.000 description 6
- 230000004044 response Effects 0.000 description 6
- 108091028043 Nucleic acid sequence Proteins 0.000 description 5
- 230000001788 irregular Effects 0.000 description 5
- 238000012216 screening Methods 0.000 description 5
- 230000007704 transition Effects 0.000 description 5
- 241001465754 Metazoa Species 0.000 description 4
- 238000013473 artificial intelligence Methods 0.000 description 4
- 230000001276 controlling effect Effects 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 4
- 230000008713 feedback mechanism Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 230000000670 limiting effect Effects 0.000 description 4
- GQYHUHYESMUTHG-UHFFFAOYSA-N lithium niobate Chemical compound [Li+].[O-][Nb](=O)=O GQYHUHYESMUTHG-UHFFFAOYSA-N 0.000 description 4
- 238000013515 script Methods 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 4
- 108010077544 Chromatin Proteins 0.000 description 3
- 208000036758 Postinfectious cerebellitis Diseases 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 108091023040 Transcription factor Proteins 0.000 description 3
- 102000040945 Transcription factor Human genes 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 3
- 230000001580 bacterial effect Effects 0.000 description 3
- 210000003483 chromatin Anatomy 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000005315 distribution function Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003623 enhancer Substances 0.000 description 3
- 238000011478 gradient descent method Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000003909 pattern recognition Methods 0.000 description 3
- 230000010399 physical interaction Effects 0.000 description 3
- 101150086837 pic gene Proteins 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 238000012163 sequencing technique Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000010146 3D printing Methods 0.000 description 2
- 208000031295 Animal disease Diseases 0.000 description 2
- 208000003174 Brain Neoplasms Diseases 0.000 description 2
- 206010006187 Breast cancer Diseases 0.000 description 2
- 208000026310 Breast neoplasm Diseases 0.000 description 2
- 208000024172 Cardiovascular disease Diseases 0.000 description 2
- 229910052691 Erbium Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 229910003327 LiNbO3 Inorganic materials 0.000 description 2
- 206010058467 Lung neoplasm malignant Diseases 0.000 description 2
- 208000018737 Parkinson disease Diseases 0.000 description 2
- 206010060862 Prostate cancer Diseases 0.000 description 2
- 208000000236 Prostatic Neoplasms Diseases 0.000 description 2
- 208000000453 Skin Neoplasms Diseases 0.000 description 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 230000006399 behavior Effects 0.000 description 2
- 210000000038 chest Anatomy 0.000 description 2
- 238000013527 convolutional neural network Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 206010012601 diabetes mellitus Diseases 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- 230000001973 epigenetic effect Effects 0.000 description 2
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 208000035474 group of disease Diseases 0.000 description 2
- 208000019622 heart disease Diseases 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 201000007270 liver cancer Diseases 0.000 description 2
- 208000014018 liver neoplasm Diseases 0.000 description 2
- 201000005202 lung cancer Diseases 0.000 description 2
- 208000020816 lung neoplasm Diseases 0.000 description 2
- 238000013507 mapping Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000001537 neural effect Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000012782 phase change material Substances 0.000 description 2
- 238000004064 recycling Methods 0.000 description 2
- 230000003362 replicative effect Effects 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 208000007056 sickle cell anemia Diseases 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 201000000849 skin cancer Diseases 0.000 description 2
- 208000017520 skin disease Diseases 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 230000004083 survival effect Effects 0.000 description 2
- VCGRFBXVSFAGGA-UHFFFAOYSA-N (1,1-dioxo-1,4-thiazinan-4-yl)-[6-[[3-(4-fluorophenyl)-5-methyl-1,2-oxazol-4-yl]methoxy]pyridin-3-yl]methanone Chemical compound CC=1ON=C(C=2C=CC(F)=CC=2)C=1COC(N=C1)=CC=C1C(=O)N1CCS(=O)(=O)CC1 VCGRFBXVSFAGGA-UHFFFAOYSA-N 0.000 description 1
- DOMQFIFVDIAOOT-ROUUACIJSA-N (2S,3R)-N-[4-(2,6-dimethoxyphenyl)-5-(5-methylpyridin-3-yl)-1,2,4-triazol-3-yl]-3-(5-methylpyrimidin-2-yl)butane-2-sulfonamide Chemical compound COC1=C(C(=CC=C1)OC)N1C(=NN=C1C=1C=NC=C(C=1)C)NS(=O)(=O)[C@@H](C)[C@H](C)C1=NC=C(C=N1)C DOMQFIFVDIAOOT-ROUUACIJSA-N 0.000 description 1
- MAYZWDRUFKUGGP-VIFPVBQESA-N (3s)-1-[5-tert-butyl-3-[(1-methyltetrazol-5-yl)methyl]triazolo[4,5-d]pyrimidin-7-yl]pyrrolidin-3-ol Chemical compound CN1N=NN=C1CN1C2=NC(C(C)(C)C)=NC(N3C[C@@H](O)CC3)=C2N=N1 MAYZWDRUFKUGGP-VIFPVBQESA-N 0.000 description 1
- UKGJZDSUJSPAJL-YPUOHESYSA-N (e)-n-[(1r)-1-[3,5-difluoro-4-(methanesulfonamido)phenyl]ethyl]-3-[2-propyl-6-(trifluoromethyl)pyridin-3-yl]prop-2-enamide Chemical compound CCCC1=NC(C(F)(F)F)=CC=C1\C=C\C(=O)N[C@H](C)C1=CC(F)=C(NS(C)(=O)=O)C(F)=C1 UKGJZDSUJSPAJL-YPUOHESYSA-N 0.000 description 1
- ZGYIXVSQHOKQRZ-COIATFDQSA-N (e)-n-[4-[3-chloro-4-(pyridin-2-ylmethoxy)anilino]-3-cyano-7-[(3s)-oxolan-3-yl]oxyquinolin-6-yl]-4-(dimethylamino)but-2-enamide Chemical compound N#CC1=CN=C2C=C(O[C@@H]3COCC3)C(NC(=O)/C=C/CN(C)C)=CC2=C1NC(C=C1Cl)=CC=C1OCC1=CC=CC=N1 ZGYIXVSQHOKQRZ-COIATFDQSA-N 0.000 description 1
- MOWXJLUYGFNTAL-DEOSSOPVSA-N (s)-[2-chloro-4-fluoro-5-(7-morpholin-4-ylquinazolin-4-yl)phenyl]-(6-methoxypyridazin-3-yl)methanol Chemical compound N1=NC(OC)=CC=C1[C@@H](O)C1=CC(C=2C3=CC=C(C=C3N=CN=2)N2CCOCC2)=C(F)C=C1Cl MOWXJLUYGFNTAL-DEOSSOPVSA-N 0.000 description 1
- APWRZPQBPCAXFP-UHFFFAOYSA-N 1-(1-oxo-2H-isoquinolin-5-yl)-5-(trifluoromethyl)-N-[2-(trifluoromethyl)pyridin-4-yl]pyrazole-4-carboxamide Chemical compound O=C1NC=CC2=C(C=CC=C12)N1N=CC(=C1C(F)(F)F)C(=O)NC1=CC(=NC=C1)C(F)(F)F APWRZPQBPCAXFP-UHFFFAOYSA-N 0.000 description 1
- MJUVRTYWUMPBTR-MRXNPFEDSA-N 1-(2,2-difluoro-1,3-benzodioxol-5-yl)-n-[1-[(2r)-2,3-dihydroxypropyl]-6-fluoro-2-(1-hydroxy-2-methylpropan-2-yl)indol-5-yl]cyclopropane-1-carboxamide Chemical compound FC=1C=C2N(C[C@@H](O)CO)C(C(C)(CO)C)=CC2=CC=1NC(=O)C1(C=2C=C3OC(F)(F)OC3=CC=2)CC1 MJUVRTYWUMPBTR-MRXNPFEDSA-N 0.000 description 1
- ABDDQTDRAHXHOC-QMMMGPOBSA-N 1-[(7s)-5,7-dihydro-4h-thieno[2,3-c]pyran-7-yl]-n-methylmethanamine Chemical compound CNC[C@@H]1OCCC2=C1SC=C2 ABDDQTDRAHXHOC-QMMMGPOBSA-N 0.000 description 1
- HCDMJFOHIXMBOV-UHFFFAOYSA-N 3-(2,6-difluoro-3,5-dimethoxyphenyl)-1-ethyl-8-(morpholin-4-ylmethyl)-4,7-dihydropyrrolo[4,5]pyrido[1,2-d]pyrimidin-2-one Chemical compound C=1C2=C3N(CC)C(=O)N(C=4C(=C(OC)C=C(OC)C=4F)F)CC3=CN=C2NC=1CN1CCOCC1 HCDMJFOHIXMBOV-UHFFFAOYSA-N 0.000 description 1
- BYHQTRFJOGIQAO-GOSISDBHSA-N 3-(4-bromophenyl)-8-[(2R)-2-hydroxypropyl]-1-[(3-methoxyphenyl)methyl]-1,3,8-triazaspiro[4.5]decan-2-one Chemical compound C[C@H](CN1CCC2(CC1)CN(C(=O)N2CC3=CC(=CC=C3)OC)C4=CC=C(C=C4)Br)O BYHQTRFJOGIQAO-GOSISDBHSA-N 0.000 description 1
- YGYGASJNJTYNOL-CQSZACIVSA-N 3-[(4r)-2,2-dimethyl-1,1-dioxothian-4-yl]-5-(4-fluorophenyl)-1h-indole-7-carboxamide Chemical compound C1CS(=O)(=O)C(C)(C)C[C@@H]1C1=CNC2=C(C(N)=O)C=C(C=3C=CC(F)=CC=3)C=C12 YGYGASJNJTYNOL-CQSZACIVSA-N 0.000 description 1
- WNEODWDFDXWOLU-QHCPKHFHSA-N 3-[3-(hydroxymethyl)-4-[1-methyl-5-[[5-[(2s)-2-methyl-4-(oxetan-3-yl)piperazin-1-yl]pyridin-2-yl]amino]-6-oxopyridin-3-yl]pyridin-2-yl]-7,7-dimethyl-1,2,6,8-tetrahydrocyclopenta[3,4]pyrrolo[3,5-b]pyrazin-4-one Chemical compound C([C@@H](N(CC1)C=2C=NC(NC=3C(N(C)C=C(C=3)C=3C(=C(N4C(C5=CC=6CC(C)(C)CC=6N5CC4)=O)N=CC=3)CO)=O)=CC=2)C)N1C1COC1 WNEODWDFDXWOLU-QHCPKHFHSA-N 0.000 description 1
- SRVXSISGYBMIHR-UHFFFAOYSA-N 3-[3-[3-(2-amino-2-oxoethyl)phenyl]-5-chlorophenyl]-3-(5-methyl-1,3-thiazol-2-yl)propanoic acid Chemical compound S1C(C)=CN=C1C(CC(O)=O)C1=CC(Cl)=CC(C=2C=C(CC(N)=O)C=CC=2)=C1 SRVXSISGYBMIHR-UHFFFAOYSA-N 0.000 description 1
- VJPPLCNBDLZIFG-ZDUSSCGKSA-N 4-[(3S)-3-(but-2-ynoylamino)piperidin-1-yl]-5-fluoro-2,3-dimethyl-1H-indole-7-carboxamide Chemical compound C(C#CC)(=O)N[C@@H]1CN(CCC1)C1=C2C(=C(NC2=C(C=C1F)C(=O)N)C)C VJPPLCNBDLZIFG-ZDUSSCGKSA-N 0.000 description 1
- YFCIFWOJYYFDQP-PTWZRHHISA-N 4-[3-amino-6-[(1S,3S,4S)-3-fluoro-4-hydroxycyclohexyl]pyrazin-2-yl]-N-[(1S)-1-(3-bromo-5-fluorophenyl)-2-(methylamino)ethyl]-2-fluorobenzamide Chemical compound CNC[C@@H](NC(=O)c1ccc(cc1F)-c1nc(cnc1N)[C@H]1CC[C@H](O)[C@@H](F)C1)c1cc(F)cc(Br)c1 YFCIFWOJYYFDQP-PTWZRHHISA-N 0.000 description 1
- XYWIPYBIIRTJMM-IBGZPJMESA-N 4-[[(2S)-2-[4-[5-chloro-2-[4-(trifluoromethyl)triazol-1-yl]phenyl]-5-methoxy-2-oxopyridin-1-yl]butanoyl]amino]-2-fluorobenzamide Chemical compound CC[C@H](N1C=C(OC)C(=CC1=O)C1=C(C=CC(Cl)=C1)N1C=C(N=N1)C(F)(F)F)C(=O)NC1=CC(F)=C(C=C1)C(N)=O XYWIPYBIIRTJMM-IBGZPJMESA-N 0.000 description 1
- KVCQTKNUUQOELD-UHFFFAOYSA-N 4-amino-n-[1-(3-chloro-2-fluoroanilino)-6-methylisoquinolin-5-yl]thieno[3,2-d]pyrimidine-7-carboxamide Chemical compound N=1C=CC2=C(NC(=O)C=3C4=NC=NC(N)=C4SC=3)C(C)=CC=C2C=1NC1=CC=CC(Cl)=C1F KVCQTKNUUQOELD-UHFFFAOYSA-N 0.000 description 1
- IRPVABHDSJVBNZ-RTHVDDQRSA-N 5-[1-(cyclopropylmethyl)-5-[(1R,5S)-3-(oxetan-3-yl)-3-azabicyclo[3.1.0]hexan-6-yl]pyrazol-3-yl]-3-(trifluoromethyl)pyridin-2-amine Chemical compound C1=C(C(F)(F)F)C(N)=NC=C1C1=NN(CC2CC2)C(C2[C@@H]3CN(C[C@@H]32)C2COC2)=C1 IRPVABHDSJVBNZ-RTHVDDQRSA-N 0.000 description 1
- KCBWAFJCKVKYHO-UHFFFAOYSA-N 6-(4-cyclopropyl-6-methoxypyrimidin-5-yl)-1-[[4-[1-propan-2-yl-4-(trifluoromethyl)imidazol-2-yl]phenyl]methyl]pyrazolo[3,4-d]pyrimidine Chemical compound C1(CC1)C1=NC=NC(=C1C1=NC=C2C(=N1)N(N=C2)CC1=CC=C(C=C1)C=1N(C=C(N=1)C(F)(F)F)C(C)C)OC KCBWAFJCKVKYHO-UHFFFAOYSA-N 0.000 description 1
- UNQYAAAWKOOBFQ-UHFFFAOYSA-N 7-[(4-chlorophenyl)methyl]-8-[4-chloro-3-(trifluoromethoxy)phenoxy]-1-(3-hydroxypropyl)-3-methylpurine-2,6-dione Chemical compound C=1C=C(Cl)C=CC=1CN1C=2C(=O)N(CCCO)C(=O)N(C)C=2N=C1OC1=CC=C(Cl)C(OC(F)(F)F)=C1 UNQYAAAWKOOBFQ-UHFFFAOYSA-N 0.000 description 1
- CYJRNFFLTBEQSQ-UHFFFAOYSA-N 8-(3-methyl-1-benzothiophen-5-yl)-N-(4-methylsulfonylpyridin-3-yl)quinoxalin-6-amine Chemical compound CS(=O)(=O)C1=C(C=NC=C1)NC=1C=C2N=CC=NC2=C(C=1)C=1C=CC2=C(C(=CS2)C)C=1 CYJRNFFLTBEQSQ-UHFFFAOYSA-N 0.000 description 1
- ZRPZPNYZFSJUPA-UHFFFAOYSA-N ARS-1620 Chemical compound Oc1cccc(F)c1-c1c(Cl)cc2c(ncnc2c1F)N1CCN(CC1)C(=O)C=C ZRPZPNYZFSJUPA-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GISRWBROCYNDME-PELMWDNLSA-N F[C@H]1[C@H]([C@H](NC1=O)COC1=NC=CC2=CC(=C(C=C12)OC)C(=O)N)C Chemical compound F[C@H]1[C@H]([C@H](NC1=O)COC1=NC=CC2=CC(=C(C=C12)OC)C(=O)N)C GISRWBROCYNDME-PELMWDNLSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- AYCPARAPKDAOEN-LJQANCHMSA-N N-[(1S)-2-(dimethylamino)-1-phenylethyl]-6,6-dimethyl-3-[(2-methyl-4-thieno[3,2-d]pyrimidinyl)amino]-1,4-dihydropyrrolo[3,4-c]pyrazole-5-carboxamide Chemical compound C1([C@H](NC(=O)N2C(C=3NN=C(NC=4C=5SC=CC=5N=C(C)N=4)C=3C2)(C)C)CN(C)C)=CC=CC=C1 AYCPARAPKDAOEN-LJQANCHMSA-N 0.000 description 1
- FEYNFHSRETUBEM-UHFFFAOYSA-N N-[3-(1,1-difluoroethyl)phenyl]-1-(4-methoxyphenyl)-3-methyl-5-oxo-4H-pyrazole-4-carboxamide Chemical compound COc1ccc(cc1)N1N=C(C)C(C(=O)Nc2cccc(c2)C(C)(F)F)C1=O FEYNFHSRETUBEM-UHFFFAOYSA-N 0.000 description 1
- IDRGFNPZDVBSSE-UHFFFAOYSA-N OCCN1CCN(CC1)c1ccc(Nc2ncc3cccc(-c4cccc(NC(=O)C=C)c4)c3n2)c(F)c1F Chemical compound OCCN1CCN(CC1)c1ccc(Nc2ncc3cccc(-c4cccc(NC(=O)C=C)c4)c3n2)c(F)c1F IDRGFNPZDVBSSE-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LXRZVMYMQHNYJB-UNXOBOICSA-N [(1R,2S,4R)-4-[[5-[4-[(1R)-7-chloro-1,2,3,4-tetrahydroisoquinolin-1-yl]-5-methylthiophene-2-carbonyl]pyrimidin-4-yl]amino]-2-hydroxycyclopentyl]methyl sulfamate Chemical compound CC1=C(C=C(S1)C(=O)C1=C(N[C@H]2C[C@H](O)[C@@H](COS(N)(=O)=O)C2)N=CN=C1)[C@@H]1NCCC2=C1C=C(Cl)C=C2 LXRZVMYMQHNYJB-UNXOBOICSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000006096 absorbing agent Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 230000003925 brain function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- DGLFSNZWRYADFC-UHFFFAOYSA-N chembl2334586 Chemical compound C1CCC2=CN=C(N)N=C2C2=C1NC1=CC=C(C#CC(C)(O)C)C=C12 DGLFSNZWRYADFC-UHFFFAOYSA-N 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002068 genetic effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000005065 mining Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000008450 motivation Effects 0.000 description 1
- FMASTMURQSHELY-UHFFFAOYSA-N n-(4-fluoro-2-methylphenyl)-3-methyl-n-[(2-methyl-1h-indol-4-yl)methyl]pyridine-4-carboxamide Chemical compound C1=CC=C2NC(C)=CC2=C1CN(C=1C(=CC(F)=CC=1)C)C(=O)C1=CC=NC=C1C FMASTMURQSHELY-UHFFFAOYSA-N 0.000 description 1
- NNKPHNTWNILINE-UHFFFAOYSA-N n-cyclopropyl-3-fluoro-4-methyl-5-[3-[[1-[2-[2-(methylamino)ethoxy]phenyl]cyclopropyl]amino]-2-oxopyrazin-1-yl]benzamide Chemical compound CNCCOC1=CC=CC=C1C1(NC=2C(N(C=3C(=C(F)C=C(C=3)C(=O)NC3CC3)C)C=CN=2)=O)CC1 NNKPHNTWNILINE-UHFFFAOYSA-N 0.000 description 1
- 238000003058 natural language processing Methods 0.000 description 1
- 238000003062 neural network model Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- LZMJNVRJMFMYQS-UHFFFAOYSA-N poseltinib Chemical compound C1CN(C)CCN1C(C=C1)=CC=C1NC1=NC(OC=2C=C(NC(=O)C=C)C=CC=2)=C(OC=C2)C2=N1 LZMJNVRJMFMYQS-UHFFFAOYSA-N 0.000 description 1
- 238000003908 quality control method Methods 0.000 description 1
- 230000008672 reprogramming Effects 0.000 description 1
- XIIOFHFUYBLOLW-UHFFFAOYSA-N selpercatinib Chemical compound OC(COC=1C=C(C=2N(C=1)N=CC=2C#N)C=1C=NC(=CC=1)N1CC2N(C(C1)C2)CC=1C=NC(=CC=1)OC)(C)C XIIOFHFUYBLOLW-UHFFFAOYSA-N 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- XGVXKJKTISMIOW-ZDUSSCGKSA-N simurosertib Chemical compound N1N=CC(C=2SC=3C(=O)NC(=NC=3C=2)[C@H]2N3CCC(CC3)C2)=C1C XGVXKJKTISMIOW-ZDUSSCGKSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- XOOUIPVCVHRTMJ-UHFFFAOYSA-L zinc stearate Chemical compound [Zn+2].CCCCCCCCCCCCCCCCCC([O-])=O.CCCCCCCCCCCCCCCCCC([O-])=O XOOUIPVCVHRTMJ-UHFFFAOYSA-L 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/067—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using optical means
- G06N3/0675—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using optical means using electro-optical, acousto-optical or opto-electronic means
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/21—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour by interference
- G02F1/225—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
Abstract
An optoelectronic computing system, comprising: a first semiconductor die having a Photonic Integrated Circuit (PIC) and a second semiconductor die having an Electronic Integrated Circuit (EIC). A PIC includes an optical waveguide where input values are encoded on respective optical signals carried by the optical waveguide. The PIC includes an optical replication distribution network with optical splitters. The PIC includes an array of optoelectronic circuit portions, each receiving an optical wave from one of the output ports of the optical replica distribution network, and each including: at least one photodetector that detects at least one light wave from the photo-electric operation. The EIC includes electrical input ports that receive respective electrical values. The first semiconductor die is electrically coupled with the second semiconductor die in a controlled collapse chip connection, wherein an electrical output port of the PIC is connected to one of the electrical input ports of the EIC.
Description
Cross Reference to Related Applications
This application claims priority from U.S. provisional application 62/820,562 filed on 3/19/2019 and U.S. patent application 16/703,278 filed on 12/4/2019. The entire disclosure of the above application is incorporated herein by reference.
Technical Field
The present disclosure relates to an optoelectronic computing system.
Background
Neuromorphic computing (neuromorphic computing) is a method of approximating the operation of the brain in the field of electronics. One prominent method of neuromorphic computation is the Artificial Neural Network (ANN), which is a collection of artificial neurons interconnected in a specific manner to process information in a manner similar to brain function. ANN has found use in a variety of applications including artificial intelligence, speech recognition, text recognition, natural language processing, and various forms of pattern recognition.
The ANN has an input layer, one or more hidden layers, and an output layer. Each layer has nodes or artificial neurons, and the nodes are interconnected between layers. Each node of the hidden layer performs a weighted sum of the signals received from nodes of the previous layer and performs a nonlinear transformation ("activation") of the weighted sum to produce an output. The weighted sum may be calculated by performing a matrix multiplication step. Therefore, computing an ANN typically involves multiple matrix multiplication steps, which are typically performed using electronic integrated circuits.
Computations performed on electronic data encoded in analog or digital form on an electronic signal (e.g., voltage or current) are typically implemented using electronic computing hardware, such as analog or digital electronics implemented in an integrated circuit (e.g., a processor, an application-specific integrated circuit (ASIC), or a system on a chip (SoC)), an electronic circuit board, or other electronic circuitry. Optical signals have been used to transmit data over long and short distances (e.g., within data centers). The operations performed on such optical signals are typically performed in the context of optical data transmission, such as within a device used to switch or filter the optical signals in a network. The use of optical signals in computing platforms has been more limited. Various components and systems for all-optical (all-optical) computing have been proposed. Such a system may include conversion from and to electrical signals at the input and output, respectively, but neither type (electrical or optical) of signal may be used for the important operations performed in the computation.
Disclosure of Invention
In general, in a first aspect, an optoelectronic computing system includes: a first semiconductor die comprising a Photonic Integrated Circuit (PIC), the PIC comprising: a plurality of optical waveguides, wherein a set of a plurality of input values are encoded on respective optical signals carried by the optical waveguides; an optical replica distribution network comprising a plurality of optical splitters, wherein each optical splitter transmits half of the power of an input optical wave at an input port to each of two output ports; and an array of optoelectronic circuit portions, each optoelectronic circuit portion receiving an optical wave from one of the output ports of the optical replica distribution network, and each optoelectronic circuit portion comprising: at least one photodetector that detects at least one light wave from the photo-electric operation; and at least one conductive line integrated in the PIC, the conductive line electrically coupled to the photodetector and electrically coupled to an electrical output port; and a second semiconductor die comprising an Electronic Integrated Circuit (EIC), the EIC comprising: a plurality of electrical input ports that receive respective electrical values; wherein the first semiconductor die and the second semiconductor die are electrically coupled in a controlled collapse chip connection, wherein the electrical output port of the PIC is connected to one of the electrical input ports of the EIC.
Embodiments of the system may include one or more of the following features.
Each of the photoelectric circuit portions includes: an opto-electronic operational module that performs operations between (1) an optical value based on one of the input values scaled by the optical replication distribution network and (2) an electrical value provided by an electrical input port; at least one photodetector that detects at least one light wave from the photovoltaic operation; and at least one conductive line integrated in the PIC, the conductive line electrically coupled to the photodetector and electrically coupled to an electrical output port.
The EIC further comprises a plurality of digital-to-analog converters (DACs) that provide electrical values to respective electrical output ports, and the electrical input port of the PIC is connected to the electrical output port of the EIC.
The optical splitters are arranged as nodes in a binary tree arrangement connected by optical waveguides as links in the binary tree arrangement.
The optical replication distribution network includes a plurality of binary tree arrangements, each binary tree arrangement distributing a different one of the plurality of input values encoded on a respective optical signal.
The light propagation lengths between the root of the binary tree arrangement and the different optoelectronic circuit parts are all different from each other.
The optical waveguides in the optical replicated distribution network are arranged in the first semiconductor die to avoid crossing any optical waveguides in the optical replicated distribution network.
The optoelectronic circuit portion is arranged in a plurality of substantially straight lines on the first semiconductor die.
The plurality of lines are optically coupled to each other by one or more optical waveguides in the optical replication distribution network.
A portion of the conductive lines integrated in the PIC connect the photodetector to a junction between conductive lines from different optoelectronic circuit portions.
The opto-electronic operational module includes a mach-zehnder interferometer configured to perform a multiplication operation between (1) an optical value based on one of the input values scaled by the optical replica distribution network and (2) an electrical value provided by an electrical input port.
The EIC further comprises a transimpedance amplifier having an input electrically coupled to an electrical output port of the PIC.
In another aspect, a system comprises: a first unit configured to generate a plurality of modulator control signals; and a processing unit. The processing unit includes: a light source or port configured to provide a plurality of light outputs; and a first set of optical modulators coupled to the light source or port and the first cell. The optical modulators of the first set of optical modulators are configured to modulate a plurality of optical outputs provided by the optical source or port based on digital input values corresponding to a first set of modulator control signals of a plurality of modulator control signals to produce an optical input vector, the optical input vector comprising a plurality of optical signals. The processing unit further comprises a matrix multiplication unit comprising a second set of light modulators. The matrix multiplication unit is coupled to the first unit and configured to convert the optical input vector to an analog output vector based on a plurality of digital weight values corresponding to a second set of modulator control signals of a plurality of modulator control signals applied to a second set of light modulators. At least one optical modulator of at least one of the first set of optical modulators or the second set of optical modulators is configured to modulate an optical signal based on a first modulator control signal of the plurality of modulator control signals, and the first unit is configured to shape the first modulator control signal to include a bandwidth enhancement associated with an amplitude variation associated with a corresponding variation of a continuous digital value corresponding to the first modulator control signal.
Embodiments of the system may include one or more of the following features. The system may include a second unit coupled to the matrix multiplication unit and configured to convert the analog output vector to a digital output vector; and a controller. The controller may include an integrated circuit configured to perform operations including: receiving an artificial neural network computation request, the artificial neural network computation request comprising an input data set, the input data set comprising a first numeric input vector; receiving a first plurality of neural network weights; and generating, by the first unit, a first plurality of modulator control signals based on the first digital input vector and a first plurality of weight control signals based on the first plurality of neural network weights.
The first unit may include a digital to analog converter (DAC).
The system may include a storage unit configured to store the data set and the plurality of neural network weights.
The integrated circuit of the controller may be further configured to perform operations including storing the input data set and the first plurality of neural network weights in a memory unit.
The controller may include an Application Specific Integrated Circuit (ASIC), and receiving the artificial neural network computation request may include receiving the artificial neural network computation request from a general-purpose data processor.
The first unit, the processing unit, the second unit, and the controller may be disposed on at least one of a multi-chip module or an integrated circuit. Receiving the artificial neural network computation request may include receiving the artificial neural network computation request from a second data processor, wherein the second data processor is external to the multi-chip module or integrated circuit, the second data processor is coupled to the multi-chip module or integrated circuit through a communication channel, and the processing unit may process data at a data rate that is at least an order of magnitude greater than a data rate of the communication channel.
The first unit, the processing unit, the second unit and the controller may be used for a photoelectric processing cycle that is repeated in a plurality of iterations. The photoelectric treatment cycle comprises: (1) at least a first light modulation operation based on at least one of the modulator control signals, and at least a second light modulation operation based on at least one of the weight control signals, and (2) at least one of (a) an electrical summing operation or (b) an electrical storage operation.
The photo-electric processing cycle may include an electrical storage operation, and the electrical storage operation is performed using a memory unit coupled to the controller. The operations performed by the controller may also include storing the input data set and the first plurality of neural network weights in a memory unit.
The electro-optical processing cycle may include an electrical summing operation, and the electrical summing operation may be performed using an electrical summing module within the matrix multiplication unit. The electrical summation module may be configured to generate currents corresponding to elements of the analog output vector, the currents representing a sum of respective elements of the optical input vector multiplied by respective neural network weights.
The first modulator control signal may comprise an analog signal associated with a plurality of predetermined amplitude levels, and each of the amplitude levels is associated with a different corresponding digital value.
The first modulator control signal may comprise an analog signal associated with two predetermined amplitude levels, and each of the amplitude levels is associated with a different corresponding binary value.
The successive digital values may comprise a plurality of successive binary values in a series of binary values.
The controller may be configured to shape the first modulator control signal to include a bandwidth enhancement for an initial portion of the second time interval by increasing a magnitude of an amplitude variation between a first predetermined amplitude level associated with the first time interval and a second predetermined amplitude level associated with the second time interval.
A series of binary values may be used to determine an amplitude level of a first modulator control signal used to modulate an optical signal according to a non-return-to-zero (NRZ) modulation mode.
The first unit may be configured to shape the first modulator control signal to include bandwidth enhancement by pumping (pumping) a current between a diode structure of a first modulator of the second set of light modulators and a capacitance connected in series between the diode structure and a circuit providing the first modulator control signal, and an amount of charge delivered by the pumping current may be determined based at least in part on a constant voltage over a time period providing successive digital values.
In another general aspect, an apparatus includes: a plurality of optical waveguides coupled to the first set of optical amplitude modulators, wherein a set of the plurality of input values is encoded on respective optical signals carried by the optical waveguides using the first set of optical amplitude modulators. The apparatus includes a plurality of replica modules, and for each of at least two subsets of the one or more optical signals, a corresponding set of one or more replica modules is configured to split the subset of the one or more optical signals into two or more replicas of the optical signal. The apparatus comprises a plurality of multiplication modules, each of the multiplication modules comprising an optical amplitude modulator of the second set of optical amplitude modulators, and for each of the at least two copies of the first subset of the one or more optical signals, the multiplication module of a corresponding one is configured to multiply the one or more optical signals of the first subset by one or more matrix element values using the optical amplitude modulator of the second set of optical amplitude modulators. The apparatus comprises one or more summing modules, and for the results of two or more multiplication modules, a corresponding one of the summing modules is configured to produce an electrical signal representing the sum of the results of the two or more multiplication modules. At least one optical amplitude modulator of at least one of the first set of optical amplitude modulators or the second set of optical amplitude modulators is configured to modulate an optical signal with a modulation value using a power that monotonically increases (monotonically increase) with respect to an absolute value of the modulation value.
Embodiments of the device may include one or more of the following features. The at least one optical amplitude modulator of at least one of the first set of optical amplitude modulators or the second set of optical amplitude modulators may comprise a coherence sensitive optical amplitude modulator configured to modulate an optical signal by a modulation value based on interference between optical waves, the optical waves having a coherence length that is at least as long as a propagation distance through the coherence sensitive optical amplitude modulator.
The coherent-sensitive optical amplitude modulator may include a Mach-Zehnder Interferometer (MZI) that distributes the optical wave guided by the input optical waveguide to a first optical waveguide arm of the Mach-Zehnder Interferometer and a second optical waveguide arm of the Mach-Zehnder Interferometer. The first optical waveguide arm may include an active phase shifter that produces a relative phase shift with respect to a phase delay of the second optical waveguide arm, and the mach-zehnder interferometer may combine the optical waves from the first and second optical waveguide arms into the at least one output optical waveguide.
The power used to modulate the optical signal by the modulation value may include power applied to the active phase shifter.
An input value of a set of multiple input values encoded on a respective optical signal may represent an element of an input vector multiplied by a matrix comprising one or more matrix element values.
A set of multiple output values may be encoded on the multiple respective electrical signals generated by the one or more summation modules, and an output value of the set of multiple output values may represent an element of an output vector generated by multiplying an input vector by a matrix.
Each of the optical signals carried by the optical waveguides may include optical waves having a common wavelength that is substantially the same for all of the optical signals.
The replica module can include at least one replica module having an optical splitter that transmits a predetermined proportion of the power of the optical wave at the input port of the replica module to a first output port of the replica module and transmits the remaining proportion of the power of the optical wave at the input port of the replica module to a second output port of the replica module.
The optical splitter may include a waveguide splitter that transmits a predetermined proportion of the power of the light wave guided by the input optical waveguide of the replica module to a first output optical waveguide of the replica module and transmits the remaining proportion of the power of the light wave guided by the input optical waveguide of the replica module to a second output optical waveguide of the replica module.
The guided modes of the input optical waveguide may be adiabatically coupled to a plurality of guided modes of each of the first and second output optical waveguides.
The optical splitter may include a beam splitter including at least one surface that transmits a predetermined proportion of the power of the optical wave at the input port and reflects a remaining proportion of the power of the optical wave at the input port.
At least one of the plurality of optical waveguides may include an optical fiber coupled to an optical coupler, the optical coupler coupling a guided mode of the optical fiber to a free-space propagation mode.
The multiplication module may include at least one coherence sensitive optical amplitude modulator configured to multiply the first subset of one or more optical signals by one or more matrix element values based on interference between optical waves having a coherence length at least as long as a propagation distance through the coherence sensitive optical amplitude modulator.
The coherence sensitive optical amplitude modulator may include a mach-zehnder interferometer (MZI) that distributes the optical wave guided by the input optical waveguide to a first optical waveguide arm of the mach-zehnder interferometer and a second optical waveguide arm of the mach-zehnder interferometer. The first optical waveguide arm may include a phase shifter that produces a relative phase shift with respect to a phase delay of the second optical waveguide arm, and the mach-zehnder interferometer may combine the plurality of optical waves from the first optical waveguide arm and the second optical waveguide arm into the at least one output optical waveguide.
The mach-zehnder interferometer may combine the lightwaves from the first and second optical waveguide arms into each of the first and second output optical waveguides. The first photo-detector may receive the light wave from the first output optical waveguide to generate a first photocurrent, the second photo-detector may receive the light wave from the second output optical waveguide to generate a second photocurrent, and the result of the coherence sensitive optical amplitude modulator may include a difference between the first photocurrent and the second photocurrent.
The coherent-sensitive optical amplitude modulator may include one or more ring resonators including at least one ring resonator coupled to the first optical waveguide and at least one ring resonator coupled to the second optical waveguide.
The first photo-detector may receive light waves from the first optical waveguide to generate a first photocurrent, the second photo-detector may receive light waves from the second optical waveguide to generate a second photocurrent, and the result of the coherently sensitive optical amplitude modulator may include a difference between the first photocurrent and the second photocurrent.
The multiplication module may include at least one coherent insensitive optical amplitude modulator configured to multiply the first subset of one or more optical signals by one or more matrix element values based on energy absorption within the optical waves.
The coherent non-sensitive optical amplitude modulator may comprise an electro-absorption modulator.
The one or more summing modules may include at least one summing module having: (1) two or more input conductors, each of the input conductors carrying an electrical signal in the form of an input current, the magnitude of the input current representing a respective result of a respective one of the multiplication modules, and (2) at least one output conductor carrying an electrical signal in the form of an output current representing a sum of the respective results, the output current being proportional to the sum of the input currents.
The two or more input and output conductors may include wires that contact at one or more junctions between the wires, and the output current may be substantially equal to the sum of the input currents.
At least a first one of the input currents may be provided in the form of at least one photocurrent generated by at least one photo-detector receiving an optical signal generated by a first one of the multiplication modules.
The first input current may be provided as a difference between two photocurrents produced by different respective photodetectors that receive different respective optical signals produced by the first multiplication module.
One of the copies of the first subset of one or more optical signals may consist of a single optical signal on which one of the input values is encoded.
A multiplication module corresponding to a copy of the first subset may multiply the encoded input value by a single matrix element value.
One of the copies of the first subset of one or more optical signals on which the plurality of input values are encoded may include more than one, and less than all, of the optical signals.
A multiplication module corresponding to a copy of the first subset may multiply the encoded input values by different respective matrix element values.
Different multiplication modules corresponding to different respective copies of the first subset of one or more optical signals may be included by different devices in optical communication to transmit one of the copies of the first subset of one or more optical signals between the different devices.
Two or more of the plurality of optical waveguides, two or more of the plurality of replica modules, two or more of the plurality of multiplication modules, and at least one of the one or more summation modules may be disposed on a substrate of a common device.
The apparatus may perform vector matrix multiplication, wherein an input vector may be provided as a set of optical signals and an output vector may be provided as a set of electrical signals.
The apparatus may further include an accumulator that integrates the input electrical signal corresponding to the output of the multiplication module or the summation module, wherein the input electrical signal is encoded using time-domain coding using switching amplitude modulation within each of the plurality of time slots, and the accumulator generates the output electrical signal, the output electrical signal being encoded at more than two amplitude levels, the amplitude levels corresponding to different duty cycles of the time-domain coding over the plurality of time slots.
Each of the two or more multiplication modules may correspond to a different subset of the one or more optical signals.
The apparatus may further comprise: a multiplication module for each replica of a second subset of the one or more optical signals different from the optical signals in the first subset of the one or more optical signals, configured to multiply the one or more optical signals of the second subset by one or more matrix element values using optical amplitude modulation.
In another general aspect, a method includes: encoding a set of multiple input values on a respective optical signal using a first set of optical amplitude modulators; for each of at least two subsets of one or more optical signals, using a corresponding set of one or more replica modules to split the subset of one or more optical signals into two or more replicas of the optical signal; for each of the at least two copies of the first subset of one or more optical signals, multiplying the one or more optical signals of the first subset by one or more matrix element values using an optical amplitude modulator of the second set of optical amplitude modulators using a corresponding multiplication module; and for the results of the two or more multiplication modules, using a summation module configured to produce an electrical signal representing a sum of the results of the two or more multiplication modules. At least one optical amplitude modulator of at least one of the first set of optical amplitude modulators or the second set of optical amplitude modulators is configured to modulate an optical signal with a modulation value using a power that monotonically increases with respect to an absolute value of the modulation value.
In another general aspect, a system includes: a storage unit configured to store the data set and a plurality of neural network weights; a digital-to-analog conversion (DAC) unit configured to generate a plurality of modulator control signals and to generate a plurality of weight control signals; a light processor comprising a laser unit configured to generate a plurality of light outputs; a plurality of optical modulators coupled to the laser unit and the DAC unit, the plurality of optical modulators configured to generate an optical input vector by modulating a plurality of optical outputs generated by the laser unit based on a plurality of modulator control signals; a light matrix multiplication unit coupled to the plurality of light modulators and the DAC unit, the light matrix multiplication unit configured to convert a light input vector into a light output vector based on a plurality of weight control signals; and a photo detection unit coupled to the light matrix multiplication unit and configured to generate a plurality of output voltages corresponding to the light output vectors; an analog-to-digital conversion (ADC) unit coupled to the photodetection unit and configured to convert the plurality of output voltages into a plurality of digital light outputs; a controller comprising an integrated circuit configured to perform the following operations: receiving, from a computer, an artificial neural network computation request comprising an input data set and a first plurality of neural network weights, wherein the input data set comprises a first digital input vector; storing the input data set and the first plurality of neural network weights in a memory unit; and generating, by the DAC unit, a first plurality of modulator control signals based on the first digital input vector and a first plurality of weight control signals based on the first plurality of neural network weights.
Embodiments of the system may include one or more of the following features. For example, the operations may further include: obtaining a first plurality of digital light outputs from the ADC unit corresponding to the light output vectors of the light matrix multiplication unit, the first plurality of digital light outputs forming a first digital output vector; performing a non-linear transformation on the first digital output vector to produce a first transformed digital output vector; and storing the first transformed digital output vector in a memory unit.
The system may have a first cycle period defined as the time elapsed between the step of storing the input data set and the first plurality of neural network weights in the memory unit and the step of storing the first transformed digital output vector in the memory unit. The first cycle period may be less than or equal to 1 ns.
In some embodiments, the operations may further comprise: an artificial neural network output generated based on the first transformed digital output vector is output.
In some embodiments, the operations may further comprise: a second plurality of modulator control signals is generated by the DAC unit based on the first converted digital output vector.
In some embodiments, the artificial neural network computation request may further include a second plurality of neural network weights, and the operations may further include: based on the obtaining of the first plurality of digital light outputs, a second plurality of weight control signals is generated by the DAC unit based on the second plurality of neural network weights. The first plurality of neural network weights and the second plurality of neural network weights may correspond to different layers of the artificial neural network.
In some embodiments, the input data set may further include a second digital input vector, and the operations may further include: generating, by the DAC unit, a second plurality of modulator control signals based on a second digital input vector; obtaining a second plurality of digital light outputs from the ADC unit corresponding to the light output vectors of the light matrix multiplication unit, the second plurality of digital light outputs forming a second digital output vector; performing a non-linear transformation on the second digital output vector to produce a second transformed digital output vector; storing the second transformed digital output vector in a storage unit; and outputting an artificial neural network output generated based on the first transformed digital output vector and the second transformed digital output vector. The light output vector of the light matrix multiplication unit is generated by a second light input vector generated based on a second plurality of modulator control signals, the second light input vector being transformed by the light matrix multiplication unit based on the first-mentioned plurality of weight control signals.
In some embodiments, the system may further comprise: an analog nonlinear unit disposed between the photo detection unit and the ADC unit, the analog nonlinear unit configured to receive a plurality of output voltages from the photo detection unit, apply a nonlinear transfer function, and output a plurality of converted output voltages to the ADC unit, and the operations further comprising: obtaining a first plurality of converted digital output voltages corresponding to the plurality of converted output voltages from the ADC unit, the first plurality of converted digital output voltages forming a first converted digital output vector; and storing the first transformed digital output vector in a memory unit.
In some embodiments, the integrated circuit of the controller may be configured to generate the first plurality of modulator control signals at a rate greater than or equal to 8 GHz.
In some embodiments, the system may further comprise: an analog storage unit disposed between the DAC unit and the plurality of light modulators, the analog storage unit configured to store an analog voltage and output the stored analog voltage; and an analog nonlinear unit disposed between the photodetection unit and the ADC unit, the analog nonlinear unit configured to receive a plurality of output voltages from the photodetection unit, apply a nonlinear transfer function, and output a plurality of converted output voltages. The analog memory cell may include a plurality of capacitors.
In some embodiments, the analog memory cell may be configured to receive and store a plurality of converted output voltages of the analog nonlinear cell and output the stored plurality of converted output voltages to the plurality of optical modulators, and the operations may further include: storing a plurality of converted output voltages of an analog non-linear unit in an analog storage unit based on generating a first plurality of modulator control signals and a first plurality of weight control signals; outputting the stored converted output voltage through the analog memory cell; obtaining a second plurality of converted digital output voltages from the ADC unit, the second plurality of converted digital output voltages forming a second converted digital output vector; and storing the second transformed digital output vector in the memory unit.
In some embodiments, the input data set of the artificial neural network computation request may include a plurality of numerical input vectors. The laser unit may be configured to generate a plurality of wavelengths. The plurality of light modulators may include: a bank of optical modulators (bank) configured to generate a plurality of optical input vectors, each optical modulator bank corresponding to one of a plurality of wavelengths and generating a respective optical input vector having a respective wavelength; and an optical multiplexer configured to combine the plurality of optical input vectors into a combined optical input vector comprising a plurality of wavelengths. The photodetection unit may be further configured to demultiplex the plurality of wavelengths and generate a plurality of demultiplexed output voltages. The operations may include: obtaining a plurality of digital demultiplexed optical outputs from the ADC unit, the plurality of digital demultiplexed optical outputs forming a plurality of first digital output vectors, wherein each of the plurality of first digital output vectors corresponds to one of the plurality of wavelengths; performing a non-linear transformation on each of the plurality of first digital output vectors to produce a plurality of transformed first digital output vectors; and storing the plurality of transformed first digital output vectors in a memory unit. Each of the plurality of digital input vectors may correspond to one of the plurality of light input vectors.
In some embodiments, the artificial neural network computation request may include a plurality of numerical input vectors. The laser unit may be configured to generate a plurality of wavelengths. The plurality of light modulators may include: an optical modulator group configured to generate a plurality of optical input vectors, each optical modulator group corresponding to one of a plurality of wavelengths and generating a respective optical input vector having a respective wavelength; and an optical multiplexer configured to combine the plurality of optical input vectors into a combined optical input vector comprising a plurality of wavelengths. The operations may include: obtaining a first plurality of digital light outputs from the ADC unit corresponding to a light output vector, the light output vector comprising a plurality of wavelengths, the first plurality of digital light outputs forming a first digital output vector; performing a non-linear transformation on the first digital output vector to produce a first transformed digital output vector; and storing the first transformed digital output vector in a memory unit.
In some embodiments, the DAC cell may include: a 1-bit DAC subunit configured to generate a plurality of 1-bit modulator control signals. The resolution of the ADC unit may be 1 bit. The resolution of the first digital input vector may be N bits. The operations may include: decomposing the first digital input vector into N1-bit input vectors, each of the N1-bit input vectors corresponding to one of the N bits of the first digital input vector; generating, by a 1-bit DAC subunit, a sequence of N1-bit modulator control signals corresponding to N1-bit input vectors; obtaining from the ADC unit a sequence of N digital 1-bit optical outputs corresponding to a sequence of N1-bit modulator control signals; constructing an N-bit digital output vector from a sequence of N digital 1-bit optical outputs; performing a non-linear transformation on the constructed N-bit digital output vector to produce a transformed N-bit digital output vector; and storing the transformed N-bit digital output vector in a memory unit.
In some embodiments, the memory unit may include: a digital input vector memory configured to store a first digital input vector and comprising at least one SRAM; and a neural network weight memory configured to store a plurality of neural network weights and including at least one DRAM.
In some embodiments, the DAC cell may include: a first DAC subunit configured to generate a plurality of modulator control signals; and a second DAC subunit configured to generate a plurality of weight control signals, wherein the first DAC subunit and the second DAC subunit are different.
In some embodiments, the laser unit may include: a laser source configured to generate light; and an optical power splitter configured to split light generated by the laser source into a plurality of optical outputs, wherein each of the plurality of optical outputs has substantially the same power.
In some embodiments, the plurality of optical modulators may include one of an MZI modulator, a ring resonator modulator, or an electro-absorption modulator.
In some embodiments, the photodetecting unit may include: a plurality of photodetectors; and a plurality of amplifiers configured to convert the photocurrent generated by the photodetector into a plurality of output voltages.
In some embodiments, the integrated circuit may be an application specific integrated circuit.
In some embodiments, the optical matrix multiplication unit may include: an input waveguide array for receiving an optical input vector; an optical interference unit in optical communication with the input waveguide array for performing a linear transformation of the optical input vector into a second optical signal array; and an array of output waveguides in optical communication with the optical interference unit for guiding the second array of optical signals, wherein at least one input waveguide in the array of input waveguides is in optical communication with each output waveguide in the array of output waveguides through the optical interference unit.
In some embodiments, the optical interference unit may include: a plurality of interconnected Mach-Zehnder interferometers (MZIs), each of the plurality of interconnected MZIs comprising: a first phase shifter configured to change a splitting ratio of the MZI; and a second phase shifter configured to shift a phase of one output of the MZI, wherein the first phase shifter and the second phase shifter are coupled to the plurality of weight control signals.
In another aspect, a system comprises: a storage unit configured to store the data set and a plurality of neural network weights; a driver unit configured to generate a plurality of modulator control signals and to generate a plurality of weight control signals; an optical processor, comprising: a laser unit configured to generate a plurality of light outputs; a plurality of optical modulators coupled to the laser unit and the driver unit, the plurality of optical modulators configured to generate an optical input vector by modulating a plurality of optical outputs generated by the laser unit based on a plurality of modulator control signals; a light matrix multiplication unit coupled to the plurality of light modulators and the driver unit, the light matrix multiplication unit configured to convert a light input vector into a light output vector based on a plurality of weight control signals; and a photo detection unit coupled to the light matrix multiplication unit and configured to generate a plurality of output voltages corresponding to the light output vectors; a comparator unit coupled to the photo-detection unit and configured to convert the plurality of output voltages into a plurality of digital 1-bit optical outputs; and a controller comprising an integrated circuit configured to perform the following operations: receiving, from a computer, an artificial neural network computation request comprising an input data set and a first plurality of neural network weights, wherein the input data set comprises a first digital input vector having an N-bit resolution; storing the input data set and the first plurality of neural network weights in a memory unit; decomposing the first digital input vector into N1-bit input vectors, each of the N1-bit input vectors corresponding to one of the N bits of the first digital input vector; generating, by a driver unit, a sequence of N1-bit modulator control signals corresponding to N1-bit input vectors; obtaining from the comparator unit a sequence of N digital 1-bit optical outputs corresponding to the sequence of N1-bit modulator control signals; constructing an N-bit digital output vector from a sequence of N digital 1-bit optical outputs; performing a non-linear transformation on the constructed N-bit digital output vector to produce a transformed N-bit digital output vector; and storing the transformed N-bit digital output vector in a memory unit.
In another aspect, a method for performing artificial neural network computations in a system having an optical matrix multiplication unit configured to convert an optical input vector to an optical output vector based on a plurality of weight control signals, the method comprising: receiving, from a computer, an artificial neural network computation request comprising an input data set and a first plurality of neural network weights, wherein the input data set comprises a first digital input vector; storing the input data set and the first plurality of neural network weights in a memory unit; generating, by a digital-to-analog conversion (DAC) unit, a first plurality of modulator control signals based on a first digital input vector and a first plurality of weight control signals based on a first plurality of neural network weights; obtaining a first plurality of digital light outputs from an analog-to-digital conversion (ADC) unit corresponding to the light output vector of the light matrix multiplication unit, the first plurality of digital light outputs forming a first digital output vector; performing, by a controller, a non-linear transformation on a first digital output vector to produce a first transformed digital output vector; storing the first transformed digital output vector in a memory unit; and outputting, by the controller, an artificial neural network output generated based on the first transformed digital output vector.
In another aspect, a method comprises: providing input information in an electronic format; converting at least a portion of the electronic input information into an optical input vector; optically converting the light input vector into a light output vector based on the light matrix multiplication; converting the light output vector into an electronic format; and electronically applying a non-linear transformation to the electronically converted light output vector to provide output information in an electronic format.
Embodiments of the method may include one or more of the following features. For example, the method may further comprise: electro-optical conversion (electronic-to-optical conversion), optical conversion (optical transformation), optical-to-electronic conversion (optical-to-electronic conversion), and nonlinear transformation for electrical application are repeated for new electronic input information corresponding to output information provided in an electronic format.
In some embodiments, the optical matrix multiplication for the initial optical transform and the optical matrix multiplication for the repeated optical transform may be the same and may correspond to the same layer of the artificial neural network.
In some embodiments, the optical matrix multiplication for the initial optical transform and the optical matrix multiplication for the repeated optical transform may be different and may correspond to different layers of the artificial neural network.
In some embodiments, the method may further comprise: the electro-optical conversion, the electro-optical conversion and the electrically applied nonlinear conversion are repeated for different parts of the electronic input information, wherein the optical matrix multiplication for the initial optical conversion and the optical matrix multiplication for the repeated optical conversion are identical and correspond to the first layer of the artificial neural network.
In some embodiments, the method may further comprise: providing intermediate information in an electronic format based on electronic output information for a plurality of portions of electronic input information generated by a first layer of an artificial neural network; and repeating the electro-optical conversion, the electro-optical conversion, and the electrically applied nonlinear conversion for each different portion of the electronic intermediate information, wherein the optical matrix multiplication for the initial optical conversion and the optical matrix multiplication for the repeated optical conversion associated with the different portion of the electronic intermediate information are the same and correspond to a second layer of the artificial neural network.
In another aspect, a system comprises: a light processor comprising a passive diffractive optical element, wherein the passive diffractive optical element is configured to transform a light input vector or matrix into a light output vector or matrix representing the result of a matrix process applied to the light input vector or matrix and a predetermined vector defined by the arrangement of the diffractive optical element.
Embodiments of the system may include one or more of the following features. For example, the matrix processing may comprise a matrix multiplication between the light input vector or matrix and a predetermined vector defined by the arrangement of the diffractive optical elements.
In some embodiments, the light processor may comprise a light matrix processing unit comprising: an input waveguide array for receiving an optical input vector; an optical interference unit comprising a passive diffractive optical component, wherein the optical interference unit is in optical communication with the input waveguide array and is configured to perform a linear transformation of an optical input vector into a second optical signal array; and an array of output waveguides in optical communication with the optical interference unit for guiding the second array of optical signals, wherein at least one input waveguide of the array of input waveguides is in optical communication with each output waveguide of the array of output waveguides through the optical interference unit.
In some embodiments, the light interference unit may include a substrate having at least one of a hole or a stripe (stripe), the hole having a size in a range of 100nm to 10 μm, and the stripe having a width in a range of 100nm to 10 μm.
In some embodiments, the optical interference unit may include a substrate having passive diffractive optical elements arranged in a two-dimensional configuration, and the substrate includes at least one of a planar substrate or a curved substrate.
In some embodiments, the substrate may comprise a planar substrate that is parallel to a direction of light propagation from the array of input waveguides to the array of output waveguides.
In some embodiments, the light processor may comprise a light matrix processing unit comprising: an input waveguide matrix for receiving the optical input matrix; an optical interference unit comprising a passive diffractive optical component, wherein the optical interference unit is in optical communication with the input waveguide matrix and is configured to perform a linear transformation of the optical input matrix into a second matrix of optical signals; and a matrix of output waveguides in optical communication with the optical interference unit for guiding the second matrix of optical signals, wherein at least one input waveguide of the matrix of input waveguides is in optical communication with each output waveguide of the matrix of output waveguides through the optical interference unit.
In some embodiments, the light interference unit may include a substrate having at least one of a hole or a stripe, a size of the hole being in a range of 100nm to 10 μm, and a width of the stripe being in a range of 100nm to 10 μm.
In some embodiments, the optical interference unit may include a substrate having passive diffractive optical components arranged in a three-dimensional configuration.
In some embodiments, the substrate may have a shape of at least one of a cube, a column, a prism, or an irregular volume.
In some embodiments, the light processor may include a light interference unit comprising a hologram (hologram) having passive diffractive optical components, the light processor configured to receive modulated light representing the light input matrix and to continuously convert the light as it passes through the hologram until it emerges from the hologram as the light output matrix.
In some embodiments, the optical interference unit may comprise a substrate having passive diffractive optical elements, and the substrate comprises at least one of silicon, silicon oxide, silicon nitride, quartz, lithium niobate, a phase change material, or a polymer.
In some embodiments, the optical interference unit may include a substrate having a passive diffractive optical element, and the substrate includes at least one of a glass substrate or an acrylic substrate.
In some embodiments, the passive diffractive optical component can be formed in part by a dopant.
In some embodiments, matrix processing may represent the processing of input data by a neural network, the input data being represented by optical input vectors.
In some embodiments, the light processor may include: a laser unit configured to generate a plurality of light outputs; a plurality of optical modulators coupled to the laser unit and configured to generate an optical input vector by modulating a plurality of optical outputs generated by the laser unit based on a plurality of modulator control signals; a light matrix processing unit coupled to the plurality of light modulators, the light matrix processing unit comprising a passive diffractive optical component configured to convert a light input vector into a light output vector based on a plurality of weights defined by the passive diffractive optical component; and a photo detection unit coupled to the light matrix processing unit and configured to generate a plurality of output electrical signals corresponding to the light output vectors.
In some embodiments, the passive diffractive optical component may be arranged in a three-dimensional configuration, the plurality of light modulators includes a two-dimensional array of light modulators, and the photodetecting unit includes a two-dimensional array of photodetectors.
In some embodiments, the light matrix processing unit may include a housing module (housing module) to support and protect the input waveguide array, the light interference unit, and the output waveguide array, the light processor including a receiving module configured to receive the light matrix processing unit, the receiving module including a first interface (interface) to enable the light matrix processing unit to receive light input vectors from the plurality of light modulators, and a second interface to enable the light matrix processing unit to transmit the light output vectors to the photodetection unit.
In some embodiments, the plurality of output electrical signals may include at least one of a plurality of voltage signals or a plurality of current signals.
In some embodiments, a system may comprise: a storage unit; a digital-to-analog conversion (DAC) unit configured to generate a plurality of modulator control signals; an analog-to-digital conversion (ADC) unit coupled to the photodetection unit and configured to convert the plurality of output electrical signals into a plurality of digital outputs; and a controller comprising an integrated circuit configured to perform the following operations: receiving an artificial neural network computation request comprising an input data set from a computer, wherein the input data set comprises a first numeric input vector; storing the input data set in a storage unit; and generating, by the DAC unit, a first plurality of modulator control signals based on the first digital input vector.
In another aspect, a method comprises: 3D printing an optical matrix processing unit comprising a passive diffractive optical component, wherein the passive diffractive optical component is configured to transform an optical input vector or matrix into an optical output vector or matrix representing a result of a matrix processing applied to the optical input vector or matrix and a predetermined vector defined by an arrangement of diffractive optical components.
In another aspect, a method comprises: generating a hologram comprising a passive diffractive optical component using one or more laser beams, wherein the passive diffractive optical component is configured to transform a light input vector or matrix into a light output vector or matrix representing the result of a matrix process applied to the light input vector or matrix and a predetermined vector defined by the arrangement of diffractive optical components.
In another aspect, a system comprises: a light processor comprising passive diffractive optical components arranged in a one-dimensional manner, wherein the passive diffractive optical components are configured to convert a light input into a light output representing a result of a matrix process applied to the light input and a predetermined vector defined by the arrangement of the diffractive optical components.
Embodiments of the system may include one or more of the following features. For example, the matrix processing may comprise a matrix multiplication between the light input and a predetermined vector defined by the arrangement of the diffractive optical components.
In some embodiments, the light processor may comprise a light matrix processing unit comprising: an input waveguide for receiving an optical input; an optical interference unit comprising a passive diffractive optical component, wherein the optical interference unit is in optical communication with the input waveguide and is configured to perform a linear transformation of the optical input; and an output waveguide in optical communication with the optical interference unit for directing the optical output.
In some embodiments, the light interference unit may include a substrate having at least one of a hole or a grating, and the hole or grating assembly may have a size in a range of 100nm to 10 μm.
In another aspect, a system comprises: a storage unit; a digital-to-analog conversion (DAC) unit configured to generate a plurality of modulator control signals; and an optical processor comprising: a laser unit configured to generate a plurality of light outputs; a plurality of optical modulators coupled to the laser unit and the DAC unit, the plurality of optical modulators configured to generate an optical input vector by modulating a plurality of optical outputs generated by the laser unit based on a plurality of modulator control signals; a light matrix processing unit coupled to the plurality of light modulators, the light matrix processing unit comprising a passive diffractive optical component configured to convert a light input vector into a light output vector based on a plurality of weights defined by the passive diffractive optical component; and a photo detection unit coupled to the light matrix processing unit and configured to generate a plurality of output electrical signals corresponding to the light output vectors. The system further comprises: an analog-to-digital conversion (ADC) unit coupled to the photodetection unit and configured to convert the plurality of output electrical signals into a plurality of digital optical outputs; and a controller comprising an integrated circuit configured to perform the following operations: receiving an artificial neural network computation request comprising an input data set from a computer, wherein the input data set comprises a first numeric input vector; storing the input data set in a storage unit; and generating, by the DAC unit, a first plurality of modulator control signals based on the first digital input vector.
Embodiments of the system may include one or more of the following features. For example, the matrix processing unit may comprise a passive diffractive optical component configured to convert the light input vector into a light output vector representing a product of a matrix multiplication between the light input vector and a predetermined vector defined by the passive diffractive optical component.
In some embodiments, the operations further comprise: obtaining a first plurality of digital light outputs from the ADC unit corresponding to the light output vector of the light matrix processing unit, the first plurality of digital light outputs forming a first digital output vector; performing a non-linear transformation on the first digital output vector to produce a first transformed digital output vector; and storing the first transformed digital output vector in a memory unit.
In some embodiments, the system may have a first cycle period defined as the time elapsed between the step of storing the input data set in the storage unit and the step of storing the first transformed digital output vector in the storage unit, and wherein the first cycle period may be less than or equal to 1 ns.
In some embodiments, the operations may further comprise: an artificial neural network output generated based on the first transformed digital output vector is output.
In some embodiments, the operations may further comprise: a second plurality of modulator control signals is generated by the DAC unit based on the first converted digital output vector.
In some embodiments, the input data set may further include a second digital input vector, and wherein the operations may further include: generating, by the DAC unit, a second plurality of modulator control signals based on a second digital input vector; obtaining a second plurality of digital light outputs from the ADC unit corresponding to the light output vector of the light matrix processing unit, the second plurality of digital light outputs forming a second digital output vector; performing a non-linear transformation on the second digital output vector to produce a second transformed digital output vector; storing the second transformed digital output vector in a storage unit; and outputting an artificial neural network output generated based on the first transformed digital output vector and the second transformed digital output vector, wherein the optical output vector of the optical matrix processing unit is generated from a second optical input vector generated based on the second plurality of modulator control signals, the second optical input vector being transformed by the optical matrix processing unit based on a plurality of weights defined by the passive diffractive optical component.
In some embodiments, the system may further comprise: an analog nonlinear unit disposed between the photodetection unit and the ADC unit, the analog nonlinear unit configured to receive the plurality of output electrical signals from the photodetection unit, apply a nonlinear transfer function, and output a plurality of converted output electrical signals to the ADC unit, wherein the operations may further comprise: obtaining a first plurality of converted digital output electrical signals corresponding to the plurality of converted output electrical signals from the ADC unit, the first plurality of converted digital output electrical signals forming a first transformed digital output vector; and storing the first transformed digital output vector in a memory unit.
In some embodiments, the integrated circuit of the controller may be configured to generate the first plurality of modulator control signals at a rate greater than or equal to 8 GHz.
In some embodiments, the system may further comprise: an analog storage unit disposed between the DAC unit and the plurality of light modulators, the analog storage unit configured to store an analog voltage and output the stored analog voltage; and an analog nonlinear unit disposed between the photodetection unit and the ADC unit, the analog nonlinear unit configured to receive the plurality of output electrical signals from the photodetection unit, apply a nonlinear transfer function, and output a plurality of converted output electrical signals.
In some embodiments, the analog memory cell may include a plurality of capacitors.
In some embodiments, the analog memory cell may be configured to receive and store a plurality of converted output electrical signals of the analog nonlinear cell and output the stored plurality of converted output electrical signals to a plurality of optical modulators, and wherein the operations may further comprise: storing the plurality of converted output electrical signals of the analog non-linear unit in an analog storage unit based on generating a first plurality of modulator control signals; outputting the stored converted output electrical signal through the analog storage unit; obtaining a second plurality of converted digital output electrical signals from the ADC unit, the second plurality of converted digital output electrical signals forming a second converted digital output vector; and storing the second transformed digital output vector in the memory unit.
In some embodiments, the artificial neural network computing the requested input data set may comprise a plurality of digital input vectors, wherein the laser unit may be configured to produce a plurality of wavelengths, and wherein the plurality of light modulators may comprise: an optical modulator group configured to generate a plurality of optical input vectors, each optical modulator group corresponding to one of a plurality of wavelengths and generating a respective optical input vector having a respective wavelength; and an optical multiplexer configured to combine the plurality of optical input vectors into a combined optical input vector comprising a plurality of wavelengths. The photodetecting unit may be further configured to demultiplex a plurality of wavelengths and generate a plurality of demultiplexed output electrical signals, and the operations may include: obtaining a plurality of digital demultiplexed optical outputs from the ADC unit, the plurality of digital demultiplexed optical outputs forming a plurality of first digital output vectors, wherein each of the plurality of first digital output vectors corresponds to one of the plurality of wavelengths; performing a non-linear transformation on each of the plurality of first digital output vectors to produce a plurality of transformed first digital output vectors; and storing a plurality of transformed first digital output vectors in a memory unit, wherein each of the plurality of digital input vectors corresponds to one of the plurality of optical input vectors.
In some embodiments, the artificial neural network computation request may include a plurality of digital input vectors, wherein the laser unit is configured to produce a plurality of wavelengths, and wherein the plurality of optical modulators may include: an optical modulator group configured to generate a plurality of optical input vectors, each optical modulator group corresponding to one of a plurality of wavelengths and generating a respective optical input vector having a respective wavelength; and an optical multiplexer configured to combine the plurality of optical input vectors into a combined optical input vector comprising a plurality of wavelengths. The operations may include: obtaining a first plurality of digital light outputs from the ADC unit corresponding to a light output vector, the light output vector comprising a plurality of wavelengths, the first plurality of digital light outputs forming a first digital output vector; performing a non-linear transformation on the first digital output vector to produce a first transformed digital output vector; and storing the first transformed digital output vector in a memory unit.
In some embodiments, the DAC cell may include: a 1-bit DAC unit configured to generate a plurality of 1-bit modulator control signals, wherein a resolution of the ADC unit may be 1 bit, and wherein a resolution of the first digital input vector may be N bits. The operations may include: decomposing the first digital input vector into N1-bit input vectors, each of the N1-bit input vectors corresponding to one of the N bits of the first digital input vector; generating, by a 1-bit DAC unit, a sequence of N1-bit modulator control signals corresponding to N1-bit input vectors; obtaining from the ADC unit a sequence of N digital 1-bit optical outputs corresponding to a sequence of N1-bit modulator control signals; constructing an N-bit digital output vector from a sequence of N digital 1-bit optical outputs; performing a non-linear transformation on the constructed N-bit digital output vector to produce a transformed N-bit digital output vector; and storing the transformed N-bit digital output vector in a memory unit.
In some embodiments, the memory unit may include: a digital input vector memory configured to store a first digital input vector and comprising at least one SRAM.
In some embodiments, the laser unit may include: a laser source configured to generate light; and an optical power splitter configured to split light generated by the laser source into a plurality of optical outputs, wherein each of the plurality of optical outputs has substantially the same power.
In some embodiments, the plurality of optical modulators includes one of a MZI modulator, a ring resonance modulator, or an electro-absorption modulator.
In some embodiments, the photodetecting unit may include: a plurality of photodetectors; and a plurality of amplifiers configured to convert the photocurrent generated by the photodetector into a plurality of output electrical signals.
In some embodiments, the integrated circuit may comprise an application specific integrated circuit.
In some embodiments, the light matrix processing unit may include: an input waveguide array for receiving an optical input vector; an optical interference unit in optical communication with the input waveguide array for performing a linear transformation of the optical input vector into a second optical signal array, wherein the optical interference unit comprises a passive diffractive optical component; and an array of output waveguides in optical communication with the optical interference unit for guiding the second array of optical signals, wherein at least one input waveguide in the array of input waveguides is in optical communication with each output waveguide in the array of output waveguides through the optical interference unit.
In another aspect, a system comprises: a storage unit; a driver unit configured to generate a plurality of modulator control signals; an optical processor, comprising: a laser unit configured to generate a plurality of light outputs; a plurality of optical modulators coupled to the laser unit and the driver unit, the plurality of optical modulators configured to generate an optical input vector by modulating a plurality of optical outputs generated by the laser unit based on a plurality of modulator control signals; a light matrix processing unit coupled to the plurality of light modulators and the driver unit, the light matrix processing unit comprising a passive diffractive optical component configured to convert a light input vector into a light output vector based on a plurality of weight control signals defined by the passive diffractive optical component; and a photo detection unit coupled to the light matrix processing unit and configured to generate a plurality of output electrical signals corresponding to the light output vectors. The system further includes a comparator unit coupled to the photodetection unit and configured to convert the plurality of output electrical signals into a plurality of digital 1-bit optical outputs; and a controller comprising an integrated circuit configured to perform the following operations: receiving an artificial neural network computation request comprising an input data set from a computer, wherein the input data set comprises a first digital input vector having a resolution of N bits; storing the input data set in a storage unit; decomposing the first digital input vector into N1-bit input vectors, each of the N1-bit input vectors corresponding to one of the N bits of the first digital input vector; generating, by a driver unit, a sequence of N1-bit modulator control signals corresponding to N1-bit input vectors; obtaining from the comparator unit a sequence of N digital 1-bit optical outputs corresponding to the sequence of N1-bit modulator control signals; constructing an N-bit digital output vector from a sequence of N digital 1-bit optical outputs; performing a non-linear transformation on the constructed N-bit digital output vector to produce a transformed N-bit digital output vector; and storing the transformed N-bit digital output vector in a memory unit.
Embodiments of the system may include one or more of the following features. For example, the light matrix processing unit may comprise a light matrix multiplication unit configured to convert the light input vector into a light output vector representing a product of a matrix multiplication between the input vector represented by the light input vector and a predetermined vector defined by the passive diffractive optical component.
In another aspect, a method for performing artificial neural network computations in a system having an optical matrix processing unit, the method comprising: receiving, from a computer, an artificial neural network computation request comprising an input data set, the input data set comprising a first numeric input vector; storing the input data set in a storage unit; generating, by a digital-to-analog conversion (DAC) unit, a first plurality of modulator control signals based on a first digital input vector; converting the light input vector into a light output vector by using a light matrix processing unit comprising an arrangement of passive diffractive optical elements, wherein the light output vector represents a result of matrix processing applied to the light input vector and a predetermined vector defined by the arrangement of diffractive optical elements; obtaining a first plurality of digital light outputs from an analog-to-digital conversion (ADC) unit corresponding to the light output vector of the light matrix processing unit, the first plurality of digital light outputs forming a first digital output vector; performing, by a controller, a non-linear transformation on a first digital output vector to produce a first transformed digital output vector; storing the first transformed digital output vector in a memory unit; and outputting, by the controller, an artificial neural network output generated based on the first transformed digital output vector.
Embodiments of the method may include one or more of the following features. For example, converting the light input vector into the light output vector may comprise converting the light input vector into the light output vector representing a product of a matrix multiplication between the digital input vector and a predetermined vector defined by the arrangement of the diffractive optical element.
In another aspect, a method comprises: providing input information in an electronic format; converting at least a portion of the electronic input information into an optical input vector; optically converting, by an optical processor comprising a passive diffractive optical component, an optical input vector into an optical output vector based on optical matrix processing; converting the light output vector into an electronic format; and electronically applying a non-linear transformation to the electronically converted light output vector to provide output information in an electronic format.
Embodiments of the method may include one or more of the following features. For example, optically converting the light input vector into the light output vector may include optically converting the light input vector into the light output vector based on a light matrix multiplication between a digital input vector represented by the light input vector and a predetermined vector defined by the passive diffractive optical component.
In some embodiments, the method may further comprise: electro-optical conversion, photoelectric conversion, and nonlinear conversion for electrical application are repeated for new electronic input information corresponding to output information provided in an electronic format.
In some embodiments, the optical matrix process for the initial optical transform and the optical matrix process for the repeated optical transform may be the same and may correspond to the same layer of the artificial neural network.
In some embodiments, the method may further comprise: the electro-optical conversion, the electro-optical conversion, and the nonlinear conversion of the electrical application are repeated for different portions of the electronic input information, wherein the optical matrix process for the initial optical conversion and the optical matrix process for the repeated optical conversion may be the same and correspond to one layer of the artificial neural network.
In another aspect, a system comprises: an optical matrix processing unit configured to process an input vector of length N, wherein the optical matrix processing unit includes a directional coupler (directional coupler) of layers N +2 and phase shifters of layers N, and N is a positive integer.
Embodiments of the system may include one or more of the following features. For example, the optical matrix processing unit may include no more than N +2 layers of directional couplers.
In some embodiments, the light matrix processing unit may comprise a light matrix multiplication unit.
In some embodiments, the optical matrix processing unit may include a substrate and interconnection interferometers disposed on the substrate, wherein each interferometer includes an optical waveguide disposed on the substrate, and the directional couplers and the phase shifters are part of the interconnection interferometers.
In some embodiments, the optical matrix processing unit may include a layer of attenuators (attenuators) after the last layer of directional couplers.
In some embodiments, a layer of attenuators may include N attenuators.
In some embodiments, the system may include one or more homodyne detectors (homodyne detectors) for detecting the output from the attenuator.
In some embodiments, N-3, and the optical matrix processing unit may include: an input (terminal) configured to receive an input vector; a first layer of directional couplers coupled to the input; a first layer phase shifter coupled to the first layer directional coupler; a second layer directional coupler coupled to the first layer phase shifter; a second layer phase shifter coupled to the second layer directional coupler; a third layer directional coupler coupled to the second layer phase shifter; a third tier phase shifter coupled to the third tier directional coupler; a fourth layer directional coupler coupled to the third layer phase shifter; and a fifth layer directional coupler coupled to the fourth layer directional coupler.
In some embodiments, N-4, and the optical matrix processing unit may include: an input configured to receive an input vector; a first, second, third and fourth tier of directional couplers, each tier of directional couplers followed by a tier of phase shifters, wherein the first tier of directional couplers is coupled to the input; a second to last layer (second-to-last layer) directional coupler coupled to the fourth layer phase shifter; and a final layer directional coupler coupled to the second to last layer directional coupler.
In some embodiments, N-8, and the optical matrix processing unit may include: an input configured to receive an input vector; eight layers of directional couplers, each layer of directional couplers followed by a layer of phase shifters, wherein a first layer of directional couplers is coupled to the input; a second to last layer directional coupler coupled to the eighth layer phase shifter; and a final layer directional coupler coupled to the second to last layer directional coupler.
In some embodiments, the optical matrix multiplication unit may include: an input configured to receive an input vector; n layers of directional couplers, each layer of directional couplers followed by a layer of phase shifters, wherein a first layer of directional couplers is coupled to the input; a second to last layer directional coupler coupled to the nth layer directional coupler; and a final layer directional coupler coupled to the second to last layer directional coupler.
In some embodiments, N is an even number.
In some embodiments, each ith layer directional coupler comprises N/2 directional couplers, where i is an odd number, and each jth layer directional coupler comprises N/2-1 directional couplers, where j is an even number.
In some embodiments, for each ith layer of directional couplers with i being an odd number, the kth directional coupler may be coupled to the (2k-1) th and 2 kth outputs of the previous layer, k being an integer from 1 to N/2.
In some embodiments, for each jth tier directional coupler where j is an even number, the mth directional coupler may be coupled to the (2m) th and (2m +1) th outputs of the previous tier, m being an integer from 1 to N/2-1.
In some embodiments, each ith layer phase shifter may include N phase shifters, where i is an odd number, and each jth layer phase shifter may include N-2 phase shifters, where j is an even number.
In some embodiments, N may be an odd number.
In some embodiments, each layer of directional couplers may include (N-1)/2 directional couplers.
In some embodiments, each layer of phase shifters may include N-1 phase shifters.
In another aspect, a system comprises: a generator (generator) configured to generate a first data set, wherein the generator comprises an optical matrix processing unit; and a discriminator (discriminator) configured to receive a second data set comprising data from the first data set and data from the third data set, the data in the first data set having similar characteristics (characteristics) as the data in the third data set, and to classify the data in the second data set as either data from the first data set or data from the third data set.
Embodiments of the method may include one or more of the following features. For example, the light matrix processing unit may comprise at least one of: (i) the optical matrix multiplying unit, (ii) the passive diffractive optical element, or (iii) the optical matrix processing unit.
In some embodiments, the third data set may comprise real data, the generator is configured to generate synthetic data (synthesized data) similar to the real data, and the discriminator is configured to classify the data as either the real data or the synthetic data.
In some embodiments, the generator may be configured to generate a data set for training at least one of an automated driving vehicle (vehicle), a medical diagnostic system, a fraud detection system, a weather forecast system, a financial prediction system, a face recognition system, a speech recognition system, or a product defect detection system.
In some embodiments, the generator may be configured to generate an image that is similar to an image of at least one of a real object or a real scene, and the discriminator is configured to classify the received image as (i) an image of the real object or the real scene, or (ii) a composite image generated by the generator.
In some embodiments, the real object may include at least one of a person, an animal, a cell, a tissue, or a product, and the real scene includes a scene encountered by the vehicle.
In some embodiments, the discriminator may be configured to classify the received image as being (i) an image of an actual person, an actual animal, an actual cell, an actual tissue, an actual product, or an actual scene encountered by the vehicle, or (ii) a composite image generated by the generator.
In some embodiments, the vehicle may include at least one of a motorcycle, an automobile, a truck, a train, a helicopter, an airplane, a submarine, a ship, or a drone.
In some embodiments, the generator may be configured to generate an image of a tissue or cell associated with at least one of a human disease, an animal disease, or a plant disease.
In some embodiments, the generator may be configured to generate an image of tissue or cells associated with a human disease, and the disease includes at least one of cancer, parkinson's disease, sickle cell anemia, heart disease, cardiovascular disease, diabetes, chest disease, or skin disease.
In some embodiments, the generator may be configured to generate an image of a tissue or cell associated with the cancer, and the cancer may include at least one of skin cancer, breast cancer, lung cancer, liver cancer, prostate cancer, or brain cancer.
In some embodiments, the system may further comprise a random noise generator configured to generate random noise input to the generator, and the generator is configured to generate the first data set based on the random noise.
In another aspect, a system comprises: a random noise generator configured to generate random noise; and a generator configured to generate data based on the random noise, wherein the generator includes an optical matrix processing unit.
Embodiments of the system may include one or more of the following features. For example, the light matrix processing unit may include at least one of (i) the light matrix multiplication unit described above, (ii) the passive diffractive optical component described above, or (iii) the light matrix processing unit described above.
In another aspect, a system comprises: an optical circuit configured to perform a logic function (logic function) on two input signals, the optical circuit comprising: a first directional coupler having two inputs configured to receive two input signals and two outputs; a first pair (pair) of phase shifters configured to modify the phase of the signal at the two outputs of the first directional coupler; a second directional coupler having two inputs configured to receive signals from the first pair of phase shifters and two outputs; and a second pair of phase shifters configured to modify the phase of the signals at the two outputs of the second directional coupler.
Embodiments of the method may include one or more of the following features. For example, the phase shifter may be configured to cause the optical circuit to perform a rotation (rotation):
in some embodiments, when the input signals x1 and x2 are provided to both inputs of the first directional coupler, the phase shifter may be configured to cause the optical circuit to perform the operations of:
in some embodiments, the optical circuit may include a first photodetector configured to generate absolute values of signals from the second pair of phase shifters to cause the optical circuit to perform operations of:
in some embodiments, the light circuit may comprise a comparator configured to compare the output signal of the first photodetector with a threshold value to generate a binary value to cause the light circuit to generate the output:
in some embodiments, the optical circuit may include a feedback mechanism (feedback mechanism) configured to cause an output signal of the photodetector to be fed back to the input of the first directional coupler and through the first directional coupler, the first pair of phase shifters, the second directional coupler, and the second pair of phase shifters, and detected by the photodetector to cause the optical circuit to perform operations of:
it produces the outputs AND (x1, x2) AND OR (x1, x 2).
In some embodiments, the optical circuit may include: a third directional coupler having two inputs configured to receive signals from the second pair of phase shifters and two outputs; a third pair of phase shifters configured to modify the phase of the signal at the two outputs of the third directional coupler; a fourth directional coupler having two inputs configured to receive signals from the third pair of phase shifters and two outputs; a fourth pair of phase shifters configured to modify the phase of the signal at the two outputs of the fourth directional coupler; and a second photodetector configured to generate an absolute value of a signal from the fourth pair of phase shifters to cause the optical circuit to perform operations of:
it produces the outputs AND (x1, x2) AND OR (x1, x 2).
In some embodiments, a system may include a Bitonic sorter (sorting function) configured to perform a sorting function of the Bitonic sorter using optical circuitry.
In some embodiments, a system may include an apparatus configured to perform a hashing function using optical circuitry.
In some embodiments, the hash function may include secure hash algorithm (SHA-2) 2.
Generally speaking, systems for performing computations use different types of operations to produce computation results, each performed on a signal (e.g., an electrical or optical signal) that is most appropriate for the fundamental physical characteristics of the operation (e.g., in terms of energy consumption and/or speed). For example, three such operations are: copying (copying), summing (summation), and multiplying (multiplication). The replication may be performed using optical power splitting (optical power splitting), the summation may be performed using current-based summation (electrical current-based summation), and the multiplication may be performed using optical amplitude modulation (optical amplitude modulation), as described in more detail below. An example of a calculation that can be performed using these three types of operations is to multiply a vector by a matrix (e.g., as employed by artificial neural network calculations). Various other calculations may be performed using these operations, which represent a general set of linear operations that may perform various calculations, including but not limited to: vector-vector dot product (vector-vector dot product), vector-vector element-by-element multiplication (vector-vector element-by-element multiplication), vector-scalar element-by-element multiplication (vector-scalar element-by-element multiplication), or matrix-matrix element-by-element multiplication (matrix-matrix element-by-element multiplication). Some examples described herein illustrate techniques and configurations for vector-matrix multiplication, but corresponding techniques and configurations may be used for any of these types of computations.
Aspects may have one or more of the following advantages.
The optoelectronic computing systems described herein that use electrical and optical signals may facilitate increased flexibility and/or efficiency. In the past, there may be potential challenges associated with combining optical (or photonic) and electrical (or electronic) integrated devices on a common platform (e.g., a common semiconductor die, or multiple semiconductor dies combined in a controlled collapsed chip connection or "flip-chip" arrangement). Such potential challenges may include, for example, input/output (I/O) packaging or temperature control. For those systems described herein, potential challenges may be increased when used with a relatively large number of optical input/output ports (ports) and a relatively large number of electrical input/output ports (e.g., 4 or more optical input/output ports, 200 or more electrical input/output ports). For example, in a controlled collapse chip connection, a semiconductor die having a photonic integrated circuit (e.g., implementing an optical processor with reference to FIG. 1A as described below) may include electrical input and output ports that connect with electrical output ports of a corresponding electronic integrated circuit (e.g., implementing controller 110, memory unit 120, digital-to-analog converter (DAC) unit 130, and/or analog-to-digital converter (ADC) unit 160 with reference to FIG. 1A as described below). For example, controlled collapse chip connections may use solder balls (or "bumps") of alloy composition that are in direct contact with metal pads integrated to the die, wherein the need for more complex, less compact packaging of wire-to-pad bonds is eliminated. Using an appropriate system design may mitigate these potential challenges. For example, the system may use a high density packaging arrangement that uses temperature control (e.g., thermoelectric cooling) to control thermal expansion between different material types (e.g., semiconductor materials (e.g., silicon), glass materials (silicon dioxide or "Silica"), ceramic materials, etc.), and/or uses an enclosing housing (sealing) as a heat sink and provides a degree of sealing (sealing). With this temperature stabilization technique, different Coefficients of Thermal Expansion (CTE) and the resulting misalignment between the system ports and the ports of the packaged high density fiber array can be limited.
For the copy operation, since optical power splitting is passive, power does not need to be consumed to perform the operation. In addition, the frequency bandwidth of the electrical separator has limitations related to the RC time constant. In contrast, the frequency bandwidth of the optical splitter is virtually infinite. Different types of optical power splitters (optical power splitters) may be used, including waveguide splitters (waveguide optical splitters) or free-space beam splitters (free-space beam splitters), as described in more detail below.
For multiplication operations, one value may be encoded as an optical signal and another value may be encoded as an amplitude scaling coefficient (e.g., multiplying by a value in the range of 0 to 1). After the scaling factor is set, the multiplication operation in the optical domain requires less (or no) conditioning of the electrical signal and thus reduces constraints due to electrical noise, power consumption and bandwidth limitations. By appropriate selection of the detection scheme, signed (signed) results (e.g., multiplying by a value between-1 and + 1) may be obtained, as described in more detail below.
For the summing operation, different techniques may be used to achieve a result in which the magnitude of the current in the conductor is determined based on the sum of the different contributions. In the case of input current signals, when two or more conductors carrying those input current signals are combined at a junction (junction), the single conductor carrying the output current signal represents the sum of those input current signals. In the case of an input optical signal, when two or more different wavelength light waves impinge on the detector, the current signal carried on the photocurrent produced by the detector represents the sum of the power in the input optical signal. Both produce an electrical signal (e.g., current) as an output representing the sum, but one uses current as an input (based on the sum of current-input-based summation), also known as "electrical summation" performed in the "electrical domain"), and the other uses light waves as an input (based on the sum of light-input-based summation), also known as "optical-electrical summation" performed in the "optical-electrical domain"). However, in some embodiments, a summation based on current inputs is used rather than a summation based on optical inputs, which enables a single optical wavelength to be used in the system, avoiding potentially complex components of the system that may need to be provided and maintaining multiple wavelengths.
The combination of these basic operations performed by these modules may be arranged to provide means to perform linear operations, such as vector-matrix multiplication (vector-matrix multiplication) with arbitrary matrix element sizes. Other implementations of matrix multiplication using optical signals and interferometers for combining signals using optical interference have been limited to providing vector matrix multiplication with certain limitations, such as unitary matrices (unitary matrices) or diagonal matrices. In addition, some other embodiments may rely on large-scale phase alignment of multiple optical signals as they propagate through a relatively large number of optical components (e.g., optical modulators). Alternatively, embodiments described herein may relax this phase alignment constraint by converting the optical signal to an electrical signal after propagating through fewer optical components (e.g., after propagating through no more than a single optical amplitude modulator), which allows the use of optical signals with reduced coherence, or even incoherent optical signals that do not rely on optical modulators that interfere constructively/destructively.
For time domain coding of optical and electrical signals, as will be described in more detail below, analog electronic circuits may be optimized for operation at a particular power level (level), which may be helpful if the circuit is operating at high speed. Such time-domain coding is useful in reducing any challenges that may be associated with precisely controlling the relatively large number of clearly distinguishable intensity levels of each symbol. In contrast, when applying precise control of the duty cycle in the time domain over a plurality of slots (time slots) within a single symbol duration (single symbol duration), a relatively constant amplitude may be used (for "on" levels, an amplitude with zero or close to zero is at an "off" level).
By integrating photons and electrons on a common substrate (e.g., a silicon chip) or connecting fabricated dies using a flip-chip configuration as described above, modules can be conveniently fabricated on a large scale and coupled in a compact system. Routing signals on the substrate as optical signals rather than electrical signals in a manner that allows grouping of photodetectors in a portion of the substrate and/or in a compact die layout (as described in more detail below) may help avoid long electronic routing and its associated challenges (e.g., parasitic capacitance, inductance, and cross-talk).
For embodiments of the system using sub-matrix multiplication, each element of the output vector may be computed simultaneously using different means (e.g., different cores, different processors, different computers, different servers), helping to alleviate some potential limitations (e.g., memory walls), and helping to scale the overall system to very large matrices. In some embodiments, different means may be used to multiply each sub-matrix by the corresponding sub-vector. The sum can then be calculated by collecting or accumulating summands (summands) from different devices. Intermediate results in the form of optical signals can be conveniently transmitted between devices even if the devices are separated by relatively large distances.
Other aspects include other combinations of the features described above and other features expressed as methods, apparatus, systems, program products, and in other ways.
Particular embodiments of the subject matter described in this specification can be implemented to realize one or more of the following advantages. The ANN computational throughput (throughput), latency (latency), or both may be improved. The power efficiency of the ANN calculation may be improved.
In another aspect, an apparatus comprises: a plurality of optical waveguides, wherein a set of a plurality of input values are encoded on respective optical signals carried by the optical waveguides; a plurality of replica modules, and for each of at least two subsets of the one or more optical signals, a respective set of the one or more replica modules is configured to split the subset of the one or more optical signals into two or more replicas (copies) of the optical signals; a plurality of multiplication modules, and for each of at least two copies of a first subset of the one or more optical signals, a respective multiplication module is configured to multiply the one or more optical signals of the first subset by one or more matrix element values using optical amplitude modulation, wherein at least one of the multiplication modules comprises an optical amplitude modulator comprising one input port and two output ports, and a pair of correlated optical signals is provided from the two output ports such that a difference between amplitudes of the correlated optical signals corresponds to a result of multiplying the input value by the signed matrix element value; and for the results of the two or more multiplication modules, a respective one of the summation modules is configured to produce an electrical signal representing the sum of the results of the two or more multiplication modules.
Embodiments of the device may include one or more of the following features. For example, an input value of a set of multiple input values encoded on a respective optical signal may represent an element of an input vector multiplied by a matrix comprising one or more matrix element values.
In some embodiments, a set of multiple output values may be encoded on respective electrical signals generated by one or more summing modules, and an output value of the set of multiple output values may represent an element of an output vector generated by multiplying an input vector by a matrix.
In some embodiments, each optical signal carried by the optical waveguide may include optical waves having a common wavelength that is substantially the same for all optical signals.
In some embodiments, the replica module can include at least one replica module having an optical splitter that transmits a predetermined proportion of the power of the optical wave at the input port to the first output port and transmits the remaining proportion of the power of the optical wave at the input port to the second output port.
In some embodiments, the optical splitter may include a waveguide splitter that transmits a predetermined proportion of the power of the optical wave guided by the input optical waveguide to the first output optical waveguide and transmits the remaining proportion of the power of the optical wave guided by the input optical waveguide to the second output optical waveguide.
In some embodiments, the guided mode of the input optical waveguide may be adiabatically (adiabatically) coupled to the guided mode of each of the first output optical waveguide and the second output optical waveguide.
In some embodiments, the optical splitter may include a beam splitter including at least one surface that transmits a predetermined proportion of the power of the optical wave at the input port and reflects the remaining proportion of the power of the optical wave at the input port.
In some embodiments, at least one of the plurality of optical waveguides may include an optical fiber coupled to an optical coupler, the optical coupler coupling a guided mode of the optical fiber to a free-space propagation mode.
In some embodiments, the multiplication module may include at least one coherence-sensitive multiplication module configured to multiply the first subset of one or more optical signals by one or more matrix element values using optical amplitude modulation based on interference between optical waves, the optical waves having a coherence length that is at least as long as a propagation distance through the coherence-sensitive multiplication module.
In some embodiments, the coherence sensitive multiplication module may include a mach-zehnder interferometer (MZI) that separates a lightwave guided by an input optical waveguide into a first optical waveguide arm (optical waveguide arm) of the MZI and a second optical waveguide arm of the MZI, the first optical waveguide arm including a phase shifter that produces a relative phase shift with respect to a phase delay of the second optical waveguide arm, and the MZI combines lightwaves from the first optical waveguide arm and the second optical waveguide arm into at least one output optical waveguide.
In some embodiments, the MZI may combine light waves from the first and second optical waveguide arms into each of the first and second output optical waveguides, the first photo-detector may receive the light waves from the first output optical waveguide to generate a first photocurrent, the second photo-detector may receive the light waves from the second output optical waveguide to generate a second photocurrent, and the result of the coherence-sensitive multiplication module may include a difference between the first photocurrent and the second photocurrent.
In some embodiments, the coherence sensitive multiplication module can include one or more ring resonators (ring resonators) including at least one ring resonator coupled to the first optical waveguide and at least one ring resonator coupled to the second optical waveguide.
In some embodiments, the first photo detector may receive a light wave from the first optical waveguide to generate a first photocurrent, the second photo detector may receive a light wave from the second optical waveguide to generate a second photocurrent, and the result of the coherence sensitive multiplication module may include a difference between the first photocurrent and the second photocurrent.
In some embodiments, the multiplication module may include at least one coherent-insensitive multiplication module configured to multiply the first subset of one or more optical signals by one or more matrix element values using optical amplitude modulation based on energy absorption within the optical waves.
In some embodiments, the coherent non-sensitive multiplication module may comprise an electro-absorption modulator (electro-absorption modulator).
In some embodiments, the one or more summing modules may include at least one summing module having: (1) two or more input conductors, each input conductor carrying an electrical signal in the form of an input current, the magnitude of the input current being representative of a respective result of a respective one of the multiplication modules, and (2) at least one output conductor carrying an electrical signal representative of a sum of the respective results in the form of an output current, the output current being proportional to the sum of the input currents.
In some embodiments, the two or more input and output conductors may include a plurality of wires that contact at one or more junctions between the wires, and the output current is substantially equal to the sum of the input currents.
In some embodiments, at least a first one of the input currents may be provided in the form of at least one photocurrent generated by at least one photodetector receiving an optical signal generated by a first one of the multiplication modules.
In some embodiments, the first input current may be provided as a difference between two photocurrents generated by different respective photodetectors that receive different respective optical signals generated by the first multiplication module.
In some embodiments, one of the copies of the first subset of one or more optical signals may consist of a single optical signal, wherein one of the input values is encoded on the single optical signal.
In some embodiments, a multiplication module corresponding to a copy of the first subset may multiply the encoded input value by a single matrix element value.
In some embodiments, one of the copies of the first subset of one or more optical signals on which the plurality of input values are encoded may include more than one, and less than all, of the optical signals.
In some embodiments, a multiplication module corresponding to a copy of the first subset may multiply the encoded input values by different respective matrix element values.
In some embodiments, different multiplication modules corresponding to different respective copies of the first subset of one or more optical signals may be included by different devices in optical communication to transmit one of the copies of the first subset of one or more optical signals between the different devices.
In some embodiments, at least one of two or more of the plurality of optical waveguides, two or more of the plurality of replica modules, two or more of the plurality of multiplication modules, and one or more summation modules may be disposed on a substrate of a common device.
In some embodiments, the apparatus performs a vector matrix multiplication, wherein the input vector may be provided as a set of optical signals and the output vector may be provided as a set of electrical signals.
In some embodiments, the apparatus may further comprise an accumulator that combines the input electrical signals corresponding to the outputs of the multiplication module or the summation module, wherein the input electrical signals may be encoded using time domain encoding (on-off amplitude modulation) using switching amplitude modulation within each of the plurality of time slots, and the accumulator may generate the output electrical signals encoded at more than two amplitude levels corresponding to different duty cycles of the time domain encoding over the plurality of time slots.
In some embodiments, each of the two or more of the multiplication modules corresponds to a different subset of the one or more optical signals.
In some embodiments, the apparatus may further include a multiplication module for each copy of a second subset of the one or more optical signals different from the optical signals in the first subset of the one or more optical signals, configured to multiply the one or more optical signals of the second subset by the one or more matrix element values using optical amplitude modulation.
In another aspect, a method comprises: encoding a set of multiple input values on respective optical signals; for each of at least two subsets of one or more optical signals, using a respective set of one or more replica modules to divide the subset of one or more optical signals into two or more replicas of the optical signal; for each of at least two copies of a first subset of the one or more optical signals, using a respective multiplication module to multiply the one or more optical signals of the first subset by one or more matrix element values using optical amplitude modulation, wherein at least one multiplication module comprises an optical amplitude modulator comprising one input port and two output ports, and a pair of correlated optical signals is provided from the two output ports such that a difference between the amplitudes of the correlated optical signals corresponds to a result of multiplying the input value by the signed matrix element value; and for the results of the two or more multiplication modules, using a summation module configured to produce an electrical signal representing a sum of the results of the two or more multiplication modules.
In another aspect, a method comprises: encoding a set of input values representing elements of an input vector on a respective optical signal; encoding a set of coefficients representing matrix elements as amplitude modulation levels of a set of optical amplitude modulators coupled to the optical signals, wherein at least one optical amplitude modulator comprising one input port and two output ports provides a pair of correlated optical signals from the two output ports such that a difference between amplitudes of the correlated optical signals corresponds to a result of multiplying an input value by a signed matrix element value; and encoding a set of output values representing elements of an output vector on respective electrical signals, wherein at least one of the electrical signals is in the form of a current whose magnitude corresponds to the sum of the respective elements of the input vector multiplied by the respective elements of a row (row) of the matrix.
Embodiments of the method may include one or more of the following features. For example, the at least one optical signal may be provided by a first optical waveguide, and the first optical waveguide may be coupled to an optical splitter that transmits a predetermined proportion of the power of the optical wave guided by the first optical waveguide to a second output optical waveguide, and transmits the remaining proportion of the power of the optical wave guided by the first optical waveguide to a third optical waveguide.
In another aspect, an apparatus comprises: a plurality of optical waveguides encoding a set of input values representing elements of an input vector on respective optical signals carried by the optical waveguides; a set of optical amplitude modulators coupled to the optical signals, encoding a set of coefficients representing matrix elements as amplitude modulation levels, wherein at least one optical amplitude modulator comprising one input port and two output ports provides a pair of correlated optical signals from the two output ports such that a difference between amplitudes of the correlated optical signals corresponds to a result of multiplying an input value by a value of a signed matrix element; a plurality of summation modules encoding a set of output values representing elements of an output vector on respective electrical signals, wherein at least one of the electrical signals is in the form of a current whose magnitude corresponds to the sum of a respective element of an input vector multiplied by a respective element of a row (row) of the matrix.
In another aspect, a method for multiplying an input vector by a given matrix includes: encoding a set of input values representing elements of an input vector on respective ones of a set of optical signals; coupling a first set of one or more devices to a first set of one or more waveguides that provide a first subset of the set of optical signals and producing a result of multiplying a first sub-matrix of a given matrix by a value encoded on the first subset of the set of optical signals; coupling a second set of one or more devices to a second set of one or more waveguides that provide a second subset of the set of optical signals and producing a result of multiplying a second sub-matrix of the given matrix by values encoded on the second subset of the set of optical signals; coupling a third set of one or more devices to a third set of one or more waveguides that provide a copy of the first subset of the set of optical signals produced by the first optical splitter and produce a result of multiplying a third sub-matrix of the given matrix by values encoded on the first subset of the set of optical signals; coupling a fourth set of one or more devices to a fourth set of one or more waveguides that provide copies of a second subset of the set of optical signals produced by the second optical splitter and produce a result of a fourth sub-matrix of the given matrix multiplied by values encoded on the second subset of the set of optical signals; wherein the first, second, third and fourth sub-matrices connected together form a given matrix; and wherein at least one output value representing an element of an output vector is encoded on an electrical signal, the output vector corresponding to the input vector multiplied by a given matrix, the electrical signal generated by a device in communication with the first set of one or more devices and the second set of one or more devices.
Embodiments of the method may include one or more of the following features. For example, each pair of the first set of one or more devices, the second set of one or more devices, the third set of one or more devices, and the fourth set of one or more devices may be mutually exclusive (mutuallyexclusive).
In another aspect, an apparatus comprises: a first set of one or more devices configured to receive the first set of optical signals and produce a result of multiplying the first matrix by values encoded on the first set of optical signals; a second set of one or more devices configured to receive the second set of optical signals and produce a result of the second matrix multiplied by values encoded on the second set of optical signals; a third set of one or more devices configured to receive the third set of optical signals and produce a result of multiplying the third matrix by values encoded on the third set of optical signals; a fourth set of one or more devices configured to receive the fourth set of optical signals and to generate a result of the fourth matrix multiplied by the values encoded on the fourth set of optical signals; and a configurable connection path between two or more of the first set of one or more devices, the second set of one or more devices, the third set of one or more devices, or the fourth set of one or more devices, wherein a first configuration of the configurable connection path is configured to (1) provide a copy of the first set of optical signals as at least one of the second set of optical signals, the third set of optical signals, or the fourth set of optical signals, and (2) provide one or more signals from the first set of one or more devices and one or more signals from the second set of one or more devices to a summing module, the summing module configured to produce an electrical signal representing a sum of values encoded on the signals received by the summing module.
In another aspect, an apparatus comprises: a first set of one or more devices configured to receive the first set of optical signals and produce a result based on optical amplitude modulation of one or more optical signals of the first set of optical signals; a second set of one or more devices configured to receive the second set of optical signals and produce a result based on optical amplitude modulation of one or more optical signals of the second set of optical signals; a third set of one or more devices configured to receive the third set of optical signals and produce a result based on optical amplitude modulation of one or more optical signals of the third set of optical signals; a fourth set of one or more devices configured to receive the fourth set of optical signals and produce a result based on optical amplitude modulation of one or more of the fourth set of optical signals; and a configurable connection path between two or more of the first set of one or more devices, the second set of one or more devices, the third set of one or more devices, or the fourth set of one or more devices, wherein a first configuration of the configurable connection path is configured to (1) provide a copy of the first set of optical signals as the third set of optical signals, or (2) provide one or more signals from the first set of one or more devices and one or more signals from the second set of one or more devices to a summing module, the summing module configured to produce an electrical signal representing a sum of values encoded on signals received by the summing module.
Embodiments of the device may include one or more of the following features. For example, each pair of the first set of one or more devices, the second set of one or more devices, the third set of one or more devices, and the fourth set of one or more devices may be mutually exclusive.
In some embodiments, the first configuration of the configurable connection path is configured to (1) provide a copy of the first set of optical signals as a third set of optical signals, and (2) provide one or more signals from the first set of one or more devices and one or more signals from the second set of one or more devices to a summing module, the summing module configured to produce an electrical signal representing a sum of values encoded on at least two different signals received by the summing module.
In some embodiments, the first configuration of the configurable connection path may be configured to provide a copy of the first set of optical signals as a third set of optical signals, and the second configuration of the configurable connection path may be configured to provide one or more signals from the first set of one or more devices and one or more signals from the second set of one or more devices to a summing module, the summing module configured to produce an electrical signal representing a sum of values encoded on signals received by the summing module.
In another aspect, an apparatus comprises: a plurality of optical waveguides, wherein a set of a plurality of input values are encoded on respective optical signals carried by the optical waveguides; a plurality of replica modules, for each of at least two subsets of the one or more optical signals, the plurality of replica modules comprising a respective set of one or more replica modules configured to divide the subset of the one or more optical signals into two or more replicas of the optical signal; a plurality of multiplication modules, for each of the at least two copies of the first subset of one or more optical signals, the plurality of multiplication modules including a respective multiplication module configured to multiply the one or more optical signals of the first subset by one or more values using optical amplitude modulation; and one or more summation modules, the one or more summation modules comprising, for the results of the two or more multiplication modules, a summation module configured to produce an electrical signal representing a sum of the results of the two or more multiplication modules, wherein the result comprises at least one result encoded on the electrical signal, and the result is derived from a copy of the optical signal that propagates through no more than a single optical amplitude modulator before being converted into the electrical signal.
In another aspect, a system comprises: a first unit configured to generate a plurality of modulator control signals; and a processor comprising: a light source configured to provide a plurality of light outputs; a plurality of optical modulators coupled to the light source and the first unit, the plurality of optical modulators configured to generate an optical input vector by modulating a plurality of optical outputs provided by the light source based on a plurality of modulator control signals, the optical input vector comprising a plurality of optical signals; and a matrix multiplication unit coupled to the plurality of optical modulators and the first unit, the matrix multiplication unit configured to convert the optical input vector into an analog output vector based on the plurality of weight control signals. The computing system further includes a second unit coupled to the matrix multiplication unit and configured to convert the analog output vector to a digital output vector; and a controller comprising an integrated circuit configured to perform the following operations: receiving an artificial neural network computation request, the artificial neural network computation request comprising an input data set, the input data set comprising a first numeric input vector; receiving a first plurality of neural network weights; and generating, by the first unit, a first plurality of modulator control signals based on the first digital input vector and a first plurality of weight control signals based on the first plurality of neural network weights.
Embodiments of the system may include one or more of the following features. For example, the first unit may include a digital-to-analog converter (DAC).
In some embodiments, the second unit may include an analog-to-digital converter (ADC).
In some embodiments, the system may include a storage unit configured to store the data set and the plurality of neural network weights.
In some embodiments, the integrated circuit of the controller may be further configured to perform operations including storing the input data set and the first plurality of neural network weights in the memory unit.
In some embodiments, the first unit may be configured to generate a plurality of weight control signals.
In some embodiments, the controller may comprise an Application Specific Integrated Circuit (ASIC), and receiving the artificial neural network computation request may comprise receiving the artificial neural network computation request from a general purpose data processor.
In some embodiments, the first unit, the processing unit, the second unit, and the controller may be disposed on at least one of a multi-chip module or an integrated circuit. Receiving the artificial neural network computation request may include receiving the artificial neural network computation request from a second data processor, wherein the second data processor may be external to the multi-chip module or integrated circuit, the second data processor may be coupled to the multi-chip module or integrated circuit through a communication channel (communication channel), and the processing unit may process data at a data rate that is at least an order of magnitude greater than a data rate of the communication channel.
In some embodiments, the first unit, the processing unit, the second unit and the controller may be used for a photo-electric processing cycle that is repeated in a plurality of iterations, and the photo-electric processing cycle comprises: (1) at least a first light modulation operation based on at least one of the plurality of modulator control signals, and at least a second light modulation operation based on at least one of the weight control signals, and (2) at least one of (a) an electrical summing operation or (b) an electrical storage operation.
In some embodiments, the photovoltaic processing cycle may include an electrical storage operation, and the electrical storage operation is performed using a memory unit coupled to the controller, wherein the operations performed by the controller may further include storing the input data set and the first plurality of neural network weights in the memory unit.
In some embodiments, the optoelectronic processing cycle may include an electrical summation operation, and the electrical summation operation may be performed using an electrical summation module within the matrix multiplication unit, wherein the electrical summation module may be configured to generate currents corresponding to elements of an analog output vector representing a sum of respective elements of the optical input vector multiplied by respective neural network weights.
In some embodiments, the electro-optical processing loop may include at least one signal path on which no more than one first light modulation operation is performed in a single loop iteration based on at least one of the plurality of modulator control signals and no more than one second light modulation operation is performed in a single loop iteration based on at least one of the weight control signals.
In some embodiments, the first light modulation operation may be performed by one of a plurality of light modulators coupled to a light source of the light output and the matrix multiplication unit, and the second light modulation operation may be performed by a light modulator included in the matrix multiplication unit.
In some embodiments, the electro-optical processing loop may include at least one signal path on which no more than one electrical storage operation is performed in a single loop iteration.
In some embodiments, the light source may include a laser unit configured to produce a plurality of light outputs.
In some embodiments, the matrix multiplication unit may include: an input waveguide array for receiving an optical input vector, and the optical input vector comprises a first array of optical signals; an optical interference unit in optical communication with the input waveguide array for performing a linear transformation of the optical input vector into a second optical signal array; and an array of output waveguides in optical communication with the optical interference unit for guiding the second array of optical signals, wherein at least one input waveguide in the array of input waveguides is in optical communication with each output waveguide in the array of output waveguides through the optical interference unit.
In some embodiments, the optical interference unit may include: a plurality of interconnected Mach-Zehnder interferometers (MZIs), each of the plurality of interconnected MZIs comprising: a first phase shifter configured to change a splitting ratio of the MZI; and a second phase shifter configured to shift a phase of one output of the MZI, wherein the first phase shifter and the second phase shifter are coupled to the plurality of weight control signals.
In some embodiments, the matrix multiplication unit may include: a plurality of replica modules, wherein each replica module corresponds to a subset of the one or more optical signals of the optical input vector and is configured to split the subset of the one or more optical signals into two or more replicas of the optical signal; a plurality of multiplication modules, wherein each multiplication module corresponds to a subset of the one or more optical signals and is configured to multiply the one or more optical signals of the subset by one or more matrix element values using optical amplitude modulation; and one or more summation modules, wherein each summation module is configured to produce an electrical signal representing a sum of results of two or more of the multiplication modules.
In some embodiments, the at least one multiplication module comprises an optical amplitude modulator comprising one input port and two output ports, and a pair of correlated optical signals may be provided from the two output ports such that a difference between the amplitudes of the correlated optical signals corresponds to a result of multiplying the input value by the signed matrix element value.
In some embodiments, the matrix multiplication unit may be configured to multiply the light input vector by a matrix comprising one or more matrix element values.
In some embodiments, a set of multiple output values may be encoded on the respective electrical signals generated by the one or more summation modules, and an output value of the set of multiple output values may represent an element of an output vector generated by multiplying the optical input vector by the matrix.
In some embodiments, the system may include a memory unit configured to store the input data set and the neural network weights, the second unit may include an analog-to-digital conversion (ADC) unit, and the operations may further include: obtaining a first plurality of digital outputs from the ADC unit corresponding to the analog output vector of the matrix multiplication unit, the first plurality of digital outputs forming a first digital output vector; performing a non-linear transformation on the first digital output vector to produce a first transformed digital output vector; and storing the first transformed digital output vector in a memory unit.
In some embodiments, the system has a first cycle period defined as the time elapsed between the step of storing the input data set and the first plurality of neural network weights in the storage unit and the step of storing the first transformed digital output vector in the storage unit, and wherein the first cycle period is less than or equal to 1 ns.
In some embodiments, the operations may further comprise: an artificial neural network output generated based on the first transformed digital output vector is output.
In some embodiments, the first unit may comprise a digital-to-analog conversion (DAC) unit, and the operations may further comprise: a second plurality of modulator control signals is generated by the DAC unit based on the first converted digital output vector.
In some embodiments, the first unit may comprise a digital-to-analog conversion (DAC) unit, the artificial neural network computation request may further comprise a second plurality of neural network weights, and wherein the operations may further comprise: based on the obtaining of the first plurality of digital outputs, a second plurality of weight control signals is generated by the DAC unit based on the second plurality of neural network weights.
In some embodiments, the first plurality of neural network weights and the second plurality of neural network weights may correspond to different layers of the artificial neural network.
In some embodiments, the first unit may comprise a digital-to-analog conversion (DAC) unit, and the input data set may further comprise a second digital input vector. The operations may further include: generating, by the DAC unit, a second plurality of modulator control signals based on a second digital input vector; obtaining a second plurality of digital outputs from the ADC unit corresponding to the analog output vector of the matrix multiplication unit, the second plurality of digital outputs forming a second digital output vector; performing a non-linear transformation on the second digital output vector to produce a second transformed digital output vector; storing the second transformed digital output vector in a storage unit; and outputting an artificial neural network output generated based on the first transformed digital output vector and the second transformed digital output vector. The analog output vector of the matrix multiplication unit may be generated by a second optical input vector generated based on a second plurality of modulator control signals, the second optical input vector being converted by the matrix multiplication unit based on the first-mentioned plurality of weight control signals.
In some embodiments, the system may include a memory unit configured to store the input data sets and the neural network weights, and the second unit may include an analog-to-digital conversion (ADC) unit. The system may further comprise: an analog nonlinear unit disposed between the matrix multiplication unit and the ADC unit, the analog nonlinear unit configurable to receive a plurality of output voltages from the matrix multiplication unit, apply a nonlinear transfer function, and output a plurality of converted output voltages to the ADC unit. The operations performed by the integrated circuit of the controller may further include: obtaining a first plurality of converted digital output voltages corresponding to the plurality of converted output voltages from the ADC unit, the first plurality of converted digital output voltages forming a first converted digital output vector; and storing the first transformed digital output vector in a memory unit.
In some embodiments, the integrated circuit of the controller may be configured to generate the first plurality of modulator control signals at a rate greater than or equal to 8 GHz.
In some embodiments, the first unit may include a digital-to-analog conversion (DAC) unit and the second unit may include an analog-to-digital conversion (ADC) unit. The matrix multiplication unit may include: a light matrix multiplication unit coupled to the plurality of light modulators and the DAC unit, the light matrix multiplication unit configured to convert a light input vector into a light output vector based on a plurality of weight control signals; and a photo detection unit coupled to the light matrix multiplication unit and configured to generate a plurality of output voltages corresponding to the light output vectors.
In some embodiments, the system may further comprise: an analog storage unit disposed between the DAC unit and the plurality of light modulators, the analog storage unit configured to store an analog voltage and output the stored analog voltage; and an analog nonlinear unit disposed between the photodetection unit and the ADC unit, the analog nonlinear unit configured to receive a plurality of output voltages from the photodetection unit, apply a nonlinear transfer function, and output a plurality of converted output voltages.
In some embodiments, the analog memory cell may include a plurality of capacitors.
In some embodiments, the analog memory cell may be configured to receive and store a plurality of converted output voltages of the analog nonlinear cell, and output the stored plurality of converted output voltages to the plurality of optical modulators. The operations may further include: storing a plurality of converted output voltages of an analog non-linear unit in an analog storage unit based on generating a first plurality of modulator control signals and a first plurality of weight control signals; outputting the stored converted output voltage through the analog memory cell; obtaining a second plurality of converted digital output voltages from the ADC unit, the second plurality of converted digital output voltages forming a second converted digital output vector; and storing the second transformed digital output vector in the memory unit.
In some embodiments, the system may include a storage unit configured to store the input data set and the neural network weights, and the input data set of the artificial neural network computation request may include a plurality of numerical input vectors. The light source may be configured to generate a plurality of wavelengths. The plurality of light modulators may include: an optical modulator group configured to generate a plurality of optical input vectors, each optical modulator group corresponding to one of a plurality of wavelengths and generating a respective optical input vector having a respective wavelength; and an optical multiplexer configured to combine the plurality of optical input vectors into a combined optical input vector comprising a plurality of wavelengths. The photodetection unit may be further configured to demultiplex the plurality of wavelengths and generate a plurality of demultiplexed output voltages. The operations may include: obtaining a plurality of digital demultiplexed optical outputs from the ADC unit, the plurality of digital demultiplexed optical outputs forming a plurality of first digital output vectors, wherein each of the plurality of first digital output vectors corresponds to one of the plurality of wavelengths; performing a non-linear transformation on each of the plurality of first digital output vectors to produce a plurality of transformed first digital output vectors; and storing the plurality of transformed first digital output vectors in a memory unit. Each of the plurality of digital input vectors corresponds to one of the plurality of light input vectors.
In some embodiments, the system may include a storage unit configured to store the input data set and the neural network weights, the second unit may include an analog-to-digital conversion (ADC) unit, and the artificial neural network computation request may include a plurality of digital input vectors. The light source may be configured to generate a plurality of wavelengths. The plurality of light modulators may include: an optical modulator group configured to generate a plurality of optical input vectors, each optical modulator group corresponding to one of a plurality of wavelengths and generating a respective optical input vector having a respective wavelength; and an optical multiplexer configured to combine the plurality of optical input vectors into a combined optical input vector comprising a plurality of wavelengths. The operations may include: obtaining a first plurality of digital light outputs from the ADC unit corresponding to a light output vector, the light output vector comprising a plurality of wavelengths, the first plurality of digital light outputs forming a first digital output vector; performing a non-linear transformation on the first digital output vector to produce a first transformed digital output vector; and the first transformed digital output vector in a storage unit.
In some embodiments, the first unit may include a digital-to-analog conversion (DAC) unit, the second unit may include an analog-to-digital conversion (ADC) unit, and the DAC unit may include: a 1-bit DAC subunit configured to generate a plurality of 1-bit modulator control signals. The resolution of the ADC unit may be 1 bit and the resolution of the first digital input vector may be N bits. The operations may include: decomposing the first digital input vector into N1-bit input vectors, each of the N1-bit input vectors corresponding to one of the N bits of the first digital input vector; generating, by a 1-bit DAC subunit, a sequence of N1-bit modulator control signals corresponding to N1-bit input vectors; obtaining from the ADC unit a sequence of N digital 1-bit optical outputs corresponding to a sequence of N1-bit modulator control signals; constructing an N-bit digital output vector from a sequence of N digital 1-bit optical outputs; performing a non-linear transformation on the constructed N-bit digital output vector to produce a transformed N-bit digital output vector; and storing the transformed N-bit digital output vector in a memory unit.
In some embodiments, the system may include a storage unit configured to store the input data set and the neural network weights. The memory cell may include: a digital input vector memory configured to store a first digital input vector and comprising at least one SRAM; and a neural network weight store configured to store a plurality of neural network weights and comprising at least one DRAM.
In some embodiments, the first unit may include a digital-to-analog conversion (DAC) unit, the digital-to-analog conversion unit including: a first DAC subunit configured to generate a plurality of modulator control signals; and a second DAC subunit configured to generate a plurality of weight control signals, wherein the first DAC subunit and the second DAC subunit are different.
In some embodiments, the light source may include: a laser source configured to generate light; and an optical power splitter configured to split light generated by the laser source into a plurality of optical outputs, wherein each of the plurality of optical outputs has substantially the same power.
In some embodiments, the plurality of optical modulators includes one of a MZI modulator, a ring resonance modulator, or an electro-absorption modulator.
In some embodiments, the photodetecting unit may include: a plurality of photodetectors; and a plurality of amplifiers configured to convert the photocurrent generated by the photodetector into a plurality of output voltages.
In some embodiments, the integrated circuit may be an application specific integrated circuit.
In some embodiments, the system may include a plurality of optical waveguides coupled between the optical modulator and the matrix multiplication unit, wherein the optical input vector may include a set of multiple input values encoded on respective optical signals carried by the optical waveguides, and each optical signal carried by one of the optical waveguides may include an optical wave having a common wavelength that is substantially the same for all of the optical signals.
In some embodiments, the replica module can include at least one replica module having an optical splitter that transmits a predetermined proportion of the power of the optical wave at the input port to the first output port and transmits the remaining proportion of the power of the optical wave at the input port to the second output port.
In some embodiments, the optical splitter may include a waveguide splitter that transmits a predetermined proportion of the power of the optical wave guided by the input optical waveguide to the first output optical waveguide and transmits the remaining proportion of the power of the optical wave guided by the input optical waveguide to the second output optical waveguide.
In some embodiments, the guided mode of the input optical waveguide may be adiabatically (adiabatically) coupled to the guided mode of each of the first output optical waveguide and the second output optical waveguide.
In some embodiments, the optical splitter may include a beam splitter including at least one surface that transmits a predetermined proportion of the power of the optical wave at the input port and reflects the remaining proportion of the power of the optical wave at the input port.
In some embodiments, at least one of the plurality of optical waveguides may include an optical fiber coupled to an optical coupler, the optical coupler coupling a guided mode of the optical fiber to a free-space propagation mode.
In some embodiments, the multiplication module may include at least one coherence-sensitive multiplication module configured to multiply the first subset of one or more optical signals by one or more matrix element values using optical amplitude modulation based on interference between optical waves, the optical waves having a coherence length that is at least as long as a propagation distance through the coherence-sensitive multiplication module.
In some embodiments, the coherence-sensitive multiplication module can include a mach-zehnder interferometer (MZI) that splits a lightwave guided by an input optical waveguide into a first optical waveguide arm of the MZI and a second optical waveguide arm of the MZI, the first optical waveguide arm including a phase shifter that produces a relative phase shift with respect to a phase delay of the second optical waveguide arm, and the MZI can combine lightwaves from the first optical waveguide arm and the second optical waveguide arm into at least one output optical waveguide.
In some embodiments, the MZI may combine light waves from the first and second optical waveguide arms into each of the first and second output optical waveguides, the first photo-detector may receive the light waves from the first output optical waveguide to generate a first photocurrent, the second photo-detector may receive the light waves from the second output optical waveguide to generate a second photocurrent, and the result of the coherence-sensitive multiplication module may include a difference between the first photocurrent and the second photocurrent.
In some embodiments, the coherence sensitive multiplication module can include one or more ring resonators including at least one ring resonator coupled to the first optical waveguide and at least one ring resonator coupled to the second optical waveguide.
In some embodiments, the first photo detector may receive a light wave from the first optical waveguide to generate a first photocurrent, the second photo detector may receive a light wave from the second optical waveguide to generate a second photocurrent, and the result of the coherence sensitive multiplication module may include a difference between the first photocurrent and the second photocurrent.
In some embodiments, the multiplication module may include at least one coherent insensitive multiplication module configured to multiply the first subset of one or more optical signals by one or more matrix element values using optical amplitude modulation based on energy absorption within the optical waves.
In some embodiments, the coherent insensitive multiplication module may include an electro-absorption modulator.
In some embodiments, the one or more summing modules may include at least one summing module having: (1) two or more input conductors, each input conductor carrying an electrical signal in the form of an input current, the magnitude of the input current being representative of a respective result of a respective one of the multiplication modules, and (2) at least one output conductor carrying an electrical signal representative of a sum of the respective results in the form of an output current, the output current being proportional to the sum of the input currents.
In some embodiments, the two or more input and output conductors may include wires that contact at one or more junctions between the wires, and the output current is substantially equal to the sum of the input currents.
In some embodiments, at least a first one of the input currents may be provided in the form of at least one photocurrent generated by at least one photodetector receiving an optical signal generated by a first one of the multiplication modules.
In some embodiments, the first input current may be provided as a difference between two photocurrents generated by different respective photodetectors that receive different respective optical signals generated by the first multiplication module.
In some embodiments, one of the copies of the first subset of one or more optical signals may consist of a single optical signal, wherein one of the input values is encoded on the single optical signal.
In some embodiments, a multiplication module corresponding to a copy of the first subset may multiply the encoded input value by a single matrix element value.
In some embodiments, one of the copies of the first subset of one or more optical signals on which the plurality of input values are encoded may include more than one, and less than all, of the optical signals.
In some embodiments, a multiplication module corresponding to a copy of the first subset may multiply the encoded input values by different respective matrix element values.
In some embodiments, different multiplication modules corresponding to different respective copies of the first subset of one or more optical signals may be included by different devices in optical communication to transmit one of the copies of the first subset of one or more optical signals between the different devices.
In some embodiments, at least one of two or more of the plurality of optical waveguides, two or more of the plurality of replica modules, two or more of the plurality of multiplication modules, and one or more summation modules may be disposed on a substrate of a common device.
In some embodiments, the apparatus performs a vector matrix multiplication, wherein the input vector may be provided as a set of optical signals and the output vector may be provided as a set of electrical signals.
In some embodiments, the apparatus may further comprise an accumulator that combines the input electrical signal corresponding to the output of the multiplication module or the summation module, wherein the input electrical signal may be encoded using time-domain coding using switching amplitude modulation within each of the plurality of time slots, and the accumulator may generate the output electrical signal, the output electrical signal being encoded at more than two amplitude levels, the amplitude levels corresponding to different duty cycles of the time-domain coding over the plurality of time slots.
In some embodiments, each of the two or more of the multiplication modules corresponds to a different subset of the one or more optical signals.
In some embodiments, the apparatus may further include a multiplication module for each copy of a second subset of the one or more optical signals different from the optical signals in the first subset of the one or more optical signals, configured to multiply the one or more optical signals of the second subset by the one or more matrix element values using optical amplitude modulation.
In another aspect, a system comprises: a storage unit configured to store the data set and a plurality of neural network weights; and a driver unit configured to generate a plurality of modulator control signals. The system includes an optoelectronic processor comprising: a light source configured to provide a plurality of light outputs; a plurality of optical modulators coupled to the light source and the driver unit, the plurality of optical modulators configured to generate a light input vector by modulating a plurality of light outputs generated by the light source based on a plurality of modulator control signals; a matrix multiplication unit coupled to the plurality of optical modulators and the driver unit, the matrix multiplication unit configured to convert an optical input vector into an analog output vector based on a plurality of weight control signals; and a comparator unit coupled to the matrix multiplication unit and configured to convert the analog output vector into a plurality of digital 1-bit outputs. The system includes a controller including an integrated circuit configured to: receiving an artificial neural network computation request comprising an input data set and a first plurality of neural network weights, wherein the input data set comprises a first digital input vector having an N-bit resolution; storing the input data set and the first plurality of neural network weights in a memory unit; decomposing the first digital input vector into N1-bit input vectors, each of the N1-bit input vectors corresponding to one of the N bits of the first digital input vector; generating, by a driver unit, a sequence of N1-bit modulator control signals corresponding to N1-bit input vectors; obtaining from the comparator unit a sequence of N digital 1-bit outputs corresponding to the sequence of N1-bit modulator control signals; constructing an N-bit digital output vector from the sequence of N digital 1-bit outputs; performing a non-linear transformation on the constructed N-bit digital output vector to produce a transformed N-bit digital output vector; and storing the transformed N-bit digital output vector in a memory unit.
Embodiments of the system may include one or more of the following features. For example, receiving an artificial neural network computation request may include receiving an artificial neural network computation request from a general purpose computer (general purpose computer).
In some embodiments, the driver unit may be configured to generate a plurality of weight control signals.
In some embodiments, the matrix multiplication unit may include: a light matrix multiplication unit coupled to the plurality of light modulators and the driver unit, the light matrix multiplication unit configured to convert a light input vector into a light output vector based on a plurality of weight control signals; and a photo detection unit coupled to the light matrix multiplication unit and configured to generate a plurality of output voltages corresponding to the light output vectors.
In some embodiments, the matrix multiplication unit may include: an input waveguide array for receiving an optical input vector; an optical interference unit in optical communication with the input waveguide array for performing a linear transformation of the optical input vector into a second optical signal array; and an array of output waveguides in optical communication with the optical interference unit for guiding the second array of optical signals, wherein at least one input waveguide in the array of input waveguides is in optical communication with each output waveguide in the array of output waveguides through the optical interference unit.
In some embodiments, the optical interference unit may include: a plurality of interconnected Mach-Zehnder interferometers (MZIs), each of the plurality of interconnected MZIs comprising: a first phase shifter configured to change a splitting ratio of the MZI; and a second phase shifter configured to shift a phase of one output of the MZI, wherein the first phase shifter and the second phase shifter are coupleable to the plurality of weight control signals.
In some embodiments, the matrix multiplication unit may include: a plurality of replica modules, for each of at least two subsets of one or more optical signals of the optical input vector, the plurality of replica modules comprising a respective set of one or more replica modules configured to divide the subset of one or more optical signals into two or more replicas of the optical signal; a plurality of multiplication modules, for each of the at least two copies of the first subset of one or more optical signals, the plurality of multiplication modules including a respective multiplication module configured to multiply the one or more optical signals of the first subset by one or more matrix element values using optical amplitude modulation; and one or more summation modules, the one or more summation modules comprising, for the results of the two or more multiplication modules, a summation module configured to produce an electrical signal representing a sum of the results of the two or more multiplication modules.
In some embodiments, the at least one multiplication module may comprise an optical amplitude modulator comprising one input port and two output ports, and the pair of correlated optical signals may be provided from the two output ports such that a difference between the amplitudes of the correlated optical signals corresponds to a result of multiplying the input value by the signed matrix element value.
In some embodiments, the matrix multiplication unit may be configured to multiply the light input vector by a matrix comprising one or more matrix element values.
In some embodiments, a set of multiple output values may be encoded on the respective electrical signals generated by the one or more summation modules, and an output value of the set of multiple output values may represent an element of an output vector generated by multiplying the optical input vector by the matrix.
In another aspect, a method is provided for performing artificial neural network computations in a system having a matrix multiplication unit configured to convert an optical input vector to an analog output vector based on a plurality of weight control signals. The method comprises the following steps: receiving an artificial neural network computation request comprising an input data set and a first plurality of neural network weights, wherein the input data set comprises a first numerical input vector; storing the input data set and the first plurality of neural network weights in a memory unit; generating a first plurality of modulator control signals based on the first digital input vector and a first plurality of weight control signals based on the first plurality of neural network weights; obtaining a first plurality of digital outputs corresponding to the output vectors of the matrix multiplication unit, the first plurality of digital outputs forming a first digital output vector; performing, by a controller, a non-linear transformation on a first digital output vector to produce a first transformed digital output vector; storing the first transformed digital output vector in a memory unit; and outputting, by the controller, an artificial neural network output generated based on the first transformed digital output vector.
Embodiments of the method may include one or more of the following features. For example, receiving the artificial neural network computation request may include receiving the artificial neural network computation request from a computer over a communication channel.
In some embodiments, generating the first plurality of modulator control signals may include generating the first plurality of modulator control signals by a digital-to-analog conversion (DAC) unit.
In some embodiments, deriving the first plurality of digital outputs may include deriving the first plurality of digital outputs from an analog-to-digital conversion (ADC) unit.
In some embodiments, a method may comprise: applying a first plurality of modulator control signals to a plurality of optical modulators coupled to the light source and the DAC unit; and generating an optical input vector using the plurality of optical modulators by modulating a plurality of optical outputs generated by the laser unit based on the plurality of modulator control signals.
In some embodiments, the matrix multiplication unit may be coupled to a plurality of optical modulators and DAC units, and the method may include: a matrix multiplication unit is used to convert the optical input vector into an analog output vector based on a plurality of weight control signals.
In some embodiments, the ADC unit may be coupled to a matrix multiplication unit, and the method may comprise: the analog output vector is converted into a first plurality of digital outputs using an ADC unit.
In some embodiments, the matrix multiplication unit may include an optical matrix multiplication unit coupled to the plurality of optical modulators and the DAC unit. Converting the light input vector to the analog output vector may include converting the light input vector to the light output vector based on a plurality of weight control signals using a light matrix multiplication unit. The method can comprise the following steps: a plurality of output voltages corresponding to the light output vectors are generated using a photo-detection unit coupled to the optical matrix multiplication unit.
In some embodiments, a method may comprise: receiving an optical input vector at an input waveguide array; performing a linear transformation of the optical input vector into a second array of optical signals using an optical interference unit in optical communication with the input waveguide array; and directing the second array of optical signals using an array of output waveguides in optical communication with the optical interference unit, wherein at least one input waveguide in the array of input waveguides is in optical communication with each output waveguide in the array of output waveguides through the optical interference unit.
In some embodiments, the optical interference unit may include: a plurality of interconnected Mach-Zehnder interferometers (MZIs), each of the plurality of interconnected MZIs may include a first phase shifter and a second phase shifter, and the first phase shifter and the second phase shifter may be coupled to a plurality of weight control signals. The method can comprise the following steps: the splitting ratio of the MZI is changed using a first phase shifter and the phase of one output of the MZI is shifted using a second phase shifter.
In some embodiments, a method may comprise: for each of at least two subsets of one or more optical signals of the optical input vector, dividing the subset of one or more optical signals into two or more replicas of the optical signal using a respective set of one or more replica modules; for each of the at least two copies of the first subset of one or more optical signals, using a respective multiplication module to multiply the one or more optical signals of the first subset by one or more matrix element values using optical amplitude modulation; and for the results of the two or more multiplication modules, using a summation module configured to produce an electrical signal representing a sum of the results of the two or more multiplication modules.
In some embodiments, the at least one multiplication module may comprise an optical amplitude modulator comprising one input port and two output ports, and the pair of correlated optical signals may be provided from the two output ports such that a difference between the amplitudes of the correlated optical signals corresponds to a result of multiplying the input value by the signed matrix element value.
In some embodiments, a method may include multiplying an optical input vector by a matrix including one or more matrix element values using a matrix multiplication unit.
In some embodiments, the method may include encoding a set of multiple output values on the respective electrical signals generated by the one or more summation modules, and representing elements of an output vector using output values of the set of multiple output values, the output vector generated by multiplying the optical input vector by a matrix.
In another aspect, a method comprises: providing input information in an electronic format; converting at least a portion of the electronic input information into an optical input vector; photoelectrically converting an optical input vector into an analog output vector based on matrix multiplication; and electronically applying a non-linear transformation to the analog output vector to provide output information in an electronic format.
Embodiments of the method may include one or more of the following features. For example, the method may further comprise: the electro-optical conversion, the photoelectric conversion, and the nonlinear conversion for the electrical application are repeated for new electronic input information corresponding to output information provided in an electronic format.
In some embodiments, the matrix multiplication for the initial photoelectric conversion and the matrix multiplication for the repeated photoelectric conversion may be the same and may correspond to the same layer of the artificial neural network.
In some embodiments, the matrix multiplication for the initial photoelectric conversion and the matrix multiplication for the repeated photoelectric conversion may be different and may correspond to different layers of the artificial neural network.
In some embodiments, the method may further comprise: the electro-optical conversion, the electro-optical conversion and the non-linear transformation of the electrical application are repeated for different parts of the electrical input information, wherein the matrix multiplication for the initial electro-optical conversion and the matrix multiplication for the repeated electro-optical conversion are the same and correspond to the first layer of the artificial neural network.
In some embodiments, the method may further comprise: providing intermediate information in an electronic format based on electronic output information for a plurality of portions of electronic input information generated by a first layer of an artificial neural network; and repeating the electro-optical conversion, and the electrically applied nonlinear transformation for each of the different portions of the electronic intermediate information, wherein the matrix multiplication for the initial electro-optical conversion and the matrix multiplication for the repeated electro-optical conversion associated with the different portions of the electronic intermediate information are the same and correspond to a second layer of the artificial neural network.
In another aspect, a system is provided for performing artificial neural network computations. The system comprises: a first unit configured to generate a plurality of vector control signals and generate a plurality of weight control signals; a second unit configured to provide an optical input vector based on a plurality of vector control signals; and a matrix multiplication unit coupled to the second unit and the first unit, the matrix multiplication unit configured to convert the optical input vector into the output vector based on a plurality of weight control signals. The system includes a controller including an integrated circuit configured to: receiving an artificial neural network computation request comprising an input data set and a first plurality of neural network weights, wherein the input data set comprises a first numerical input vector; and generating, by a first unit, a first plurality of vector control signals based on the first digital input vector and a first plurality of weight control signals based on the first plurality of neural network weights; wherein the first unit, the second unit, the matrix multiplication unit and the controller are used for a photo-electric processing cycle that is repeated in a plurality of iterations, and the photo-electric processing cycle comprises: (1) at least two light modulation operations, and (2) at least one of (a) an electrical summing operation or (b) an electrical storage operation.
In another aspect, a method is provided for performing artificial neural network computations. The method comprises the following steps: providing input information in an electronic format; converting at least a portion of the electronic input information into an optical input vector; and converting the optical input vector to the output vector based on a matrix multiplication using a set of neural network weights. The providing and converting are performed in a photoelectric processing loop, the photoelectric processing loop being repeated in a plurality of iterations using different respective sets of neural network weights and different respective input information, and the photoelectric processing loop comprising: (1) at least two light modulation operations, and (2) at least one of (a) an electrical summing operation or (b) an electrical storage operation.
The details of one or more embodiments of the subject matter described in this disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the disclosure will become apparent from the description, the drawings, and the claims.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. In case of conflict with a patent application or patent application publication incorporated by reference herein, the present disclosure, including definitions, will control.
Drawings
The disclosure is best understood from the following detailed description when read with the accompanying drawing figures. It is emphasized that, according to common practice, the various features of the drawings are not to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity.
Fig. 1A is a schematic diagram of an example of an Artificial Neural Network (ANN) computing system.
Fig. 1B is a schematic diagram of an example of an optical matrix multiplication unit.
Fig. 1C and 1D are schematic diagrams of example configurations of interconnected mach-zehnder interferometers (MZIs).
FIG. 1E is a schematic diagram of an example of a MZI.
Fig. 1F is a schematic diagram of an example of a wavelength division multiplexing ann (wavelength division multiplexed ann) computing system.
Fig. 2A is a flow chart illustrating an example of a method for performing an ANN calculation.
FIG. 2B is a diagram illustrating an aspect of the method of FIG. 2A.
Fig. 3A and 3B are schematic diagrams of an example of an ANN computing system.
Fig. 4A is a schematic diagram of an example of an ANN computing system with 1-bit internal resolution (internal resolution).
Fig. 4B is a mathematical representation of the operation of the ANN computing system of fig. 4A.
Fig. 5 is a schematic diagram of an example of an Artificial Neural Network (ANN) computing system.
Fig. 6 is a schematic diagram of an example of an optical matrix multiplication unit.
Fig. 7 is a schematic diagram of an example of an Artificial Neural Network (ANN) computing system.
Fig. 8 is a diagram of an example of an optical matrix multiplication unit.
Fig. 9 is a schematic diagram of an example of an Artificial Neural Network (ANN) computing system.
Fig. 10 is a diagram of an example of an optical matrix multiplication unit.
Fig. 11 is a diagram of an example of a compact matrix multiplier unit (compact matrix multiplier unit).
Fig. 12A shows a diagram of a comparison photon matrix multiplier cell.
FIG. 12B is a diagram of a compact interconnection interferometer.
Fig. 13 is a diagram of a compact matrix multiplier cell.
Fig. 14 is a diagram of generating an optical reactive network (optical reactive network).
FIG. 15 is a diagram of a Mach-Zehnder interferometer.
Fig. 16, 17A, and 17B are diagrams of photonic circuits.
FIG. 18 is a schematic diagram of an example of an optoelectronic computing system.
Fig. 19A and 19B are schematic diagrams of example system configurations.
Fig. 20A is a schematic diagram of an example of a symmetric differential configuration (symmetric differential configuration).
Fig. 20B and 20C are circuit diagrams of examples of the system module.
Fig. 21A is a schematic diagram of an example of a symmetric differential configuration.
Fig. 21B is a schematic diagram of an example of the system configuration.
Fig. 22A is a schematic diagram of an example optical amplitude modulator.
Fig. 22B-22D are schematic diagrams of examples of optical amplitude modulators using optical detection in a symmetric differential configuration.
Fig. 23A to 23C are photoelectric circuit diagrams of an example system configuration.
24A-24E are schematic diagrams of example computing systems using multiple optoelectronic systems.
Fig. 25 is a flow chart illustrating an example of a method for performing an ANN calculation.
Fig. 26 and 27 are schematic diagrams of examples of ANN computing systems.
Fig. 28 is a schematic diagram of an example of a neural network computing system using a passive 2D optical matrix multiplication unit (passive 2D optical matrix multiplication unit).
FIG. 29 is a schematic diagram of an example of a neural network computing system using a passive 3D light matrix multiplication unit.
FIG. 30 is a schematic diagram of an example of an artificial neural network computing system with 1-bit internal resolution, where the system uses a passive 2D light matrix multiplication unit.
FIG. 31 is a schematic diagram of an example of an artificial neural network computing system with 1-bit internal resolution, where the system uses a passive 3D light matrix multiplication unit.
Fig. 32A is a schematic diagram of an example of an Artificial Neural Network (ANN) computing system.
Fig. 32B is a schematic diagram of an example of the photoelectric matrix multiplication unit.
Fig. 33 is a flow chart illustrating an example of a method for performing an ANN calculation using an optoelectronic processor.
FIG. 34 is a diagram illustrating an aspect of the method of FIG. 33.
Fig. 35A is a schematic diagram of an example of a wavelength division multiplexing ANN computing system using an electro-optical processor.
Fig. 35B and 35C are schematic diagrams of examples of the wavelength division multiplexing photoelectric matrix multiplication unit.
Fig. 36 and 37 are schematic diagrams of examples of an ANN calculation system using a photoelectric matrix multiplication unit.
FIG. 38 is a schematic diagram of an example of an artificial neural network computing system with 1-bit internal resolution, where the system uses an opto-electronic matrix multiplication unit.
Fig. 39A is a schematic diagram of an example of a mach-zehnder modulator.
Fig. 39B is a graph showing an intensity-voltage curve of the mach-zehnder modulator of fig. 39A.
FIG. 40 is a schematic diagram of a homodyne detector.
FIG. 41 is a schematic diagram of a computing system including optical fibers, each of which carries a signal having a plurality of wavelengths.
Fig. 42 is a graph of modulation value probability distributions and an example relationship between modulator power and modulation value.
FIG. 43 is a diagram of an example of a Mach-Zehnder modulator.
Fig. 44 is a diagram of an example of a charge-pump bandwidth boosting circuit.
Fig. 45A-45G are diagrams of example layouts of portions of a photonic integrated circuit and an electronic integrated circuit on a die in a controlled collapse chip connection configuration.
Like reference numbers and designations in the various drawings indicate like elements.
Detailed Description
Fig. 1A illustrates a diagram of an example of an Artificial Neural Network (ANN) computing system 100. System 100 includes a controller 110, a memory unit 120, a digital-to-analog conversion (DAC) unit 130, an optical processor 140, and an analog-to-digital conversion (ADC) unit 160. The controller 110 is coupled to the computer 102, the memory unit 120, the DAC unit 130, and the ADC unit 160. The controller 110 includes an integrated circuit configured to control the operation of the ANN computing system 100 to perform ANN computations.
The integrated circuit of the controller 110 may be an application specific integrated circuit specifically configured to perform the steps of the ANN calculation process. For example, the integrated circuit may implement microcode or firmware specific to performing ANN computation processing. As such, the controller 110 may have a reduced instruction set relative to general-purpose processors used in conventional computers (e.g., the computer 102). In some embodiments, the integrated circuit of the controller 110 may include two or more circuits configured to perform different steps of the ANN calculation process.
In an example operation of the ANN computing system 100, the computer 102 may issue an artificial neural network computation request to the ANN computing system 100. The ANN calculation request may include neural network weights defining the ANN, and an input data set processed by the provided ANN. The controller 110 receives the ANN calculation request and stores the input data set and the neural network weights in the storage unit 120.
The input data set may correspond to various digital information to be processed by the ANN. Examples of input data sets include image files, audio (audio) files, LiDAR (LiDAR) point clouds, and GPS coordinate sequences, and the operation of the ANN computing system 100 will be described based on receiving the image files as input data sets. In general, the size of an input data set can vary widely, from hundreds of data points (data points) to millions of data points or more. For example, a digital image file having a 1 million pixels (megapixel) resolution has approximately one million pixels, and each of the one million pixels may be a data point processed by the ANN. Due to the large number of data points in a typical input data set, the input data set is typically divided into a plurality of digital input vectors of smaller size to be processed separately by the light processor 140. As an example, for a gray scale digital image (greyscale digital image), the elements of the digital input vector may be 8-bit values representing the image intensity, and the digital input vector may have a length ranging from tens of elements (e.g., 32 elements, 64 elements) to hundreds of elements (e.g., 256 elements, 512 elements). In general, an input data set of arbitrary size may be divided into digital input vectors of a size suitable for processing by the light processor 140. In case the number of elements of the input data set is not evenly divisible by the length of the digital input vector, zero padding (zero padding) may be used to pad the data set such that it is evenly divisible by the length of the digital input vector. The processed outputs of the respective digital input vectors may be processed to reconstruct a complete output, which is the result of processing the input data set by the ANN. In some embodiments, the splitting of the input data set into a plurality of input vectors and subsequent vector-level processing may be implemented using block matrix multiplication techniques (block matrix multiplication techniques).
Neural network weights are a set of values that define the connectivity (connectivity) of the artificial neurons of the ANN, including the relative importance or weight of those connections. The ANN may include one or more hidden layers with corresponding node sets. In the case of an ANN with a single hidden layer, the ANN may be defined by two sets of neural network weights, one set corresponding to the connectivity between the input nodes and the nodes of the hidden layer, and a second set corresponding to the connectivity between the hidden layer and the output nodes. Each set of neural network weights describing connectivity corresponds to a matrix implemented by the optical processor 140. For ANN's with two or more hidden layers, an additional set of neural network weights are needed to define connectivity between the additional hidden layers. As such, in a typical case, the neural network weights included in the ANN calculation request may include multiple sets of neural network weights that represent connectivity between respective layers of the ANN.
Since the input data set to be processed is typically divided into a plurality of smaller digital input vectors for separate processing, the input data set is typically stored in a digital memory. However, the speed of memory operations between the memory and processors of the computer 102 is significantly slower than the rate at which the ANN computing system 100 can perform ANN calculations. For example, the ANN computing system 100 may perform tens to hundreds of ANN computations during a typical memory read period of the computer 102. As such, during the process of processing the ANN calculation request, if the ANN calculation of the ANN calculation system 100 involves multiple data transfers between the system 100 and the computer 102, the rate at which the ANN calculation can be performed by the ANN calculation system 100 may be limited below its full processing rate. For example, if the computer 102 were to access an input data set from its own storage and provide a digital input vector to the controller 110 upon request, the operation of the ANN computing system 100 may be significantly slowed by the time required for the series of data transfers required between the computer 102 and the controller 110. Notably, the memory access latency (latency) of the computer 102 is typically non-deterministic, which further complicates and slows the speed at which the digital input vector may be provided to the ANN computing system 100. Furthermore, processor cycles of the computer 102 may be wasted in managing data transfers between the computer 102 and the ANN computing system 100.
Rather, in some embodiments, the ANN computing system 100 stores the entire input data set in the storage unit 120, the storage unit 120 being part of the ANN computing system 100 and dedicated to the ANN computing system 100. The dedicated storage unit 120 allows transactions (transactions) between the storage unit 120 and the controller 110 to be particularly suitable for allowing a smooth and uninterrupted data flow between the storage unit 120 and the controller 110. This uninterrupted data flow can significantly improve the overall throughput of the ANN computing system 100 by allowing the optical processor 140 to perform matrix multiplication at its full processing rate without being limited by the slow memory operations of a conventional computer (e.g., computer 102). Furthermore, because all of the data needed in performing the ANN calculation is provided by the computer 102 to the ANN computing system 100 in a single transaction, the ANN computing system 100 can perform its ANN calculation in an exclusive manner independent of the computer 102. This unique operation of the ANN computing system 100 reduces the computational burden on the computer 102 and eliminates external dependencies in the operation of the ANN computing system 100, improving the performance of the system 100 and the computer 102.
The internal operation of the ANN computing system 100 will now be described. The light processor 140 includes a laser unit 142, a modulator array 144, a detection unit 146, and an Optical Matrix Multiplication (OMM) unit 150. The optical processor 140 operates by encoding a length N digital input vector onto a length N optical input vector and propagating the optical input vector through the OMM unit 150. The OMM unit 150 receives an optical input vector of length N and performs an N × N matrix multiplication on the received optical input vector in the optical domain. The N × N matrix multiplication performed by the OMM unit 150 is determined by the internal configuration of the OMM unit 150. The internal configuration of the OMM unit 150 may be controlled by an electrical signal, such as the electrical signal generated by the DAC unit 130.
The OMM unit 150 may be implemented in various ways. Fig. 1B shows a diagram of an example of the OMM unit 150. The OMM unit 150 may include an array of input waveguides 152 to receive the optical input vectors; an optical interference unit 154 in optical communication with the array of input waveguides 152; and an array of output waveguides 156 in optical communication with the optical interference unit 154. The optical interference unit 154 linearly transforms the optical input vector into a second optical signal array. The array of output waveguides 156 guides the array of second optical signals output by the optical interference unit 154. At least one of the array of input waveguides 152 is in optical communication with each of the array of output waveguides 156 through an optical interference unit 154. For example, for an optical input vector of length N, the OMM unit 150 may include N input waveguides 152 and N output waveguides 156.
The optical interference unit may include a plurality of interconnected mach-zehnder interferometers (MZIs). Fig. 1C and 1D show diagrams of examples of configurations 157 and 158 of an interconnect MZI. The MZIs may be interconnected in various ways (e.g., in configurations 157 or 158) to enable linear transformation of the optical input vector received by the array of input waveguides 152.
FIG. 1E shows a diagram of an example of an MZI 170. The MZI 170 includes a first input waveguide 171, a second input waveguide 172, a first output waveguide 178, and a second output waveguide 179. Further, each MZI 170 of the plurality of interconnected MZIs includes a first phase shifter 174, the first phase shifter 174 configured to change a splitting ratio (splitting ratio) of the MZI 170; and a second phase shifter 176 configured to shift the phase of one output of the MZI 170, such as the light exiting the MZI 170 through a second output waveguide 179. The first phase shifter 174 and the second phase shifter 176 of the MZI 170 are coupled to a plurality of weight control signals generated by the DAC cell 130. The first phase shifter 174 and the second phase shifter 176 are examples of reconfigurable components of the OMM unit 150. Examples of the reconfiguration component include a thermo-optical phase shifter (thermo-optical phase shifter) or an electro-optical phase shifter (electro-optical phase shifter). The thermo-optic phase shifter operates by heating the waveguide to change the refractive index of the waveguide and cladding material, which translates into a change in phase. The electro-optic phase shifter operates by applying an electric field (e.g., lithium niobate (LiNbO3), reverse-biasing a PN junction) or a current (e.g., forward-biasing a PIN junction), which changes the refractive index of the waveguide material. By changing the weight control signals, the phase delay of the first 174 and second 176 phase shifters of each interconnected MZI 170 may be changed, which reconfigures the optical interference unit 154 of the OMM unit 150 to achieve a particular matrix multiplication determined by the phase delay disposed over the entire optical interference unit 154. Additional embodiments of the OMM unit 150 AND the OPTICAL interference unit 154 are disclosed in U.S. patent publication No. US 2017/0351293A1, entitled "APPARATUS AND METHODS FOR OPTICAL NEURAL NETWORK," which is incorporated herein by reference in its entirety.
An optical input vector is generated by the laser unit 142 and the modulator array 144. The length N optical input vector has N independent optical signals, each having an intensity corresponding to the value of a respective element of the length N digital input vector. As an example, the laser unit 142 may produce N optical outputs. The N light outputs have the same wavelength and are optically coherent. The optical coherence of the light outputs allows the light outputs to optically interfere with each other, which is a property utilized by the OMM unit 150 (e.g., in the operation of the MZI). Further, the light outputs of the laser units 142 may be substantially identical to each other. For example, the N light outputs may be substantially uniform in their intensities (e.g., within 5%, within 3%, within 1%, within 0.5%, within 0.1%, or within 0.01%) and in their relative phases (e.g., within 10 degrees, within 5 degrees, within 3 degrees, within 1 degree, within 0.1 degrees). The uniformity of the light output may improve the fidelity (faithfull) of the light input vector to the digital input vector, thereby improving the overall accuracy of the light processor 140. In some embodiments, the light output of the laser unit 142 may have an optical power of 0.1 to 50mW each, a wavelength in the near infrared range (e.g., between 900nm and 1600 nm), and a linewidth of less than 1 nm. The optical output of the laser unit 142 may be a single transverse mode (transverse-mode) optical output.
In some embodiments, the laser unit 142 includes a single laser source and an optical power splitter (optical power splitter). A single laser source is configured to generate laser light. The optical power splitter is configured to split light generated by the laser source into N optical outputs having substantially the same intensity and phase. By splitting a single laser output into multiple outputs, optical coherence of the multiple light outputs can be achieved. For example, the single laser source may be a semiconductor laser diode, a vertical-cavity surface-emitting laser (VCSEL), a Distributed Feedback (DFB) laser, or a Distributed Bragg Reflector (DBR) laser. For example, the optical power splitter may be 1: an N multimode interference (MMI) splitter comprising a plurality of 1: 2MMI splitter or multi-stage splitter of directional coupler (multi-stage splitter), or star coupler (star coupler). In some other embodiments, a master-slave laser configuration (master-slave laser configuration) may be used, in which the slave laser is injection locked (injection locked) by the master laser to have a stable phase relationship to the master laser.
The optical output of the laser unit 142 is coupled to a modulator array 144. The modulator array 144 is configured to receive an optical input from the laser unit 142 and modulate the intensity of the received optical input based on a modulator control signal (which is an electrical signal). Examples of the modulator include a mach-zehnder interference (MZI) modulator, a ring resonator modulator (ring resonator), and an electro-absorption modulator (electro-absorption modulator). The modulator array 144 has N modulators, each modulator receiving one of the N optical outputs of the laser unit 142. The modulator receives control signals corresponding to elements of the digital input vector and modulates the intensity of the light. The control signal may be generated by the DAC unit 130.
The DAC unit 130 is configured to generate a plurality of modulator control signals and generate a plurality of weight control signals under the control of the controller 110. For example, the DAC unit 130 receives a first DAC control signal from the controller 110, the first DAC control signal corresponding to a digital input vector to be processed by the optical processor 140. The DAC unit 130 generates modulator control signals, which are analog signals adapted to drive the modulator array 144 and the OMM 150, based on the first DAC control signal. For example, the analog signal may be a voltage or a current, depending on the technology and design of the modulators of the array 144. The voltage may have an amplitude ranging from 0.1V to 10V, and the current may have an amplitude ranging from 100 μ A to 100 mA. In some embodiments, the DAC unit 130 may include a modulator driver configured to buffer, amplify, or condition the analog signals so that the modulators of the array 144 and the OMM 150 may be adequately driven. For example, certain types of modulators may be driven with differential control signals. In this case, the modulator driver may be a differential driver that generates a differential electrical output based on a single-ended (single-ended) input signal. As another example, certain types of modulators may have a 3dB bandwidth that is less than the desired processing rate of the optical processor 140. In this case, the modulator driver may include a pre-emphasis circuit (pre-emphasis circuit) or other bandwidth enhancement circuit designed to extend the operating bandwidth of the modulator. For example, such bandwidth enhancement may be useful for modulators based on PIN diode structures that are forward biased to modulate the refractive index of a portion of a waveguide guiding a modulated optical wave using carrier injection. For example, if the modulator is an MZI modulator, a PIN diode structure may be used to implement a phase shifter in one or both waveguide arms of the MZI modulator. Configuring the phase shifter for forward bias operation facilitates shorter modulator lengths and a more compact overall design, which may be useful for an OMM unit 150 with a large number of modulators.
For example, in a pre-emphasis form of bandwidth enhancement (pre-emphasis form), the analog electrical signal (e.g., voltage or current) driving the modulator may be shaped to include transient pulses (overshoots) that overshoot changes in analog signal levels that represent a given digital data value of the DAC control signal in a series of digital data values (digital data values). Each digital data value may haveAny number of bits, including a single 1-bit data value, as assumed for the remainder of this example. Thus, if the value of a bit is the same as the previous value, the analog electrical signal driving the modulator is maintained at a steady-state level (e.g., a signal level X of bit value 0)0And an upper signal level X of bit value 11). However, if a bit changes from 0 to 1, the corresponding analog electrical signal used to drive the modulator may include a transient pulse that stabilizes at a steady-state value X1Previously, there was a peak X at the beginning of the bit transition (bit transition)1+(X1-X0). Likewise, if a bit changes from 1 to 0, the corresponding analog electrical signal used to drive the modulator may include a transient pulse that stabilizes at a steady-state value X 0Previously, there was a peak X at the beginning of the bit transition0+(X0-X1). The size and length of the temporal pulses may be selected to optimize bandwidth enhancement (e.g., to maximize the open area of the eye diagram of the non-return-to-zero (NRZ) modulation mode).
In a form of bandwidth enhanced charge pumping, the analog current signal driving the modulator can be shaped into a transient pulse that includes a moving precisely determined amount of charge. Fig. 44 shows a charge pump bandwidth enhancement circuit that uses a capacitance connected in series between a voltage source and a modulator to precisely control charge flow. A portion of the circuit shown in fig. 44 may be included in the modulator driver described above. In this embodiment, the modulator is represented by a modulator circuit 4400, the modulator circuit 4400 modeling the electrical characteristics of the phase shifter of the modulator as a PIN diode. The modulator circuit 4400 includes an ideal diode having a capacitance CdAnd a resistor having a resistance R. The pump capacitor (pump capacitor)4402 has a capacitance Cp. The control voltage waveform 4404 is provided to an inverter circuit 4405 to generate a drive voltage waveform 4406 whose amplitude can be precisely calibrated to move predetermined amounts of charge into or out of the modulator circuit 4400 through the pump capacitors 4402. By applying a constant voltage VDD _ IO at terminal 4408 The PIN diode modeling modulator circuit 4400 is forward biased. A charge pumping control voltage VCP is applied at terminal 4410 of the inverter 4405 to control the amount of charge pumped at the transitions of the drive voltage waveform 4406, as well as the corresponding optical phase shift applied by the modulator.
The value of the charge pumping control voltage VCP may be adjusted prior to operation such that the nominal charge Q stored in the charge pumping capacitor 4402 is based on the capacitance CpThe measured values may be accurately calibrated (e.g., due to manufacturing uncertainty, some variability). For example, the voltage VCP may be equal to the nominal charge Q divided by the capacitance Cp. The induced change in the index of refraction of the portion of the waveguide that intersects the PIN diode may then provide a phase shift of the guided light wave that is related to the amount of charge Q that moves between the PIN diode and the charge pumping capacitor 4402 (e.g., via internal capacitor C)dStorage) is linearly proportional. If the drive voltage changes from a low value to a high value, the current flowing from the charge pumping capacitor 4402 into the PIN diode will transfer a predetermined amount of charge (i.e., the integral of the positive current over time) in a short period of time. If the drive voltage changes from a high value to a low value, the current flowing from the PIN diode into the charge pumping capacitor 4402 will remove a predetermined amount of charge (i.e., the integral of the negative current over time) in a short period of time. After this relatively short switching time, a steady-state current is provided by current source 4412, and current source 4412 is controlled by switch 4414 to replace charge lost due to internal capacitance losing current through internal resistance R while the drive voltage is held (e.g., during the hold time for a particular digital value). Using such a charge pumping arrangement may have advantages such as better accuracy than other techniques, including some pre-emphasis techniques, since the amount of charge moved within a short switching time depends on a constant physical parameter (C) p) And a steady state control Value (VCP) and is therefore precisely controllable and repeatable.
In some embodiments, reduced power consumption may be achieved by designing the modulators of the modulator array 144 and/or the OMM unit 150 such that less power is consumed when operating the modulators to produce modulation values representing more commonly occurring coefficients and more power is consumed when operating the modulators to produce modulation values representing less commonly occurring coefficients. For example, for certain data sets known to have certain characteristics, power consumption may be reduced. Fig. 42 shows a modulation value probability distribution 4200 (dashed line) superimposed on a modulator power map 4202 (solid line) for a particular design of modulators and/or OMM units 150 of the modulator array 144. Both graphs are a function of the modulation value (on the horizontal axis) in normalized units (normalized units) to represent the coefficient between-1 and 1. In this embodiment, the data set includes various coefficients (e.g., vector coefficients and/or matrix coefficients) for artificial neural network computation, such that the Probability Distribution Function (PDF) of the coefficients yields a higher probability (and thus more frequent instances) for smaller coefficients (i.e., coefficients with relatively smaller absolute values). For such data sets ("low coefficient weight data sets"), reduced power consumption may be achieved by designing the modulator such that the modulator operates in a lower power state to perform calculations using smaller coefficients (higher frequency of occurrence in the data set) and operates in a higher power state to perform calculations using larger coefficients (lower frequency of occurrence in the data set).
Some optical amplitude modulators use relatively high power to modulate an optical signal with a small modulation value. For example, for coherent non-sensitive optical amplitude modulators, a modulation value close to zero may require a relatively high modulator power, for example for electro-absorption modulators, for large absorbed optical powers, the electro-absorption modulator needs to drive a diode-based absorber with a relatively high current to reduce the optical amplitude of the modulated optical signal. For a coherence sensitive optical amplitude modulator, a modulation value close to zero may require a relatively high modulator power, e.g. for an MZI modulator, the MZI modulator needs to drive a diode-based phase shifter with a relatively high current to provide a relative phase shift between the two MZI arms for destructive optical interference, thereby reducing the optical amplitude of the modulated signal.
The optical amplitude modulator can be configured to overcome this power relationship and achieve a modulator power as shown in fig. 42, which assigns a low power modulator state to a modulation value near zero. For example, as shown in FIG. 43, MZI modulator 4300 may be configured with asymmetric arms that provide a built-in passive relative phase shift (e.g., a phase shift around 180 degrees) such that only a small active relative phase shift (and thus low modulator power) is required for destructive optical interference. MZI modulator 4300 includes an input splitter 4302 that splits the incoming optical signal to provide 50% of the power to the first arm and 50% of the power to the second arm. The active phase shifter 4304 in the first arm provides a method of using a variable phase shift to change the modulation value over a range of possible values (in this embodiment, for unsigned modulation values between 0 and 1). The variable phase shift is determined based on the magnitude of the applied electrical signal, which requires a certain amount of supplied electrical power (e.g., a diode-based phase shifter formed of doped semiconductor material within or near the waveguide of the first arm). The passive phase shifter 4306 in the second arm provides a relative phase shift between the first arm and the second arm even if no power is applied to the MZI modulator 4300. For example, an optical material with a high index of refraction may be configured to impart a relative phase shift of 180 degrees between the arms such that the output optical combiner 4308 provides optical interference such that no significant optical power is coupled to its output. Various alternative configurations of active and passive phase shifters may be implemented, including (but not limited to): both the active phase shifter and the passive phase shifter may be in one arm, while there is no modulator or phase shifter in the other arm; both arms may have active and passive phase shifters (in a push-pull arrangement); or both arms may have active phase shifters and one arm may have passive phase shifters.
Alternatively, MZI modulators configured according to the symmetric differential configurations described herein may be used to provide coefficients close to zero using only a small active relative phase shift (and therefore low modulator power). For example, FIG. 22A shows an optical amplitude modulator constructed using MZIs configured according to a symmetric differential configuration, with the optical output detected as shown in FIG. 22B. A low modulation power is used to perform multiplication (using optical amplitude modulation) of modulation values with low amplitude (i.e. absolute value). Specifically, the low power applied to phase modulator 2204 corresponds to modulation of the low amplitude modulation value, resulting in a corresponding nearly equal separation (e.g., nearly 50%/50%) in the output of coupler 2206, and a low amplitude current at node 2216, representing the result of the multiplication. The symmetric differential configuration also has the advantage of being able to provide signed modulation values between-1 and +1 (as described in more detail below). While this implementation uses a phase modulator in a single arm of the MZI, other implementations may have other configurations, such as a push-pull arrangement with phase modulators in both arms to provide phase shifts of opposite sign.
The zero modulation power is shown in the example power profile shown in fig. 42 as being used to achieve a zero modulation value, but in other embodiments there may be a residual low but non-zero modulation power at the zero modulation value. For these low coefficient weight data sets, reduced power consumption can generally be achieved by using a modulator designed such that the modulator modulates the optical signal with a modulation value using an increased power relative to the absolute value of the modulation value. The exact shape of the modulation power as a function of modulation value may vary from implementation to implementation as the magnitude of the modulation value increases, and does not necessarily increase linearly. Different power consuming elements may be present in the optical amplitude modulator, which contribute to the overall power consumption. In some embodiments, the modulators are designed such that they modulate the optical signal with a modulation value using a power that monotonically increases with respect to the absolute value of the modulation value.
In some cases, the modulators of the array 144 and/or the OMM 150 may have a non-linear transfer function. For example, MZI optical modulators may have a non-linear relationship (e.g., sinusoidal dependence) between the applied control voltage and its transmission. In this case, the first DAC control signal may be adjusted or compensated based on the nonlinear transfer function of the modulator such that a linear relationship between the digital input vector and the generated optical input vector may be maintained. Maintaining such linearity is generally important to ensure that the input to the OMM unit 150 is an accurate representation of the digital input vector. In some embodiments, the compensation of the first DAC control signal may be performed by the controller 110 through a look-up table that maps values of the digital input vector to values to be output by the DAC cell 130 such that the resulting modulated optical signal is linearly proportional to the elements of the digital input vector. The look-up table may be generated by characterizing the nonlinear transfer function of the (characterizing) modulator and calculating the inverse of the nonlinear transfer function.
In some embodiments, the non-linearity of the modulator and the resulting non-linearity in the generated optical input vector may be compensated by an ANN calculation algorithm.
The optical input vectors generated by the modulator array 144 are input to the OMM unit 150. The optical input vector may be N spatially separated optical signals each having an optical power corresponding to an element of the digital input vector. For example, the optical power of the optical signal is generally in the range of 1 μ W to 10 mW. The OMM unit 150 receives the optical input vector and performs N × N matrix multiplication based on its internal configuration. The internal configuration is controlled by the electrical signal generated by the DAC cell 130. For example, the DAC unit 130 receives a second DAC control signal from the controller 110, the second DAC control signal corresponding to the neural network weights to be implemented by the OMM unit 150. The DAC unit 130 generates weight control signals, which are analog signals adapted to control reconfigurable components within the OMM unit 150, based on the second DAC control signal. For example, the analog signal may be a voltage or a current, depending on the type of reconfiguration component of the OMM unit 150. The voltage may have an amplitude ranging from 0.1V to 10V, and the current may have an amplitude ranging from 100 μ a to 10 mA.
The modulator array 144 may operate at a modulation rate different from the reconfiguration rate of the reconfigurable OMM unit 150. The light input vector produced by the modulator array 144 propagates through the OMM unit at an approximate proportion of the speed of light (e.g., 80%, 50%, or 25% of the speed of light), depending on the optical characteristics (e.g., effective index) of the OMM unit 150. For a typical OMM unit 150, the propagation time of the optical input vector is in the range of 1 to several 10 picoseconds, which corresponds to several 10 to several 100GHz of processing rate. As such, the rate at which the optical processor 140 can perform matrix multiplication operations is limited, in part, by the rate at which optical input vectors can be generated. Modulators with bandwidths of several 10GHz are readily available, and modulators with bandwidths exceeding 100GHz are under development. As such, for example, the modulation rate of the modulator array 144 may be in the range of 5GHz, 8GHz, or several 10GHz to several 100 GHz. To maintain operation of modulator array 144 at such modulation rates, the integrated circuit of controller 110 may be configured to output control signals for DAC cell 130 at a rate greater than or equal to, for example, 5GHz, 8GHz, 10GHz, 20GHz, 25GHz, 50GHz, or 100 GHz.
Depending on the type of reconfigurable components implemented by the OMM unit 150, the reconfiguration rate of the OMM unit 150 may be significantly slower than the modulation rate. For example, the reconfigurable components of the OMM unit 150 may be thermo-optic types that use micro-heaters to adjust the temperature of the optical waveguide of the OMM unit 150, which in turn affects the phase of the optical signal within the OMM unit 150 and results in a matrix multiplication. Due to the thermal time constant associated with heating and cooling of the structure, the reconfiguration rate can be limited to several 100kHz to several 10 MHz. As such, the modulator control signals used to control the modulator array 144 and the weight control signals used to reconfigure the OMM unit 150 may have significantly different speed requirements. Furthermore, the electrical characteristics of the modulator array 144 may differ significantly from the electrical characteristics of the reconfigurable components of the OMM unit 150.
To accommodate the different characteristics of the modulator control signals and the weight control signals, in some embodiments, the DAC cell 130 may include a first DAC subunit 132 and a second DAC subunit 134. The first DAC subunit 132 may be specifically arranged to generate the modulator control signals and the second DAC subunit 134 may be specifically arranged to generate the weight control signals. For example, the modulation rate of modulator array 144 may be 25GHz, and first DAC subunit 132 may have a per-channel output update rate of 25 gigasamples per second (GSPS) and a resolution of 8 bits or higher. The reconfiguration rate of the OMM unit 150 may be 1MHz and the second DAC sub-unit 134 may have an output update rate of 1 mega-samples per second (MSPS) and a resolution of 10 bits. Implementing separate first and second DAC sub-units 132, 134 allows for independent optimization of the DAC sub-units for respective signals, which may reduce overall power consumption, complexity, cost, or a combination thereof of the DAC unit 130. It is noted that although the first DAC sub-unit 132 and the second DAC sub-unit 134 are described as sub-components of the DAC unit 130, in general, the first DAC sub-unit 132 and the second DAC sub-unit 134 may be integrated on a common chip or may be implemented as separate chips.
Based on the different characteristics of the first DAC subunit 132 and the second DAC subunit 134, in some embodiments, the storage unit 120 may include a first storage subunit and a second storage subunit. The first memory subunit may be a memory dedicated to storing the input data set and the digital input vector and may have an operating speed sufficient to support the modulation rate. The second storage subunit may be a memory dedicated to storing neural network weights and may have an operating speed sufficient to support the reconfiguration rate of the OMM unit 150. In some embodiments, the first storage subunit may be implemented using SRAM and the second storage subunit may be implemented using DRAM. In some embodiments, the first memory subunit and the second memory subunit may be implemented using DRAMs. In some embodiments, the first storage unit may be implemented as part of the controller 110 or as a cache (cache) of the controller 110. In some embodiments, the first and second storage subunits may be implemented by a single physical storage device as different address spaces.
The OMM unit 150 outputs an optical output vector of length N, which corresponds to the result of an N × N matrix multiplication of the optical input vector and the neural network weights. The OMM unit 150 is coupled to the detection unit 146, and the detection unit 146 is configured to generate N output voltages corresponding to the N optical signals of the optical output vector. For example, the detection unit 146 may include an array of N photodetectors configured to absorb the optical signal and generate the photocurrent, and an array of N transimpedance amplifiers (transimpedance amplifiers) configured to convert the photocurrent to an output voltage. The bandwidth of the photodetectors and transimpedance amplifiers may be arranged based on the modulation rate of the modulator array 144. The photodetector may be formed of various materials based on the wavelength of the detected light output vector. Examples of materials for photodetectors include germanium, silicon-germanium alloys, and indium gallium arsenide (InGaAs).
The detection unit 146 is coupled to the ADC unit 160. The ADC unit 160 is configured to convert the N output voltages into N digital light outputs, which are quantized digital representations of the output voltages. For example, the ADC unit 160 may be an N-channel ADC. The controller 110 may derive N digital light outputs from the ADC unit 160 corresponding to the light output vector of the light matrix multiplication unit 150. The controller 110 may form a length N digital output vector from the N digital light outputs that corresponds to the result of an N x N matrix multiplication of the length N input digital vector.
The various electronic components of the ANN computing system 100 may be integrated in various ways. For example, the controller 110 may be an application specific integrated circuit fabricated on a semiconductor die. Other electronic components (e.g., memory unit 120, DAC unit 130, ADC unit 160, or a combination thereof) may be monolithically integrated on the semiconductor die on which controller 110 is fabricated. As another example, two or more electronic components may be integrated into a System-on-Chip (SoC). In an embodiment of the SoC, the controller 110, the memory unit 120, the DAC unit 130, and the ADC unit 160 may be fabricated on respective dies, and the respective dies may be integrated on a common platform (e.g., an interposer) that provides electrical connections between integrated components. Such an SoC approach may allow faster data transfer between the electronic components of the ANN computing system 100 relative to a method of separately placing and routing the components on a Printed Circuit Board (PCB), thereby increasing the operating speed of the ANN computing system 100. Furthermore, the SoC approach may allow the use of different manufacturing techniques for different electronic component optimizations, which may improve the performance of different components and reduce the overall cost of the monolithic integration approach. Although the integration of the controller 110, the memory unit 120, the DAC unit 130, and the ADC unit 160 has been described, in general, a subset of the components may be integrated, while other components are implemented as separate components for various reasons (e.g., performance or cost). For example, in some embodiments, memory unit 120 may be integrated with controller 110 as a functional block (functional block) within controller 110.
The various optical components of the ANN computing system 100 may also be integrated in various ways. Examples of the optical components of the ANN computing system 100 include a laser unit 142, a modulator array 144, an OMM unit 150, and photodetectors of a detection unit 146. These optical components may be integrated in various ways to improve performance and/or reduce cost. For example, the laser unit 142, the modulator array 144, the OMM unit 150, and the photodetector may be monolithically integrated on a common semiconductor substrate as a Photonic Integrated Circuit (PIC). On photonic integrated circuits formed based on compound semiconductor material systems, such as group III-V compound semiconductors (e.g., indium phosphide (InP)), lasers, modulators (e.g., electro-absorption modulators), waveguides, and photodetectors may be monolithically integrated on a single die. This monolithic integration approach may reduce the complexity of aligning the inputs and outputs of various separate optical components, which may require alignment accuracy ranging from sub-micron to several microns. As another example, the laser source of the laser unit 142 may be fabricated on a compound semiconductor die, and the optical power splitter of the laser unit 142, the modulator array 144, the OMM unit 150, and the photodetector of the detection unit 146 may be fabricated on a silicon die. PICs fabricated on silicon wafers, which may be referred to as silicon photonics technology, typically have greater integration density, higher lithographic (lithographic) resolution, and lower cost relative to group III-V based PICs. This greater integration density may be beneficial in the manufacture of the OMM unit 150 because the OMM unit 150 typically includes 10 to 100 optical components, such as power splitters and phase shifters. Furthermore, the higher lithographic resolution of silicon photonics may reduce the manufacturing variation of the OMM unit 150, thereby improving the accuracy of the OMM unit 150.
The ANN computing system 100 may be implemented in various form factors. For example, the ANN computing system 100 may be implemented as a co-processor (co-processor) that plugs into a host computer (host computer). Such an ANN computing system 100 may have a form factor such as a pci express (pci express) card and communicate with host computers over a PCIe bus. The host computer may host (host) a plurality of co-processor type ANN computing systems 100 and connect to the computer 102 over a network. Embodiments of this type may be applicable to cloud-based data centers, where server racks may be dedicated to processing ANN computation requests received from other computers or servers. As another example, the coprocessor type ANN computing system 100 may be plugged directly into the computer 102 that issued the ANN computation request.
In some embodiments, the ANN computing system 100 may be integrated onto a physical system that requires real-time ANN computing power. For example, systems that rely heavily on real-time artificial intelligence tasks (real-time intelligence conference tasks), such as autonomous vehicles, autonomous drones (unmanned planes), object or face recognition security cameras, and various Internet of Things (IoT) devices, may benefit from having the ANN computing system 100 directly integrated with other subsystems of such systems. The ANN computing system 100 with direct integration may enable real-time artificial intelligence in devices with poor or no network connectivity and enhance the reliability and availability of mission critical artificial intelligence systems.
Although DAC cell 130 and ADC cell 160 are shown coupled to controller 110, in some embodiments DAC cell 130, ADC cell 160, or both may alternatively or additionally be coupled to storage cell 120. For example, a Direct Memory Access (DMA) operation of the DAC unit 130 or the ADC unit 160 may reduce a calculation load on the controller 110 and reduce a delay of reading and writing to the memory unit 120, thereby further increasing an operation speed of the ANN calculation unit 100.
Fig. 2 shows a flow diagram of an example of a process 200 for performing an ANN calculation. The steps of process 200 may be performed by controller 110. In some embodiments, the respective steps of process 200 may be executed in parallel, combined, in a loop, or in any order.
At step 210, an Artificial Neural Network (ANN) computation request including an input data set and a first plurality of neural network weights is received. The input data set includes a first numeric input vector. The first digital input vector is a subset of the input data set. For example, it may be a sub-region of the image. The ANN calculation request may be generated by various entities (e.g., computer 102). The computer may include one or more of various types of computing devices, such as a personal computer, a server computer, a vehicle computer (vehicle computer), and a flight computer (flight computer). The ANN calculation request generally refers to an electrical signal informing or informing the ANN calculation system 100 that an ANN calculation is to be performed. In some embodiments, the ANN calculation request may be split into two or more signals. For example, a first signal may query the (query) ANN computing system 100 to check whether the system 100 is ready to receive the input data set and the first plurality of neural network weights. In response to an acknowledgement by the system 100, the computer may transmit a second signal comprising the input data set and the first plurality of neural network weights.
In step 220, the input data set and the first plurality of neural network weights are stored. The controller 110 may store the input data set and the first plurality of neural network weights in the memory unit 120. Storing the input data set and the first plurality of neural network weights in the memory unit 120 may allow flexibility in the operation of the ANN computing system 100, which may improve the overall performance of the system, for example. For example, the input data set may be divided into numeric input vectors of a set size and format by retrieving (retrieve) a desired portion of the input data set from the storage unit 120. Different portions of the input data set may be processed in various orders or shuffled (shredded) to allow various types of ANN calculations to be performed. For example, where the input and output matrix sizes are different, shuffling may allow matrix multiplication to be performed by block matrix multiplication techniques. As another example, storing the input data set and the first plurality of neural network weights in the memory unit 120 may allow for queuing of the plurality of ANN computation requests by the ANN computation system 100, which may allow the ANN computation system 100 to maintain operation at its full speed without periods of inactivity.
In some embodiments, the input data set may be stored in a first storage subunit and the first plurality of neural network weights may be stored in a second storage subunit.
In step 230, a first plurality of modulator control signals is generated based on the first digital input vector and a first plurality of weight control signals is generated based on the first plurality of neural network weights. The controller 110 may transmit the first DAC control signal to the DAC cell 130 to generate a first plurality of modulator control signals. The DAC cell 130 generates a first plurality of modulator control signals based on the first DAC control signal, and the modulator array 144 generates an optical input vector that represents a first digital input vector.
The first DAC control signal may comprise a plurality of digital values to be converted by the DAC unit 130 into a first plurality of modulator control signals. The plurality of digital values generally corresponds to the first digital input vector and may be associated by various mathematical relationships or look-up tables. For example, the plurality of digital values may be linearly proportional to the values of the elements of the first digital input vector. As another example, the plurality of digital values may be associated with elements of the first digital input vector through a lookup table configured to maintain a linear relationship between the digital input vector and the optical input vector produced by the modulator array 144.
The controller 110 may transmit the second DAC control signal to the DAC cell 130 to generate a first plurality of weight control signals. The DAC unit 130 generates a first plurality of weight control signals based on the second DAC control signal, and reconfigures the OMM unit 150 according to the first plurality of weight control signals to implement a matrix corresponding to the first plurality of neural network weights.
The second DAC control signal may include a plurality of digital values to be converted into a first plurality of weight control signals by the DAC unit 130. The plurality of digital values generally correspond to the first plurality of neural network weights and may be associated by various mathematical relationships or look-up tables. For example, the plurality of digital values may be linearly proportional to the first plurality of neural network weights. As another example, the plurality of digital values may be calculated by performing various mathematical operations on the first plurality of neural network weights to generate weight control signals, which may configure the OMM unit 150 to perform matrix multiplication corresponding to the first plurality of neural network weights.
In some embodiments, the first plurality of neural network weights representing the matrix M may be decomposed into M ═ USV by a Singular Value Decomposition (SVD) method, where U is an mxm unitary matrix, S is an mxn diagonal matrix with non-negative real numbers in the diagonals, and V is the complex conjugate of an nxn unitary matrix V. In this case, the first plurality of weight control signals may include a first plurality of OMM unit control signals corresponding to the matrix V and a second plurality of OMM unit control signals corresponding to the matrix S. Further, the OMM unit 150 may be configured with a first OMM subunit configured to implement the matrix V, a second OMM subunit configured to implement the matrix S, and a third OMM subunit configured to implement the matrix U, such that the OMM unit 150 as a whole implements the matrix M. The SVD method is further described in U.S. patent publication No. US 2017/0351293A1, entitled "APPATUS AND METHODS FOR OPTICAL NEURAL NETWORK," which is incorporated herein by reference in its entirety.
In step 240, a first plurality of digital light outputs corresponding to the light output vectors of the light matrix multiplication unit is obtained. The optical input vectors generated by the modulator array 144 are processed by the OMM unit 150 and converted to optical output vectors. The light output vector is detected by the detection unit 146 and converted into an electrical signal, which may be converted into a digital value by the ADC unit 160. The controller 110 may, for example, transmit a conversion request to the ADC unit 160 to begin converting the voltage output by the detection unit 146 to a digital light output. Once the conversion is completed, the ADC unit 160 may transmit the conversion result to the controller 110. Alternatively, the controller 110 may retrieve the conversion result from the ADC unit 160. The controller 110 may form a digital output vector from the digital light output, the digital output vector corresponding to a result of a matrix multiplication of the input digital vector. For example, the digital light output may be organized or concatenated (concatenated) to have a vector format.
In some embodiments, ADC unit 160 may be set or controlled to perform ADC conversion based on the DAC control signal being issued by controller 110 to DAC unit 130. For example, the ADC conversion may be set to start at a preset time after the DAC unit 130 generates the modulation control signal. Such control of the ADC conversion may simplify the operation of the controller 110 and reduce the number of necessary control operations.
In step 250, a non-linear transformation is performed on the first digital output vector to produce a first transformed digital output vector. The nodes or artificial neurons of the ANN operate by first performing a weighted sum of the signals received from the nodes of the previous layer, and then performing a nonlinear transformation ("activation") of the weighted sum to produce an output. Various types of ANN may implement various types of differentiable nonlinear transformations. Examples of the nonlinear transformation function include a modified linear unit (RELU) function, a Sigmoid function, a hyperbolic tangent function, an X2 function, and an | X | function. This non-linear transformation is performed on the first digital output by the controller 110 to produce a first transformed digital output vector. In some embodiments, the non-linear transformation may be performed by a dedicated digital integrated circuit within the controller 110. For example, controller 110 may include one or more modules or circuit blocks specifically adapted to accelerate the calculation of one or more types of non-linear transformations.
In step 260, the first transformed digital output vector is stored. The controller 110 may store the first transformed digital output vector in the memory unit 120. In the case where the input data set is divided into a plurality of digital input vectors, the first transformed digital output vector corresponds to the result of an ANN calculation of a portion of the input data set, e.g., the first digital input vector. As such, storing the first transformed digital output vector allows the ANN computing system 100 to perform and store additional computations on other digital input vectors of the input data set to be later aggregated into a single ANN output.
In step 270, an artificial neural network output generated based on the first transformed digital output vector is output. The controller 110 generates an ANN output that is a result of processing the input data set through an ANN defined by the first plurality of neural network weights. Where the input data set is divided into a plurality of digital input vectors, the resultant ANN output is an aggregated output comprising the first converted digital output, but may further comprise additional converted digital outputs corresponding to other portions of the input data set. Once the ANN output is generated, the generated output is transmitted to the computer (e.g., computer 102) that initiated the ANN calculation request.
Various performance metrics may be defined for the ANN computing system 100 implementing the process 200. Defining a performance index may allow the performance of the ANN computation system 100 implementing the optical processor 140 to be compared to the performance of other systems used to replace ANN computations implementing an electronic matrix multiplication unit. In one aspect, the rate at which the ANN calculations may be performed may be indicated in part by a first cycle period defined as the time elapsed between the step 220 of storing the input data set and the first plurality of neural network weights in the memory unit and the step 260 of storing the first transformed digital output vector in the memory unit. Thus, the first cycle period includes the time it takes to convert the electrical signal to an optical signal (e.g., step 230), perform a matrix multiplication in the optical domain, and convert the result back to the electrical domain (e.g., step 240). Both steps 220 and 260 involve storing data in the memory unit 120, which is a step shared between the ANN computing system 100 and a conventional ANN computing system without the optical processor 140. As such, measuring the first cycle period of the memory-to-memory transaction time may allow for an actual or fair comparison of the ANN computation throughput between the ANN computation system 100 and an ANN computation system without the optical processor 140 (e.g., a system implementing an electrical matrix multiplication unit).
Because of the rate at which the modulator array 144 can produce the optical input vector (e.g., at 25GHz) and the processing rate of the OMM unit 150 (e.g., >100GHz), the first cycle period of the ANN computation system 100 for performing a single ANN computation of a single digital input vector may be close to the inverse of the speed of the modulator array 144 (e.g., 40 ps). The first cycle period may be, for example, less than or equal to 100ps, less than or equal to 200ps, less than or equal to 500ps, less than or equal to 1ns, less than or equal to 2ns, less than or equal to 5ns, or less than or equal to 10ns, after taking into account the delay associated with the signal generation by the DAC unit 130 and the ADC conversion by the ADC unit 160.
In comparison, the multiplication runtime of an M1 vector and an M matrix of an electrical matrix multiplication unit is typically proportional to M ^2-1 processor clock cycles (processor clock cycles). For M-32, this multiplication will take about 1024 cycles, which results in a run time of over 300ns at 3GHz clock speed, which is orders of magnitude slower than the first cycle period of the ANN computing system 100.
In some embodiments, process 200 further includes the step of generating a second plurality of modulator control signals based on the first transformed digital output vector. In some types of ANN calculations, a single numeric input vector may be repeatedly propagated through or processed by the same ANN. An ANN that implements multi-pass processing may be referred to as a Recurrent Neural Network (RNN). The RNN is a neural network in which the output of the network is recycled back to the input of the neural network during the (k) th pass through the neural network and used as input during the (k +1) th pass. The RNN may have various applications in pattern recognition tasks, such as speech or handwriting recognition. Once the second plurality of modulator control signals are generated, process 200 may proceed from step 240 to step 260 to complete the first digital input vector second pass ANN. Generally speaking, recycling of the converted digital output into a digital input vector may be repeated for a predetermined number of cycles, depending on the characteristics of the RNN received in the ANN calculation request.
In some embodiments, process 200 further includes the step of generating a second plurality of weight control signals based on the second plurality of neural network weights. In some cases, the artificial neural network computation request further includes a second plurality of neural network weights. Typically, an ANN has one or more hidden layers in addition to the input and output layers. For an ANN having two hidden layers, the second plurality of neural network weights may correspond to connectivity between the first layer of the ANN and the second layer of the ANN. To process the first digital input vector through the two hidden layers of the ANN, the first digital input vector may first be processed according to process 200 until step 260, wherein the results of processing the first digital input vector through the first hidden layer of the ANN at step 260 are stored in memory unit 120. The controller 110 then reconfigures the OMM unit 150 to perform a matrix multiplication corresponding to a second plurality of neural network weights associated with a second hidden layer of the ANN. Once the OMM unit 150 is reconfigured, the process 200 may generate a plurality of modulator control signals based on the first transformed digital output vector, which generates an updated optical input vector corresponding to the output of the first hidden layer. The updated optical input vector is then processed by the reconfigured OMM unit 150, the OMM unit 150 corresponding to the second hidden layer of the ANN. In general, the steps described may be repeated until the digital input vector has been processed through all hidden layers of the ANN.
As described above, in some embodiments of the OMM unit 150, the reconfiguration rate of the OMM unit 150 may be significantly slower than the modulation rate of the modulator array 144. In this case, the throughput of the ANN computing system 100 may be adversely affected by the amount of time it takes to reconfigure the OMM unit 150 during which the ANN computation cannot be performed. To mitigate the effects of the relatively slow reconfiguration time of the OMM unit 150, batch processing (batch processing) techniques may be utilized in which two or more digital input vectors are propagated through the OMM unit 150 without configuration changes to amortize the reconfiguration time over a larger number of digital input vectors.
FIG. 2B shows a diagram 290 illustrating aspects of process 200 of FIG. 2A. For an ANN with two hidden layers, instead of processing a first digital input vector through a first hidden layer, reconfiguring the OMM unit 150 for a second hidden layer, processing the first digital input vector through the reconfigured OMM unit 150, and repeating the same operations for the remaining digital input vectors, all digital input vectors of the input data set may be processed first through the OMM unit 150 configured for the first hidden layer (configuration #1), as shown in the upper portion of fig. 290. Once all digital input vectors have been processed by the OMM unit 150 with configuration # 1, the OMM unit 150 is reconfigured to configuration # 2, which corresponds to the second hidden layer of the ANN. This reconfiguration may be significantly slower than the rate at which the OMM unit 150 may process the input vectors. Once the OMM unit 150 is reconfigured for the second hidden layer, output vectors from previous hidden layers may be batched by the OMM unit 150. For large input data sets with tens or hundreds of thousands of digital input vectors, the impact of reconfiguration time may be reduced by approximately the same factors, which may significantly reduce the portion of time spent by the ANN computing system 100 in reconfiguration.
To implement batch processing, in some embodiments, process 200 further includes the step of generating, by the DAC cell, a second plurality of modulator control signals based on a second digital input vector; a step of obtaining a second plurality of digital light outputs from the ADC unit corresponding to the light output vectors of the light matrix multiplication unit, the second plurality of digital light outputs forming a second digital output vector; a step of performing a non-linear transformation on the second digital output vector to produce a second transformed digital output vector; and storing the second transformed digital output vector in a memory unit. For example, generating the second plurality of modulator control signals may follow step 260. Furthermore, the ANN output of step 270 in this case is now based on the first transformed digital output vector and the second transformed digital output vector. The acquisition, execution and storage steps are similar to steps 240 through 260.
Batch processing techniques are one of many techniques for improving the throughput of the ANN computing system 100. Another technique for increasing the throughput of the ANN computing system 100 is by processing multiple digital input vectors in parallel using Wavelength Division Multiplexing (WDM). WDM is a technology of simultaneously propagating a plurality of optical signals of different wavelengths through a common propagation channel (e.g., a waveguide of the OMM unit 150). Unlike electrical signals, optical signals of different wavelengths can propagate through a common channel without affecting other optical signals of different wavelengths on the same channel. Further, well-known structures such as optical multiplexers (multiplexers) and demultiplexers (demultiplexers) can be used to add (multiplex) or drop (demultiplex) optical signals from a common propagation channel.
In the context of the ANN computing system 100, multiple light input vectors of different wavelengths may be independently generated,Propagate through the OMM unit 150 simultaneously, and are detected independently to enhance the throughput of the ANN computing system 100. Referring to fig. 1F, a diagram of an example of a Wavelength Division Multiplexing (WDM) Artificial Neural Network (ANN) computing system 104 is shown. The WDM ANN computing system 104 is similar to the ANN computing system 100, unless described otherwise. To implement WDM techniques, in some embodiments of the ANN computing system 104, the laser unit 142 is configured to generate multiple wavelengths, such as λ1、λ2And λ3. The multiple wavelengths may preferably be separated by a wavelength spacing large enough to allow easy multiplexing and demultiplexing onto a common propagation channel. For example, wavelength intervals greater than 0.5nm, 1.0nm, 2.0nm, 3.0nm, or 5.0nm may allow for simple multiplexing and demultiplexing. On the other hand, the range between the shortest and longest wavelengths of the plurality of wavelengths ("WDM bandwidth") may preferably be small enough such that the characteristics or performance of the OMM unit 150 remain substantially the same over the plurality of wavelengths. Optical components are typically dispersive (meaning that their optical properties vary with wavelength). For example, the power splitting ratio of the MZI may vary with wavelength. However, by designing the OMM unit 150 to have a sufficiently large operating wavelength window (operating wavelength window), and by limiting the wavelengths within the operating wavelength window, the light output vector output by the OMM unit 150 at each wavelength may be a sufficiently accurate result of the matrix multiplication implemented by the OMM unit 150. The operating wavelength window may be, for example, 1nm, 2nm, 3nm, 4nm, 5nm, 10nm, or 20 nm.
Fig. 39A shows a diagram of an example of a mach-zehnder modulator 3900 that may be used to modulate the amplitude of an optical signal. The mach-zehnder modulator 3900 includes two 1x 2-port multimode interference couplers (MMI _1x2)3902a and 3902b, two balanced arms (arm)3904a and 3904b, and a phase shifter 3906 in one arm (or one phase shifter in each arm). When a voltage is applied to the phase shifter in one arm through the signal line 3908, there will be a phase difference between the two arms 3904a and 3904b that will be converted to amplitude modulation. The 1x 2-port multimode interference couplers 3902a and 3902b and the phase shifter 3906 are configured as broadband (broadband) photonic components, and the optical path lengths of the two arms 3904a and 3904b are configured to be equal. This enables the mach-zehnder modulator 3900 to operate over a wide range of wavelengths.
FIG. 39B is a graph 3910 showing the intensity-voltage curve for a Mach-Zehnder modulator 3900 using the configuration shown in FIG. 39A for wavelengths 1530nm, 1550nm, and 1570 nm. Graph 3910 shows that mach-zehnder modulator 3900 has similar intensity-voltage characteristics for different wavelengths in the range of 1530nm to 1570 nm.
Referring back to fig. 1F, the modulator array 144 of the WDM ANN computing system 104 includes optical modulator banks (banks of optical modulators) configured to generate a plurality of optical input vectors, each of the optical modulator banks corresponding to one of the plurality of wavelengths and generating a respective optical input vector having a respective wavelength. For example, for wavelengths having lengths of 32 and 3 (e.g., λ) 1、λ2And λ3) The modulator array 144 may have 3 groups of 32 modulators each. In addition, the modulator array 144 also includes an optical multiplexer configured to combine the plurality of optical input vectors into a combined optical input vector that includes the plurality of wavelengths. For example, an optical multiplexer may combine the outputs of three modulator groups of three different wavelengths into a single propagation channel (e.g., waveguide) for each element of an optical input vector. As such, returning to the example above, the combined optical input vector will have 32 optical signals, each signal comprising 3 wavelengths.
In addition, the detection unit 146 of the WDM ANN computing system 104 is further configured to demultiplex the plurality of wavelengths and generate a plurality of demultiplexed output voltages. For example, detection unit 146 may include a demultiplexer configured to demultiplex three wavelengths included in each of the 32 signals of the multi-wavelength light output vector and route (route) 3 single-wavelength light output vectors to three sets of photodetectors coupled to three sets of transimpedance amplifiers.
Further, the ADC unit 160 of the WDM ANN computing system 104 includes a bank of ADCs configured to convert the plurality of demultiplexed output voltages of the detection unit 146. Each of the ADC banks corresponds to one of the plurality of wavelengths and produces a corresponding digital demultiplexed optical output. For example, the bank of ADCs may be coupled to a bank of transimpedance amplifiers of the detection unit 146.
In some cases, the ANN may be specially designed and the digital input vector may be specifically formed so that the multi-wavelength light output vector may be detected without demultiplexing. In this case, the detection unit 146 may be a wavelength-insensitive (wavelength-insensitive) detection unit that does not demultiplex multiple wavelengths of the multi-wavelength light output vector. As such, each of the photodetectors of the detection unit 146 effectively adds multiple wavelengths of the optical signal to a single photocurrent, and each of the voltages output by the detection unit 146 corresponds to a element-by-element sum (element-by-element sum) of matrix multiplication results of multiple digital input vectors.
Up to now, the non-linear transformation of the weighted sum performed as part of the ANN calculation is performed in the digital domain by the controller 110. In some cases, the non-linear transformation may be computationally intensive or power consuming, significantly increasing the complexity of the controller 110, or limiting the performance of the ANN computing system 100 in terms of throughput or power efficiency. As such, in some embodiments of the ANN computing system, the nonlinear transformation may be performed in the analog domain by analog electronics.
Fig. 3A illustrates a diagram of an example of an ANN computing system 300. The ANN computing system 300 is similar to the ANN computing system 100, except that an analog non-linear unit 310 is added. The analog nonlinear unit 310 is disposed between the detection unit 146 and the ADC unit 160. The analog nonlinear unit 310 is configured to receive the output voltage from the detection unit 146, apply a nonlinear transfer function, and output the converted output voltage to the ADC unit 160.
When the ADC unit 160 receives a voltage that has been nonlinearly converted by the analog nonlinear unit 310, the controller 110 may obtain a converted digital output voltage corresponding to the converted output voltage from the ADC unit 160. Since the digital output voltage obtained from the ADC unit 160 has already been non-linearly converted ("activated"), the non-linear conversion step of the controller 110 can be omitted, thereby reducing the computational burden of the controller 110. The first converted voltage obtained directly from the ADC unit 160 may then be stored as a first converted digital output vector in the memory unit 120.
The analog non-linear unit 310 may be implemented in various ways. For example, a high gain amplifier in a feedback configuration, a comparator having an adjustable reference voltage, a nonlinear IV characteristic of a diode, a breakdown characteristic of a diode (breakdown-down-behavor), a nonlinear CV characteristic of a variable capacitance, or a nonlinear IV characteristic of a variable resistance may be used to implement the analog nonlinear unit 310.
Using the analog non-linear unit 310 may improve the performance of the ANN computing system 300, such as throughput or power efficiency, by reducing the steps performed in the digital domain. Moving the non-linear transformation step out of the digital domain may allow additional flexibility and improvement in the operation of the ANN computing system. For example, in a recurrent neural network, the output of the OMM unit 150 is activated and recycled back to the input of the OMM unit 150. The activation step is performed by the controller 110 in the ANN computing system 100, which requires digitizing the output voltage of the detection unit 146 each time it passes through the OMM unit 150. However, because the activation step is now performed prior to digitization of the ADC unit 160, the number of ADC conversions required in performing the recursive neural network calculations may be reduced.
In some embodiments, the analog non-linear unit 310 may be integrated into the ADC unit 160 as a non-linear ADC unit. For example, the non-linear ADC unit may be a linear ADC unit having a non-linear look-up table that maps the linear digital output of the linear ADC unit to a desired non-linear converted digital output.
Fig. 3B illustrates a diagram of an example of an ANN computing system 302. The ANN computing system 302 is similar to the system 300 of fig. 3A, except that it further includes an analog storage unit 320. The analog storage unit 320 is coupled to the DAC unit 130 (e.g., via the first DAC subunit 132), the modulator array 144, and the analog nonlinear unit 310. The analog storage unit 320 comprises a multiplexer having a first input coupled to the DAC unit 130 and a second input coupled to the analog non-linear unit 310. This allows the analog storage unit 320 to receive signals from the DAC unit 130 or the analog nonlinear unit 310. The analog memory cell 320 is configured to store an analog voltage and output the stored analog voltage.
The analog memory cell 320 may be implemented in various ways. For example, a capacitor array may be used as an analog voltage storage component. The capacitance of the analog memory cell 320 may be charged to the input voltage by a charging circuit. The storage of the input voltage may be controlled based on a control signal received from the controller 110. The capacitor may be electrically isolated from the surrounding environment to reduce charge leakage that may lead to undesired discharge of the capacitor. Additionally (or alternatively), a feedback amplifier may be used to maintain the voltage stored on the capacitor. The storage voltage of the capacitor can be read out by a buffer amplifier, which allows the charge stored by the capacitor to be held while the storage voltage is output. These aspects of the analog memory cell 320 may be similar to the operation of a sample and hold circuit. The buffer amplifiers may perform the function of modulator drivers for driving modulator array 144.
The operation of the ANN computing system 302 will now be described. The first plurality of modulator control signals output by the DAC cell 130 (e.g., by the first DAC subunit 132) are first input to the modulator array 144 through the analog storage unit 320. In this step, the analog storage unit 320 may simply pass or buffer the first plurality of modulator control signals. The modulator array 144 generates an optical input vector based on the first plurality of modulator control signals, which propagates through the OMM unit 150 and is detected by the detection unit 146. The output voltage of the detection unit 146 is nonlinearly converted by the analog nonlinear unit 310. At this time, instead of being digitized by the ADC unit 160, the output voltage of the detection unit 146 is stored by the analog storage unit 320, which is then output to the modulator array 144 to be converted into the next optical input vector to be propagated through the OMM unit 150. The recursive process (recurrentprocessing) may be performed for a preset amount of time or a preset number of cycles under the control of the controller 110. Once the recursive processing is completed for a given digital input vector, the converted output voltage of the analog non-linear unit 310 is converted by the ADC unit 160.
The use of the analog storage unit 320 may significantly reduce the number of ADC conversions during recursive neural network computations, for example down to computing one single ADC conversion per RNN for a given digital input vector. Each ADC conversion takes a period of time and consumes a certain amount of energy. As such, the RNN computation throughput of the ANN computation system 302 may be higher than the RNN computation throughput of the ANN computation system 100.
The execution of the recurrent neural network computations may be controlled by controlling the analog memory unit 320. For example, the controller may control the analog memory cell 320 to store a voltage at a specific time and output the stored voltage at a different time. As such, the cycling of signals from the analog memory 320 to the modulator array 144 through the analog nonlinear unit 310 and back to the analog memory unit 320 may be controlled by the controller 110 controlling the storing and reading of the analog memory unit 320.
As such, in some embodiments, the controller 110 of the ANN computing system 302 may perform the following steps: storing, by an analog storage unit, a plurality of converted output voltages of an analog non-linear unit based on generating a first plurality of modulator control signals and a first plurality of weight control signals; outputting the stored converted output voltage through the analog memory cell; obtaining a second plurality of converted digital output voltages from the ADC unit, the second plurality of converted digital output voltages forming a second converted digital output vector; and storing the second transformed digital output vector in the memory unit.
The input data set processed by the ANN computing system typically includes data having a resolution greater than 1 bit. For example, a typical pixel of a grayscale digital image may have a resolution of 8 bits, i.e., 256 different levels. One way to represent and process this data in the optical domain is to encode 256 different intensity level pixels as 256 different power levels of the optical signal input to the OMM unit 150. The optical signal is essentially an analog signal and is therefore susceptible to noise and detection errors. Referring back to fig. 1A, in order to maintain 8-bit resolution of the digital input vector throughout the ANN computation system 100 and produce a true 8-bit digital optical output at the output of the ADC unit 160, each portion of the signal chain (signal chain) may preferably be designed to reproduce and maintain 8-bit resolution.
For example, the DAC cell 130 may preferably be designed to support conversion of an 8-bit digital input vector to modulator control signals of at least 8-bit resolution, such that the modulator array 144 may produce an 8-bit optical input vector that faithfully represents the digital input vector. Generally, the modulator control signals may need to have an additional resolution in excess of 8 bits of the digital input vector to compensate for the non-linear response of the modulator array 144. Furthermore, the internal configuration of the OMM unit 150 may preferably be stable enough to ensure that the values of the light output vector are not corrupted by any fluctuations in the configuration of the OMM unit 150. For example, the temperature of the OMM unit 150 may need to be stabilized within 5 degrees, 2 degrees, 1 degree, or 0.1 degrees. Furthermore, the detection unit 146 may preferably have a sufficiently low noise to not disrupt the 8-bit resolution of the optical output vector, and the ADC unit 160 may preferably be designed to support the digitization of an analog voltage having a resolution of at least 8 bits.
The power consumption and design complexity of various electronic components generally increases with bit resolution, operating speed, and bandwidth. For example, as a first order approximation, the power consumption of the ADC unit 160 may scale linearly with the sampling rate, and the scaling factor is 2^ N, where N is the bit resolution of the conversion result. Furthermore, design considerations for the DAC cell 130 and the ADC cell 160 typically result in a trade-off between sampling rate and bit resolution. As such, in some cases, it may be desirable for the ANN computing system to operate internally at a lower bit resolution than the resolution of the input data set, while maintaining the resolution of the ANN computing output.
Referring to fig. 4A, a diagram of an example of an Artificial Neural Network (ANN) computing system 400 with 1-bit internal resolution is shown. ANN computing system 400 is similar to ANN computing system 100, except that DAC unit 130 is now replaced by driver unit 430 and ADC unit 160 is now replaced by comparator unit 460.
The driver unit 430 is configured to generate a 1-bit modulator control signal and a multi-bit weight control signal. For example, the drive circuitry of driver unit 430 may receive a binary digital output directly from controller 110 and adjust the binary signal to a two-level voltage or current output suitable for driving modulator array 144.
The comparator unit 460 is configured to convert the output voltage of the detection unit 146 into a digital 1-bit light output. For example, the comparison circuit of the comparator unit 460 may receive the voltage from the detection unit 146, compare the voltage with a preset threshold voltage, and output a digital 0 or 1 when the received voltage is less than or greater than the preset threshold voltage, respectively.
Referring to fig. 4B, a mathematical representation of the operation of the ANN computing system 400 is shown. The operation of the ANN computing system 400 will now be described with reference to fig. 4B. For a given ANN calculation to be performed by the ANN calculation system 400, there is a corresponding numerical input vector V and a neural network weight matrix U. In this embodiment, the input vector V is of the element V 0To V3Is a length 4 vector, and the matrix U is with a weight U00To U334 x 4 matrix. Each element of the vector V has a resolution of 4 bits. Each 4-bit vector element has a bit 0 (bit) corresponding to 2^0 to 2^3 positions, respectively0) To bit 3 (bit)3). Thus, passing 2^0 ^ bit0+2^1*bit1+2^2*bit2+2^3*bit3Sum of 4-bit vector elements to compute decimal (decimal) (radix 10)The value is obtained. Thus, as shown, the input vector V may be similarly decomposed into V by the controller 110 simulationbit0To Vbit3。
Then, a specific ANN calculation can be performed by performing a series of matrix multiplications of the 1-bit vectors, followed by summing the respective matrix multiplication results. For example, the decomposed input vector V may be transformed by generating a sequence of 4 1-bit modulator control signals corresponding to 4 1-bit input vectors by means of the driver unit 430bit0To Vbit3Is multiplied by the matrix U. This in turn results in a sequence of 4 1-bit optical input vectors, which propagate through the OMM unit 150, the OMM unit 150 being configured to implement a matrix multiplication of the matrix U by the driver unit 430. The controller 110 may then derive a sequence of 4 digital 1-bit optical outputs from the comparator unit 460 corresponding to a sequence of 4 1-bit modulator control signals.
In the case of a 4-bit vector being decomposed into 4 1-bit vectors, each vector should be processed by the ANN computing system 400 four times as fast as other ANN computing systems (e.g., system 100) can process a single 4-bit vector to maintain the same effective ANN computing throughput. This increased internal processing speed can be seen as time-division multiplexing (time-division multiplexing) of 4 1-bit vectors into a single time slot (time) for processing the 4-bit vectors. The required increase in processing speed may be achieved at least in part by the increased operating speed of the driver unit 430 and the comparator unit 460 relative to the DAC unit 130 and the ADC unit 160, since a decrease in resolution of the signal conversion process typically results in an increase in the achievable signal conversion rate.
Although the signal slew rate in 1-bit operation is increased by a factor of four, the resulting power consumption can be significantly reduced relative to 4-bit operation. As noted above, the power consumption of the signal conversion process typically scales exponentially with bit resolution, while scaling linearly with the conversion rate. As such, a 16-fold reduction in power per transition may be a 4-fold reduction in bit resolution followed by a 4-fold increase in power due to an increase in slew rate. In summary, a 4-fold reduction in operating power may be achieved by the ANN computing system 400 over, for example, the ANN computing system 100, while maintaining the same effective ANN computing throughput.
The controller 110 may then construct a 4-bit digital output vector from the 4 digital 1-bit optical outputs by multiplying each digital 1-bit optical output by a corresponding weight 2^0 to 2^ 3. Once the 4-bit digital output vector is constructed, an ANN calculation may be performed by performing a non-linear transformation on the constructed 4-bit digital output vector to produce a converted 4-bit digital output vector; and stores the converted 4-bit digital output vector in the memory unit 120.
Alternatively (or additionally), in some embodiments, each of the 4 digital 1-bit light outputs may be non-linearly transformed. For example, a step-function nonlinear function (step-function nonlinear function) may be used for the nonlinear transformation. A converted 4-bit digital output vector can then be constructed from the non-linearly transformed digital 1-bit optical output.
Although a separate ANN computing system 400 has been shown and described, in general, the ANN computing system 100 of fig. 1A may be designed to perform functions similar to those of the ANN computing system 400. For example, the DAC cell 130 may include a 1-bit DAC sub-cell configured to generate a 1-bit modulator control signal, and the ADC cell 160 may be designed to have a resolution of 1 bit. Such a 1-bit ADC may be similar to or effectively identical to a comparator.
Further, while the operation of an ANN computing system having a 1-bit internal resolution has been described, in general, the internal resolution of the ANN computing system may be reduced to an intermediate level below the N-bit resolution of the input data set. For example, the internal resolution may be reduced to 2^ Y bits, where Y is an integer greater than or equal to 0.
Embodiments of the subject matter and the functional operations described in this disclosure can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this disclosure and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this disclosure can be implemented using one or more modules of computer program instructions encoded on a computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium may be an article of manufacture (e.g., a hard drive in a computer system or an optical disk sold through retail outlets) or an embedded system. The computer-readable medium may be separately acquired and then encoded with one or more modules of computer program instructions, for example, by transmitting the one or more modules of computer program instructions over a wired or wireless network. The computer readable medium can be a machine readable storage device, a machine readable storage substrate, a memory device, or a combination of one or more of them.
A computer program (also known as a program, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and it can be deployed in any form, including as a stand alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub-programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.
The processes and logic flows described in this disclosure can be performed by one or more programmable processors (programmable processors) executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC).
While this disclosure contains many implementation details, these should not be construed as limitations on the scope of the disclosure or of the claims, but rather as descriptions of features specific to particular embodiments of the disclosure. Certain features that are described in this disclosure in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features may in some cases be excised from the claimed combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the described embodiments is not to be understood as requiring such separation in all embodiments, and it is to be understood that the described program components and systems can generally be integrated within a single software product or packaged into multiple software products.
Thus, particular embodiments of the disclosure have been described. Other embodiments are within the scope of the following claims. Additionally, the actions recited in the claims can be performed in a different order and still achieve desirable results. For example, the optical matrix multiplication unit 150 in FIG. 1A includes an optical interference unit 154 that includes a plurality of interconnected Mach-Zehnder interferometers. In some embodiments, the optical interference unit may be implemented using a one-, two-, or three-dimensional passive diffractive optical element (passive diffractive optical element) that consumes little power. The optical interference unit using the passive diffractive optical element may have a smaller size or may handle a larger number of inputs/outputs for the same chip size, if the number of inputs/outputs remains the same, as compared to the optical interference unit including the mach-zehnder interferometer. The passive diffractive optical component can be manufactured at a lower cost than a mach-zehnder interferometer.
Referring to fig. 5, in some embodiments, an artificial neural network computing system 500 includes a controller 110, a memory unit 120, a DAC unit 506, a light processor 504, and an ADC unit 160. The memory unit 120 and the ADC unit 160 are similar to the corresponding components of the system 100 in fig. 1A. The light processor 504 is configured to perform matrix calculations using optical components. In the system 500, the weights of the optical matrix multiplication unit 502 are fixed. The DAC unit 506 is similar to the first DAC subunit 132 of the system 100 of fig. 1A.
In an example operation of the ANN computing system 500, the computer 102 may issue an artificial neural network computation request to the ANN computing system 500. The ANN calculation request may include an input data set to be processed by the provided ANN. The controller 110 receives the ANN calculation request and stores the input data set in the storage unit 120.
In some embodiments, a hybrid approach is used, where a portion of the optical matrix multiplication unit 150 includes a mach-zehnder interferometer and another portion of the optical matrix multiplication unit 150 includes a passive diffractive component.
The internal operation of the ANN computing system 500 will now be described. The light processor 504 includes the laser unit 142, the modulator array 144, the detection unit 146, and the Optical Matrix Multiplication (OMM) unit 502. The laser unit 142, modulator array 144, and detection unit 146 are similar to the corresponding components of the system 100 in fig. 1A. In this example, the OMM unit 502 includes a two-dimensional diffractive optical component, and may be implemented as a passive integrated silicon photonic chip. The optical matrix multiplication unit 502 may be configured to implement a diffractive neural network, and may perform matrix multiplication with almost zero power consumption.
The optical processor 504 operates by encoding a length N digital input vector onto a length N optical input vector, and propagating the optical input vector through the OMM unit 502. The OMM unit 502 receives an optical input vector of length N and performs an N × N matrix multiplication on the received optical input vector in the optical domain. The N × N matrix multiplication performed by the OMM unit 502 is determined by the internal configuration of the OMM unit 502. The internal configuration of the OMM unit 502 includes the size, location, and geometry of the diffractive optical element, and the doping (if any) of impurities.
The OMM unit 502 may be implemented in various ways. Fig. 6 shows a diagram of an example of an OMM unit 502 using a two-dimensional diffraction element array. The OMM unit 502 may include an array of input waveguides 602 to receive an optical input vector, a two-dimensional optical interference unit 600 in optical communication with the array of input waveguides 602, and an array of output waveguides 604 in optical communication with the optical interference unit 600. The optical interference unit 600 includes a plurality of diffractive optical elements and performs conversion (e.g., linear transformation) of the optical input vector into a second optical signal array. The array of output waveguides 604 guides the array of second optical signals output by the optical interference unit 600. At least one input waveguide of the array of input waveguides 602 is in optical communication with each output waveguide of the array of output waveguides 604 through the optical interference unit 600. For example, for an optical input vector of length N, the OMM unit 502 may include N input waveguides 602 and N output waveguides 604.
In some embodiments, optical interference unit 600 includes a substrate having diffractive components arranged in two dimensions (e.g., in a 2D array). For example, a plurality of circular holes may be drilled or etched in the substrate. The size of these apertures may be comparable in magnitude to the size of the wavelength of the input light, such that the light is diffracted by the apertures (or the structure defining the apertures). For example, the size of the pores may be in the range of 100nm to 2 μm. The holes may be of the same or different sizes. The holes may also have other cross-sectional shapes such as triangular, square, rectangular, hexagonal or irregular shapes. The substrate may be made of a material that is transparent or translucent to the input light, e.g. having a transmission rate of 1% to 99% with respect to the input light. For example, the substrate may be made of silicon, silicon oxide, silicon nitride, quartz, crystals (e.g., lithium niobate (LiNbO3)), group III-V materials (e.g., gallium arsenide or indium phosphide), erbium modified semiconductors (erbium modified semiconductors), or polymers.
In some embodiments, a holographic method (holographic method) may be used to form the two-dimensional diffractive optical element in the substrate. The substrate may be made of glass, crystal or photorefractive material.
In designing the OMM unit 502, the size and position of the diffractive components are taken into account in two dimensions (e.g., the X-direction and the Y-direction), and the relative position of the diffractive components in a third dimension (e.g., the Z-direction). Each diffractive component may be a three-dimensional structure formed in the substrate, such as a hole, column (column) or stripe (stripe) having a certain depth.
In fig. 6, the diffractive optical element is represented by a circle. The diffractive optical element may also have other shapes, such as triangular, square, rectangular or irregular shapes. The diffractive optical element can have various sizes. The diffractive optical elements do not have to be located at grid points (grid points), their position can be changed. The diagram in fig. 6 is for illustration purposes only. The actual diffractive optical element may be different from that shown in the figures. Different arrangements of diffractive optical elements may be used to implement different matrix calculations, for example different matrix multiplication functions.
The configuration of the diffractive optical element can be determined using an optimization process. For example, the substrate may be divided into an array of pixels, and each pixel may be filled with substrate material (no holes) or with air (holes). The configuration of the pixels may be iteratively modified and for each configuration of pixels, a simulation (simulation) may be performed by passing light through the diffractive optical component and evaluating the output. After performing a simulation of all possible configurations of the pixels, the configuration that provides the closest result to the desired matrix processing is selected as the diffractive optical component configuration of the OMM unit 502.
As another example, the diffractive component is initially configured as an array of apertures. The position, size and shape of the holes may be slightly different from their initial configuration. The parameters for each hole may be iteratively adjusted and simulations may be performed to find an optimal configuration of holes.
In some embodiments, a machine learning process is used to design diffractive optical components. An analytical function of how the pixel affects the input light to produce the output light is determined and an optimization process, such as a gradient descent method, is used to determine the optimal configuration of the pixel.
In some embodiments, the OMM unit 502 may be implemented as a user-changeable component, and different OMM units 502 with different optical interference units 600 may be installed for different applications. For example, system 500 may be configured as an optical character recognition system, and optical interference unit 600 may be configured to implement a neural network for performing optical character recognition. For example, a first OMM unit may have a first optical interference unit including a passive diffractive optical component configured to implement a first neural network for an optical character recognition engine for a first set of written languages and fonts. The second OMM unit may have a second optical interference unit including a passive diffractive optical component configured to implement a second neural network for the optical character recognition engine for a second set of written languages and fonts, and the like. When a user wants to apply optical character recognition to a first set of written languages and fonts using the system 500, the user can insert a first OMM unit into the system. When a user wants to apply optical character recognition to a second set of written languages and fonts using the system 500, the user can swap out the first OMM unit and insert a second OMM unit into the system.
For example, system 500 may be configured as a speech recognition system and optical intervention unit 600 may be configured to implement a neural network for performing speech recognition. For example, a first OMM unit may have a first optical interference unit including a passive diffractive optical component configured to implement a first neural network for a speech recognition engine for a first spoken language. The second OMM unit may have a second optical interference unit comprising a passive diffractive optical component configured to implement a second neural network for a second spoken language or the like for a speech recognition engine, and so on. When a user wants to use the system 500 to recognize speech in a first spoken language, the user may insert a first OMM unit into the system. When the user wants to use the system 500 to recognize speech in a second spoken language, the user can swap out the first OMM unit and insert a second OMM unit into the system.
For example, the system 500 may be part of a control unit of an autonomous vehicle, and the light interference unit 600 may be configured to implement a neural network for performing road condition recognition. For example, a first OMM unit may have a first optical interference unit including a passive diffractive optical component configured to implement a first neural network for identifying road conditions (including road signs) in the united states. The second OMM unit may have a second optical interference unit including a passive diffractive optical component configured to implement a second neural network for identifying road conditions (including road signs) in Canada. The third OMM unit may have a third optical interference unit comprising a passive diffractive optical component configured to implement a third neural network for identifying road conditions (including road markings) in mexico, and so on. When using an autonomous vehicle in the united states, a first OMM unit is plugged into the system. When the autonomous vehicle crosses a boundary and enters canada, the first OMM unit is swapped out and a second OMM unit is plugged into the system. On the other hand, when the autonomous vehicle crosses a boundary and enters mexico, the first OMM unit is swapped out and a third OMM unit is inserted into the system.
For example, system 500 may be used for gene sequencing (genetic sequencing). DNA sequences can be classified using a convolutional neural network implemented using system 500 that includes passive diffractive optical components. For example, the system 500 may implement neural networks for differentiating tumor types, predicting tumor grade (tumor grade), and predicting patient survival from gene expression patterns (gene expression patterns). For example, the system 500 may implement a neural network for identifying a subset of genes or features that are most predictive of the analyzed characteristic. For example, the system 500 may implement a neural network for predicting or inferring expression levels (expression levels) of all genes from a data map (profile) of a base set of factors. For example, the system 500 may implement neural networks for epigenetic analysis (epigenomic analysis), such as prediction of transcription factor binding sites (transcription factor binding sites), enhancer regions (enhancer regions), and chromatin accessibility from gene sequences (chromatin accessibility). For example, system 500 can implement a neural network for capturing structures within a gene sequence.
For example, the system 500 may be configured as a medical diagnostic system, and the OMM unit 502 may be configured to implement a neural network for analyzing physiological parameters (physiological parameters) to perform screening for disease. For example, the system 500 may be configured as a bacteria detection system, and the OMM unit 502 may be configured to implement a multiplication function for analyzing DNA sequences to detect certain bacterial strains.
In some embodiments, the OMM unit 502 includes a housing (e.g., a cartridge) that protects a substrate having a diffractive optical element. The housing supports an input interface coupled to an input waveguide 602 and an output interface coupled to an output waveguide 604. The input interface is configured to receive the output from the modulator array 144 and the output interface is configured to transmit the output of the OMM unit 502 to the detection unit 146. The OMM units 502 may be designed as modules suitable for handling by ordinary consumers, allowing a user to easily switch from one OMM unit 502 to another OMM unit 502. Machine learning techniques improve over time. The user may upgrade the system 500 by swapping out the old OMM unit 502 and inserting a new upgrade version.
Similar to the way optical compact discs (optical compact discs) can store digital information that can be retrieved by CD players, the OMM unit can store a neural network configuration that can be used in an optical processor. Just as optical compact discs are low cost media for distributing digital information (including audio, video and software programs) to consumers, the OMM unit may be a low cost media for distributing pre-configured neural network or matrix processing functions (e.g., multiplication, convolution or any other linear operation) to consumers.
In some embodiments, the system 500 is an optical computing platform configured to operate with OMM units provided by different companies. This allows different companies to develop different passive optical neural networks for various applications. The passive optical neural network is sold to end users in a standardized package that can be installed in an optical computing platform to allow the system 500 to perform various intelligent functions.
In some embodiments, the system may have a holder mechanism for supporting a plurality of OMM units 502, and a mechanical handling mechanism may be provided for automatically swapping out the OMM units 502. The system determines which OMM unit is required for the current application 502 and uses a mechanical processing mechanism to automatically retrieve the appropriate OMM unit from the holder mechanism and insert it into the optical processor 504.
For a particular size of optical chip, more passive diffractive components can be fabricated on the substrate than using an active interferometer (e.g., a mach-zehnder interferometer). For example, optical interference unit 154 in FIG. 1B using a Mach-Zehnder interferometer may be configured to handle a 200 × 200 matrix multiplication, while optical interference unit 600 having the same overall dimensions and using passive diffractive components (each having dimensions of about 100nm × 100 nm) may be configured to handle a 5000 × 5000 matrix multiplication.
The passive diffractive optical component consumes little power, so the OMM unit 502 can be used for low power devices, such as battery operated devices. The OMM unit 502 is adapted for edge computing (edge computing). For example, the OMM unit 502 may be used in a smart sensor, where raw data from the sensor is processed using an optical processor using the OMM unit 502. The smart sensor may be configured to transmit the processed data to the central computer server, thereby reducing the amount of raw data transmitted to the central computer server. By placing intelligent processing functions on the intelligent sensors, faults and anomalies can be detected earlier and processed more efficiently. The OMM unit 502 is suitable for applications that require handling large matrix multiplications. The OMM unit 502 is suitable for applications where the neural network has been trained and the weights have been determined and do not need to be modified.
The substrate in which the diffractive optical element is formed may be planar or curved. In the example of fig. 6, input light enters the light interference unit 600 from the left side, and output light exits the light interference unit 600 from the right side (the terms "left", "right", "upper" and "lower" refer to the directions shown in the drawing). In some embodiments, the passive diffractive optical component may be configured such that some of the output light exits the optical interference unit from an upper or lower portion, or any combination of the left, right, upper, and lower sides of the optical interference unit 600. The substrate for the light interference unit 600 may have various shapes such as a square, a rectangle, a triangle, a circle, or an ellipse. Optical interference unit 600 may include reflective components or mirrors to redirect the direction of light propagation.
In some embodiments, the artificial neural network computing system 500 may be modified by adding an analog non-linear unit 310 between the detection unit 146 and the ADC unit 160. The analog nonlinear unit 310 is configured to receive the output voltage from the detection unit 146, apply a nonlinear transfer function, and output the converted output voltage to the ADC unit 160. The controller 110 may obtain a converted digital output voltage corresponding to the converted output voltage from the ADC unit 160. Since the digital output voltage obtained from the ADC unit 160 has already been non-linearly converted ("activated"), the non-linear conversion step of the controller 110 can be omitted, thereby reducing the computational burden of the controller 110. Next, the first converted voltage directly obtained from the ADC unit 160 may be stored as a first converted digital output vector in the storage unit 120.
The optical interference unit may be implemented using passive diffractive optical components arranged in three dimensions. Referring to FIG. 7, in some embodiments, an artificial neural network computing system 700 has an optical processor 702 that includes a three-dimensional OOM unit 708. The system 700 includes a memory unit 120 and an ADC unit 160, which are similar to the corresponding components of the system 500 in fig. 5. The light processor 702 is configured to perform matrix calculations using diffractive optical elements arranged in three dimensions.
The light processor 702 includes a laser unit 704 configured to output a two-dimensional array of light beams 714 and a two-dimensional array of modulators 706 configured to modulate the two-dimensional array of light beams 714 to produce a modulated two-dimensional array of light beams 716. The light processor 702 includes a light matrix multiplication (OMM) unit 708 having a three-dimensional arrangement of diffractive optical components and configured to process a modulated two-dimensional array of light beams 716 and produce a two-dimensional array of output light beams 718. The light processor 702 includes a detection unit 710 having a two-dimensional array of light sensors to detect a two-dimensional array of output light beams 718. The ADC unit 160 converts the output of the detection unit 710 into a digital signal.
For example, the 3D OMM unit 708 may be implemented as a passive integrated silicon photonic column or cube. The optical matrix multiplication unit 708 may be configured to implement a diffraction neuron network, and may perform matrix multiplication at almost zero power consumption.
There are many ways to encode the input data for use by the light processor 702. For example, a length N × N digital input vector may be encoded onto a size N × N optical input matrix, which propagates through the OMM unit 708. The OMM unit 708 performs (N × N) × (N × N) matrix multiplication on the received light input matrix in the optical domain. The (N × N) × (N × N) matrix multiplication performed by the OMM unit 708 is determined by the internal configuration of the OMM unit 708, including the size, position and geometry of the diffractive optical components arranged in three dimensions, and the doping of impurities (if any).
The OMM unit 708 may be implemented in various ways. Fig. 8 shows a diagram of an example of an OMM unit 708 using a three-dimensional arrangement of diffractive components. The OMM unit 708 may include an input waveguide matrix for receiving the optical input matrix 802, a three-dimensional optical interference unit 804 in optical communication with the input waveguide matrix, and an output waveguide matrix in optical communication with the optical interference unit 804 for providing an optical output matrix 806. The optical interference unit 804 includes a plurality of diffractive optical elements and performs conversion (e.g., linear transformation) of an optical input (e.g., an nxn vector or matrix) to an optical output (e.g., an nxn vector or matrix). The matrix of output waveguides guides the optical signals output by the optical interference unit 804. At least one input waveguide of the matrix of input waveguides is in optical communication with each output waveguide of the matrix of output waveguides via an optical interference unit 804. For example, for an optical input vector of length N × N, the OMM unit 708 may include N × N input waveguides and N × N output waveguides.
In some embodiments, optical interference unit 804 includes a substrate block having diffractive components arranged in three dimensions (e.g., in a 3D matrix). For example, a plurality of holes may be drilled or etched in each of a plurality of substrate slices, and the plurality of substrate slices may be combined to form a substrate block. The size of these apertures may be comparable in magnitude to the size of the wavelength of the input light, such that the light is diffracted by the apertures (or the structure defining the apertures). The holes may be of the same or different sizes. The holes may also have other cross-sectional shapes such as triangular, square, rectangular, hexagonal or irregular shapes. In some embodiments, holographic methods can be used to form three-dimensional diffractive optical elements throughout a substrate block. The substrate may be made of a material that is transparent or translucent to the input light, e.g. having a transmission rate of 1% to 99% with respect to the input light.
When designing the OMM unit 708, the dimensions and positions of the diffractive components in the x, y, and z directions are considered. The configuration of the diffractive optical element can be determined using an optimization process. For example, the substrate block may be divided into a three-dimensional matrix of pixels, and each pixel may be filled with substrate material (no holes) or with air (holes). The configuration of the pixels may be iteratively modified and for each configuration of pixels, a simulation may be performed by passing light through the diffractive optical component and evaluating the output. After performing a simulation of all possible configurations of the pixels, the configuration that provides the closest result to the desired matrix processing is selected as the diffractive optical component configuration of the OMM unit 708.
As another example, the diffractive component is initially configured as a three-dimensional matrix of holes. The position, size and shape of the holes may be slightly different from their initial configuration. The parameters for each hole may be iteratively adjusted and simulations may be performed to find an optimal configuration of holes.
In some embodiments, a machine learning process is used to design a three-dimensional diffractive optical component. It is determined how the pixels affect the analytical function of the input light and a gradient descent method is used to determine the optimal configuration of the pixels.
In some embodiments, the OMM unit 708 may be implemented as a user-changeable component, and different OMM units 708 with different optical interference units 804 may be installed for different applications. For example, system 700 may be configured as a medical diagnostic system and optical interference unit 804 may be configured to implement a neural network for analyzing physiological parameters to perform screening for disease. For example, a first OMM unit may have a first optical interference unit including a 3D passive diffractive optical component configured to implement a first neural network for screening a first set of diseases. The second OMM unit may have a second optical interference unit comprising a 3D passive diffractive optical component configured to implement a second neural network for screening a second set of diseases, and so on. The first and second OMM units may be developed by different companies that specialize in developing technologies for screening different diseases. When a user wants to screen a first group of diseases using the system 700, the user may plug a first OMM unit into the system. When a user wants to screen a second group of diseases using the system 700, the user may swap out the first OMM unit and insert a second OMM unit into the system.
For example, the system 700 may be configured as an optical character recognition system, and the optical interference unit 804 may be configured to implement a neural network for performing optical character recognition. For example, the system 700 may be configured as a speech recognition system and the optical interference unit 804 may be configured to implement a neural network for performing speech recognition. For example, the system 700 may be part of a control unit of an autonomous vehicle, and the light interference unit 804 may be configured to implement a neural network for performing road condition recognition.
For example, system 700 can be used for gene sequencing. DNA sequences can be classified using a convolutional neural network implemented using system 700 that includes passive diffractive optical components. For example, system 700 may implement neural networks for differentiating tumor types, predicting tumor grade, and predicting patient survival from gene expression patterns. For example, the system 700 may implement a neural network for identifying a subset of genes or features that are most predictive of the analyzed characteristic. For example, the system 700 may implement a neural network for predicting or inferring expression levels of all genes from a data graph of a gene set. For example, the system 700 can implement neural networks for epigenetic analysis, such as predicting transcription factor binding sites, enhancer regions, and chromatin accessibility from gene sequences. For example, system 700 may implement a neural network for capturing structures within a gene sequence. For example, system 700 may be configured as a bacteria detection system, and optical interference unit 804 may be configured to implement a multiplication function for analyzing DNA sequences to detect certain bacterial strains.
In some embodiments, the OMM unit 708 includes a housing (e.g., a cartridge) that protects a substrate with a 3D diffractive optical element. The housing supports an input interface coupled to the input waveguide and an output interface coupled to the output waveguide. The input interface is configured to receive an output from the modulator array 706 and the output interface is configured to transmit the output of the OMM unit 708 to the detection unit 710. The OMM units 708 may be designed as modules suitable for handling by ordinary consumers, allowing a user to easily switch from one OMM unit 708 to another OMM unit 708. Machine learning techniques improve over time. The user may upgrade the system 700 by swapping out the old OMM unit 708 and inserting a new upgraded version.
In some embodiments, system 700 is an optical computing platform configured to operate with OMM units provided by different companies. This allows different companies to develop different 3D passive optical neural networks for various applications. The 3D passive optical neural network is sold to end users in a standardized package that can be installed in an optical computing platform to allow the system 700 to perform various intelligent functions.
In some embodiments, the system may have a holder mechanism for supporting multiple OMM units 708, and a mechanical handling mechanism may be provided for automatically swapping out the OMM units 708. The system determines which OMM unit 708 is required for the current application and uses a mechanical processing mechanism to automatically retrieve the appropriate OMM unit 708 from the holder mechanism and insert it into the optical processor 702.
In some embodiments, the artificial neural network computing system 700 may be modified by adding an analog non-linear unit between the detection unit 710 and the ADC unit 160. The analog nonlinear unit is configured to receive the output voltage from the detection unit 710, apply a nonlinear transfer function, and output the converted output voltage to the ADC unit 160. The controller 110 may obtain a converted digital output voltage corresponding to the converted output voltage from the ADC unit 160. Since the digital output voltage obtained from the ADC unit 160 has already been non-linearly converted ("activated"), the non-linear conversion step of the controller 110 can be omitted, thereby reducing the computational burden of the controller 110. Next, the first converted voltage directly obtained from the ADC unit 160 may be stored as a first converted digital output vector in the storage unit 120.
The optical interference unit may be implemented using passive diffractive optical components arranged in one dimension. Referring to fig. 9, in some embodiments, the artificial neural network computing system 900 has a light processor 906 that includes a one-dimensional light multiplication unit 916. The system 900 includes a storage unit 120, which is similar to the corresponding components of the system 100 in FIG. 1A. The light processor 906 is configured to perform multiplication calculations using diffractive optical components arranged in one dimension (along the light propagation axis).
The light processor 906 includes: a laser unit 908 configured to output a laser beam 910; and a modulator 912 configured to modulate the laser beam 910 to produce a modulated beam 914. The light processor 906 includes a one-dimensional light multiplication unit 916 having a one-dimensional arrangement of diffractive optical elements and configured to process the modulated light beam 914 and produce an output light beam 918. The light processor 906 comprises a detection unit 920, the detection unit 920 having a light sensor for detecting the output light beam 916. The output of the detection unit 920 is converted into a digital signal by the ADC unit 930.
For example, the light multiplication unit 916 may be implemented as a passive integrated silicon photonic waveguide with diffractive optical components (e.g., gratings or holes). The optical multiplication unit 916 may be configured to perform multiplication operations with almost zero power consumption.
There are many ways to encode the input data for use by the light processor 906. For example, a digital input vector may be encoded as an optical input propagating through optical multiplication unit 916. The optical multiplication unit 916 performs multiplication on the received optical input in the optical domain. The multiplication performed by the optical multiplication unit 916 is determined by the internal configuration of the optical multiplication unit 916, including, for example, the size, position, and geometry of the diffractive optical elements arranged in one dimension along the optical propagation path, and the doping (if any) of impurities.
The optical multiplication unit 916 may be implemented in various ways. Fig. 10 is a diagram showing an example of the light multiplication unit 916 using one-dimensional arrangement of diffraction elements. The optical multiplication unit 916 may include an input waveguide for receiving the optical input 1002, a one-dimensional optical interference unit 1004 in optical communication with the input waveguide, and an output waveguide in optical communication with the optical interference unit 1004 for providing an optical output 1006. The optical interference unit 1004 includes a plurality of diffractive optical elements and performs conversion (e.g., linear transformation) of the optical input to the optical output. The output wave guides the optical signal output by the light guide interference unit 1004.
In some embodiments, the optical interference unit 1004 includes an elongated substrate having diffractive components arranged in one dimension along the optical propagation path. For example, a plurality of holes may be drilled or etched in the substrate. The size of these apertures may be comparable in magnitude to the size of the wavelength of the input light, such that the light is diffracted by the apertures (or the structure defining the apertures). The holes may be of the same or different sizes. The substrate may be made of a material that is transparent or translucent to the input light, e.g. having a transmission rate of 1% to 99% with respect to the input light. In some embodiments, holographic methods may also be used to form diffractive optical elements in the substrate.
When designing the optical interference unit 1004, the size and position of the diffractive components along the propagation path of the optical beam are considered. The configuration of the diffractive optical element can be determined using an optimization process. For example, the substrate may be divided into a series of pixels, and each pixel may be filled with substrate material (no holes) or with air (holes). The configuration of the pixels may be iteratively modified and for each configuration of pixels, a simulation may be performed by passing light through the diffractive optical component and evaluating the output. After performing a simulation of all possible configurations of pixels, the configuration that provides the closest result to the desired multiplication process is selected as the diffractive optical element configuration of the optical interference unit 1004.
As another example, the diffractive component is initially configured as a series of holes. The position and size of the holes may be slightly different from their initial configuration. The parameters for each hole may be iteratively adjusted and simulations may be performed to find an optimal configuration of holes.
In some embodiments, a machine learning process is used to design a one-dimensional diffractive optical component. It is determined how the pixels affect the analytical function of the input light and a gradient descent method is used to determine the optimal configuration of the pixels.
In some embodiments, the light multiplication unit 916 may be implemented as a user variable component, and different light multiplication units 916 with different light interference units 1004 may be installed for different applications. For example, system 900 may be configured as a bacteria detection system, and optical interference unit 1004 may be configured to implement a multiplication function for analyzing DNA sequences to detect certain bacterial strains. For example, the first optical multiplication unit may have a first optical interference unit comprising a 1D passive diffractive optical component configured to implement a first multiplication function for detecting the first group of bacteria. The second optical multiplication unit may have a second optical interference unit comprising a 1D passive diffractive optical component configured to implement a second multiplication function for detecting a second group of bacteria, and so on. The first and second optical multiplication units may be developed by different companies that specialize in developing techniques for detecting different bacteria. When a user wants to use the system 900 to detect a first group of bacteria, the user can insert a first optical multiplication unit into the system. When a user wants to use the system 900 to detect a second group of bacteria, the user can swap out the first optical multiplication unit and insert a second optical multiplication unit into the system. By using a one-dimensional diffractive optical component, the laser unit 908, the modulator 912, the detection unit 920, and the ADC unit 930 can be manufactured at low cost.
In some embodiments, the light multiplication unit 916 includes a housing (e.g., a cassette) that protects the substrate with the 1D diffractive optical element. The housing supports an input interface coupled to the input waveguide and an output interface coupled to the output waveguide. The input interface is configured to receive the output from the modulator 912, and the output interface is configured to transmit the output of the optical multiplication unit 916 to the detection unit 920. The optical multiplication units 916 may be designed as modules suitable for handling by ordinary consumers, allowing a user to easily switch from one optical multiplication unit 916 to another optical multiplication unit 916. Machine learning techniques improve over time. A user may upgrade system 900 by swapping out old optical multiplication units 916 and inserting a new upgraded version.
In some embodiments, system 900 is an optical computing platform configured to operate with optical multiplication units provided by different companies. This allows different companies to develop different 1D passive optical multiplication functions for various applications. The 1D passive optical multiplication functions are sold to end users in standardized packages that can be installed in optical computing platforms to allow the system 900 to perform various intelligent functions.
In some embodiments, the system may have a holder mechanism for supporting a plurality of optical multiplication units 916, and a mechanical handling mechanism may be provided for automatically swapping out the optical multiplication units 916. The system determines which optical multiplication unit 916 is needed for the current application and uses a mechanical processing mechanism to automatically retrieve the appropriate optical multiplication unit 916 from the holder mechanism and insert it into the optical processor 906.
In some embodiments, the artificial neural network computing system 900 may be modified by adding an analog non-linear unit between the detection unit 920 and the ADC unit 930. The analog nonlinear unit is configured to receive the output voltage from the detection unit 920, apply a nonlinear transfer function, and output the converted output voltage to the ADC unit 930. The controller 902 may obtain a converted digital output voltage from the ADC unit 930 corresponding to the converted output voltage. Because the digital output voltage from the ADC unit 930 has been non-linearly transformed ("activated"), the non-linear transformation step of the controller 902 may be omitted, thereby reducing the computational burden on the controller 902. Next, the first converted voltage directly obtained from the ADC unit 930 may be stored as a first converted digital output vector in the memory unit 120.
Passive chips with passive diffractive optical components have many advantages. First, because the active components (usually the most bulky components) have been eliminated, any chip of a given size can contain a larger neural network. A typically useful neural network may include millions of weights, which is challenging to implement on an active chip, and may require multiple data runs through the chip and reprogramming of the chip. In contrast, a single passive chip may be able to support the entire neural network. Second, the very low power consumption of passive chips is important for "edge" applications, as such applications may require small footprint (footprint) and low power consumption. Third, passive chips can be manufactured at very low cost because they do not contain active components.
The optical matrix multiplication unit with passive diffractive optical components may also be used in a wavelength division multiplexed artificial neural network computing system. For example, the OMM unit 150 of the system 104 in fig. 1F may be replaced with an OMM unit that uses passive diffractive optical components. In this example, the second DAC subunit 134 may be removed.
In some embodiments, the optical processor (e.g., 504, 702) may perform matrix processing other than matrix multiplication. The optical matrix multiplication units 502 and 708 may be replaced by optical matrix processing units that perform other types of matrix processing.
Fig. 25 shows a flow diagram of an example of a method 2500 of performing an ANN calculation using an ANN calculation system 500, 700, or 900, the ANN calculation system 500, 700, or 900 including one or more optical matrix multiplication units or optical multiplication units with passive diffractive components, such as a 2D OMM unit 502, a 3D OMM unit 708, or a 1D OM unit 916. The steps of process 2500 may be performed, at least in part, by controller 110 or 902. In some embodiments, the respective steps of method 2500 may be run in parallel, combined, in a loop, or in any order.
In step 2510, an Artificial Neural Network (ANN) computation request is received that includes an input data set. The input data set includes a first numeric input vector. The first digital input vector is a subset of the input data set. For example, it may be a sub-region of the image. The ANN calculation request may be generated by various entities (e.g., computer 102). The computer may include one or more of various types of computing devices, such as personal computers, server computers, vehicle computers, and flight computers. The ANN calculation request generally refers to an electrical signal informing or informing the ANN calculation system 500, 700, or 900 of the to-be-performed ANN calculation. In some embodiments, the ANN calculation request may be split into two or more signals. For example, the first signal may query the ANN computing system 500, 700, or 900 to check whether the system 500, 700, or 900 is ready to receive an input data set. In response to an acknowledgement by system 500, 700, or 900, the computer may transmit a second signal comprising the input data set.
In step 2520, the input data set is stored. The controller 110 may store the input data set in the storage unit 120. Storing the input data set in the memory unit 120 may allow flexibility in the operation of the ANN computing system 500, 700, or 900, such as may improve the overall performance of the system. For example, the input data set may be divided into numeric input vectors of a set size and format by retrieving a desired portion of the input data set from the storage unit 120. Different portions of the input data set may be processed in various orders or shuffled to allow various types of ANN calculations to be performed. For example, where the input and output matrix sizes are different, shuffling may allow matrix multiplication to be performed by block matrix multiplication techniques. As another example, storing the input data set in the storage unit 120 may allow for queuing of multiple ANN computation requests by the ANN computation system 500, 700, or 900, which may allow the system 500, 700, or 900 to maintain operation at its full speed without periods of inactivity.
In step 2530, a first plurality of modulator control signals are generated based on the first digital input vector. The controller 110 may transmit the first DAC control signal to the DAC cell 506, 712, or 904 to generate a first plurality of modulator control signals. The DAC unit 506, 712, or 904 generates a first plurality of modulator control signals based on the first DAC control signal, and the modulator array 144, 706 or the modulator 912 generates an optical input vector that represents a first digital input vector.
The first DAC control signal may comprise a plurality of digital values to be converted into a first plurality of modulator control signals by DAC cells 506, 712, or 904. The plurality of digital values generally corresponds to the first digital input vector and may be associated by various mathematical relationships or look-up tables. For example, the plurality of digital values may be linearly proportional to the values of the elements of the first digital input vector. As another example, the plurality of digital values may be associated with elements of the first digital input vector through a lookup table configured to maintain a linear relationship between the digital input vector and the optical input vector produced by the modulator array 144, 706 or the modulator 912.
In some embodiments, the 2D OMM unit 502, the 3D OMM unit 708, or the 1D OM unit 916 is configured to perform optical matrix processing or optical multiplication based on the optical input vector and a plurality of neural network weights implemented using passive diffractive components. The plurality of neural network weights representing the matrix M may be decomposed into M ═ USV by a Singular Value Decomposition (SVD) method, where U is an mxm unitary matrix, S is an mxn diagonal matrix with non-negative real numbers in diagonals, and V is a complex conjugate of an nxn unitary matrix V. In this case, the passive diffractive components may be configured to implement the matrix V, the matrix S, and the matrix U such that the OMM unit 502 or 708 as a whole implements the matrix M.
In step 2540, a first plurality of digital light outputs corresponding to the light output vectors of the light matrix multiplication unit or light multiplication is obtained. The optical input vectors generated by the modulator arrays 144, 706 or the modulator 912 are processed by the 2D OMM unit 502, the 3D OMM unit 708 or the 1D OM unit 916 and converted to optical output vectors. The light output vector is detected by the detection unit 146, 710 or 920 and converted into an electrical signal, which may be converted into a digital value by the ADC unit 160 or 930. The controller 110 or 902 may, for example, transmit a conversion request to the ADC unit 160 or 930 to begin converting the voltage output by the detection unit 146, 710 or 920 to a digital light output. Once the conversion is complete, the ADC unit 160 or 930 may transmit the conversion result to the controller 110 or 902. Alternatively, the controller 110 or 902 may retrieve the conversion result from the ADC unit 160 or 930. The controller 110 or 902 may form a digital output vector from the digital light output, the digital output vector corresponding to the result of a matrix multiplication or a vector multiplication of the input digital vector. For example, the digital light output may be organized or concatenated to have a vector format.
In some embodiments, the ADC unit 160 or 930 may be set or controlled to perform ADC conversion based on the DAC control signal being issued by the controller 110 or 902 to the DAC unit 506, 712, or 904. For example, the ADC conversion may be set to start at a preset time after the DAC unit 506, 712, or 904 generates the modulation control signal. Such control of the ADC conversion may simplify the operation of the controller 110 or 902 and reduce the number of necessary control operations.
In step 2550, a non-linear transformation is performed on the first digital output vector to produce a first transformed digital output vector. The nodes or artificial neurons of the ANN operate by first performing a weighted sum of the signals received from the nodes of the previous layer, and then performing a nonlinear transformation ("activation") of the weighted sum to produce an output. Various types of ANN may implement various types of differentiable nonlinear transformations. Examples of nonlinear transformation functions include modified Linear Unit (RELU) functions, sigmoid functions, hyperbolic tangent functions, X ^2 functions, and | X | functions. This non-linear transformation is performed on the first digital output by the controller 110 or 902 to produce a first transformed digital output vector. In some embodiments, the non-linear transformation may be performed by a dedicated digital integrated circuit within the controller 110 or 902. For example, the controller 110 or 902 may include one or more modules or circuit blocks specifically adapted to accelerate the calculation of one or more types of non-linear transformations.
In step 2560, the first transformed digital output vector is stored. The controller 110 or 902 may store the first transformed digital output vector in the memory unit 120. In the case where the input data set is divided into a plurality of digital input vectors, the first transformed digital output vector corresponds to the result of an ANN calculation of a portion of the input data set, e.g., the first digital input vector. As such, storing the first transformed digital output vector allows the ANN computation system 500, 700, or 900 to perform and store additional computations on other digital input vectors of the input data set to be later aggregated into a single ANN output.
In step 2570, an artificial neural network output generated based on the first transformed digital output vector is output. The controller 110 or 902 generates an ANN output that is a result of processing the input data set through an ANN defined by the first plurality of neural network weights. Where the input data set is divided into a plurality of digital input vectors, the resultant ANN output is an aggregated output comprising the first converted digital output, but may further comprise additional converted digital outputs corresponding to other portions of the input data set. Once the ANN output is generated, the generated output is transmitted to the computer (e.g., computer 102) that initiated the ANN calculation request.
The 2D OMM unit 502, 3D OMM unit 708, or 1D OM unit 916 may represent weight coefficients for a hidden layer of the neural network. If the neural network has multiple hidden layers, additional 2D OMM units 502, 3D OMM units 708, or 1D OM units 916 may be coupled in series. Fig. 26 illustrates an example of an ANN computing system 2600 for implementing a neural network having two hidden layers. The first 2D light matrix multiplication unit 2604 represents the weight coefficients of the first hidden layer, and the second 2D light matrix multiplication unit 2606 represents the weight coefficients of the second hidden layer. ANN computing system 2600 includes controller 110, storage unit 120, DAC unit 506, and photo-electric processor 2602. The memory unit 120 and the DAC unit 506 are similar to the corresponding components of the system 500 in fig. 5. The opto-electronic processor 2602 is configured to perform matrix calculations using optical and electronic components.
The optoelectronic processor 2602 includes a first laser unit 142a, a first modulator array 144a, a first 2D light matrix multiplication unit 2604, a first detection unit 146a, a first analog nonlinearity unit 310a, an analog storage unit 320, a second laser unit 142b, a second modulator array 144b, a second 2D light matrix multiplication unit 2606, a second detection unit 146b, a second analog nonlinearity unit 310b, and an ADC unit 160. The operation of the first laser unit 142, the first modulator array 144a, the first detection unit 146a, the first analog nonlinear unit 310a, and the analog storage unit 320 is similar to the corresponding components shown in fig. 3B. The first 2D OMM unit 2604 is similar to the 2D OMM 502 of fig. 5. The output of the analog memory unit 320 drives the second modulator array 144b, and the second modulator array 144b modulates the laser light from the second laser unit 142b to produce a light vector. The light vectors from second modulator array 144b are processed by second 2D OMM unit 2606, and second 2D OMM unit 2606 performs matrix multiplication and generates light output vectors, which are detected by second detection unit 246 b. The second detection unit 246b is configured to generate an output voltage of the optical signal corresponding to the optical output vector from the second 2D OMM unit 2606. The ADC unit 160 is configured to convert the output voltage into a digital output voltage. The controller 110 may derive a digital output from the ADC unit 160 corresponding to the light output vector of the second 2D OMM unit 2606. The controller 110 may form a digital output vector from the digital output, the digital output vector corresponding to a result of a second matrix multiplication of a non-linear transformation of a result of a first matrix multiplication of the input digital vector. The second laser unit 142b is combined with the first laser unit 142a by using a beam splitter to divert some of the light from the first laser unit 142a to the second modulator array 144 b.
The above principles may be applied to implement a neural network having three or more hidden layers, where the weight coefficients of each hidden layer are represented by a corresponding 2D OMM unit.
Fig. 27 illustrates an example of an ANN computing system 2700 for implementing a neural network having two hidden layers. The first 3D light matrix multiplication unit 2704 represents the weight coefficients of the first hidden layer and the second 3D light matrix multiplication unit 2706 represents the weight coefficients of the second hidden layer. The ANN computing system 2700 includes a controller 110, a memory unit 120, a DAC unit 712, and a photo processor 2702. The memory unit 120 and the DAC unit 712 are similar to the corresponding components of the system 700 in fig. 7. The electro-optical processor 2702 is configured to perform matrix calculations using optical and electronic components.
The electro-optical processor 2702 includes a first laser unit 704a, a first modulator array 706a, a first 3D light matrix multiplication unit 2704, a first detection unit 710a, a first analog non-linear unit 310a, an analog storage unit 320, a second laser unit 704b, a second modulator array 706b, a second 3D light matrix multiplication unit 2706, a second detection unit 710b, a second analog non-linear unit 310b, and an ADC unit 160. The operation of the first laser unit 704a, the first modulator array 706a, the first detection unit 710a, the first analog nonlinear unit 310a, and the analog storage unit 320 is similar to the corresponding components shown in fig. 3B. The first 3D OMM unit 2704 is similar to the 3D OMM 708 of fig. 7. The output of the analog memory unit 320 drives a second modulator array 706b, which second modulator array 706b modulates the laser light from the second laser unit 704b to produce a light vector. The light vectors from the second modulator array 706b are processed by a second 3D OMM unit 2706, which second 3D OMM unit 2706 performs matrix multiplication and generates light output vectors, which are detected by a second detection unit 710 b. The second detection unit 710b is configured to generate an output voltage of the optical signal corresponding to the optical output vector from the second 3D OMM unit 2706. The ADC unit 160 is configured to convert the output voltage into a digital output voltage. The controller 110 may derive a digital output from the ADC unit 160 corresponding to the light output vector of the second 3D OMM unit 2406. The controller 110 may form a digital output vector from the digital output, the digital output vector corresponding to a result of a second matrix multiplication of a non-linear transformation of a result of a first matrix multiplication of the input digital vector. The second laser unit 704b may be combined with the first laser unit 704a by using a beam splitter to divert some of the light from the first laser unit 704a to the second modulator array 706 b.
The above principles may be applied to implement a neural network having three or more hidden layers, where the weight coefficients of each hidden layer are represented by a corresponding 3D OMM unit.
The 2D OMM unit 502 and the 3D OMM unit 708 with passive diffractive optical components are adapted for a Recurrent Neural Network (RNN), where the output of the network during the (k) th pass through the neural network is recycled back to the input of the neural network and used as input during the (k +1) th pass, so that the weighting coefficients of the neural network remain the same during multi-pass.
Fig. 28 illustrates an example of a neural network computing system 2800, which can be used to implement a recurrent neural network. The system 2800 includes an optical processor 2802 that operates in a similar manner to the optical processor 140 of fig. 3B, except that the OMM unit 150 is replaced by a 2D OMM unit 2804, which 2D OMM unit 2804 may be similar to the 2D OMM unit 502 of fig. 6. The neural network weights of the 2D OMM unit 2804 are fixed, so the system 2800 does not require the second DAC subunit 134 used in the system 302 of fig. 3B.
Fig. 29 illustrates an example of a neural network computing system 2900, which may be used to implement a recurrent neural network. The system 2900 includes a light processor 2902 that operates in a manner similar to the light processor 140 of fig. 3B, except that the laser unit 142, modulator array 144, OMM unit 150, and detection unit 146 are replaced by the laser unit 704, modulator array 706, 3D OMM unit 2904, and detection unit 710, respectively, of fig. 7. The neural network weights of the 3D OMM unit 2904 are fixed, so the system 2900 does not require the second DAC subunit 134 used in the system 302 of fig. 3B.
Fig. 30 is a diagram illustrating an example of an artificial neural network computing system 3000 with a 1-bit internal resolution. The ANN computing system 3000 is similar to the ANN computing system 400 of fig. 4A, except that the OMM unit 150 is replaced by a 2D OMM unit 3004 (which is similar to the 2D OMM unit 502 of fig. 5), and the second driver subunit 434 is omitted. The ANN computing system 3000 operates in a manner similar to the ANN computing system 400 in that an input vector is decomposed into a plurality of 1-bit vectors, and then certain ANN computations may be performed by summing the respective matrix multiplication results after performing a series of matrix multiplications of the 1-bit vectors.
Fig. 31 is a diagram illustrating an example of an artificial neural network computing system 3100 having a 1-bit internal resolution. ANN computing system 3100 is similar to ANN computing system 400 of fig. 4A, except that OMM unit 150 is replaced by 3D OMM unit 3104 (which is similar to 3D OMM unit 708 of fig. 7) and second driver subunit 434 is omitted. In the example of fig. 31, the laser unit 142, modulator array 144, and detection unit 146 of fig. 4A are replaced by the laser unit 704, modulator array 706, and detection unit 710 of fig. 7, respectively. The ANN computing system 3100 operates in a manner similar to the ANN computing system 400 in that an input vector is decomposed into a plurality of 1-bit vectors, and then certain ANN computations may be performed by summing the respective matrix multiplication results after performing a series of matrix multiplications of the 1-bit vectors.
The principle of the optical diffraction neural network is described below. An optically diffractive neural network can be implemented as several layers of diffractive or transmissive optical media. Based on the Huygens-Fresnel principle, each point in the diffractive medium can be considered a secondary light source (secondary light source). For each light source, far field diffraction (far field diffraction) can be described by the following equation:
here, the indices l and i denote the ith neuron in the l-th layer neural network, λ is the wavelength of light, and r is the distance, where:
the output from each secondary light source can be written as the input multiplied by the phase and intensity modulation of the light source:
here, t is transmission modulation (transmission modulation) which is a plurality of terms (complex term) including both amplitude and phase modulation, and
is the sum of the inputs from all previous light sources. In general, the output can be combined into the far field diffraction time w and amplitude | a | and an additional phase term (phase term). Thus, each point in each layer may be considered a neuron that takes input from multiple neurons from a previous layer and adds additional phase and intensity modulation before outputting to the next layer.
The following describes a compact design (compact design) of a compact photon matrix multiplier cell that can implement general unitary matrix multiplication. Referring to fig. 11, a photonic matrix multiplier unit 1100 includes a modulator 1102, a plurality of interconnected interferometers 1104, and an attenuator (attenuator) 1106. Interconnect interferometer 1104 includes directional coupler layers (or groups or sets) 1108a, 1108b, 1108c, 1108d, and 1108e (collectively 1108) and phase shifter layers (or groups or sets) 1110a, 1110b, 1110c, and 1110d (collectively 1110). Each directional coupler layer (or group or set of directional couplers) may include one or more directional couplers. Each phase shifter layer may include one or more phase shifters. In this example, the interconnect interferometer 1104 includes a five-layer directional coupler 1108 and a four-layer phase shifter. In other embodiments, the photonic matrix multiplier cell 1100 may have different directional couplers and phase shifter layers. Compared to conventional matrix multiplier units using interconnected mach-zehnder interferometers, the photonic matrix multiplier unit 1100 has a directional coupler 1108, the directional coupler 1108 being positioned in such a way that the number of layers of the directional coupler 1108 is reduced.
Here, the term "layer" in the phrases "directional coupler layer" and "phase shifter layer" refers to a group or set of directional couplers or phase shifters based on their position in the photonic matrix multiplier unit 1100 relative to the input and output ports. In the example of fig. 11, the input optical signal is processed by a first layer directional coupler 1108a, then by a second layer phase shifter 1110a, then by a third layer directional coupler 1108b, then by a fourth layer phase shifter 1110b, and so on.
For example, a conventional matrix multiplier cell using interconnected mach-zehnder interferometers may require 2N layers of directional couplers, while photonic matrix multiplier cell 1100 requires only N +2 layers of directional couplers. N represents the number of input signals, or the number of digits in the input vector. The grid architecture (mesh architecture) used in the photonic matrix multiplier unit 1100 may have the most compact geometry of the photonic interconnection interferometer that can perform general matrix calculations.
Fig. 12A shows a graph comparing the interconnection interferometer 1104 of the photonic matrix multiplier unit 1100 with conventionally designed interconnection interferometers for various numbers of input signals. When there are 4 input signals, the interconnect mach-zehnder interferometer 1200 according to the conventional design requires 8 layers of directional couplers, while the interconnect interferometer 1202 according to the new compact design requires only 6 layers of directional couplers. When there are 3 input signals, the interconnect mach-zehnder interferometer 1204 according to the conventional design requires 6 layers of directional couplers, while the interconnect interferometer 1206 according to the new compact design requires only 5 layers of directional couplers. When there are 8 input signals, the interconnect mach-zehnder interferometer 1208 according to the conventional design requires 16 layers of directional couplers, while the interconnect interferometer 1210 according to the new compact design requires only 10 layers of directional couplers.
Generally, when there are n input signals, an interconnected mach-zehnder interferometer according to a conventional design requires 2n layers of directional couplers, while an interconnected interferometer according to a new compact design requires only n +2 layers of directional couplers.
In conventional designs, there are n layers of mach-zehnder interferometers for n input signals, and each mach-zehnder interferometer includes a directional coupler, followed by a pair of phase shifters, followed by another directional coupler. Thus, the n-layer mach-zehnder interferometer has 2 n-layer directional couplers. As a result, in conventional designs, n layers of phase shifters and 2n layers of directional couplers are required for n input signals.
In contrast, in the new compact design, one layer of directional couplers is followed by a first layer of phase shifters, followed by a layer of directional couplers, followed by a second layer of phase shifters, followed by a layer of directional couplers, followed by a third layer of phase shifters, and so on. After the last phase shifter, there are two layers of directional couplers. As a result, for n input signals, there are n layers of phase shifters and n +2 layers of directional couplers.
Because directional couplers occupy a large amount of space, reducing the number of directional couplers from 2 · n to n +2 can allow the size of the photonic matrix multiplier cell 1100 to be significantly reduced compared to conventional designs.
FIG. 12B shows a diagram of a compact interconnection interferometer 1212 in accordance with the new design, where the number of input signals is 5.
The compact design decomposition using gradient descent is described below. The compact design of the photon matrix multiplier described above can employ any unitary matrix U and use an analytical decomposition algorithm (analytical decomposition algorithm) to determine which phases need to be implemented using phase shifters and thus implement the matrix U. For example, the phase can be extracted from a given matrix U by using gradient descent. The gradient descent process is as follows. Starting with a fixed matrix U and initializing random weights theta for compactly designed phase shifters. The matrix U 'is constructed using a compact design, i.e., U' CompactDesign (θ). Next, look at the loss function (loss function) L ═ U-U' | ^2, which is the Frobenius norm of the matrix, and minimize the function using gradient descent (i.e., by updating θ using gradient updates).
Referring to fig. 13, homodyne detection (e.g., taking out real parts at the output) is used, thus providing an additional attenuator layer 1302 prior to detection to simulate an orthogonal matrix. This means that along with θ, the diagonal weight (diagonalweight) x of the attenuator also needs to be learned. In this way, the phase and diagonal weights required for U can be known, and the decomposition can be obtained in a value-wise manner.
The following describes light generating an impedance network (OGAN) that includes a generator configured to efficiently generate loyalty data (faithful data). Fig. 14 shows an example of a light generation reactive network 1400 in which the generator 1404 includes a neural network configured or trained to generate a synthetic image 1410 similar to a real image, and the discriminator 1402 includes a neural network trained to determine whether the input image is real or synthetic. An initial training image set 1406 is provided to train the discriminator 1402 so that the discriminator 1402 learns the features of the real images. Similarly, the generator 1404 is trained using a set of training images (not shown) so that the generator 1404 can generate a composite image 1410 having features similar to those of the real images.
In some embodiments, the training of the discriminator 1402 is performed electronically, for example, using a transistor-based data processor, such as a central processing unit or a general purpose graphics processor unit (general purpose graphics processor unit), to calculate weights for the neural layer of the discriminator 1402. Similarly, training of the generator 1404 is also performed electronically to calculate weights of the neural layer of the generator 1404.
The composite image 1410 generated by the generator 1404 may be provided to the discriminator 1402 to further train the discriminator 1402 so that the discriminator 1402 can more accurately detect a real image. The detection results of the discriminator 1402 may also be used to further train the generator 1404 so that the generator 1404 may produce a more realistic composite image 1410, i.e., closer to a real image.
Light generation reactance network 1400 has many applications. For example, in some applications, it may be difficult or expensive to obtain a large number of real images for training the discriminator 1402. To train the discriminator 1402 to detect (e.g., cancer cells), a large number of images of cancer cells are required during the training phase. Obtaining a large number of images of cancer cells from a cancer patient can be difficult and expensive, and thus there may not be enough samples to train the discriminator 1402 with sufficient accuracy. To improve the discriminator 1402, the generator 1404 is trained to generate a realistic image of the cancer cells, and the synthesized realistic image 1410 of the cancer cells is used to further train the discriminator 1402, thereby improving the ability of the discriminator 1402 to detect cancer cells.
In some embodiments, the generator 1404 may be an optical chip that contains active components, such as active phase shifters for modifying weights of the neural network. After training generator 1404, the active components are fixed to fix the weights. The random noise 1408 is fed to the generator 1404, and the generator 1404 then generates a composite image 1410 based on the random noise 1408, wherein the composite image 1410 is similar to a real image of a cancer cell.
In some embodiments, generator 1404 is implemented using an optical matrix multiplication unit as shown in fig. 5, 7, and/or 9. After determining the weights of the neural network, the optical matrix multiplication unit is configured based on the determined weights to implement the neural network. Because the input to generator 1404 is random noise 1408, it is not necessary to have an array of modulators, allowing generator 1404 to have a small footprint.
Whether generator 1404 is implemented using a passive optical chip or an optical chip with active components, trained generator 1404 can produce a realistic image (e.g., a realistic image similar to a cancer cell) that can then be provided to discriminator 1402 to further train and refine discriminator 1402. The generator 1404 has a high throughput and can generate the composite image 1410 at a rate potentially several orders of magnitude faster than using a conventional electronic data processor (e.g., a general purpose graphics processing unit). The generator 1404 has low power consumption, possibly several orders of magnitude lower, than when using a conventional electronic data processor.
The generator 1404 has a variety of applications. For example, the composite image generated by generator 1404 may have many applications in the medical field. The generator 1404 may be configured to synthesize images of tissue associated with certain diseases, and the synthesized images may be used to train the discriminator 1402 to identify tissue associated with diseases. For example, the composite image generated by generator 1404 may have many applications in the field of automated driving or navigation. For example, the generator 1404 may be configured to generate composite images of various traffic conditions, and the composite images may be used to train the discriminator 1402 to identify traffic conditions. For example, the composite image generated by the generator 1404 may have many applications in the field of manufacturing quality control. For example, the generator 1404 may be configured to generate a composite image of a product having a defect, and the composite image may be used to train the discriminator 1402 to detect the defective product.
In some embodiments, light generation reactance network 1400 includes a coherent light source (coherent light source), filters for input of random amplitudes and phases, where both amplitudes and phases follow a known distribution. Light-generating reactance network 1400 includes a mesh of interferometers (interferometers) for fast processing of information. Light generation reactance network 1400 may be designed to have an architecture that does not require shuffle (shuffle) weights, i.e., does not reprogram the interferometer. Light generation countermeasure network 1400 may also be designed to include fast phase shifters with operating rates greater than 1 GHz. Light generation reactance network 1400 may have a fast implementation of nonlinearity. For example, it may have (i) non-linearity in the analog electronics domain, (ii) simple optical non-linearity, or (iii) non-linearity in the digital electronics domain.
The following describes a novel photonic circuit having interconnected mach-zehnder interferometers and configured to implement logic gates (logic gates). Referring to fig. 15, the mach-zehnder interferometer 1500 includes a phase shifter 1502 configured to cause the mach-zehnder interferometer 1500 to effect the following rotations:
referring to fig. 16, photonic circuit 1600 may implement XOR gates and OR gates. Photonic circuit 1600 includes mach-zehnder interferometer 1500, detector 1602, and comparator 1604 with analog electronic thresholds. When input signals x1 and x2 are provided to photonic circuit 1600, mach-zehnder interferometer 1500 performs the following operations:
the analog electronic threshold of comparator 1604 is biased (biased) to 1/2 to remove
The factor, and therefore the output of the comparator 1604 is:
the photonic circuit 1600 produces the following results for various combinations of input signals x1, x 2:
in the above, the first pair of digits is the input signal, the second pair of digits is the output of the detector 1602, and the third pair of digits is the output of the comparator 1604. When the input (x1, x2) — 0, the mach-zehnder interferometer 1500 performs multiplication, producing a result (0,0), the detector 1602 outputs (0,0), and the comparator 1604 produces a result (0, 0). When the input (x1, x2) — 0,1, the mach-zehnder interferometer 1500 performs multiplication, producing a result
Detector 1602 output
And comparator 1604 produces a result (1, 1). When the input (x1, x2) is (1,0), the mach-zehnder interferometer 1500 performs multiplication, producing a result
Detector 1602 output
And comparator 1604 produces a result (1, 1). When the input (x1, x2) is (1,1), the mach-zehnder interferometer 1500 performs multiplication, producing a result
Detector 1602 output
And comparator 1604 produces a result (0, 1). The result indicates that detector 1602 generates at first output 1606a 
And in the second placeTwo output 1606b generation
Comparator 1604 removes
The factors to produce an XOR (x1, x2) at the first output 1608a and an OR (x1, x2) at the second output 1608 b.
Referring to fig. 17A, photonic circuit 1700 may implement AND gates AND OR gates. Photonic circuit 1700 includes mach-zehnder interferometer 1500 and detector 1602, where the output of detector 1602 is recycled once. When input signals x1 and x2 are provided to photonic circuit 1700, mach-zehnder interferometer 1500 and detector 1602 produce an output:
the output of detector 1602 is recycled back to the input of photonic circuit 1700, and after the signal second mach-zehnder interferometer 1500 and detector 1602, detector 1602 produces a final output:
in the above, the first pair of digits is the input signal, the second pair of digits is the output of the detector 1602 after the first pass, and the third pair of digits is the output of the detector 1602 after the second pass. When the input (x1, x2) — 0, the detector 1602 outputs (0,0) after the first pass through the mach-zehnder interferometer 1500, and the detector 1602 outputs (0,0) after the second pass mach-zehnder interferometer 1500. When inputting (x1, x) 2) When the value is (0,1), the detector 1602 outputs the first time after passing through the mach-zehnder interferometer 1500
And after the second mach-zehnder interferometer 1500, the detector 1602 outputs (0, 1). When the input (x1, x2) — 1,0, the detector 1602 outputs after a first pass through the mach-zehnder interferometer 1500
And after the second mach-zehnder interferometer 1500, the detector 1602 outputs (0, 1). When the input (x1, x2) — 1, the detector 1602 outputs after a first pass through the mach-zehnder interferometer 1500
And after the second mach-zehnder interferometer 1500, the detector 1602 outputs (1, 1). The above result indicates that after two passes, the detector 1602 produces a signal at the first output 1704 representing an AND (x1, x2), AND produces a signal at the second output 1706 representing an OR (x1, x 2).
FIG. 17B shows another embodiment of a photonic circuit 1710 including a first Mach-Zehnder interferometer 1712, a first detector 1714, a second Mach-Zehnder interferometer 1716, and a second detector 1718. The second detector 1718 produces a first output 1720 representing an AND (x1, x2) AND a second output 1722 representing an OR (x1, x 2).
The implementation of logic gates (e.g., AND, OR, AND XOR gates) using photonic circuits including mach-zehnder interferometers, directional couplers, planar optical waveguides, AND photodetectors is described above. Logic gates may be used to generate comparators to sort the algorithm, for example, an algorithm similar to the Bitonic sorter described in the linking URL < https:// en. wikipedia. org/wiki/Bitonic sorter >. As another example, logic gates may be used to construct a hashing algorithm (hashing algorithm) similar to SHA-2, which is described in the link URL < https:// en. wikipedia. org/wiki/SHA-2>, which is a standard proposed by NIST and has many applications including, for example, bitcoin mining and creation of bitcoin addresses. Because the logic circuits implemented using the photonic circuits described above are mostly passive, they can have less delay and lower power consumption than CMOS logic gates. There is no optical nonlinearity in the design of the optical logic gate. The non-linear response results from the detection of a signal using a photodetector.
Incoherent or low-coherence optical computing system
The following describes an optoelectronic computing system that processes incoherent or low coherence optical signals when performing matrix calculations. The light processor 140 of the ANN computing system 100 in fig. 1 includes a laser unit 142 that produces N light outputs having the same wavelength and that are optically coherent. The optical matrix multiplication unit 150 performs N × N matrix multiplication in the optical domain, where the optical signals remain coherent from the input of the OMM unit 150 to the output of the OMM unit 150. The advantages of the OMM unit 150 performing matrix multiplication in the optical domain have been described above. The following describes an optoelectronic computing system that does not require that the optical signals be coherent throughout the matrix multiplication process, where a portion of the computation is performed in the optical domain and a portion of the computation is performed in the electrical domain. The advantages of electro-optical computing systems have been described in the summary above.
Optoelectronic computing systems use different types of operations to produce computational results, each operation being performed on a signal (e.g., an electrical or optical signal) that is most suitable for the fundamental physical characteristics of the operation (e.g., in terms of energy consumption and/or speed). For example, the replication may be performed using optical power splitting, the summation may be performed using current-based summation, and the multiplication may be performed using optical amplitude modulation. An example of a calculation that may be performed using these three types of operations is to multiply a vector by a matrix (e.g., as employed by artificial neural network calculations). Various other calculations may be performed using these operations, which represent a general set of linear operations that may perform various calculations, including but not limited to: vector-vector dot product, vector-vector element-by-element multiplication, vector-scalar element-by-element multiplication, or matrix-matrix element-by-element multiplication.
Referring to fig. 18, an example of an optoelectronic computing system 1800 includes a set of optical ports/ light sources 1802A, 1802B, etc. that provide optical signals. For example, in some embodiments, optical port/light source 1802A may include an optical input coupler that provides an optical signal that is coupled to optical path 1803. In other embodiments, optical port/light source 1802A may include a modulated light source, such as a laser (e.g., for a coherent-sensitive embodiment) or a Light Emitting Diode (LED) (e.g., for a coherent-insensitive embodiment), that generates an optical signal that is coupled into optical path 1803. Some embodiments may include a combination of ports that couple optical signals into system 1800 and sources that generate optical signals within system 1800. The optical signal may include any light wave (e.g., an electromagnetic wave whose spectrum includes wavelengths in a range between about 100nm and about 1 mm) that has been or is being modulated with information using any of a variety of forms of modulation. Optical path 1803 may be defined, for example, based on a guided mode of an optical waveguide (e.g., a waveguide embedded in a Photonic Integrated Circuit (PIC) or an optical fiber) or based on a predetermined free-space path between optical port/light source 1802A and another module of system 1800.
In some embodiments, the optoelectronic computing system 1800 is configured to perform computations on an array of input values encoded on respective optical signals provided by the optical ports/ light sources 1802A, 1802B, etc. For example, for various machine learning applications based on neural networks, the computation may implement vector-matrix multiplication (or vector-by-matrix multiplication), in which an input vector is multiplied by a matrix to produce an output vector as a result. The light signal may represent elements of a vector, possibly including only a subset of selected elements of the vector. For example, for some neural network models, the size of the matrix used in the computation may be larger than the size of the matrix that may be loaded into a hardware system (e.g., an engine or co-processor of a larger system) that performs the vector matrix multiplication portion of the computation. Thus, performing a portion of the computation may involve dividing the matrix and vector into smaller segments (segments) that may be provided to the hardware system separately.
The modules shown in FIG. 18 may be for a 64 by 64 matrix of elements, for exampleA relatively large matrix (or sub-matrix) performs part of a larger system of vector matrix multiplications. For purposes of illustration, however, the modules will be described in the context of an example calculation that performs vector matrix multiplication using a 2 x 2 matrix of elements. The modules referenced in this example would include two copy modules 1804A and 1804B, four multiplication modules 1806A, 1806B, 1806C, and 1806D, and two summation modules, of which only one summation module 1808 is shown in fig. 18. These modules will input vectors 
Multiplication matrix
To generate an output vector
For the vector matrix multiplication
Output vector
Each of the two elements of (a) may be represented by a different equation, as shown below.
yA＝MAxA+MBxB
yB＝MCxA+MDxB
These equations can be broken down into separate steps that can be performed in the system 1800 using a basic set of operations: a copy operation, a multiply operation, and a sum operation. In these equations, each element of the input vector occurs twice, so there are two copy operations. There are also four multiplication operations and there are two summation operations. For systems that implement vector matrix multiplication using larger matrices, the number of operations performed will be larger, and using matrices that are not square in shape (i.e., different numbers of columns and rows), the number of relative instances of each operation will be different.
In this example, the copy operation is performed by the copy modules 1804A and 1804B. Input vector xAAnd xBAre represented by values encoded on optical signals from optical ports/ light sources 1802A and 1802B, respectively. Each of these values is used in two equations, so each value is replicated to provide two resulting copies to different respective multiplication modules. For example, as described in more detail below, values may be encoded in a particular time slot using light waves that have been modulated to have power from a set of multiple power levels, or light waves that have duty cycles from a set of multiple duty cycles. The values are copied by copying the optical signal on which the values are encoded. Is encoded with a representation element x AIs replicated by the replication module 1804A and encoded with a representation element xBThe optical signal of the value of (B) is replicated by the replication module 1804B. Each replication module may be implemented, for example, using an optical power splitter, such as a waveguide splitter that couples guided modes in an input waveguide to each of two output waveguides on a Y-splitter that gradually (e.g., adiabatically) splits the power, or a free-space splitter that uses a dielectric interface or film with one or more layers to transmit and reflect two output beams, respectively, from an input beam.
In this disclosure, it is said that the copy is encoded with the representation element x by the copy module 1804AAWhen the optical signal of (2) is an optical signal, it means that the element x is generated based on the input signalAThe output signal of the replica module 1804A does not necessarily have the same amplitude as the input signal. For example, if the replication module 1804A evenly splits the input signal power between the two output signals, each of the two output signals will have a power equal to or less than 50% of the input signal power. The two output signals are copies of each other, and the amplitude of each output signal of the copy module 1804A is different from the amplitude of the input signal. And, in having In some embodiments of a set of multiple replica modules for replicating a given optical signal or subset of optical signals, each individual replica module does not necessarily split power evenly between its generated replicas, but the set of replica modules may be collectively configured to provide replicas having substantially equal power as the input of a downstream module (e.g., a downstream multiplication module).
In this embodiment, the multiplication operations are performed by four multiplication modules 1806A, 1806B, 1806C, and 1806D. For each copy of an optical signal, a multiplication module multiplies the copy of the optical signal by matrix element values, which may be performed using optical amplitude modulation. For example, multiplication module 1806A will input vector element xAMultiplication by matrix element MA. Vector element xACan be encoded on the optical signal and the matrix element MAMay be encoded as an amplitude modulation level (am) of the optical amplitude modulator.
Is encoded with vector elements xAMay be encoded using different forms of amplitude modulation. The amplitude of the optical signal may correspond to a particular instantaneous power level P of the physical lightwave within a particular time slotAOr may correspond to a particular energy of a physical lightwave at a particular time slot A(the power integrated over time yields the total energy). For example, the power of the laser source may be modulated to have a particular power level from a predetermined set of multiple power levels. In some embodiments, it may be useful to operate the electronic circuit near an optimized operating point, so instead of varying the power over many possible power levels, an optimized "on" power level is used, where the signal is modulated to be "on" and "off (at zero power) for a particular portion of the time slot. The portion of the time that the power is at the "on" level corresponds to a particular energy level. Any of these particular values of power or energy may be mapped to element xAA specific value (using a linear or non-linear mapping relationship). After the signal is in the electrical domain, an actual integration over time (actual integration) of a specific total energy level is producedon over time) may occur downstream of system 1800, as described in more detail below.
In addition, the term "amplitude" may refer to the amplitude of a signal represented by the instantaneous or integrated power in an optical wave, or may equivalently refer to the "electromagnetic field amplitude" of an optical wave. This is because the electromagnetic field amplitude has a well-defined relationship to the signal amplitude (e.g., by integrating the electromagnetic field strength (proportional to the square of the electromagnetic field amplitude) over the transverse dimension of the guided mode or free space beam to produce instantaneous power). This results in a relationship between the modulation values, since by a specific value 
A modulator that modulates the amplitude of the electromagnetic field can also be considered to modulate the amplitude of the power-based signal by a corresponding value M (since the optical power is proportional to the square of the electromagnetic field amplitude).
Used by multiplication modules to encode matrix elements MAThe optical amplitude modulator of (a) may operate by changing the amplitude of the optical signal (i.e., the power in the optical signal) using any of a variety of physical interactions. For example, the modulator may include a ring resonator, an electro-absorption modulator, a thermo-electric optical modulator (thermal-optical modulator), or a mach-zehnder interference (MZI) modulator. In some techniques, a portion of the power is absorbed as part of a physical interaction, and in other techniques, the power is transferred using a physical interaction that modifies other characteristics of the optical wave than its power, such as its polarization or phase, or modifies the coupling of optical power between different optical structures (e.g., using a tunable resonator). For optical amplitude modulators that operate using interference (e.g., constructive and/or destructive interference) between light waves that have traveled on different paths, a coherent light source (e.g., a laser) may be used. For an optical amplitude modulator that operates using absorption, either a coherent or incoherent or low coherence light source, such as an LED, may be used.
In one example of a waveguide 1 x 2 optical amplitude modulator, a phase modulator is used to modulate power in an optical wave by placing the phase modulator in one of a plurality of waveguides of the modulator. For example, a waveguide 1 × 2 optical amplitude modulator may split an optical wave guided by an input optical waveguide into a first arm and a second arm. The first arm includes a phase shifter that produces a relative phase shift with respect to the phase delay of the second arm. The modulator then combines the light waves from the first and second arms. In some embodiments, the different phase delay values multiply the power in the light waves guided by the input optical waveguide by a value between 0 and 1 through constructive or destructive interference. In some embodiments, the first and second arms combine into each of two output waveguides, and the difference between the photocurrents produced by the respective photodetectors receiving the light waves from the two output waveguides provides a signed multiplication result (e.g., a value between-1 and 1), as described in more detail below. By appropriate choice of amplitude scaling of the coded light signal, the range of matrix element values can be mapped to any range of positive values (0 to M) or signed values (-M to M).
In this embodiment, the summing operation is performed by two summing modules, where summing module 1808 (shown in FIG. 18) is used to calculate output vector element yBThe summation is performed in the equation (1). A corresponding summing module (not shown) is used in the calculation of the output vector element yAThe summation is performed in the equation (1). The summing module 1808 produces an electrical signal representing the sum of the results of the two multiplication modules 1806C and 1806D. In this example, the electrical signal is a current isumIn a form proportional to the sum of the powers in the output optical signals produced by the multiplication modules 1806C and 1806D, respectively. In some embodiments, this current i is generatedsumThe summing operation of (a) is performed in the optical-electrical domain, and in other embodiments in the electrical domain. Alternatively, some embodiments may use optical-domain summing for some summing modules and electrical-domain summing for other summing modules.
In embodiments where the summation is performed in the electrical domain, the summation module 1808 may be implemented using: (1) two or more input conductors, each input conductor carrying an input current, the magnitude of the input current representing the result of one of the multiplication modules, and (2) at least one input And an output conductor carrying a current that is the sum of the input currents. This can occur, for example, if the conductors are wires that contact at a junction. For example, and without being bound by theory, this relationship can be understood based on Kirchhoff's current law, which indicates that the current flowing into a node is equal to the current flowing out of the node. For these embodiments, the signals 1810A and 1810B provided to the summing module 1808 are input currents that may be generated by photodetectors that are part of a multiplication module that generates respective photocurrents whose amplitudes are proportional to the power in the received optical signal. The summing module 1808 then provides an output current isum. The instantaneous value of the output current (instant value) or the integrated value of the output current (integrated value) may then be used to represent the quantitative value of the sum (quantitative value).
In embodiments where the summing is performed in the photo-electric domain, the summing module 1808 may be implemented using photo-detectors (e.g., photo-diodes) that receive the optical signals generated by the different respective multiplication modules. For these embodiments, signals 1810A and 1810B provided to summing module 1808 are input optical signals, each of which includes a light wave whose power represents the result of one of the multiplying modules. Output current i in this embodiment sumIs the photocurrent generated by the photodetector. Since the wavelengths of the light waves are different (e.g., sufficiently different that no significant constructive or destructive interference occurs between them), the photocurrent will be proportional to the sum of the powers of the received optical signals. The photocurrent is also substantially equal to the sum of the respective currents that would result in the respective detected optical powers being detected by the separate equivalent photodetectors. The wavelengths of the light waves are different but close enough that the photodetectors have substantially the same response (e.g., wavelengths within the substantially flat detection bandwidth of the photodetectors). As described above, summing in the electrical domain using current summing can achieve a simpler system architecture by avoiding the need for multiple wavelengths.
FIG. 19A illustrates a system for an implementation of a system that performs vector matrix multiplication using a 2 x 2 matrix of elements1900 in which the summing operation is performed in the electrical domain. In this example, the input vector is
And the matrix is
Each element of the input vector is encoded on a different optical signal. Two different replication modules 1902 perform optical replication operations to separate computations on different paths (e.g., an "up" path and a "down" path). There are four multiplication modules 1904, each multiplication module 1904 multiplying a different matrix element using light amplitude modulation. At the output of each multiplication module 1904, there is a photo detection module 1906 that converts the optical signal into an electrical signal in the form of a current. The summing module 1908 performs the summing in the electrical domain using the summing module 1908 to combine the two upper paths of different input vector elements and using the summing module 1908 to combine the two lower paths of different input vector elements. Thus, each element of the output vector is encoded on a different electrical signal. As shown in fig. 19A, as the calculation proceeds, each component of the output vector is incrementally produced to produce the following results for the upper and lower paths, respectively.
M11v1+M12v2
M21v1+M22v2
The configuration of system 1900 may be implemented using any of a variety of optoelectronic technologies. In some embodiments, there is a common substrate (e.g., semiconductor (e.g., silicon)) that can support the integrated optical and electronic components. The optical path may be implemented in a waveguide structure having a material with a higher optical index (pl) surrounded by a material with a lower optical index (pl), which defines a waveguide for propagating the optical wave carrying the optical signal. The electrical path may be implemented by a conductive material for propagating electrical current carrying electrical signals. (in fig. 19A to 20A, 21A to 24E, the thickness of the lines representing the paths is used to distinguish between optical paths (represented by thicker lines) and electrical paths (represented by thinner lines or dashed lines) unless otherwise noted.) optical devices (e.g., splitters and optical amplitude modulators) as well as electrical devices (e.g., photodetectors and operational amplifiers (op-amps)) can be fabricated on a common substrate. Alternatively, different portions of the system may be implemented using different devices having different substrates, and those devices may communicate over a communication channel. For example, optical fibers may be used to provide a communication channel to transmit optical signals between multiple devices used to implement an overall system. Those optical signals may represent different subsets of input vectors provided when performing vector matrix multiplication and/or different subsets of intermediate results calculated when performing vector matrix multiplication, as described in more detail below.
In the present disclosure, the figures may show optical waveguides passing through electrical signal lines, with the understanding that optical waveguides do not intersect electrical signal lines. The electrical signal lines and the optical waveguides may be arranged in different layers of the device.
Fig. 19B illustrates an example configuration of a system 1920 for an implementation of a system that performs vector matrix multiplication using a 2 x 2 matrix of elements, where the summation operation is performed in the optical-electrical domain. In this example, two different respective wavelengths λ are used1And λ2Different input vector elements are encoded on the optical signal. Also, the optical output signals of the multiplication modules 1904 are combined in the optical combiner module 1910 such that the optical waveguide directs two optical signals at two wavelengths to each photo-electric summation module 1912, which can be implemented using a photo-detector, such as the photo-detection module 1906 used in the example of fig. 19A. However, in this example, the sum is represented by the photocurrent indicative of the power in the two wavelengths, rather than the current leaving the junction between the different conductors.
In the present disclosure, when the drawings show two optical waveguides crossing each other, it will be clear from the description whether the two optical waveguides are actually optically coupled to each other. For example, two waveguides that appear to cross each other as shown from a top view of the device may be implemented in different layers and thus do not cross each other. For example, the optical signal λ 2Provided as input to the replicationOptical path of module 1902 and provision of optical signal M from multiplication module 190411V1The optical paths to the optical combiner module 1910 are not optically coupled to each other, although in the figures they may appear to cross each other. Similarly, the optical signal λ is provided from the replica module 19022Optical path to multiplication module 1904 and provision of optical signal M from multiplication module 190421V1The optical paths to the optical combiner modules 1910 are not optically coupled to each other, although in the figures they may appear to cross each other.
The system configuration shown in fig. 19A and 19B may be extended to realize a system configuration for performing vector matrix multiplication using an m × n element matrix. In this example, the input vector is
And the matrix is
For example, the input vector element v1To vnIs provided by n waveguides and each input vector element is processed by one or more copy modules to provide m copies of the input vector element to m respective paths. There are M x n multiplication modules, each multiplying a different matrix element with the light amplitude modulation to produce a representation Mij·vj(i-1 … m, j-1 … n)) or an optical signal. Using the ith summation module (i ═ 1 … M) to combine and represent M ij·vj(j-1 … n) to yield the following results for the m paths, respectively.
M11v1+M12v2+…+M1nvn
M21v1+M22v2+…+M2nvn
…
Mm1v1+Mm2v2+…+Mmnvn
Since optical amplitude modulation can reduce the power in an optical signal from its full value to a lower value, the reductionLow to zero (or near zero) power and therefore any value between 0 and 1 can be multiplied. However, some calculations may require multiplication by a value greater than 1 and/or multiplication by a signed (positive or negative) value. First, to extend the range to 0 to Mmax(wherein M ismax>1) The original modulation of the optical signal may comprise passing through MmaxExplicit (explicit) or implicit (implicit) scaling of original vector element amplitudes (or equivalently, by 1/M)maxScaling values mapped to particular vector element magnitudes in a linear mapping) such that a range of 0 to 1 of matrix element magnitudes quantitatively corresponds to a range of 0 to M in the calculationmax. Second, to fit a positive range of matrix element values from 0 to MmaxExtension to signed range-MmaxTo MmaxA symmetric differential configuration may be used, as described in more detail below. Similarly, symmetric differential configurations may also be used to extend the positive range of values encoded on various signals to signed ranges of values.
Fig. 20A shows an example of a symmetric differential configuration 2000 for providing a signed range of values for values encoded on an optical signal. In this example, there are two correlated light signals, encoded as unsigned values, specified as 
And
wherein each value is assumed to be between 0 (e.g., corresponding to near zero optical power) and VmaxE.g., optical power corresponding to a maximum power level. The relationship between two optical signals is when one optical signal uses a "main" value
When encoding, the other optical signal uses the corresponding anti-symmetry value
Coding, so that the principal value is coded on an optical signal
From 0 to V, monotonically increasing (monotonically increasing)maxAntisymmetric values encoded on paired optical signals
From VmaxMonotonically decreases (monotonically decrease) to 0. Or, conversely, when the principal value is encoded on an optical signal
From VmaxAntisymmetric values encoded on the paired optical signals when monotonically decreasing to 0
Monotonically increasing from 0 to Vmax. After the optical signals in the upper and lower paths are converted into current signals by the respective photo detection modules 1906, a difference between the current signals may be generated by a current subtraction module 2002. Encoding
And
leads to a useful signed value V1The encoded current, given as:
with unsigned primary values
Monotonically increasing from 0 to VmaxAnd the antisymmetric value paired therewith
From VmaxMonotonically decreasing to 0, signed value V 1at-VmaxAnd VmaxMonotonically increases in between. There are various techniques that may be used to implement the symmetric differential configuration of fig. 20A, as shown in fig. 20B and 20C.
In fig. 20B, the optical signals are detected in a common-terminal configuration, where two photodiode detectors are connected to a common terminal 2032 (e.g., inverting terminal) of an operational amplifier 2030. In this configuration, current 2010 generated from first photodiode detector 2012 and current 2014 generated from second photodiode detector 2016 are combined at junction 2018 between the three conductors to produce difference current 2020 between current 2010 and current 2014. Current 2010 and current 2014 are provided from opposite sides of the respective photodiodes connected at the other end to provide the same magnitude vbiasBut a voltage source (not shown) of bias voltage of opposite sign as shown in fig. 20B. In this configuration, a difference is generated due to the behavior of the current contacting at common node 2018. Difference current 2020 represents a signed value encoded on the electrical signal that corresponds to a difference between unsigned values encoded on the detected optical signal. The operational amplifier 2030 may be configured as a transimpedance amplifier (TIA) configuration in which the other terminal 2024 is connected to ground and the output terminal 2026 is fed back to the common terminal 2032 using a resistive component 2028, the resistive component 2028 providing a voltage proportional to the difference current 2020. Such a TIA configuration would provide the resulting value as an electrical signal in the form of a voltage signal.
In fig. 20C, the optical signal is detected in a differential terminal configuration, where two photodiode detectors are connected to different terminals of an operational amplifier 2050. In this configuration, the current 2040 generated from the first photodiode detector 2042 is connected to the inverting terminal 2052, and the current 2044 generated from the second photodiode detector 2046 is connected to the non-inverting terminal 2054. The currents 2040 and 2044 are provided from the same end of the respective photodiodes, which are connected at the other end to provide the same magnitude vbiasAnd a voltage source (not shown) of the same sign of bias voltage as shown in fig. 20C. The output 2056 of the operational amplifier 2050 in this configuration provides the difference between the current 2040 and the current 2044A proportional current. In this configuration, a difference is generated due to the behavior of the circuit of the operational amplifier 2050. The difference current flowing from output 2056 represents the signed value encoded on the electrical signal, which corresponds to the difference between the unsigned values encoded on the detected optical signal.
Fig. 21A shows an example of a symmetric differential configuration 2100 for providing a signed range of values for values encoded as modulation levels for an optical amplitude modulator implementing the multiplication module 1904. In this example, there are two related modulators configured to pass a signal designated as 
And
assuming that each value is between 0 (e.g., corresponding to an optical power modulated down to near zero) and Mmax(e.g., corresponding to optical power maintained near a maximum power level). The relationship between the two modulation levels is when one modulation level is configured at the "primary" value
While the other modulation level is configured at the corresponding "antisymmetric" value
So that when the dominant value of a modulator
Monotonically increasing from 0 to MmaxWhile the antisymmetric value of the other modulator
From MmaxMonotonically decreases to 0. Or, conversely, when the principal value of a modulator
From MmaxMonotonyWhen reduced to 0, the antisymmetric value of the other modulator
Monotonically increasing from 0 to Mmax. After the replication modules 1902 replicate the input optical signal encoded with the value V, each modulator provides a modulated output optical signal to a corresponding photo-detection module 1906. The multiplication module 1904 in the upper path includes an AND
Multiply and provide the value
A modulator of the encoded optical signal. The multiply module 1904 in the lower path includes an AND
Multiply and provide the value
A modulator of the encoded optical signal. After the light signals are converted to current signals by the respective photo detection modules 1906, the difference between them may be generated by the current subtraction module 2102. Encoding 
And
results in multiplying the current encoded by V by a signed value M11Given as:
with unsigned primary values
Monotonically increasing from 0 to MmaxAnd paired therewithAntisymmetric value of
From MmaxMonotonically decreasing to 0, signed value M11at-MmaxAnd MmaxMonotonically increases in between.
Fig. 21B illustrates an example configuration of a system 2110 for an implementation of system 1800 that performs vector matrix multiplication using a 2 x 2 matrix of elements, where the summation operation is performed in the electrical domain and has signed elements of the input vector and signed elements of the matrix. In this example, for each signed element of the input vector, there are two correlated light signals encoding unsigned values. For a first signed input vector element value V1Two are assigned as
And
and for a second signed input vector element value V2Two are assigned as
And
is set to zero. Each unsigned value encoded on the optical signal is received by the replication module 2112, and the replication module 2112 performs one or more optical replication operations that produce four copies of the optical signal on four respective optical paths. In some embodiments of the replication module 2112, there are three different Y-waveguide splitters, each configured to split using a different power ratio (which may be achieved using any of a variety of photonic devices, for example). For example, the first separator may use a 1: a power ratio of 4 to transfer 25% (1/4) of the power to the first path, the second splitter may use a 1: a power ratio of 3 is split to transfer 25% (1/4 ═ 1/3 × 3/4) of the power to the second path, and the second path The three separators may use 1: the power ratio of 2 is split to transfer 25% (1/4 ═ 1/2 × 2/3 × 3/4) of the power to the third path and the remaining 25% of the power to the fourth path. For example, respective splitters that are part of the replication module 2112 can be arranged in different portions of the substrate to properly distribute different replicas to different paths within the system. In other embodiments of the replication module 2112, different numbers of paths may be separated, suitably at different separation rates. For example, the first separator may use a 1: a power ratio of 2 is split to provide two intermediate optical signals of substantially the same power (e.g., 50% of the power of the input optical wave to each of the two output ports). Next, a solution having 1: a second splitter of power ratio of 2 to split one of these intermediate optical signals to transfer 25% of the input optical wave power to each of the first and second paths, and a splitter having a 1: a 2 power ratio third splitter to split the other of the intermediate optical signals to transfer 25% of the input optical wave power to each of the third and fourth paths.
An optical replication distribution network having this type of binary tree topology offers particular advantages. For example, because binary tree optical replication distribution networks may use a symmetric design (e.g., Y-shaped adiabatic waveguide taper) on a uniform 1:2 power splitter for all wavelengths, the network may be wavelength independent, facilitating its use for multiple wavelengths. Furthermore, a non-uniform power splitter may have coupled sections that require precise control of length to convert different power ratios (e.g., 1/n, 1/(n-1), … …, etc. for an n-branch network). However, such accuracy can be difficult in existing manufacturing variations. This binary tree optical replication distribution network also facilitates shortening of the electrical paths of the partially compact die layout, as described in more detail below with reference to fig. 45A-45G.
The configuration of system 2110 also includes other modules arranged as shown in fig. 21B to provide two different output electrical signals representing output vectors that are the result of a vector matrix multiplication performed by system 100. There are 16 different multiplication modules 1904 that modulate different copies of the optical signal representing the input vector, and 16 different photo-detection modules 1906 to provide electrical signals representing intermediate results of the calculations. There are also two different summation modules 2114A and 2114B that calculate the overall summation of each output electrical signal. In the figure, signal lines that electrically couple the photodetection module 1906 to the summing module 2114B are shown in dashed lines. Because each overall sum may include some antisymmetric terms (anti-symmetric terms) subtracted from the pairwise principal terms (paired main terms) from any symmetric differential configuration for the vector elements and/or matrix elements, summing modules 2114A and 2114B may include mechanisms for adding some terms in the sum after being inverted (inverted) (equivalently, subtracted from the non-inverted terms). For example, in some embodiments, the summing modules 2114A and 2114B include inverting and non-inverting input ports, such that the terms to be added in the overall demand sum may be connected to the non-inverting input ports and the terms to be subtracted in the overall demand sum may be connected to the inverting input ports. An exemplary embodiment of such a summing module is an operational amplifier, wherein the non-inverting terminal is connected to a conductor conducting a current representing the signal to be added and the inverting terminal is connected to a conductor conducting a current representing the signal to be subtracted. Alternatively, if inversion of the antisymmetric terms is performed by other means, an inverting input port may not be required on the summing block. The summation modules 2114A and 2114B generate the following summation results, respectively, to complete the vector matrix multiplication.
In the present disclosure, when the drawings show two electrical signal lines crossing each other, it is clear from the description whether the two electrical signal lines are electrically coupled to each other. For example, bearer M21 +V1+Signal informationThe signal line is not electrically coupled to the carrier M11 +V1 -Signal line or carrier M of signal11 -V1 -Signal lines for signals.
The system configuration shown in fig. 21B can be extended to implement a system configuration that performs vector matrix multiplication using an m x n matrix of elements, where the input vector and matrix include signed elements.
There are various techniques that may be used to implement the symmetric differential configuration of fig. 21B. Some of these techniques utilize a 1 x 2 optical amplitude modulator to implement the multiplication module 1904 and/or provide pairs of optical signals associated with the primary and anti-symmetric pairs. Fig. 22A shows an example of a 1 × 2 optical amplitude modulator 2200. In this example, the 1 × 2 optical amplitude modulator 2200 includes an input optical splitter 2202 that splits an input optical signal to provide 50% of the power to a first path that includes a phase modulator 2204 (also referred to as a phase shifter) and 50% of the power to a second path that does not include a phase modulator. The paths may be defined in different ways depending on whether the optical amplitude modulator is implemented as a free space interferometer or as a waveguide interferometer. For example, in a free space interferometer, one path is defined by the transmission of a wave through a beam splitter, and the other path is defined by the reflection of the wave from the beam splitter. In a waveguide interferometer, each path is defined by a different optical waveguide that has been coupled to an incoming waveguide (e.g., in a Y-splitter). The phase modulator 2204 may be configured to generate the phase shift such that the total phase delay of the first path differs from the total phase delay of the second path by a configurable phase shift value (e.g., a value that may be arranged as a phase shift somewhere between 0 degrees and 180 degrees).
The 1 x 2 optical amplitude modulator 2200 includes a 2 x 2 coupler 2206 that combines the optical waves from the first and second input paths using optical interference or optical coupling in a particular manner to transfer power into the first and second output paths at different rates, depending on the phase shift. For example, in a free space interferometer, a phase shift of 0 degrees results in constructive interference of substantially all input power split between the two paths to achieve decouplingOne output path of the splitter of combiner 2206 exits, and a phase shift of 180 degrees causes substantially all input power split between the two paths to constructively interfere to exit from the other output path of the splitter implementing coupler 2206. In a waveguide interferometer, a phase shift of 0 degrees results in substantially all of the input power split between the two paths being coupled to one output waveguide of coupler 2206, and a phase shift of 180 degrees results in substantially all of the input power split between the two paths being coupled to the other output waveguide of coupler 2206. The phase shift between 0 and 180 degrees may then multiply the power in the light wave (and the value encoded on the light wave) by a value between 0 and 1 by partial constructive or destructive interference or partial waveguide coupling. Multiplication by any value between 0 and 1 may then be mapped to multiplication by 0 and M as described above maxAny value between.
In addition, the relationship between the power in the two optical waves emitted from modulator 2200 follows the relationship between the power of the primary and anti-symmetric pairs described above. As the magnitude of the optical power of one signal increases, the magnitude of the optical power of the other signal decreases, and thus the difference between the detected photocurrents may produce a signed vector element, or multiplied by a signed matrix element, as described herein. For example, the pair of correlated optical signals may be provided from two output ports of modulator 2200 such that the difference between the amplitudes of the correlated optical signals corresponds to the result of multiplying the input value by the signed matrix element value. Fig. 22B shows a symmetric differential configuration 2210 of a 1 × 2 optical amplitude modulator 2200 with optical signals arranged at the output to be detected in the common-terminal version of the symmetric differential configuration of fig. 20B. The current signals corresponding to the photocurrents produced by the pair of photodetectors 2212 and 2214 are combined at junction point 2216 to provide an output current signal having a magnitude corresponding to the difference between the magnitudes of the associated light signals. In other embodiments, such as in the symmetric difference distribution of fig. 20C, the photocurrents detected from the two output optical signals may be combined using different circuits.
Other techniques may be used to construct a 1 x 2 optical amplitude modulator for implementing the multiplication module 1904 and/or to provide optical signal pairs associated with the primary and anti-symmetric pairs. Fig. 22C shows another example of a symmetric differential configuration 2220 for another type of 1 x 2 optical amplitude modulator. In this example, the 1 × 2 optical amplitude modulator includes a ring resonator 2222 configured to split the optical power of an optical signal at the input port 2221 into two output ports. The ring resonator 2222 (also referred to as a "micro ring") may be fabricated, for example, by forming a circular waveguide on a substrate, where the circular waveguide is coupled to a straight waveguide (straight waveguide) corresponding to the input port 2221. As the wavelength of the optical signal approaches the resonant wavelength associated with ring resonator 2222, the lightwaves coupled into the ring circulate around the ring on clockwise path 2226 and destructively interfere at the coupling location such that the reduced power lightwaves exit to the first output port via path 2224. The circulating lightwave is also coupled out of the ring such that another lightwave exits on path 2228 through the curved waveguide, which directs the lightwave out of the second output port.
Since the time scale of the optical power circulating around the ring resonator 2222 is small compared to the time scale of the amplitude modulation of the optical signal, an anti-symmetric power relationship is quickly established between the two output ports such that the optical wave detected by the photodetector 2212 and the optical wave detected by the photodetector 2214 form a major and anti-symmetric pair. The resonant wavelength of ring resonator 2222 may be adjusted to monotonically decrease/increase the primary/anti-symmetric signal to achieve a signed result, as described above. When the ring is completely non-resonant, all power leaves the first output port via path 2224, and when it is completely resonant, all power leaves the second output port via path 2228 with appropriate adjustment of certain other parameters (e.g., quality factor and coupling coefficient). In particular, in order to achieve full power transfer, the coupling coefficients characterizing the coupling efficiency between the (characterizing) waveguide and the ring resonator should be matched. In some embodiments, it may be useful to have a relatively shallow tuning curve (tuning curve), which may be achieved by decreasing the quality factor of the ring resonator 2222 (e.g., by increasing the loss) and correspondingly increasing the coupling coefficient into and out of the ring. The shallow tuning curve provides less amplitude sensitivity to the resonant wavelength. Techniques such as temperature control may also be used for tuning and/or stabilization of the resonant wavelength.
Fig. 22D shows another example of a symmetric differential configuration 2230 of another type of 1 x 2 optical amplitude modulator. In this example, the 1 × 2 optical amplitude modulator includes two ring resonators 2232 and 2234. The optical power of the optical signal at input port 2231 is split into two ports. As the wavelength of the optical signal approaches the resonant wavelength associated with the two ring resonators 2232 and 2234, the reduced power optical wave exits the first output port via path 2236. A portion of the optical wave is also coupled into ring resonator 2232, which circulates around the ring on clockwise path 2238, and is also coupled into ring resonator 2234, which circulates around the ring on counterclockwise path 2240. The circulating lightwave is then coupled out of the ring so that another lightwave exits the second output port via path 2242. In this example, the light wave detected by photodetector 2212 and the light wave detected by photodetector 2214 also form a primary and anti-symmetric pair.
Fig. 23A and 23B illustrate different examples of using an optical amplitude modulator, such as using a 1 x 2 optical amplitude modulator 2200, for implementing a system 1800 for performing vector matrix multiplication on a 2 x 2 matrix of elements.
FIG. 23A illustrates an example configuration of an optoelectronic system 2300A, which includes optical amplitude modulators 2302A and 2302B that provide values representative of signed vector elements of an input vector. Optical amplitude modulator 2302A provides a pair of optical signals that encode a pair of values for a first signed vector element 
And
and optical amplitude modulator 2302B provides a pair of optical signals that encode a pair of values for the second signed vector element
And
a Vector Matrix Multiplier (VMM) subsystem 2310A receives the input optical signal, performs splitting, multiplying, and some summing operations as described above, and provides an output current signal to be processed by additional circuitry. In some examples, the output current signal represents a partial sum that is further processed to produce a final sum that results in signed vector elements of the output vector. In this example, some final summing operations are performed as a subtraction between different partial sums represented by the current signals at the inverting and non-inverting terminals of operational amplifiers 2306A and 2306B. The subtraction is used to provide signed values as described above (e.g., with reference to fig. 21B). This example also illustrates how certain elements become part of multiple modules. In particular, the optical replication performed by waveguide splitter 2303 may be considered to be part of a replication module (e.g., one of replication modules 2112 in FIG. 21B) and part of a multiplication module (e.g., one of multiplication modules 1904 in FIG. 21B). The optical amplitude modulator used within the VMM subsystem 2310A is configured for detection in a common-terminal configuration shown in fig. 20B.
Fig. 23B illustrates an example configuration of the photoelectric system 2300B similar to that of the photoelectric system 2300A illustrated in fig. 23A. However, the VMM subsystem 2310B includes an optical modulator configured to detect in the differential terminal configuration shown in fig. 20C. In this example, the output current signal of the VMM subsystem 2310B also represents a partial sum that is further processed to produce a final sum that results in a signed vector element of the output vector. The final summing operation performed as a subtraction between different partial sums represented by the current signals of the inverting and non-inverting terminals of the operational amplifiers 2306A and 2306B is different from the example of fig. 23A. However, as described above (e.g., with reference to FIG. 21B), the final subtraction still results in the signed value being provided.
Fig. 23C illustrates an example configuration of an optoelectronic system 2300C that uses an alternative arrangement of a VVM subsystem 2310C with detection in a common terminal configuration (as in the VVM subsystem 2310A shown in fig. 23A), but with the optical signal carrying the result of the multiplication module routed through the subsystem within the waveguide (e.g., within a semiconductor substrate) to a portion of the substrate that includes a detector arranged to convert the optical signal to an electrical signal. In some embodiments, the grouping of such detectors allows for shortened electrical paths, potentially reducing electrical crosstalk or other damage due to long electrical paths that would otherwise be used. The optical waveguides may be routed within one layer of the substrate (route), or to prevent waveguide crossover (and associated losses) that may be encountered within a single layer, the waveguides may also be routed within multiple layers of the substrate to allow greater flexibility in routing paths that cross in two dimensions of the substrate but not in a third dimension (of the depth in the substrate). Various other changes may be made in the system configuration, including changes to components included in the VMM subsystem. For example, optical amplitude modulators 2302A and 2302B may be included as part of a VMM subsystem. Alternatively, the VMM subsystem may include an optical input port for receiving paired primary and anti-symmetric optical signals generated by modules other than the optical amplitude modulator, or for interfacing with other types of subsystems. In some embodiments, in addition to grouping detectors and using multiple layers for waveguides on a substrate, an alternative way to avoid waveguide crossover losses and still limit electrical path length involves rearranging the layout of the waveguides and the elements on the photonic integrated circuit die. For example, some manufacturing processes may introduce additional cost and/or complexity in order to provide multiple waveguide layers on a substrate. Conversely, the optical wiring may contain an optical replication distribution network that facilitates shortening the electrical paths of some compact die layouts, as described below with reference to FIGS. 45A-45G.
The long wires between a given photodetector and the downstream port have associated parasitic capacitances that result in increased power consumption down the wire to drive the signal. To limit power loss in the system, the layout of elements on a die containing a Photonic Integrated Circuit (PIC) implementing the optical processor may be optimized to allow for compact electrical routing. For example, the portions of the PIC (e.g., vector matrix multiplier subsystem 2310A or vector matrix multiplier subsystem 2310B) that implement distributed optoelectronic processing may be arranged so as to have a relatively narrow "optical ribbon" comprising: an optical waveguide that carries an optical signal of an optical input (e.g., from an optical modulator that provides elements of an input vector); optoelectronic nodes (e.g., including MZI modulators and detectors); and a wire carrying an electrical signal of the electrical output (e.g., a transimpedance amplifier feeding an element for providing an output vector). In some embodiments, the transimpedance amplifier (e.g., TIAs 2306A and 2306B) is part of an Electronic Integrated Circuit (EIC) flip-chip connected to a Photonic Integrated Circuit (PIC). The optical drop-out line comprises a plurality of "strands", wherein the plurality of strands comprises portions of the optical replication distribution network, and optoelectronic "nodes" (nodes) corresponding to specific columns of the matrix multiplication, which intersect with "slices", the slices comprising elements corresponding to specific rows of the matrix multiplication. These tiles in the PIC also overlap with corresponding tiles in the EIC, as described in more detail below.
Fig. 45A shows an example of one strand 4500 in such an optical flat cable. This strand 4500 includes: a binary tree light guide network that optically allocates corresponding input vector elements as intermediate nodes in a binary tree arrangement using a 1:2 splitter 4502; and optoelectronic node 4504, which performs optoelectronic operations as a leaf node in a binary tree arrangement. Alternatively, a strand may comprise two binary trees that assign respective primary and anti-symmetric values for the element, but one binary tree may be sufficient for some system configurations in which, for example, the matrix is limited to contain only positive weights for a particular software algorithm. In addition, the PIC would contain a wire (not shown) extending from node 4504, contacting the other strands of wire at the node. The root of each subnetwork of the optical replication distribution network may be fed by a root modulator (not shown) that modulates the optical waves according to the elements of the input vector (e.g., an MZI modulator such as 2302A or 2302B). In some embodiments, optoelectronic node 4504 at the leaf node of each optical replication distribution network includes a MZI modulator 4505 that multiplies by a matrix element, and a pair of photodetectors 4507 at the output of the MZI modulator for photoelectric conversion. The length of the conductive lines used to electrically route these electrical signals is dependent in part on the width of the entire optical flat cable. For N x N arrays of elements (e.g., multiplication of an N x N matrix), there are N sets of shares in the flat cable, each set having its own optical replication distribution network. Because the length of the longest wire may need to travel distances of up to N strands, each subnetwork (i.e., each binary tree) of the optical replication distribution network needs to occupy a narrow width. For simplicity and clarity of illustration, an example of 4 x 4 array elements is depicted, but in some implementations the value of N may be significantly increased (e.g., 32, 64, 128 or more).
As described above, an optical replica distribution network with tolerance to errors and wavelength independence can be manufactured by a binary tree topology, which allocates a given value to a node of a strand. As a motivation to consider the asymmetric arrangement of the binary tree in strand 4500, consider the possible size of the symmetric binary tree under an N × N matrix multiplication. Because a column is a tree of N elements whose width (N) is greater than depth (log2(N)), the tree can be arranged so that the narrowest dimension exceeds its depth. However, the last layer of the binary tree at the leaf needs to fit a symmetrical distribution of nodes across the width of the tree, so the waveguides in the tree need to have 90 degree turns to expand to a sufficiently large width. There will be a limit to the narrowness of this depth dimension based on the minimum radius of curvature needed to support the waveguide (to limit bend loss), resulting in a minimum width (e.g., about 40 microns) on each level of the tree. Thus, in this example, the total width is proportional to log2(N) times 40 microns. Instead, consider a symmetrical arrangement using a binary tree in strand 4500. In this asymmetric arrangement, the optical transmission lengths between the roots of the binary tree arrangement and the different opto-electronic nodes are different. In other asymmetric arrangements, some (but not necessarily all) of the lengths are different. In some asymmetric arrangements with a binary tree topology, the root may not be at the end of a strand, but may be somewhere between the two ends corresponding to the leaf nodes. The asymmetry contributes to the formation of narrow strands. The width of the 1: 2Y-shaped separator can be limited to about 1 micron per arm (i.e., about 2 microns in total) without changing orientation, and can take about 10 microns without making a 90 degree turn. The widest portion of the strands is at the top node, which has the width of the rectangular node + log2(N) the width of the adjacent waveguide. The width of each node is large enough to accommodate the width of the arm of the MZI modulator 2 (i.e. 20 microns or less). The width of this adjacent waveguide is about 2.5 microns (being the waveguide itself and its spacing from neighbors). Thus, the total width of the strands is proportional to 20 microns plus log2(N) times 2.5 microns, which may be much narrower than in the case of a symmetric binary tree.
Fig. 45B shows how a flex 4510 may be laid out on a PIC die. The flex 4510 comprises a first line 4512A of patches 4514 disposed on one side of a die; and a second line 4512B of the tile 4514 disposed on the other side of the die. Connection 4515 is provided by extending one or more waveguides in each strand. The sheets are distributed in two or more substantially straight lines, with the waveguides distributed over different portions of the die area (in this case, different ends of the die area) being connected within the strand by optical fibers replicating the distribution network, thereby achieving a more compact arrangement. Expanding the waveguide in this manner does increase the total optical insertion loss (e.g., by about 1dB/cm of the additional waveguide length), but such additional loss can typically persist. The number of lines of a slab to which the extended waveguides (e.g., 2 lines, 3 lines, 4 or more) connect can be selected to jointly optimize the adaptation to the die area and the total power loss in the overall system. For a large number of tiles, the substantially linear tiles may be arranged in uniformly spaced columns. Furthermore, the amount of waveguide extension can be limited by computational constraints, e.g., the propagation time over the length of the strand is significantly less than the time of a clock cycle, resulting in a limit to the total length of the strand (e.g., less than 10 cm).
Fig. 45C shows an arrangement of flex 4510 (sheet boundaries not shown) superimposed over an arrangement of bumps 4516 for electrically coupling pads (e.g., composed of a conductive material such as a metal or alloy) on the PIC that provide electrical input and output ports with corresponding pads on the EIC that provide electrical output and input ports. For example, a signal is provided through an output port of the EIC to control the MZI modulator (e.g., two bumps per MZI in a given optoelectronic node). In some embodiments, there are one or more additional bumps per optoelectronic node (e.g., a bump for temperature control of a given MZI modulator), as well as additional bumps for various other electrical signal exchanges between the PIC and the EIC. To convert electrical signals from the EIC to the PIC for control and to receive electrical signals from the PIC to the EIC, pads in the PIC would be aligned with corresponding pads at bump locations in the EIC. One example of a bump connecting the PIC output port to the EIC input port is a bump (not shown) connecting a pad in the chip that provides the summed current from the wires of multiple optoelectronic nodes to a pad of the TIA input in the EIC. A typical bump diameter may be about 100 microns, although the bump may be smaller (e.g., 50 microns). Thus, in some embodiments, the pitch of the bumps (e.g., 100 microns) may be greater than the pitch required for the sheets in the strands, in which case the sheets may be spread apart to provide a generally uniform sheet spacing.
Fig. 45D shows another example of a drop-in line 4520 that depicts an example of a tile 4522 that includes a root modulator 4524 that is used to modulate data values onto one of the strands of light waves that feed the optical replication distribution network. Among the strands, including the strand fed by root modulator 4524, is also an array of opto-electronic nodes 4526 (4 nodes in this example). In node 4526 there are a set of 4528 bumps (e.g., modulation weights for matrix multiplication) that are used to convey the phase modulation values from the EIC to the arms of the PIC MZI modulator. The patch 4522 also includes wires ending at pads, a plurality of which are connected via bumps 4530 with pads of the input of TIA 4532 in the EIC. It is the length of these wires in the dimension through the strands that should be optimized to remain relatively short, as this dimension scales by N, which may be relatively large in some implementations.
In fig. 45D, bumps 4528, 4530 and TIA 4532 are shown overlying tile 4522, but are not part of tile 4522. Because the root modulator 4524 of tile 4522 is placed at a different location on the die than the nodes of the optical replication distribution network, the waveguide portion connecting modulators 4524 contains the optical delay portion (or other form of optical delay) of the waveguide, matching the total effective optical distance and corresponding time delay to the root modulators of the other tiles. Thus, in this example, waveguide portion 4534 is longer than waveguide portion 4536.
Fig. 45E shows another optical flex 4540 for a different optoelectronic computing system that performs more computations with EICs instead of PICs. In this example, there is still a similar configuration of four tiles 4542, 4544, 4546 and 4548 in the PIC for 4 x 4 matrix multiplication. However, the optical waves carrying the modulated data values are detected and coupled to the EIC via bumps in the EIC connected to the TIA. Multiplication and addition as part of the VMM operation is then performed electronically using the digital values by digital circuitry in the EIC. For such calculations, in case synchronous communication occurs in the digital domain, time differences caused by different waveguide lengths can be compensated, and thus no optical delay is needed. Alternatively, another optoelectronic computing system may include an MZI modulator for performing weight multiplication, and the result of the optoelectronic multiplication may be detected and coupled to the EIC to perform the summation electronically using the digital value.
Fig. 45F shows another example of an optical flex 4550 and the types of electro-optical processing that may occur within tile 4552 in which various types of data processing are performed in the PIC. Typically, photodiodes are used to convert optical signals encoded on different strands distributed on a flex into electrical signals. These electrical signals are fed to data processing circuit 4560 in the PIC. The PIC also includes a data upload circuit 4570 for uploading results to flip-chip connected EICs or any other form of integrated electronic circuit operation.
Fig. 45G shows a view of an opto-electronic computing system 4580, showing an exemplary arrangement of various functions within the system including weight values (W #, #) for multiplication of matrix elements, Photodiodes (PD) for optical or electrical summation, and ADC modules for converting analog electrical signals to digital electrical signals. Different portions of the functionality may be included in the PIC or EIC in system 4580.
In some arrangements, the matrix multiplication may have different numbers of rows and columns. For example, for an M × N matrix multiplier, there are M electrical tiles (1 per row) in the EIC and M tiles in the PIC, where each tile has N weight modulators, corresponding to one of the N strands of the optical flat cable. As mentioned above, to better fit into the grains, rather than the long rows of M slices, there may be multiple rows: m/2 tiles in the first row and M/2 tiles in the second row, or four rows of M/4, M/4 tiles, etc. In some cases, four rows may be sufficient because the return on spatial distribution may be reduced, but in some cases the number of rows may be larger but smaller than M.
In some implementations, the EIC includes circuitry for components such as weight drivers, data drivers, memory (e.g., to store matrix weights for modulators and accumulation results), DACs, ADCs, digital logic (e.g., for accumulation), and portions of a digital data bus for communicating with other chips. For most cases, limited communication is required between different tiles (e.g. different rows in a matrix) due to the limited correlation between data computed in different tiles. Thus, the layout may allow the (short) rows added (by the current) to a given TIA (and corresponding element in the output vector) to be relatively independent in the layout. In most cases, there is no relationship between a given output vector and the input vector of the next iteration, but in some iterations of the computation (e.g., neural network computation), there is a correlation between the elements of the output vector and the corresponding elements of the input vector used in the next iteration. Rarely, there may be further correlation between other elements, such as when all elements are added as part of a normalized calculation that divides each element by the cumulative sum. Thus, in the layout, components that need to communicate with each other more frequently may be arranged together.
Fig. 24A illustrates an example configuration of a system 2400A for an implementation of system 1800, where there are multiple devices 2410 carrying (host) different multiplication modules (e.g., multiplication modules 1806A, 1806B, 1806C, and 1806D), each configured as a VMM subsystem to perform vector matrix multiplication on different subsets of vector elements through different sub-matrices of a larger matrix. For example, each multiplication module may be configured similar to the configuration of system 2110 (fig. 21B), but instead of implementing the VMM subsystem using a 2 x 2 matrix of elements, each multiplication module may be configured to implement the VMM subsystem using a matrix having a size as large as that which can be efficiently manufactured on a single device having a common substrate for the modules within that device. For example, each multiplication module may implement the VMM subsystem using a 64 x 64 element matrix.
Different VMM subsystems are arranged to combine the results of each sub-matrix appropriately to produce the result of a larger combined matrix (e.g., the elements of a 128-element vector multiplied by a 128 x 128-element matrix). Each set of optical ports or light sources 2402 provides a set of light signals that represent a different subset of the vector elements of a larger input vector. The replication module 2404 is configured to replicate all optical signals within a group of received optical signals (encoded on optical waves guided in a group 2403 of 64 optical waveguides) and provide the group of optical signals to each of two different groups of optical waveguides, in this example a group 2405A of 64 optical waveguides and a group 2405B of 64 optical waveguides. This copying operation is performed, for example, by using an array of waveguide splitters, each splitter in the array copies one element of a subset of input vector elements (e.g., a subset of 64 elements for each copy module 2404) by splitting the light waves in the set of optical waveguides 2403 into a first corresponding light wave in the set of optical waveguides 2405A and a second corresponding light wave in the set of optical waveguides 2405B. If multiple wavelengths (e.g., W wavelengths) are used in some embodiments, the number of separate waveguides (and thus the number of separate ports or sources in 2402) may be reduced by, for example, 1/W. Each VMM subsystem 2410 performs vector matrix multiplication, providing its partial results as a set of electrical signals (a subset of the elements used to output the vector), with corresponding partial results from different VMM subsystems 2410 summed together by a summing module 2414 as shown in fig. 24A using any of the techniques described herein (e.g., summing currents at junctions between conductors). In some embodiments, for any number of levels of recursion, vector matrix multiplication using the desired matrix may be performed recursively by combining the results from the smaller sub-matrices, ending with the use of a single-element light amplitude modulator at the root level (root level) of the recursion. At different levels of recursion, the VMM subsystem devices may be more compact (e.g., different data centers connected by long haul fiber networks at one level, different multi-chip devices connected by fiber in data centers at another level, different chips in devices connected by fiber at another level, and different portions of modules on the same chip connected by on-chip waveguides at another level).
Fig. 24B shows another example configuration of system 2400B, where additional devices are used for light transmission and reception to each VMM subsystem 2410. At the output of each VMM subsystem 2410, an optical transmitter array 2420 is used to couple each optical signal to a channel within the optical transmission line (e.g., fibers in a fiber bundle between the VMM subsystems 2410. the VMM subsystems 2410 may be carried by a separate device (host) and/or distributed at a remote location, or waveguides in a set of waveguides on an integrated device, such as a SoC carrying the VMM subsystems 2410 on a common substrate). An optical receiver array 2422 is used to output each subset of vector elements to convert the optical signals to electrical signals before the corresponding pairs of partial results are summed by the summing module 2414.
Fig. 24C illustrates another example configuration of system 2400C in which VMM subsystem 2410 may be reconfigured to enable different vector matrix multiplications for different sub-matrices to be rearranged in different ways. For example, the shape of a larger matrix formed by combining different sub-matrices may be configurable. In this example, two different subsets of optical signals are provided to the optical switch 2430 from each set of optical ports or light sources 2402. There is also an electrical switch 2440 that can rearrange the subset of electrical signals that represent the partial results to be summed by the summing module 2414 to provide one output vector or a separate output vector for the desired computation. For example, instead of vector matrix multiplication using a 2m × 2n size matrix composed of four m × n sized sub-matrices, the VMM subsystem 2410 may be rearranged to use a 2m × n size matrix or a m × 2n size matrix.
Fig. 24D illustrates another example configuration of system 2400D, where VMM subsystem 2410 may be otherwise reconfigured. Optical switch 2430 may receive up to four separate sets of optical signals and may be configured to provide different sets of optical signals to different VMM subsystems 2410 or to replicate any set of optical signals to multiple VMM subsystems 2410. Also, the electrical switch 2440 can be configured to provide any combination of the received sets of electrical signals to the summing module 2414. This greater reconfigurability enables a greater variety of different vector matrix multiplication calculations, including multiplication using matrices of sizes m x 3n, 3m x n, m x 4n, 4m x n.
FIG. 24E shows another example configuration of system 2400E that includes additional circuitry that can perform various operations (e.g., digital logic operations) to enable the configuration of system 2400E (e.g., an optoelectronic system for a complete optoelectronic computing system, or for a larger computing platform) to be used to implement a computing technique, such as artificial neural networks or other forms of machine learning. Data storage subsystem 2450 may include volatile storage media (e.g., SRAM and/or DRAM) and/or non-volatile storage media (e.g., solid state disk and/or hard disk). The data storage subsystem 2450 may also include a hierarchical cache module. The stored data may include, for example, training data, intermediate result data, or production data for feeding to an online computing system (online computing system). The data storage subsystem 2450 may be configured to provide concurrent access (concurrent access) to input data to modulate on different optical signals provided by the optical port or light source 2402. Conversion of data stored in digital form to analog form available for modulation may be performed by circuitry (e.g., a digital-to-analog converter) included at the output of data storage subsystem 2450, or at the input of optical port or light source 2402, or split between the two. An auxiliary processing subsystem (auxiliary processing subsystem)2460 may be configured to perform auxiliary operations (e.g., non-linear operations, data shuffling, etc.) on data, which may be cycled through multiple iterations of vector matrix multiplication using the VMM subsystem 2410. The result data 2462 from those ancillary operations may be transmitted to the data storage subsystem 2450 in digital form. The data retrieved by the data storage subsystem 2450 may be used to modulate an optical signal with the appropriate input vector and to provide control signals (not shown) for the modulation level used to place the optical amplitude modulator in the VMM subsystem 2410. The conversion of data encoded in analog form on electrical signals to digital form can be performed by circuitry (e.g., an analog-to-digital converter) within auxiliary processing subsystem 2460.
In some embodiments, a digital controller (not shown in the figures) is provided to control the operation of the data storage subsystem 2450, the hierarchical cache module, various circuits (e.g., digital-to-analog and analog-to-digital converters), the VMM subsystem 2410, and the light source 2402. For example, a digital controller is configured to execute program code to implement a neural network having a plurality of hidden layers. The digital controller iteratively performs matrix processing associated with respective layers of the neural network. The digital controller performs a first iteration of matrix processing by taking first matrix data from the data storage subsystem 2450, where the first matrix data represents coefficients of a first layer of the neural network, and arranging the modulation levels of the optical amplitude modulators in the VMM subsystem 2410 based on the taken data. The digital controller takes a set of input data from the data storage subsystem and arranges the modulation levels for the light sources 2402 to generate a set of optical input signals representing the elements of the first input vector.
The VMM subsystem 2410 performs matrix processing, representing processing of signals by the first layer of the neural network, based on the first input vector and the first matrix data. After the auxiliary processing subsystem 2450 generates the first set of result data 2462, the digital controller performs a second iteration of the matrix processing by retrieving second matrix data representing coefficients of a second layer of the neural network from the data storage subsystem, and arranging modulation levels of the optical amplitude modulator in the VMM subsystem 2410 based on the second matrix data. The first set of result data 2462 is used as a second input vector to arrange the modulation levels of the light sources 2402. The VMM subsystem 2410 performs matrix processing, representing processing of signals by the second layer of the neural network, based on the second input vector and the second matrix data, and so on. In the last iteration, an output of the signal processed by the last layer of the neural network is produced.
In some embodiments, when performing calculations associated with the hidden layer of the neural network, the resulting data 2462 is not transmitted to the data storage subsystem 2450, but is used by the digital controller to directly control a digital-to-analog converter that generates control signals for placement of the modulation level of the optical amplitude modulator in the VMM subsystem 2410. This reduces the time required to store data to and access data from data storage subsystem 2450.
Other processing techniques may be incorporated into other examples of system configurations. For example, various techniques used with other kinds of vector matrix multiplication subsystems (e.g., subsystems that use optical interference without electrical summing or signed multiplication as described herein) may be incorporated into some system configurations, such as some techniques described in U.S. patent publication No. US 2017/0351293, which is incorporated herein by reference.
Referring to fig. 32A, an Artificial Neural Network (ANN) calculation system 3200 includes a photoelectric matrix multiplication unit 3220, and the photoelectric matrix multiplication unit 3220 has, for example, a copy module, a multiplication module, and a summation module as shown in fig. 18 to 24D, to be able to process incoherent or low coherent optical signals when performing matrix calculation. The artificial neural network computing system 3200 includes a controller 110, a memory unit 120, a DAC unit 130, and an ADC unit 160, similar to those of the system 100 of fig. 1A. The controller 110 receives requests from the computer 102 and transmits computational output to the computer 102, similar to that shown in FIG. 1A.
The optoelectronic processor 3210 includes a light source 3230, which may be similar to the laser unit 142 of fig. 1A, wherein a plurality of output signals of the light source 3230 are coherent. The light source 3230 may also use light emitting diodes to generate multiple output signals that are incoherent or have low coherence. The electro-optical matrix multiplication unit 3220 includes a modulator array 144, the modulator array 144 receiving modulator control signals generated by the first DAC subunit 132 based on the input vectors, similar to the operations performed by the optical processor 140 of fig. 1A. The output of modulator array 144 may be compared to the output of optical port/light source 1802 in fig. 18. The optical matrix multiplication unit 3220 processes the optical signals from the modulator array 144 in a manner similar to the way the replication module 1804, multiplication module 1806, and summation module 1808 process the optical signals from the optical ports/optical sources 1802 in fig. 18.
Referring to fig. 32B, the photoelectric matrix multiplication unit 3220 receives an input vector
And multiplying the input vector by the matrix
To generate an output vector
The electro-optical matrix multiplication unit 3220 includes m optical paths 1803_1, 1803_2, … …, 1803_ m (collectively 1803) carrying optical signals representing input vectors. The replication module 1804_1 transfers the input optical signal v 1Are provided to the multiplication modules 1806_11, 1806_21, … …, 1806_ m 1. The replication module 1804_2 transfers the input optical signal v2Are provided to the multiplication modules 1806_12, 1806_22, … …, 1806_ m 2. The replication module 1804_ n outputs the optical signal vnAre provided to the multiplication modules 1806_1n, 1806_2n, … …, 1806_ mn.
As described above, the optical signal v provided by the replication module 1804_11Are identical (or substantially identical) with respect to each other, but are identical to the optical signal v provided by the modulator array 1441Are different in magnitude. For example, if the replication module 1804_1 evenly divides the optical signal v provided by the modulator array 144 among the m signals1Will have a signal power equal to or less than the optical signal v provided by the modulator array 14411/m of the power of (1).
The multiplication module 1806_11 inputs the signal v1And matrix element M11Multiplying to produce M11·v1. The multiplication module 1806_21 inputs the signal v1And matrix element M21Multiplying to produce M21·v1. The multiplication module 1806_ m1 inputs the signal v1And matrix element Mm1Multiplying to produce Mm1V 1. The multiplication module 1806_12 inputs the signal v2And matrix element M12Multiplying to produce M12·v2. The multiplication module 1806_22 inputs the signal v 2And matrix element M22Multiplying to produce M22·v2. The multiplication module 1806_ m2 inputs the signal v2And matrix element Mm2Multiplying to produce Mm2·v2. The multiplication module 1806_1n inputs the signal vnAnd matrix element M1nMultiplying to produce M1n·vn. The multiplication module 1806_2n inputs the signal vnAnd matrix element M2nMultiplying to produce M2n·vn. The multiplication module 1806_ mn inputs the signal vnAnd matrix element MmnMultiplying to produce Mmn·vnAnd so on.
The second DAC subunit 134 generates control signals based on the values of the matrix elements and transmits the control signals to the multiplication module 1806 to enable the multiplication module 1806 to multiply the values of the input vector elements by the values of the matrix elements, for example using optical amplitude modulation. For example, the multiplication module 1806_11 may comprise an optical amplitude modulator and may be implemented by combining matrix elements M11As applied to represent the input vector element v1The input vector elements v may be implemented1Multiplication by matrix element M11。
The summing module 1808_1 receives the outputs of the multiplication modules 1806_11, 1806_12, … …, 1806_1n and produces a signal equal to M11v1+M12v2+…+M1nvnSum of (a) y1. The summing module 1808_2 receives the outputs of the multiplication modules 1806_21, 1806_22, … …, 1806_2n and produces a signal equal to M 21v1+M22v2+…+M2nvnSum of (a) y2. The summing module 1808_ n receives the output of the multiplication modules 1806_ m1, 1806_ m 2, … …, 1806_ mnAnd produces a signal equal to Mm1v1+Mm2v2+…+MmnvnSum of (a) yn。
In the system 3200, the output of the photo matrix multiplication unit 3220 is provided to the ADC unit 160 without passing through the detection unit 146 as is the case in the system 100 of fig. 1A. This is because the multiplication module 1806 or the summation module 1808 has already converted the optical signal to an electrical signal, and therefore no separate detection unit 146 is required in the system 3200.
Fig. 33 illustrates a flow diagram of an example of a method 3300 of performing an ANN calculation using the ANN calculation system 3200 of fig. 32A. The steps of method 3300 may be performed by controller 110 of system 3200. In some embodiments, the respective steps of method 3300 may be performed in parallel, combined, in a loop, or in any order.
In step 3310, an Artificial Neural Network (ANN) computation request including an input data set and a first plurality of neural network weights is received. The input data set includes a first numeric input vector. The first digital input vector is a subset of the input data set. For example, it may be a sub-region of the image. The ANN calculation request may be generated by various entities (e.g., the computer 102 of fig. 32A). The computer may include one or more of various types of computing devices, such as personal computers, server computers, vehicle computers, and flight computers. The ANN calculation request generally refers to an electrical signal that informs or informs the ANN calculation system 100 that an ANN calculation is to be performed. In some embodiments, the ANN calculation request may be split into two or more signals. For example, a first signal may query (query) the ANN computing system 3300 to check whether the system 3300 is ready to receive the input data set and the first plurality of neural network weights. In response to an acknowledgement by system 3300, computer 102 may transmit a second signal comprising the input data set and the first plurality of neural network weights.
In step 3320, the input data set and the first plurality of neural network weights are stored. The controller 110 may store the input data set and the first plurality of neural network weights in the memory unit 120. Storing the input data set and the first plurality of neural network weights in the memory unit 120 may allow flexibility in the operation of the ANN computing system 3300, such as may improve the overall performance of the system. For example, the input data set may be divided into numeric input vectors of a set size and format by retrieving (retrieve) a desired portion of the input data set from the storage unit 120. Different portions of the input data set may be processed in various orders or shuffled (shredded) to allow various types of ANN calculations to be performed. For example, where the input and output matrix sizes are different, shuffling may allow matrix multiplication to be performed by block matrix multiplication techniques. As another example, storing the input data set and the first plurality of neural network weights in the memory unit 120 may allow for queuing of the plurality of ANN computation requests by the ANN computation system 3300, which may allow the system 3300 to maintain operation at its full speed without periods of inactivity.
In some embodiments, the input data set may be stored in a first storage subunit and the first plurality of neural network weights may be stored in a second storage subunit.
In step 3330, a first plurality of modulator control signals is generated based on the first digital input vector and a first plurality of weight control signals is generated based on the first plurality of neural network weights. The controller 110 may transmit the first DAC control signal to the DAC cell 130 to generate a first plurality of modulator control signals. The DAC cell 130 generates a first plurality of modulator control signals based on the first DAC control signal, and the modulator array 144 generates an optical input vector that represents a first digital input vector.
The first DAC control signal may comprise a plurality of digital values to be converted by the DAC unit 130 into a first plurality of modulator control signals. The plurality of digital values generally corresponds to the first digital input vector and may be associated by various mathematical relationships or look-up tables. For example, the plurality of digital values may be linearly proportional to the values of the elements of the first digital input vector. As another example, the plurality of digital values may be associated with elements of the first digital input vector through a lookup table configured to maintain a linear relationship between the digital input vector and the optical input vector produced by the modulator array 144.
The controller 110 may transmit the second DAC control signal to the DAC cell 130 to generate a first plurality of weight control signals. The DAC unit 130 generates a first plurality of weight control signals based on the second DAC control signal, and reconfigures the photo matrix multiplication unit 3220 in accordance with the first plurality of weight control signals, implementing a matrix corresponding to the first plurality of neural network weights.
The second DAC control signal may include a plurality of digital values to be converted into a first plurality of weight control signals by the DAC unit 130. The plurality of digital values generally correspond to the first plurality of neural network weights and may be associated by various mathematical relationships or look-up tables. For example, the plurality of digital values may be linearly proportional to the first plurality of neural network weights. As another example, the plurality of digital values may be calculated by performing various mathematical operations on the first plurality of neural network weights to generate weight control signals, which may configure the photoelectric matrix multiplication unit 3220 to perform matrix multiplication corresponding to the first plurality of neural network weights.
In step 3340, a first plurality of digital outputs corresponding to the electrical output vector of the photo matrix multiplication unit 3220 is obtained. The optical input vector produced by the modulator array 144 is processed by the photo matrix multiplication unit 3220 and converted to an electrical output vector. The electrical output vector is converted to a digital value by the ADC unit 160. The controller 110 may, for example, transmit a conversion request to the ADC unit 160 to start converting the voltage output by the photo matrix multiplication unit 3220 to a digital output. Once the conversion is completed, the ADC unit 160 may transmit the conversion result to the controller 110. Alternatively, the controller 110 may retrieve the conversion result from the ADC unit 160. The controller 110 may form a digital output vector from the digital output, the digital output vector corresponding to a result of a matrix multiplication of the input digital vector. For example, the digital output may be organized or concatenated to have a vector format.
In some embodiments, ADC unit 160 may be set or controlled to perform ADC conversion based on the DAC control signal being issued by controller 110 to DAC unit 130. For example, the ADC conversion may be set to start at a preset time after the DAC unit 130 generates the modulation control signal. Such control of the ADC conversion may simplify the operation of the controller 110 and reduce the number of necessary control operations.
In step 3350, a non-linear transformation is performed on the first digital output vector to produce a first transformed digital output vector. The nodes or artificial neurons of the ANN operate by first performing a weighted sum of the signals received from the nodes of the previous layer, and then performing a nonlinear transformation ("activation") of the weighted sum to produce an output. Various types of ANN may implement various types of differentiable nonlinear transformations. Examples of the nonlinear transformation function include a modified linear unit (RELU) function, an S-type function, a hyperbolic tangent function, an X2 function, and an | X | function. This non-linear transformation is performed on the first digital output by the controller 110 to produce a first transformed digital output vector. In some embodiments, the non-linear transformation may be performed by a dedicated digital integrated circuit within the controller 110. For example, controller 110 may include one or more modules or circuit blocks specifically adapted to accelerate the calculation of one or more types of non-linear transformations.
In step 3360, the first transformed digital output vector is stored. The controller 110 may store the first transformed digital output vector in the memory unit 120. In the case where the input data set is divided into a plurality of digital input vectors, the first transformed digital output vector corresponds to the result of an ANN calculation of a portion of the input data set, e.g., the first digital input vector. As such, storing the first transformed digital output vector allows the ANN computing system 3200 to perform and store additional computations on other digital input vectors of the input data set to be later aggregated into a single ANN output.
In step 3370, an artificial neural network output generated based on the first transformed digital output vector is output. The controller 110 generates an ANN output that is a result of processing the input data set through an ANN defined by the first plurality of neural network weights. Where the input data set is divided into a plurality of digital input vectors, the resultant ANN output is an aggregated output comprising the first converted digital output, but may further comprise additional converted digital outputs corresponding to other portions of the input data set. Once the ANN output is generated, the generated output is transmitted to the computer (e.g., computer 102) that initiated the ANN calculation request.
Various performance metrics may be defined for the ANN computing system 3200 implementing the method 3300. Defining a performance index may allow the performance of the ANN computing system 3200 implementing the photo-electric processor 3210 to be compared to the performance of other systems used in place of the ANN computation implementing an electronic matrix multiplication unit. In one aspect, the rate at which the ANN computation can be performed can be indicated in part by a first cycle period defined as the elapsed time between the step 3320 of storing the input data set and the first plurality of neural network weights in the memory unit and the step 3360 of storing the first transformed digital output vector in the memory unit. Thus, the first cycle period includes the time it takes to convert the electrical signal to an optical signal (e.g., step 3330), perform a matrix multiplication (e.g., step 3340) in the optical and electrical domains. Both steps 3320 and 3360 involve storing data in the memory unit 120, which is a step shared between the ANN computing system 3200 and a conventional ANN computing system without the optoelectronic processor 3210. As such, measuring the first cycle period stored to the stored transaction time (memory-to-memory transaction time) may allow for an actual or fair comparison of ANN computation throughput between the ANN computation system 3200 and an ANN computation system without the optoelectronic processor 3210 (e.g., a system implementing an electrical matrix multiplication unit).
Because of the rate at which the modulator array 144 can produce the optical input vector (e.g., at 25GHz) and the processing rate of the photo matrix multiplication unit 3220 (e.g., >25GHz), the first cycle period of the ANN computation system 3200 for performing a single ANN computation of a single digital input vector may be close to the inverse of the speed of the modulator array 144 (e.g., 40 ps). The first cycle period may be, for example, less than or equal to 100ps, less than or equal to 200ps, less than or equal to 500ps, less than or equal to 1ns, less than or equal to 2ns, less than or equal to 5ns, or less than or equal to 10ns, after taking into account the delay associated with the signal generation by the DAC unit 130 and the ADC conversion by the ADC unit 160.
In comparison, the multiplication runtime of an M1 vector and an M matrix of an electrical matrix multiplication unit is typically proportional to M ^2-1 processor clock cycles (processor clock cycles). For M-32, this multiplication will take about 1024 cycles, which results in a run time of over 300ns at 3GHz clock speed, which is orders of magnitude slower than the first cycle period of the ANN computing system 3200.
In some embodiments, method 3300 further includes the step of generating a second plurality of modulator control signals based on the first converted digital output vector. In some types of ANN calculations, a single numeric input vector may be repeatedly propagated through or processed by the same ANN. As described above, ANNs that implement multi-pass processing (multi-pass processing) may be referred to as Recurrent Neural Networks (RNNs). The RNN is a neural network in which the output of the network is recycled back to the input of the neural network during the (k) th pass through the neural network and used as input during the (k +1) th pass. The RNN may have various applications in pattern recognition tasks, such as speech or handwriting recognition. Once the second plurality of modulator control signals are generated, method 3300 may proceed from step 3340 to step 3360 to complete the first digital input vector second pass ANN. Generally speaking, recycling of the converted digital output into a digital input vector may be repeated for a predetermined number of cycles, depending on the characteristics of the RNN received in the ANN calculation request.
In some embodiments, the method 3300 further includes the step of generating a second plurality of weight control signals based on the second plurality of neural network weights. In some cases, the artificial neural network computation request further includes a second plurality of neural network weights. As noted above, generally, an ANN has one or more hidden layers in addition to the input and output layers. For an ANN having two hidden layers, the second plurality of neural network weights may correspond to connectivity between the first layer of the ANN and the second layer of the ANN. To process the first digital input vector through the two hidden layers of the ANN, the first digital input vector may be first processed according to method 3300 until step 3360, wherein the result of processing the first digital input vector through the first hidden layer of the ANN at step 3360 is stored in the storage unit 120. The controller 110 then reconfigures the photoelectric matrix multiplication unit 3220 to perform a matrix multiplication corresponding to a second plurality of neural network weights associated with a second hidden layer of the ANN. Once the photo matrix multiplication unit 3220 is reconfigured, the method 3300 may generate a plurality of modulator control signals based on the first transformed digital output vector, which generates an updated optical input vector corresponding to the output of the first hidden layer. The updated light input vector is then processed by the reconfigured photo matrix multiplication unit 3220, the photo matrix multiplication unit 3220 corresponding to the second hidden layer of the ANN. In general, the steps described may be repeated until the digital input vector has been processed through all hidden layers of the ANN.
In some embodiments of the electro-optic matrix multiplication unit 3220, the rate of reconfiguration of the electro-optic matrix multiplication unit 3220 may be significantly slower than the modulation rate of the modulator array 144. In this case, the throughput of the ANN calculation system 3200 may be adversely affected by the amount of time it takes to reconfigure the photo matrix multiplication unit 3220 during which the ANN calculation cannot be performed. To mitigate the effects of the relatively slow reconfiguration time of the electro-optic matrix multiplication unit 3220, batch processing techniques may be utilized in which two or more digital input vectors are propagated through the electro-optic matrix multiplication unit 3220 without configuration changes to spread the reconfiguration time (amortize) over a larger number of digital input vectors.
Fig. 34 shows a diagram 3290 illustrating aspects of the method 3300 of fig. 33. For an ANN with two hidden layers, instead of processing the first digital input vector by the first hidden layer, reconfiguring the photo matrix multiplication unit 3220 for the second hidden layer, processing the first digital input vector by the reconfigured photo matrix multiplication unit 3220, and repeating the same operations for the remaining digital input vectors, all digital input vectors of the input data set may be processed first by the photo matrix multiplication unit 3220 configured for the first hidden layer (configuration #1), as shown in the upper part of fig. 3290. Once all digital input vectors have been processed by the photo matrix multiplication unit 3220 with configuration # 1, the photo matrix multiplication unit 3220 is reconfigured to configuration # 2, which corresponds to the second hidden layer of the ANN. This reconfiguration may be significantly slower than the rate at which the opto-electronic matrix multiplication unit 3220 may process the input vectors. Once the photo matrix multiplication unit 3220 is reconfigured for the second hidden layer, the output vectors from the previous hidden layer may be batched by the photo matrix multiplication unit 3220. For large input data sets with tens or hundreds of thousands of digital input vectors, the impact of reconfiguration time may be reduced by approximately the same factors, which may significantly reduce the portion of time the ANN computing system 3200 spends in reconfiguration.
To implement batch processing, in some embodiments, method 3300 further includes the step of generating, by the DAC unit, a second plurality of modulator control signals based on the second digital input vector; a step of obtaining a second plurality of digital outputs corresponding to the output vectors of the photoelectric matrix multiplication unit from the ADC unit, the second plurality of digital outputs forming a second digital output vector; a step of performing a non-linear transformation on the second digital output vector to produce a second transformed digital output vector; and storing the second transformed digital output vector in a memory unit. For example, generating the second plurality of modulator control signals may be after step 3360. Furthermore, the ANN output of step 3370 in this case is now based on the first transformed digital output vector and the second transformed digital output vector. The acquiring, executing, and storing steps are similar to steps 3340 through 3360.
Batch processing techniques are one of many techniques for improving the throughput of the ANN computing system 3200. Another technique for improving the throughput of the ANN computing system 3200 is by processing multiple digital input vectors in parallel using Wavelength Division Multiplexing (WDM). As described above, WDM is a technique of simultaneously propagating a plurality of optical signals of different wavelengths through a common propagation channel (e.g., a waveguide of the optical-electrical matrix multiplication unit 3220). Unlike electrical signals, optical signals of different wavelengths can propagate through a common channel without affecting other optical signals of different wavelengths on the same channel. In addition, optical signals can be added (multiplexed) or dropped (demultiplexed) from a common propagation channel using well-known structures such as optical multiplexers and demultiplexers.
In the context of the ANN computing system 3200, multiple optical input vectors of different wavelengths may be independently generated, simultaneously propagated through the optical paths and optical processing components (e.g., optical amplitude modulators) of the optoelectronic matrix multiplication unit 3220, and independently processed by electronic processing components (e.g., detectors and/or summation modules) to enhance the throughput of the ANN computing system 3200.
Referring to fig. 35A, in some embodiments, a Wavelength Division Multiplexing (WDM) Artificial Neural Network (ANN) computing system 3500 includes an optoelectronic processor 3510, the optoelectronic processor 3510 including an optoelectronic matrix multiplication unit 3520, the optoelectronic matrix multiplication unit 3520 having a replication module, a multiplication module, and a summation module as shown in fig. 18-24D to enable processing of incoherent or low coherent optical signals when performing matrix calculations, wherein the optical signals are encoded at a plurality of wavelengths. WDM ANN computing system 3500 is similar to ANN computing system 3200 except that WDM technology is used therein, for some embodiments of ANN computing system 3500, light source 3230 is configured to generate a plurality of wavelengths, e.g., λ1、λ2And λ3Similar to the system 104 of fig. 1F.
The multiple wavelengths may preferably be separated by a wavelength spacing large enough to allow easy multiplexing and demultiplexing onto a common propagation channel. For example, wavelength intervals greater than 0.5nm, 1.0nm, 2.0nm, 3.0nm, or 5.0nm may allow for simple multiplexing and demultiplexing. On the other hand, a range between the shortest wavelength and the longest wavelength of the plurality of wavelengths ("WDM bandwidth") may preferably be small enough such that the characteristics or performance of the electro-optical matrix multiplication unit 3520 remain substantially the same over the plurality of wavelengths. Optical components are typically dispersive (meaning that their optical properties vary with wavelength). For example, the power splitting ratio of the MZI may vary with wavelength. However, by designing the electro-optical matrix multiplication unit 3520 to have a sufficiently large operating wavelength window (operating wavelength window), and by limiting the wavelengths within the operating wavelength window, the electrical output vector output by the electro-optical matrix multiplication unit 3520 for each wavelength may be a sufficiently accurate result of the matrix multiplication implemented by the electro-optical matrix multiplication unit 3520. The operating wavelength window may be, for example, 1nm, 2nm, 3nm, 4nm, 5nm, 10nm, or 20 nm.
The modulator array 144 of the WDM ANN computing system 3500 includes optical modulator groups (banks of optical modules) configured to generate a plurality of optical input vectors, each of the optical modulator groups corresponding to one of the plurality of wavelengths and generating a corresponding optical input vector having a corresponding wavelength. For example, for wavelengths having lengths of 32 and 3 (e.g., λ)1、λ2And λ3) The modulator array 144 may have 3 groups of 32 modulators each. In addition, the modulator array 144 also includes an optical multiplexer configured to combine the plurality of optical input vectors into a combined optical input vector that includes the plurality of wavelengths. For example, an optical multiplexer may combine the outputs of three modulator groups of three different wavelengths into a single propagation channel (e.g., waveguide) for each element of an optical input vector. As such, returning to the example above, the combined optical input vector will have 32 optical signals, each signal comprising 3 wavelengths.
The optoelectronic processing component of the WDM ANN computing system 3500 is further configured to demultiplex a plurality of wavelengths and generate a plurality of demultiplexed output electrical signals. Referring to fig. 35B, the optical electrical matrix multiplication unit 3520 includes an optical path 1803, the optical path 1803 configured to receive a combined optical input vector comprising a plurality of wavelengths from the modulator array 144. For example, optical path 1803_1 is received at wavelength λ 1、λ2And λ3Combined light input vector element v of1. At a wavelength λ1、λ2And λ3Light input vector element v of1Are provided to the multiplication modules 3530_11, 3530_21, … …, and 3530_ m 1. In some embodiments where the multiplication module 3530 outputs an electrical signal, the multiplication module 3530_11 output represents M11·v1Corresponding to a wavelength lambda1、λ2And λ3Input vector element v of1. Corresponding to a wavelength lambda1、λ2And λ3Input vector element v of1The output electrical signals of the multiplication module 3530_11 are shown as (λ 1), (λ 2), and (λ 3), respectively. Similar signs apply to the outputs of the other multiplication modules. The multiplication module 3530_21 outputs a representation M21·v1Respectively corresponding to the wavelength lambda1、λ2And λ3Input vector element v of1. The multiplication module 3530_ M1 outputs a representation Mm1·v1Corresponding to a wavelength lambda1、λ2And λ3Input vector element v of1。
At a wavelength λ1、λ2And λ3Light input vector element v of2Are provided to the multiplication modules 3530_12, 3530_22, … …, and 3530_ m 2. Multiplication module 3530_12 outputs a representation of M12·v2Corresponding to a wavelength lambda1、λ2And λ3Input vector element v of2. Multiplication module 3530_22 outputs a representation M22·v2Corresponding to a wavelength lambda 1、λ2And λ3Input vector element v of2. The multiplication module 3530_ M2 outputs a representation Mm2·v2Corresponding to a wavelength lambda1、λ2And λ3Input vector element v of2。
Including wavelength lambda1、λ2And λ3Light input vector element v ofnAre provided to the multiplication blocks 3530_1n, 3530_2n, … …, and 3530_ mn. The multiplication module 3530_1n outputs a representation M1n·vnCorresponding to a wavelength lambda1、λ2And λ3Input vector element v ofn. The multiplication module 3530_2n outputs a representation M2n·vnCorresponding to a wavelength lambda1、λ2And λ3Input vector element v ofn. The multiplication module 3530_ mn outputs a representation of Mmn·vnCorresponding to a wavelength lambda1、λ2And λ3Input vector element v ofnAnd so on.
For example, each multiplication module 3530 may include a demultiplexer configured to demultiplex three wavelengths contained in each of the 32 signals of the multi-wavelength light vector and route (route) 3 single-wavelength light output vectors to three sets of photodetectors (e.g., photodetectors 2012, 2016 (FIG. 20B) or 2042, 2046 (FIG. 20C)) coupled to three sets of operational or transimpedance amplifiers (e.g., operational amplifiers 2030 (FIG. 20B) or 2050 (FIG. 20C)).
Three sets of summation modules 1808 receive the outputs from the multiplication module 3530 and produce sums y of the input vectors corresponding to the various wavelengths. For example, three summing modules 1808_1 receive the outputs of the multiplication modules 3530_11, 3530_12, … …, 3530_1n and generate signals corresponding respectively to the wavelength λ1、λ2And λ3Input vector element v of1Sum of (a) y1(λ1)、y1(λ2)、y1(λ 2) where the sum y at each wavelength1Is equal to M11v1+M12v2+…+M1nvn. Three summing modules 1808_2 receive the outputs of the multiplication modules 3530_21, 3530_22, … …, 3530_2n and generate signals corresponding to the wavelengths λ respectively1、λ2And λ3Input vector element v of2Sum of (a) y2(λ1)、y2(λ2)、y2(λ 3) where the sum y at each wavelength2Is equal to M21v1+M22v2+…+M2nvn. The three summation modules 1808_ n receive the outputs of the multiplication modules 3530_ m1, 3530_ m2, … …, 3530_ mn and generate the outputs corresponding to the wavelengths λ respectively1、λ2And λ3Input vector element v ofnSum of (a) yn(λ1)、yn(λ2)、yn(λ 3) where the sum y at each wavelengthnIs equal to Mm1v1+Mm2v2+…+Mmnvn。
Referring again to fig. 35A, the ADC unit 160 of the WDM ANN computing system 3500 includes ADC groups (banks of ADCs) configured to convert a plurality of demultiplexed output voltages (demultiplexed output voltages) of the photo matrix multiplication unit 3520. Each ADC bank corresponds to one of a plurality of wavelengths and produces a corresponding digital demultiplexed output. For example, a group of ADCs 160 may be coupled to a group of summing modules 1808, for example.
In some cases, the ANN may be specially designed and the digital input vector may be specifically formed such that the multi-wavelength product of the multiplication module 3530 may be added without demultiplexing. In this case, the multiplication module 3530 may be a wavelength-insensitive (wavelegnth-insensitive) multiplication module that does not demultiplex the multiple wavelengths of the multi-wavelength product. As such, each photodetector of the multiplication module 3530 effectively adds multiple wavelengths of the optical signal to a single photocurrent, and each voltage output by the multiplication module 3530 corresponds to a sum of products of vector elements and matrix elements for the multiple wavelengths. The summation module 1808 (only one group is required) outputs an element-by-element sum (element-by-element sum) of matrix multiplication results of a plurality of digital input vectors.
Fig. 35C illustrates an example configuration of a system 3500 for an implementation of a wavelength division multiplexed optoelectronic matrix multiplication unit 3520 that performs vector matrix multiplication using a 2 x 2 matrix of elements, where the summation operation is performed in the electrical domain. In this embodiment, the input vector is
And the matrix is
In this embodiment, the input vector has a plurality of wavelengths λ1、λ2And λ3And each element of the input vector is encoded on a different optical signal. Two different replication modules 1902 perform optical replication operations to separate computations on different paths (e.g., an "up" path and a "down" path). There are four multiplication modules 1904, each multiplication module 1904 multiplying a different matrix element using light amplitude modulation. The output of each multiplication module 1904 is provided to a demultiplexer and a set of photo-detection modules 3310, which photo-detection modules 3310 convert the wavelength division multiplexed optical signal to the wavelength λ1、λ2And λ3An electrical signal in the form of an associated electrical current. Using a wavelength lambda1、λ2And λ3A related set of summation modules 3320 combine the two upper paths of different input vector elements and use the wavelength λ1、λ2And λ3A related set of summation modules 3320 combine the two lower paths of different input vector elements, where the summation modules 3320 perform the summation in the electrical domain. Thus, each element of the output vector for each wavelength is encoded on a different electrical signal. As shown in fig. 35A, as the calculation proceeds, each component of the output vector is incrementally produced to produce the following results for the upper and lower paths, respectively, for each wavelength.
M11v1+M12v2
M21v1+M22v2
The system 3500 configuration may be implemented using any of a variety of opto-electronic technologies. In some embodiments, there is a common substrate (e.g., semiconductor (e.g., silicon)) that can support the integrated optical and electronic components. The optical path may be implemented in a waveguide structure having a material with a higher optical index (pl) surrounded by a material with a lower optical index (pl), which defines a waveguide for propagating the optical wave carrying the optical signal. The electrical path may be implemented by a conductive material for propagating electrical current carrying electrical signals. (in FIG. 35C, the thickness of the lines representing the paths are used to distinguish between optical paths (represented by thicker lines) and electrical paths (represented by thinner lines or dashed lines).). Alternatively, different portions of the system may be implemented using different devices having different substrates, and those devices may communicate over a communication channel. For example, optical fibers may be used to provide a communication channel to transmit optical signals between multiple devices used to implement an overall system. Those optical signals may represent different subsets of input vectors provided when performing vector matrix multiplication and/or different subsets of intermediate results calculated when performing vector matrix multiplication, as described in more detail below.
Up to now, the non-linear transformation of the weighted sum performed as part of the ANN calculation is performed in the digital domain by the controller 110. In some cases, the non-linear transformation may be computationally intensive or power consuming, significantly increasing the complexity of the controller 110, or limiting the performance of the ANN computing system 3200 (fig. 32A) in terms of throughput or power efficiency. As such, in some embodiments of the ANN computing system, the nonlinear transformation may be performed in the analog domain by analog electronics.
Fig. 36 is a diagram illustrating an example of an ANN computing system 3600. ANN computing system 3600 is similar to ANN computing system 3200 except that an analog nonlinear unit 310 is added. The analog nonlinear unit 310 is disposed between the photoelectric matrix multiplication unit 3220 and the ADC unit 160. The analog nonlinear unit 310 is configured to receive the output voltage from the photo matrix multiplication unit 3220, apply a nonlinear transfer function, and output the converted output voltage to the ADC unit 160.
When the ADC unit 160 receives a voltage that has been nonlinearly converted by the analog nonlinear unit 310, the controller 110 may obtain a converted digital output voltage corresponding to the converted output voltage from the ADC unit 160. Since the digital output voltage obtained from the ADC unit 160 has already been non-linearly converted ("activated"), the non-linear conversion step of the controller 110 can be omitted, thereby reducing the computational burden of the controller 110. The first converted voltage obtained directly from the ADC unit 160 may then be stored as a first converted digital output vector in the memory unit 120.
The analog nonlinear unit 310 may be implemented in various ways, as discussed above with respect to the analog nonlinear unit 310 of fig. 3A. Using the analog non-linear unit 310 may improve the performance of the ANN computing system 3600, such as throughput or power efficiency, by reducing the steps performed in the digital domain. Moving the non-linear transformation step out of the digital domain may allow additional flexibility and improvement in the operation of the ANN computing system. For example, in a recurrent neural network, the output of the photo matrix multiplication unit 3220 is activated and recycled back to the input of the photo matrix multiplication unit 3220. The activation step is performed by the controller 110 in the ANN computing system 3200, which requires digitizing the output voltage of the photo matrix multiplication unit 3220 each time it passes through the photo matrix multiplication unit 3220. However, because the activation step is now performed prior to digitization of the ADC unit 160, the number of ADC conversions required in performing the recursive neural network calculations may be reduced.
In some embodiments, the analog non-linear unit 310 may be integrated into the ADC unit 160 as a non-linear ADC unit. For example, the non-linear ADC unit may be a linear ADC unit having a non-linear look-up table that maps the linear digital output of the linear ADC unit to a desired non-linear converted digital output.
Fig. 37 is a diagram illustrating an example of an ANN computing system 3700. The ANN computing system 3700 is similar to the system 3600 of fig. 36, except that it further includes an analog memory unit 320. The analog storage unit 320 is coupled to the DAC unit 130 (e.g., via the first DAC subunit 132), the modulator array 144, and the analog nonlinear unit 310. The analog storage unit 320 comprises a multiplexer having a first input coupled to the first DAC subunit 132 and a second input coupled to the analog non-linear unit 310. This allows the analog storage unit 320 to receive signals from the first DAC sub-unit 132 or the analog non-linear unit 310. The analog memory cell 320 is configured to store an analog voltage and output the stored analog voltage. The analog memory cell 320 can be implemented in various ways, as discussed above with respect to the analog memory cell 320 of FIG. 3B.
The operation of the ANN computing system 3700 will now be described. The first plurality of modulator control signals output by the DAC cell 130 (e.g., by the first DAC subunit 132) are first input to the modulator array 144 through the analog storage unit 320. In this step, the analog storage unit 320 may simply pass or buffer the first plurality of modulator control signals. The modulator array 144 generates an optical input vector based on the first plurality of modulator control signals, which propagates through the photo matrix multiplication unit 3220. The output voltage of the photoelectric matrix multiplication unit 3220 is nonlinearly converted by the analog nonlinear unit 310. At this time, instead of being digitized by the ADC unit 160, the output voltage of the analog nonlinear unit 310 is stored by the analog storage unit 320, which is then output to the modulator array 144 to be converted into the next optical input vector to be propagated through the photo matrix multiplication unit 3220. The recursive process (recurrentprocessing) may be performed for a preset amount of time or a preset number of cycles under the control of the controller 110. Once the recursive processing is completed for a given digital input vector, the converted output voltage of the analog non-linear unit 310 is converted by the ADC unit 160.
The advantages of using the analog memory cell 320 in the system 3700 are similar to the advantages of using the analog memory cell 320 in the system 302 of fig. 3B. Similarly, the performance of the recurrent neural network computations using system 3700 may be similar to system 302 of fig. 3B.
As discussed above with respect to the system 400 of fig. 4A, there are advantages to using an ANN computing system that operates internally at a lower bit resolution than the resolution of the input data set while maintaining the resolution of the ANN computing output. Referring to fig. 38, a diagram of an example of an Artificial Neural Network (ANN) computing system 3800 having a 1-bit internal resolution is shown. ANN computing system 3800 is similar to ANN computing system 3200 (fig. 32A), except that DAC unit 130 is now replaced by driver unit 430, and ADC unit 160 is now replaced by comparator unit 460.
The driver unit 430 and the comparator unit 460 in the system 3800 of fig. 38 operate in a similar manner as the driver unit 430 and the comparator unit 460 in the system 400 of fig. 4A. The mathematical representation of the operation of the ANN computing system 3800 in fig. 38 is similar to the mathematical representation of the operation of the ANN computing system 400 shown in fig. 4A.
The ANN computation system 3800 performs an ANN computation by performing a series of matrix multiplications of 1-bit vectors, followed by summing the respective matrix multiplication results. Using the example shown in fig. 4A, the decomposed input vector V may be transformed by generating a sequence of 4 1-bit modulator control signals corresponding to 4 1-bit input vectors by means of the driver unit 430 bit0To Vbit3Is multiplied by the matrix U. This in turn results in a sequence of 4 1-bit optical input vectors, which are processed by an opto-electronic matrix multiplication unit 3220 configured by the driver unit 430 to implement the matrix multiplication of the matrix U. The controller 110 may then derive a sequence of 4 digital 1-bit optical outputs from the comparator unit 460 corresponding to a sequence of 4 1-bit modulator control signals.
In the case of a 4-bit vector being decomposed into 4 1-bit vectors, each vector should be processed by the ANN computing system 3800 four times faster than other ANN computing systems, such as system 3200 (fig. 32A), can process a single 4-bit vector to maintain the same effective ANN computing throughput. This increased internal processing speed can be seen as time-division multiplexing (time-division multiplexing) of 4 1-bit vectors into a single time slot (time) for processing the 4-bit vectors. The required increase in processing speed may be achieved at least in part by the increased operating speed of the driver unit 430 and the comparator unit 460 relative to the DAC unit 130 and the ADC unit 160, since a decrease in resolution of the signal conversion process typically results in an increase in the achievable signal conversion rate.
In this example, although the signal slew rate in 1-bit operation is increased by a factor of four, the resulting power consumption can be significantly reduced relative to 4-bit operation. As noted above, the power consumption of the signal conversion process typically scales exponentially with bit resolution, while scaling linearly with the conversion rate. As such, a 16-fold reduction in power per transition may be a 4-fold reduction in bit resolution followed by a 4-fold increase in power due to an increase in slew rate. In summary, a 4-fold reduction in operating power may be achieved by the ANN computing system 3800 over, for example, the ANN computing system 3200, while maintaining the same effective ANN computing throughput.
The controller 110 may then construct a 4-bit digital output vector from the 4 digital 1-bit optical outputs by multiplying each digital 1-bit optical output by a corresponding weight 2^0 to 2^ 3. Once the 4-bit digital output vector is constructed, an ANN calculation may be performed by performing a non-linear transformation on the constructed 4-bit digital output vector to produce a converted 4-bit digital output vector; and stores the converted 4-bit digital output vector in the memory unit 120.
Alternatively (or additionally), in some embodiments, each of the 4 digital 1-bit light outputs may be non-linearly transformed. For example, a step-function nonlinear function (step-function nonlinear function) may be used for the nonlinear transformation. A converted 4-bit digital output vector can then be constructed from the non-linearly transformed digital 1-bit optical output.
Although a separate ANN computing system 3800 has been shown and described, in general, the ANN computing system 3200 of fig. 32A may be designed to implement functionality similar to the ANN computing system 3800. For example, the DAC cell 130 may include a 1-bit DAC sub-cell configured to generate a 1-bit modulator control signal, and the ADC cell 160 may be designed to have a resolution of 1 bit. Such a 1-bit ADC may be similar to or effectively identical to a comparator.
Further, while the operation of an ANN computing system having a 1-bit internal resolution has been described, in general, the internal resolution of the ANN computing system may be reduced to an intermediate level below the N-bit resolution of the input data set. For example, the internal resolution may be reduced to 2^ Y bits, where Y is an integer greater than or equal to 0.
Various alternative system configurations or signal processing techniques may be used with the various embodiments of the different systems, subsystems and modules described herein.
In some embodiments, it may be useful for some or all of the VMM subsystems to be replaced with alternative subsystems, including subsystems using different embodiments of various replication, multiplication, and/or summation modules. For example, the VMM subsystem may include an optical replication module as described herein and an electrical summation module as described herein, but the multiplication module may be replaced with a subsystem that performs multiplication operations in the electrical domain rather than the optical domain. In this example, the optical amplitude modulator array may be replaced by a detector array to convert the optical signal to an electrical signal, followed by an electronic subsystem (e.g., ASIC, processor, or SoC). Alternatively, if optical signal routing is to be used for a summing module configured to detect optical signals, the electronics subsystem may include, for example, electro-optical conversion using an array of electrically-modulated optical sources.
In some embodiments, it may be useful to be able to use a single wavelength for some or all of the optical signals for some or all of the VMM computations. Alternatively, in some embodiments, to help reduce the number of optical input ports that may be needed, the input ports may receive multiplexed optical signals having different values encoded on different optical waves of different wavelengths. Those light waves may then be separated at appropriate locations in the system, depending on whether any of the replication, multiplication, and/or summation modules are configured to operate on multiple wavelengths. However, even in a multi-wavelength embodiment, it may be useful to use the same wavelength, for example, for different subsets of optical signals used in the same VMM subsystem.
In some embodiments, accumulators may be used to implement time-domain encoding of optical and electrical signals received by the various modules, thereby alleviating the need for electronic circuitry to operate efficiently at a large number of different power levels. For example, a signal encoded using binary (on-off) amplitude modulation with a particular duty cycle over N time slots of each symbol may be converted to a signal with N amplitude levels per symbol after the signal passes through an accumulator (an analog electronic accumulator that combines the current or voltage of the electrical signal). Thus, if optical devices (e.g., phase modulators in optical amplitude modulators) are capable of operating at a symbol bandwidth (B), they may instead operate at a symbol bandwidth of B/100, where each symbol value uses N-100 time slots. A 50% integrated amplitude has a 50% duty cycle (e.g., the first 50 time slots at a non-zero "on" level followed by 50 time slots at a zero or near-zero "off" level), while a 10% integrated amplitude has a 10% duty cycle (e.g., the first 10 time slots at a non-zero "on" level followed by 90 time slots at a zero "off" level). In the examples described herein, such an accumulator may be positioned on the path of each electrical signal anywhere within the VMM subsystem, consistent for each electrical signal, e.g., before or after the summing module for all electrical signals in the VMM subsystem. The VMM subsystem may also be configured so that there is no significant relative time shift between different electrical signals that maintain the alignment of different symbols.
Referring to fig. 40, in some embodiments, homodyne detection may be used to derive the phase and amplitude of the modulated signal. The homodyne detector 4000 includes a beam splitter 4002 including a 2 × 2 multimode interference (MMI) coupler, two photodetectors 4004a and 4004b, and a subtractor 4006. Beam splitter 4002 receives input signals E1 and E2, and the output of beam splitter 402 is detected by photodetectors 4004a and 4004 b. For example, the input signal E1 may be the signal to be detected, and the input signal E2 may be generated by a local oscillator with constant laser power. The local oscillator signal E2 is mixed with the input signal E1 by the beam splitter 4002 before the signals are detected by the photodetectors 4004a and 4004 b. Subtractor 4006 outputs photodetectorDifference between outputs of 4004a and 4004 b. Output 4008 of subtractor 4006 and | E1||E2In (θ), where E1I and I E2I is the amplitude of the two input optical fields and θ is their relative phase. Since the output is related to the product of two optical fields, an extremely weak optical signal can be detected even at a single photon level.
For example, the homodyne detector 4000 may be used in the systems shown in fig. 1A, 1F, 3A to 4A, 5, 7, 9, 18 to 24E, 26 to 32B, and 35A to 38. The homodyne detector 4000 provides gain on the signal and therefore a better signal to noise ratio (signal noise ratio). For coherent systems, homodyne detector 4000 provides the additional benefit of revealing phase information of the signal by detecting the polarity of the result.
In the embodiment of FIG. 19B, the configuration of system 1920 includes a 2 x 2 matrix of elements, where two different respective wavelengths λ are used1And λ2Two input vector elements are encoded on two optical signals. A configuration may be used, for example, where two optical fibers are used to provide two optical signals to system 1920. For example, a system performing matrix processing on a 4 x 4 matrix may receive four input optical signals carried on four optical fibers. Although more optical fibers may be used to carry more input optical signals for systems that handle larger matrices, it is difficult to couple a large number of optical fibers to an optoelectronic chip because the coupling between the optical fibers and the optoelectronic chip takes up considerable space.
One way to reduce the number of optical fibers required to carry the optical signal to the optoelectronic chip is to use wavelength division multiplexing. A single optical fiber may be used to multiplex and transmit multiple optical signals having different wavelengths. For example, referring to FIG. 41, in computing system 4100, there is a wavelength λ1Is modulated by a first modulator 4104 to produce a first modulated light signal 4120 representing a first input vector element V1. Having a wavelength λ2Is modulated by a second modulator 4108 to produce a second modulated light signal 4122 representing a second input vector element V2. The first and second modulated optical signals are combined by a multiplexer 4110 To generate a wavelength division multiplexed signal that is transmitted over an optical fiber 4112 to an opto-electronic chip 4114, the opto-electronic chip 4114 comprising a plurality of matrix multiplication modules 4116a, 4116b, 4116c and 4116d (collectively 4116) and 4118a, 4118b, 4118c and 4118d (collectively 4118).
Inside the optochip 4114, the wavelength division multiplexed signal is demultiplexed by the demultiplexer 4118 to separate the optical signal 4120 and the optical signal 4122. In this example, the optical signal 4120 is replicated by the replication module 4124 to produce a replica of the optical signal that is transmitted to the matrix multiplication modules 4116a and 4118 a. The optical signal 4122 is replicated by a replication module 4126 to produce a replica of the optical signal that is transmitted to the matrix multiplication modules 4116b and 4118 b. The outputs of the matrix multiplication modules 4116a and 4116b are combined using an optical coupler 4120a and the combined signal is detected by a photodetector 4122 a.
Having a wavelength λ1Is modulated by a third modulator 4128 to produce a third modulated light signal 4132 representing a third input vector element V3. Having a wavelength λ2Is modulated by a fourth modulator 4130 to produce a fourth modulated light signal 4134 representative of a fourth input vector element V4. The third and fourth modulated optical signals are combined by the multiplexer 4136 to produce a wavelength division multiplexed signal that is transmitted through the optical fiber 4138 to the opto-electronic chip 4114.
Inside the optoelectronic chip 4114, the wavelength division multiplexed signal provided by the optical fiber 4138 is demultiplexed by the demultiplexer 4140 to separate the optical signals 4132 and 4134. In this example, the optical signal 4132 is replicated by the replication module 4142 to produce a replica of the optical signal that is transmitted to the matrix multiplication modules 4116c and 4118 c. The optical signal 4134 is replicated by the replication module 4144 to produce a replica of the optical signal that is transmitted to the matrix multiplication modules 4116d and 4118 d. The outputs of the matrix multiplying units 4116c and 4116d are combined using an optical coupler 4120b, and the combined signal is detected by a photodetector 4122 b. The outputs of the matrix multiplication units 4118a and 4118b are combined using an optical coupler, and the combined signal is detected by a photodetector. The outputs of the matrix multiplication units 4118c and 4118d are combined using an optical coupler, and the combined signal is detected by a photodetector.
In some embodiments, a multiplexer may multiplex optical signals having three or more (e.g., 10 or 100) wavelengths to produce a wavelength division multiplexed signal transmitted by a single fiber, and a demultiplexer internal to the optoelectronic chip may demultiplex the wavelength division multiplexed signal to separate signals having different wavelengths. This allows more optical signals to be transmitted in parallel over the optical fiber to the optoelectronic chip, increasing the data processing throughput of the optoelectronic chip.
In some examples, the laser unit 142 of fig. 1A includes a single laser that provides light waves that can be modulated with different optical signals. In that case, the light waves in the respective waveguides of the system have a common wavelength that is substantially the same as each other within the resolution of the linewidth of the laser light. For example, the light waves may have wavelengths within 1nm of each other. However, the laser unit 142 may also include a plurality of lasers capable of wavelength division multiplexing operation using different optical signals modulated onto different respective optical waves (e.g., each having a linewidth of 1nm or less). The different light waves may have peak wavelengths that are separated from each other by a wavelength distance greater than the line width of a single laser (e.g., greater than 1 nm). In some examples, wavelength division multiplexing systems may use optical signals modulated onto optical waves having wavelengths of a few nanometers (e.g., 3nm or greater). However, if the demultiplexer has a better resolution, the difference between different wavelengths in a WDM system can also be less than 3 nm.
The digital controllers (e.g., for controlling the components shown in fig. 24E) and functional operations described in this disclosure may be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures in this disclosure and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this disclosure can be implemented using one or more modules of computer program instructions encoded on a computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium may be an article of manufacture (e.g., a hard drive in a computer system or an optical disk sold through retail outlets) or an embedded system. The computer readable medium may be separately acquired and then encoded with one or more modules of computer program instructions, for example, over a wired or wireless network. The computer readable medium can be a machine readable storage device, a machine readable storage substrate, a memory device, or a combination of one or more of them.
A computer program (also known as a program, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and it can be deployed in any form, including as a stand alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub-programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.
The processes and logic flows described in this disclosure can be performed by one or more programmable processors (programmable processors) executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC).
While the disclosure has been described in connection with certain embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims, which scope is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures as is permitted under the law.
For example, fig. 42 shows a probability distribution function for a data set in which small coefficients occur more frequently. In another example, it is assumed that the data set has the property that the Probability Distribution Function (PDF) of the coefficients yields a higher probability (and thus more frequent instances) for large coefficients (i.e. coefficients with relatively large absolute values). For such data sets ("high coefficient weighted data sets"), reduced power consumption may be achieved by designing the modulator such that the modulator operates in a lower power state for computational calculations using larger coefficients (which occur more often in the data set) and smaller coefficients (which occur less often in the data set) in a high power state.
Some background information for the various systems described in this specification is disclosed in us provisional application 62/680 filed on 5.6.2018, 944, us provisional application 62/744, 706 filed on 12.10.2018, and us application 16/431, 167 filed on 4.6.2019. The entire disclosure of the above application is incorporated herein by reference.
For example, the optical replication distribution network may include a plurality of optical splitters, a plurality of directional couplers, or both. For example, the optical replica distribution network may comprise a cascade of directional couplers having N output ports, wherein each output port outputs 1/N of the input power to the optical replica distribution network.
While the disclosure is defined in the appended claims, it should be understood that the disclosure may also be defined in accordance with the following embodiments:
example 1: a system, comprising:
a storage unit configured to store the data set and a plurality of neural network weights;
a digital-to-analog converter (DAC) unit configured to generate a plurality of modulator control signals and to generate a plurality of weight control signals;
an optical processor, comprising:
a laser unit configured to generate a plurality of light outputs;
a plurality of optical modulators coupled to the laser unit and the DAC unit, the plurality of optical modulators configured to generate an optical input vector by modulating a plurality of optical outputs generated by the laser unit based on a plurality of modulator control signals;
a light matrix multiplication unit coupled to the plurality of light modulators and the DAC unit, the light matrix multiplication unit configured to convert a light input vector into a light output vector based on a plurality of weight control signals; and a photo detection unit coupled to the light matrix multiplication unit and configured to generate a plurality of output voltages corresponding to the light output vectors;
An analog-to-digital converter (ADC) unit coupled to the photodetection unit and configured to convert the plurality of output voltages into a plurality of digital light outputs;
a controller comprising an integrated circuit configured to perform the following operations:
receiving, from a computer, an artificial neural network computation request comprising an input data set and a first plurality of neural network weights, wherein the input data set comprises a first digital input vector;
storing the input data set and the first plurality of neural network weights in a memory unit; and
a first plurality of modulator control signals is generated based on the first digital input vector and a first plurality of weight control signals is generated based on the first plurality of neural network weights by the DAC unit.
Example 2: the system of embodiment 1, wherein the operations further comprise:
obtaining a first plurality of digital light outputs from the ADC unit corresponding to the light output vectors of the light matrix multiplication unit, the first plurality of digital light outputs forming a first digital output vector;
performing a non-linear transformation on the first digital output vector to produce a first transformed digital output vector; and
the first transformed digital output vector is stored in a memory unit.
Example 3: the system of embodiment 2, wherein the system has a first cycle period defined as the time elapsed between the step of storing the input data set and the first plurality of neural network weights in the memory unit and the step of storing the first transformed digital output vector in the memory unit, and
wherein the first cycle period is less than or equal to 1 ns.
Example 4: the system of embodiment 2, wherein the operations further comprise:
an artificial neural network output generated based on the first transformed digital output vector is output.
Example 5: the system of embodiment 2, wherein the operations further comprise:
a second plurality of modulator control signals is generated by the DAC unit based on the first converted digital output vector.
Example 6: the system of embodiment 2, wherein the artificial neural network computation request further includes a second plurality of neural network weights, and
wherein the operations further comprise:
based on the obtaining of the first plurality of digital light outputs, a second plurality of weight control signals is generated by the DAC unit based on the second plurality of neural network weights.
Example 7: the system of embodiment 6, wherein the first plurality of neural network weights and the second plurality of neural network weights correspond to different layers of the artificial neural network.
Example 8: the system of embodiment 2, wherein the input data set further comprises a second digital input vector, and
wherein the operations further comprise:
generating, by the DAC unit, a second plurality of modulator control signals based on a second digital input vector;
obtaining a second plurality of digital light outputs from the ADC unit corresponding to the light output vectors of the light matrix multiplication unit, the second plurality of digital light outputs forming a second digital output vector;
performing a non-linear transformation on the second digital output vector to produce a second transformed digital output vector;
storing the second transformed digital output vector in a storage unit; and
outputting an artificial neural network output generated based on the first transformed digital output vector and the second transformed digital output vector,
wherein the light output vector of the light matrix multiplication unit is generated by a second light input vector generated based on a second plurality of modulator control signals, the second light input vector being transformed by the light matrix multiplication unit based on the first-mentioned plurality of weight control signals.
Example 9: the system of embodiment 1, further comprising:
an analog nonlinear unit disposed between the photodetection unit and the ADC unit, the analog nonlinear unit configured to receive a plurality of output voltages from the photodetection unit, apply a nonlinear transfer function, and output a plurality of converted output voltages to the ADC unit,
Wherein the operations further comprise:
obtaining a first plurality of converted digital output voltages from the ADC unit corresponding to the plurality of converted output voltages, the first plurality of converted digital output voltages forming a first converted digital output vector; and
the first transformed digital output vector is stored in a memory unit.
Example 10: the system of embodiment 1 wherein the integrated circuit of the controller is configured to generate the first plurality of modulator control signals at a rate greater than or equal to 8 GHz.
Example 11: the system of embodiment 1, further comprising:
an analog storage unit disposed between the DAC unit and the plurality of light modulators, the analog storage unit configured to store an analog voltage and output the stored analog voltage; and
an analog nonlinear unit disposed between the photo detection unit and the ADC unit, the analog nonlinear unit configured to receive a plurality of output voltages from the photo detection unit, apply a nonlinear transfer function, and output a plurality of converted output voltages.
Example 12: the system of embodiment 11, wherein the analog memory cell comprises a plurality of capacitors.
Example 13: the system of embodiment 11, wherein the analog memory cell is configured to receive and store a plurality of converted output voltages of the analog nonlinear cell and output the stored plurality of converted output voltages to the plurality of optical modulators, an
Wherein the operations further comprise:
storing a plurality of converted output voltages of an analog non-linear unit in an analog storage unit based on generating a first plurality of modulator control signals and a first plurality of weight control signals;
outputting the stored converted output voltage through the analog memory cell;
obtaining a second plurality of converted digital output voltages from the ADC unit, the second plurality of converted digital output voltages forming a second converted digital output vector; and
the second transformed digital output vector is stored in the memory unit.
Example 14: the system of embodiment 1, wherein the input data set of the artificial neural network computation request includes a plurality of numerical input vectors,
wherein the laser unit is configured to generate a plurality of wavelengths,
wherein the plurality of light modulators includes:
a bank of optical modulators (bank) configured to generate a plurality of optical input vectors, each optical modulator bank corresponding to one of a plurality of wavelengths and generating a respective optical input vector having a respective wavelength; and
an optical multiplexer configured to combine the plurality of optical input vectors into a combined optical input vector comprising a plurality of wavelengths,
wherein the photodetecting unit is further configured to demultiplex a plurality of wavelengths and generate a plurality of demultiplexed output voltages, an
Wherein the operations include:
obtaining a plurality of digital demultiplexed optical outputs from the ADC unit, the plurality of digital demultiplexed optical outputs forming a plurality of first digital output vectors, wherein each of the plurality of first digital output vectors corresponds to one of the plurality of wavelengths;
performing a non-linear transformation on each of the plurality of first digital output vectors to produce a plurality of transformed first digital output vectors; and
storing a plurality of transformed first digital output vectors in a memory unit,
wherein each of the plurality of digital input vectors corresponds to one of the plurality of optical input vectors.
Example 15: the system of embodiment 1, wherein the artificial neural network computation request includes a plurality of numerical input vectors,
wherein the laser unit is configured to generate a plurality of wavelengths,
wherein the plurality of light modulators includes:
an optical modulator group configured to generate a plurality of optical input vectors, each optical modulator group corresponding to one of a plurality of wavelengths and generating a respective optical input vector having a respective wavelength; and
an optical multiplexer configured to combine the plurality of optical input vectors into a combined optical input vector comprising a plurality of wavelengths, an
Wherein the operations include:
obtaining a first plurality of digital light outputs from the ADC unit corresponding to a light output vector, the light output vector comprising a plurality of wavelengths, the first plurality of digital light outputs forming a first digital output vector;
Performing a non-linear transformation on the first digital output vector to produce a first transformed digital output vector; and
the first transformed digital output vector is stored in a memory unit.
Example 16: the system of embodiment 1, wherein the DAC cell comprises:
a 1-bit DAC subunit configured to generate a plurality of 1-bit modulator control signals,
where the resolution of the ADC unit is 1 bit,
wherein the resolution of the first digital input vector is N bits, an
Wherein the operations include:
decomposing the first digital input vector into N1-bit input vectors, each of the N1-bit input vectors corresponding to one of the N bits of the first digital input vector;
generating, by a 1-bit DAC subunit, a sequence of N1-bit modulator control signals corresponding to N1-bit input vectors;
obtaining from the ADC unit a sequence of N digital 1-bit optical outputs corresponding to a sequence of N1-bit modulator control signals;
constructing an N-bit digital output vector from a sequence of N digital 1-bit optical outputs;
performing a non-linear transformation on the constructed N-bit digital output vector to produce a transformed N-bit digital output vector; and
the transformed N-bit digital output vector is stored in a memory unit.
Example 17: the system of embodiment 1, wherein the storage unit comprises:
a digital input vector memory configured to store a first digital input vector and comprising at least one SRAM; and
a neural network weight memory configured to store a plurality of neural network weights and including at least one DRAM.
Example 18: the system of embodiment 1, wherein the DAC cell comprises:
a first DAC subunit configured to generate a plurality of modulator control signals; and
a second DAC subunit configured to generate a plurality of weight control signals,
wherein the first DAC sub-unit and the second DAC sub-unit are different.
Example 19: the system of embodiment 1, wherein the laser unit comprises:
a laser source configured to generate light; and
an optical power splitter configured to split light generated by the laser source into a plurality of optical outputs, wherein each of the plurality of optical outputs has substantially the same power.
Example 20: the system of embodiment 1 wherein the plurality of optical modulators comprises one of a MZI modulator, a ring resonator modulator, or an electro-absorption modulator.
Example 21: the system of embodiment 1, wherein the photodetecting unit comprises:
A plurality of photodetectors; and
a plurality of amplifiers configured to convert the photocurrent generated by the photodetector into a plurality of output voltages.
Example 22: the system of embodiment 1, wherein the integrated circuit is an application specific integrated circuit.
Example 23: the system of embodiment 1, wherein the optical matrix multiplication unit comprises:
an input waveguide array for receiving an optical input vector;
an optical interference unit in optical communication with the input waveguide array for performing a linear transformation of the optical input vector into a second optical signal array; and
an array of output waveguides in optical communication with the optical interference unit for guiding the second array of optical signals, wherein at least one input waveguide in the array of input waveguides is in optical communication with each output waveguide in the array of output waveguides through the optical interference unit.
Example 24: the system of embodiment 23, wherein the optical interference unit comprises:
a plurality of interconnected Mach-Zehnder interferometers (MZIs), each of the plurality of interconnected MZIs comprising:
a first phase shifter configured to change a splitting ratio of the MZI; and
a second phase shifter configured to shift a phase of one output of the MZI,
wherein the first phase shifter and the second phase shifter are coupled to a plurality of weight control signals.
Example 25: a system, comprising:
a storage unit configured to store the data set and a plurality of neural network weights;
a driver unit configured to generate a plurality of modulator control signals and to generate a plurality of weight control signals;
an optical processor, comprising:
a laser unit configured to generate a plurality of light outputs;
a plurality of optical modulators coupled to the laser unit and the driver unit, the plurality of optical modulators configured to generate an optical input vector by modulating a plurality of optical outputs generated by the laser unit based on a plurality of modulator control signals;
a light matrix multiplication unit coupled to the plurality of light modulators and the driver unit, the light matrix multiplication unit configured to convert a light input vector into a light output vector based on the weight control signal; and
a photo detection unit coupled to the light matrix multiplication unit and configured to generate a plurality of output voltages corresponding to the light output vectors;
a comparator unit coupled to the photo-detection unit and configured to convert the plurality of output voltages into a plurality of digital 1-bit optical outputs; and
a controller comprising an integrated circuit configured to perform the following operations:
receiving, from a computer, an artificial neural network computation request comprising an input data set and a first plurality of neural network weights, wherein the input data set comprises a first digital input vector having an N-bit resolution;
Storing the input data set and the first plurality of neural network weights in a memory unit;
decomposing the first digital input vector into N1-bit input vectors, each of the N1-bit input vectors corresponding to one of the N bits of the first digital input vector;
generating, by a driver unit, a sequence of N1-bit modulator control signals corresponding to N1-bit input vectors;
obtaining from the comparator unit a sequence of N digital 1-bit optical outputs corresponding to the sequence of N1-bit modulator control signals;
constructing an N-bit digital output vector from a sequence of N digital 1-bit optical outputs;
performing a non-linear transformation on the constructed N-bit digital output vector to produce a transformed N-bit digital output vector; and
the transformed N-bit digital output vector is stored in a memory unit.
Example 26: a method for performing artificial neural network computations in a system having an optical matrix multiplication unit configured to convert an optical input vector to an optical output vector based on a plurality of weight control signals, the method comprising:
receiving, from a computer, an artificial neural network computation request comprising an input data set and a first plurality of neural network weights, wherein the input data set comprises a first digital input vector;
Storing the input data set and the first plurality of neural network weights in a memory unit;
generating, by a digital-to-analog conversion (DAC) unit, a first plurality of modulator control signals based on a first digital input vector and a first plurality of weight control signals based on a first plurality of neural network weights;
obtaining a first plurality of digital light outputs from an analog-to-digital conversion (ADC) unit corresponding to the light output vector of the light matrix multiplication unit, the first plurality of digital light outputs forming a first digital output vector;
performing, by a controller, a non-linear transformation on a first digital output vector to produce a first transformed digital output vector;
storing the first transformed digital output vector in a memory unit; and
an artificial neural network output generated based on the first transformed digital output vector is output by the controller.
Example 27: a method, comprising:
providing input information in an electronic format;
converting at least a portion of the electronic input information into an optical input vector;
optically converting the light input vector into a light output vector based on the light matrix multiplication;
converting the light output vector into an electronic format; and
a non-linear transformation is electronically applied to the electronically converted light output vector to provide output information in an electronic format.
Example 28: the method of embodiment 27, further comprising:
electro-optical conversion (electronic-to-optical conversion), optical conversion (optical transformation), optical-to-electronic conversion (optical-to-electronic conversion), and nonlinear transformation for electrical application are repeated for new electronic input information corresponding to output information provided in an electronic format.
Example 29: the method of embodiment 28 wherein the optical matrix multiplication for the initial optical transform and the optical matrix multiplication for the repeated optical transforms are the same and correspond to the same layer of the artificial neural network.
Example 30: the method of embodiment 28 wherein the optical matrix multiplication for the initial optical transform and the optical matrix multiplication for the repeated optical transforms are different and correspond to different layers of the artificial neural network.
Example 31: the method of embodiment 27, further comprising:
repeating electro-optical conversion, electro-optical conversion, and nonlinear conversion for electrical applications for different portions of the electronic input information,
wherein the optical matrix multiplication for the initial optical transform and the optical matrix multiplication for the repeated optical transform are the same and correspond to the first layer of the artificial neural network.
Example 32: the method of embodiment 31, further comprising:
Providing intermediate information in an electronic format based on electronic output information for a plurality of portions of electronic input information generated by a first layer of an artificial neural network; and
repeating electro-optical conversion, electro-optical conversion and nonlinear conversion for electrical application for each different part of the electrical intermediate information,
wherein the optical matrix multiplication for the initial optical transformation and the optical matrix multiplication for the repeated optical transformations associated with different parts of the electronic intermediate information are identical and correspond to the second layer of the artificial neural network.
Example 33: a system, comprising:
a light processor comprising a passive diffractive optical component, wherein the passive diffractive optical component is configured to transform a light input vector or matrix into a light output vector or matrix representing the result of a matrix process applied to the light input vector or matrix and a predetermined vector defined by the arrangement of the diffractive optical component.
Example 34: the system of embodiment 33, wherein the matrix processing comprises a matrix multiplication between the light input vector or matrix and a predetermined vector defined by the arrangement of diffractive optical elements.
Example 35: the system of embodiment 33, wherein the light processor comprises a light matrix processing unit comprising:
An array of input waveguides for receiving an optical input vector,
an optical interference unit comprising a passive diffractive optical component, wherein the optical interference unit is in optical communication with the input waveguide array and is configured to perform a linear transformation of an optical input vector into a second optical signal array; and
an array of output waveguides in optical communication with the optical interference unit for guiding the second array of optical signals, wherein at least one input waveguide of the array of input waveguides is in optical communication with each output waveguide of the array of output waveguides through the optical interference unit.
Example 36: the system of embodiment 35, wherein the light interference unit comprises a substrate having at least one of a hole or a stripe, a size of the hole being in a range of 100nm to 10 μm, and a width of the stripe being in a range of 100nm to 10 μm.
Example 37: the system of embodiment 35, wherein the optical interference unit comprises a substrate having passive diffractive optical elements arranged in a two-dimensional configuration, and the substrate comprises at least one of a planar substrate or a curved substrate.
Example 38: the system of embodiment 37, wherein the substrate comprises a planar substrate parallel to a direction of light propagation from the array of input waveguides to the array of output waveguides.
Example 39: the system of embodiment 33, wherein the light processor comprises a light matrix processing unit comprising:
an input waveguide matrix for receiving the optical input matrix,
an optical interference unit comprising a passive diffractive optical component, wherein the optical interference unit is in optical communication with the input waveguide matrix and is configured to perform a linear transformation of the optical input matrix into a second matrix of optical signals; and
an output waveguide matrix in optical communication with the optical interference unit for guiding the second matrix of optical signals, wherein at least one input waveguide of the input waveguide matrix is in optical communication with each output waveguide of the output waveguide matrix through the optical interference unit.
Example 40: the system of embodiment 39, wherein the light interference unit comprises a substrate having at least one of a hole or a stripe (stripe), the hole having a size in the range of 100nm to 10 μm and the stripe having a width in the range of 100nm to 10 μm.
Example 41: the system of embodiment 39, wherein the optical interference unit comprises a substrate having passive diffractive optical elements arranged in a three-dimensional configuration.
Example 42: the system of embodiment 41, wherein the substrate has a shape of at least one of a cube, a cylinder, a prism, or an irregular volume.
Example 43: the system of embodiment 39, wherein the light processor comprises a light interference unit comprising a hologram (hologram) having passive diffractive optical elements, the light processor configured to receive the modulated light representing the light input matrix and to successively convert the light as it passes through the hologram until the light emerges from the hologram as the light output matrix.
Example 44: the system of embodiment 35 or 39, wherein the optical interference unit comprises a substrate with passive diffractive optical elements, and the substrate comprises at least one of silicon, silicon oxide, silicon nitride, quartz, lithium niobate, phase change material, or a polymer.
Example 45: the system of embodiment 35 or 39, wherein the optical interference unit comprises a substrate with passive diffractive optical elements and the substrate comprises at least one of a glass substrate or an acrylic substrate.
Example 46: the system of embodiment 33, wherein the passive diffractive optical component is partially formed from a dopant.
Example 47: the system of embodiment 33, wherein the matrix processing represents processing of input data by the neural network, the input data being represented by the light input vector.
Example 48: the system of embodiment 33, wherein the light processor comprises:
A laser unit configured to generate a plurality of light outputs;
a plurality of optical modulators coupled to the laser unit and configured to generate an optical input vector by modulating a plurality of optical outputs generated by the laser unit based on a plurality of modulator control signals;
a light matrix processing unit coupled to the plurality of light modulators, the light matrix processing unit comprising a passive diffractive optical component configured to convert a light input vector into a light output vector based on a plurality of weights defined by the passive diffractive optical component; and
a photo detection unit coupled to the light matrix processing unit and configured to generate a plurality of output electrical signals corresponding to the light output vectors.
Example 49: the system of embodiment 48, wherein the passive diffractive optical element is arranged in a three-dimensional configuration, the plurality of light modulators comprises a two-dimensional array of light modulators, and the photodetecting unit comprises a two-dimensional array of photodetectors.
Example 50: the system of embodiment 48 wherein the optical matrix processing unit comprises a housing module (housing module) to support and protect the input waveguide array, the optical interference unit, and the output waveguide array, an
The optical processor includes a receiving module configured to receive the optical matrix processing unit, the receiving module including a first interface (interface) enabling the optical matrix processing unit to receive the optical input vectors from the plurality of optical modulators, and a second interface enabling the optical matrix processing unit to transmit the optical output vectors to the photodetecting unit.
Example 51: the system of embodiment 48, wherein the output electrical signal comprises at least one of a plurality of voltage signals or a plurality of current signals.
Example 52: the system of embodiment 48, further comprising:
a storage unit;
a digital-to-analog conversion (DAC) unit configured to generate a plurality of modulator control signals;
an analog-to-digital conversion (ADC) unit coupled to the photodetection unit and configured to convert the plurality of output electrical signals into a plurality of digital outputs; and
a controller comprising an integrated circuit configured to perform the following operations:
receiving an artificial neural network computation request comprising an input data set from a computer, wherein the input data set comprises a first numeric input vector;
storing the input data set in a storage unit; and
a first plurality of modulator control signals is generated based on the first digital input vector by a DAC unit.
Example 53: a method, comprising:
3D printing an optical matrix processing unit comprising a passive diffractive optical component, wherein the passive diffractive optical component is configured to transform an optical input vector or matrix into an optical output vector or matrix representing a result of a matrix processing applied to the optical input vector or matrix and a predetermined vector defined by an arrangement of diffractive optical components.
Example 54: a method, comprising:
a hologram is generated using one or more laser beams, comprising a passive diffractive optical component, wherein the passive diffractive optical component is configured to transform a light input vector or matrix into a vector or matrix representing the result of a matrix process applied to the light input vector or matrix and a predetermined vector defined by the arrangement of the diffractive optical components.
Example 55: a system, comprising:
a light processor comprising passive diffractive optical components arranged in a one-dimensional manner, wherein the passive diffractive optical components are configured to convert a light input into a light output representing a result of a matrix process applied to the light input and a predetermined vector defined by the arrangement of the diffractive optical components.
Example 56: the system of embodiment 55, wherein the matrix processing comprises matrix multiplication between the light input and a predetermined vector defined by the arrangement of diffractive optical elements.
Example 57: the system of embodiment 55, wherein the light processor comprises a light matrix processing unit comprising:
an input waveguide for receiving an optical input,
an optical interference unit comprising a passive diffractive optical component, wherein the optical interference unit is in optical communication with the input waveguide and is configured to perform a linear transformation of the optical input; and
An output waveguide in optical communication with the optical interference unit for directing the optical output.
Example 58: the system of embodiment 57, wherein the light interference unit comprises a substrate having at least one of a hole or a grating (grating) with a dimension in a range of 100nm to 10 μm.
Example 59: a system, comprising:
a storage unit;
a digital-to-analog conversion (DAC) unit configured to generate a plurality of modulator control signals;
an optical processor, comprising:
a laser unit configured to generate a plurality of light outputs;
a plurality of optical modulators coupled to the laser unit and the DAC unit, the plurality of optical modulators configured to generate an optical input vector by modulating a plurality of optical outputs generated by the laser unit based on a plurality of modulator control signals;
a light matrix processing unit coupled to the plurality of light modulators, the light matrix processing unit comprising a passive diffractive optical component configured to convert a light input vector into a light output vector based on a plurality of weights defined by the passive diffractive optical component; and
a photo detection unit coupled to the light matrix processing unit and configured to generate a plurality of output electrical signals corresponding to the light output vectors;
An analog-to-digital conversion (ADC) unit coupled to the photodetection unit and configured to convert the output plurality of electrical signals into a plurality of digital optical outputs;
a controller comprising an integrated circuit configured to perform the following operations:
receiving an artificial neural network computation request comprising an input data set from a computer, wherein the input data set comprises a first numeric input vector;
storing the input data set in a storage unit; and
a first plurality of modulator control signals is generated based on the first digital input vector by a DAC unit.
Example 60: the system of embodiment 59, wherein the matrix processing unit comprises a passive diffractive optical component configured to convert the light input vector into a light output vector, the light output vector representing a product of a matrix multiplication between the light input vector and a predetermined vector defined by the passive diffractive optical component.
Example 61: the system of embodiment 59, wherein the operations further comprise:
obtaining a first plurality of digital light outputs from the ADC unit corresponding to the light output vector of the light matrix processing unit, the first plurality of digital light outputs forming a first digital output vector;
performing a non-linear transformation on the first digital output vector to produce a first transformed digital output vector; and
The first transformed digital output vector is stored in a memory unit.
Example 62: the system of embodiment 61, wherein the system has a first cycle period defined as the time elapsed between the step of storing the input data set in the storage unit and the step of storing the first transformed digital output vector in the storage unit, an
Wherein the first cycle period is less than or equal to 1 ns.
Example 63: the system of embodiment 61, wherein the operations further comprise:
an artificial neural network output generated based on the first transformed digital output vector is output.
Example 64: the system of embodiment 61, wherein the operations further comprise:
a second plurality of modulator control signals is generated by the DAC unit based on the first converted digital output vector.
Example 65: the system of embodiment 61, wherein the input data set further comprises a second digital input vector, an
Wherein the operations further comprise:
generating, by the DAC unit, a second plurality of modulator control signals based on a second digital input vector;
obtaining a second plurality of digital light outputs from the ADC unit corresponding to the light output vector of the light matrix processing unit, the second plurality of digital light outputs forming a second digital output vector;
Performing a non-linear transformation on the second digital output vector to produce a second transformed digital output vector;
storing the second transformed digital output vector in a storage unit; and
outputting an artificial neural network output generated based on the first transformed digital output vector and the second transformed digital output vector,
wherein the light output vector of the light matrix processing unit is generated by a second light input vector generated based on a second plurality of modulator control signals, the second light input vector being converted by the light matrix multiplication unit based on a plurality of weights defined by the passive diffractive optical component.
Example 66: the system of embodiment 59, further comprising:
an analog nonlinear unit disposed between the photodetecting unit and the ADC unit, the analog nonlinear unit configured to receive the plurality of output electrical signals from the photodetecting unit, apply a nonlinear transfer function, and output a plurality of converted output electrical signals to the ADC unit,
wherein the operations further comprise:
obtaining a first plurality of converted digital output electrical signals corresponding to the plurality of converted output electrical signals from the ADC unit, the first plurality of converted digital output electrical signals forming a first transformed digital output vector; and
The first transformed digital output vector is stored in a memory unit.
Example 67: the system of embodiment 59 wherein the integrated circuit of the controller is configured to generate the first plurality of modulator control signals at a rate greater than or equal to 8 GHz.
Example 68: the system of embodiment 59, further comprising:
an analog storage unit disposed between the DAC unit and the plurality of light modulators, the analog storage unit configured to store an analog voltage and output the stored analog voltage; and
an analog nonlinear unit disposed between the photodetection unit and the ADC unit, the analog nonlinear unit configured to receive the plurality of output electrical signals from the photodetection unit, apply a nonlinear transfer function, and output a plurality of converted output electrical signals.
Example 69: the system of embodiment 68, wherein the analog memory cell comprises a plurality of capacitors.
Example 70: the system of embodiment 68, wherein the analog memory unit is configured to receive and store the plurality of converted output electrical signals of the analog nonlinear unit and to output the stored plurality of converted output electrical signals to the plurality of optical modulators, an
Wherein the operations further comprise:
storing the plurality of converted output electrical signals of the analog non-linear unit in an analog storage unit based on generating a first plurality of modulator control signals;
Outputting the stored converted output electrical signal through the analog storage unit;
obtaining a second plurality of converted digital output electrical signals from the ADC unit, the second plurality of converted digital output electrical signals forming a second converted digital output vector; and
the second transformed digital output vector is stored in the memory unit.
Example 71: the system of embodiment 59, wherein the input dataset of the artificial neural network computation request includes a plurality of numerical input vectors,
wherein the laser unit is configured to generate a plurality of wavelengths,
wherein the plurality of light modulators includes:
an optical modulator group configured to generate a plurality of optical input vectors, each optical modulator group corresponding to one of a plurality of wavelengths and generating a respective optical input vector having a respective wavelength; and
an optical multiplexer configured to combine the plurality of optical input vectors into a combined optical input vector comprising a plurality of wavelengths,
wherein the photodetecting unit is further configured to demultiplex a plurality of wavelengths and generate a plurality of demultiplexed output electrical signals, an
Wherein the operations include:
obtaining a plurality of digital demultiplexed optical outputs from the ADC unit, the plurality of digital demultiplexed optical outputs forming a plurality of first digital output vectors, wherein each of the plurality of first digital output vectors corresponds to one of the plurality of wavelengths;
Performing a non-linear transformation on each of the plurality of first digital output vectors to produce a plurality of transformed first digital output vectors; and
storing a plurality of transformed first digital output vectors in a memory unit,
wherein each of the plurality of digital input vectors corresponds to one of the plurality of optical input vectors.
Example 72: the system of embodiment 59, wherein the artificial neural network computation request comprises a plurality of numerical input vectors,
wherein the laser unit is configured to generate a plurality of wavelengths,
wherein the plurality of light modulators includes:
a plurality of optical modulator groups configured to generate a plurality of optical input vectors, each optical modulator group corresponding to one of a plurality of wavelengths and generating a respective optical input vector having a respective wavelength; and
an optical multiplexer configured to combine the plurality of optical input vectors into a combined optical input vector comprising a plurality of wavelengths, an
Wherein the operations include:
obtaining a first plurality of digital light outputs from the ADC unit corresponding to a light output vector, the light output vector comprising a plurality of wavelengths, the first plurality of digital light outputs forming a first digital output vector;
performing a non-linear transformation on the first digital output vector to produce a first transformed digital output vector; and
The first transformed digital output vector is stored in a memory unit.
Example 73: the system of embodiment 59, wherein the DAC unit comprises:
a 1-bit DAC unit configured to generate a plurality of 1-bit modulator control signals,
where the resolution of the ADC unit is 1 bit,
wherein the resolution of the first digital input vector is N bits, an
Wherein the operations include:
decomposing the first digital input vector into N1-bit input vectors, each of the N1-bit input vectors corresponding to one of the N bits of the first digital input vector;
generating, by a 1-bit DAC unit, a sequence of N1-bit modulator control signals corresponding to N1-bit input vectors;
obtaining from the ADC unit a sequence of N digital 1-bit optical outputs corresponding to a sequence of N1-bit modulator control signals;
constructing an N-bit digital output vector from a sequence of N digital 1-bit optical outputs;
performing a non-linear transformation on the constructed N-bit digital output vector to produce a transformed N-bit digital output vector; and
the transformed N-bit digital output vector is stored in a memory unit.
Example 74: the system of embodiment 59, wherein the storage unit comprises a digital input vector memory, is configured to store a first digital input vector, and comprises at least one SRAM.
Example 75: the system of embodiment 59, wherein the laser unit comprises:
a laser source configured to generate light; and
an optical power splitter configured to split light generated by the laser source into a plurality of optical outputs, wherein each of the plurality of optical outputs has substantially the same power.
Example 76: the system of embodiment 59, wherein the plurality of optical modulators comprises one of a MZI modulator, a ring resonator modulator, or an electro-absorption modulator.
Example 77: the system of embodiment 59, wherein the photodetecting unit comprises:
a plurality of photodetectors; and
a plurality of amplifiers configured to convert the photocurrent generated by the photodetector into a plurality of output electrical signals.
Example 78: the system of embodiment 59, wherein the integrated circuit comprises an application specific integrated circuit.
Example 79: the system of embodiment 59, wherein the light matrix processing unit comprises:
an input waveguide array for receiving an optical input vector;
an optical interference unit in optical communication with the input waveguide array for performing a linear transformation of the optical input vector into a second optical signal array, wherein the optical interference unit comprises a passive diffractive optical component; and
An array of output waveguides in optical communication with the optical interference unit for guiding the second array of optical signals, wherein at least one input waveguide in the array of input waveguides is in optical communication with each output waveguide in the array of output waveguides through the optical interference unit.
Example 80: a system, comprising:
a storage unit;
a driver unit configured to generate a plurality of modulator control signals;
an optical processor, comprising:
a laser unit configured to generate a plurality of light outputs;
a plurality of optical modulators coupled to the laser unit and the driver unit, the plurality of optical modulators configured to generate an optical input vector by modulating a plurality of optical outputs generated by the laser unit based on a plurality of modulator control signals;
a light matrix processing unit coupled to the plurality of light modulators and the driver unit, the light matrix processing unit comprising a passive diffractive optical component configured to convert a light input vector into a light output vector based on a plurality of weight control signals defined by the passive diffractive optical component; and
a photo detection unit coupled to the light matrix processing unit and configured to generate a plurality of output electrical signals corresponding to the light output vectors;
A comparator unit coupled to the photo-detection unit and configured to convert the plurality of output electrical signals into a plurality of digital 1-bit optical outputs; and
a controller comprising an integrated circuit configured to perform the following operations:
receiving an artificial neural network computation request comprising an input data set from a computer, wherein the input data set comprises a first digital input vector having a resolution of N bits;
storing the input data set in a storage unit;
decomposing the first digital input vector into N1-bit input vectors, each of the N1-bit input vectors corresponding to one of the N bits of the first digital input vector;
generating, by a driver unit, a sequence of N1-bit modulator control signals corresponding to N1-bit input vectors;
obtaining from the comparator unit a sequence of N digital 1-bit optical outputs corresponding to the sequence of N1-bit modulator control signals;
constructing an N-bit digital output vector from a sequence of N digital 1-bit optical outputs;
performing a non-linear transformation on the constructed N-bit digital output vector to produce a transformed N-bit digital output vector; and
the transformed N-bit digital output vector is stored in a memory unit.
Example 81: the system of embodiment 80, wherein the light matrix processing unit comprises a light matrix multiplication unit configured to convert the light input vector into a light output vector, the light output vector representing a product of a matrix multiplication between an input vector represented by the light input vector and a predetermined vector defined by the diffractive optical element.
Example 82: a method for performing artificial neural network computations in a system having an optical matrix processing unit, the method comprising:
receiving, from a computer, an artificial neural network computation request comprising an input data set, the input data set comprising a first numeric input vector;
storing the input data set in a storage unit;
generating, by a digital-to-analog conversion (DAC) unit, a first plurality of modulator control signals based on a first digital input vector;
converting the light input vector into a light output vector by using a light matrix processing unit including an arrangement of diffractive optical elements, wherein the light output vector represents a result of matrix processing applied to the light input vector and a predetermined vector defined by the arrangement of diffractive optical elements;
obtaining a first plurality of digital light outputs from an analog-to-digital conversion (ADC) unit corresponding to the light output vector of the light matrix processing unit, the first plurality of digital light outputs forming a first digital output vector;
performing, by a controller, a non-linear transformation on a first digital output vector to produce a first transformed digital output vector;
storing the first transformed digital output vector in a memory unit; and
an artificial neural network output generated based on the first transformed digital output vector is output by the controller.
Example 83: the method of embodiment 82 wherein converting the light input vector to the light output vector comprises converting the light input vector to the light output vector representing a product of a matrix multiplication between a digital input vector and a predetermined vector defined by the arrangement of diffractive optical elements.
Example 84: a method, comprising:
providing input information in an electronic format;
converting at least a portion of the electronic input information into an optical input vector;
optically converting, by an optical processor comprising a passive diffractive optical component, an optical input vector into an optical output vector based on optical matrix processing;
converting the light output vector into an electronic format; and
a non-linear transformation is electronically applied to the electronically converted light output vector to provide output information in an electronic format.
Example 85: the method of embodiment 84 wherein optically converting the light input vector to the light output vector comprises optically converting the light input vector to the light output vector based on a light matrix multiplication between the input vector represented by the light input vector and a predetermined vector defined by the passive diffractive optical element.
Example 86: the method of embodiment 84, further comprising:
Electro-optical conversion, photoelectric conversion, and nonlinear conversion for electrical application are repeated for new electronic input information corresponding to output information provided in an electronic format.
Example 87: the method of embodiment 86 wherein the light matrix processing for the initial light transform and the light matrix processing for the repeated light transforms are the same and correspond to the same layer of the artificial neural network.
Example 88: the method of embodiment 84, further comprising:
repeating electro-optical conversion, electro-optical conversion, and nonlinear conversion for electrical applications for different portions of the electronic input information,
wherein the optical matrix processing for the initial optical transform and the optical matrix processing for the repeated optical transform are the same and correspond to one layer of the artificial neural network.
Example 89: a system, comprising:
an optical matrix processing unit configured to process an input vector of length N, wherein the optical matrix processing unit includes a directional coupler (directional coupler) of layers N +2 and phase shifters of layers N, and N is a positive integer.
Example 90: the system of embodiment 89 wherein the optical matrix processing unit comprises no more than N +2 layers of directional couplers.
Example 91: the system of embodiment 89 wherein the optical matrix processing unit comprises an optical matrix unit.
Example 92: the system of embodiment 89, wherein the light matrix processing unit comprises:
a substrate, and
interconnection interferometers arranged on the substrate, wherein each interferometer comprises an optical waveguide arranged on the substrate, and the directional couplers and the phase shifters are part of the interconnection interferometers.
Example 93: the system of embodiment 89, wherein the optical matrix processing unit comprises a layer of attenuators (attenuators) after the last layer of directional couplers.
Example 94: the system of embodiment 93 wherein the one-layer attenuator comprises N attenuators.
Example 95: the system of embodiment 93, comprising one or more homodyne detectors (homodyne detectors) for detecting an output from the attenuator.
Example 96: the system of embodiment 89, wherein N-3 and the optical matrix processing unit comprises:
an input (terminal) configured to receive an input vector;
a first layer of directional couplers coupled to the input;
a first layer phase shifter coupled to the first layer directional coupler;
a second layer directional coupler coupled to the first layer phase shifter;
a second layer phase shifter coupled to the second layer directional coupler;
a third layer directional coupler coupled to the second layer phase shifter;
A third tier phase shifter coupled to the third tier directional coupler;
a fourth layer directional coupler coupled to the third layer phase shifter; and
and a fifth layer directional coupler coupled to the fourth layer directional coupler.
Example 97: the system of embodiment 89, wherein N-4 and the optical matrix processing unit comprises:
an input configured to receive an input vector;
a first, second, third and fourth tier of directional couplers, each tier of directional couplers followed by a tier of phase shifters, wherein the first tier of directional couplers is coupled to the input;
a second to last layer (second-to-last layer) directional coupler coupled to the fourth layer phase shifter; and
a final layer directional coupler coupled to the next to last layer directional coupler.
Example 98: the system of embodiment 89, wherein N-8 and the optical matrix processing unit comprises:
an input configured to receive an input vector;
eight layers of directional couplers, each layer of directional couplers followed by a layer of phase shifters, wherein a first layer of directional couplers is coupled to the input;
a second to last layer directional coupler coupled to the eighth layer phase shifter; and
a final layer directional coupler coupled to the next to last layer directional coupler.
Example 99: the system of embodiment 89, wherein the light matrix processing unit comprises:
an input configured to receive an input vector;
n layers of directional couplers, each layer of directional couplers followed by a layer of phase shifters, wherein a first layer of directional couplers is coupled to the input;
a second-to-last layer directional coupler coupled to the nth layer phase shifter; and
a final layer directional coupler coupled to the next to last layer directional coupler.
Example 100: the system of embodiment 99, wherein N is an even number.
Example 101: the system of embodiment 100 wherein each ith layer directional coupler comprises N/2 directional couplers, where i is an odd number, an
Each j-th layer directional coupler includes N/2-1 directional couplers, where j is an even number.
Example 102: the system of embodiment 100 wherein for each ith layer directional coupler for which i is an odd number, the kth directional coupler is coupled to the (2k-1) th and 2 kth outputs of the previous layer, k being an integer from 1 to N/2.
Example 103: the system of embodiment 100 wherein for each jth tier directional coupler where j is an even number, the mth directional coupler is coupled to the (2m) th and (2m +1) th outputs of the previous tier, m being an integer from 1 to N/2-1.
Example 104: the system of embodiment 100 wherein each ith layer shifter comprises N shifters, wherein i is an odd number, and
each jth layer shifter includes N-2 shifters, where j is an even number.
Example 105: the system of embodiment 99, wherein N is an odd number.
Example 106: the system of embodiment 105 wherein each layer of directional couplers comprises (N-1)/2 directional couplers.
Example 107: the system of embodiment 105, wherein each layer of phase shifters comprises N-1 phase shifters.
Example 108: a system, comprising:
a generator (generator) configured to generate a first data set, wherein the generator comprises an optical matrix processing unit; and
a discriminator (discriminator) configured to receive a second data set comprising data from the first data set and data from the third data set, the data in the first data set having similar characteristics (characteristics) as the data in the third data set, and to classify the data in the second data set as either data from the first data set or data from the third data set.
Example 109: the system of embodiment 108, wherein the light matrix processing unit comprises at least one of: (i) the optical matrix multiplication unit of any one of embodiments 1 to 25, (ii) the passive diffractive optical component of any one of embodiments 32 to 52, 55 to 81, or (iii) the optical matrix processing unit of any one of embodiments 89 to 107.
Example 110: the system of embodiment 108, wherein the third data set includes real data, the generator is configured to generate synthesized data similar to the real data, and the discriminator is configured to classify the data as either the real data or the synthesized data.
Example 111: the system of embodiment 108, wherein the generator is configured to generate the dataset for training at least one of an automated driving vehicle (vehicle), a medical diagnostic system, a fraud detection system, a weather forecast system, a financial forecasting system, a face recognition system, a voice recognition system, or a product defect detection system.
Example 112: the system of embodiment 108, wherein the generator is configured to generate an image that is similar to an image of at least one of a real object or a real scene, and the discriminator is configured to classify the received image as (i) an image of the real object or the real scene, or (ii) a composite image generated by the generator.
Example 113: the system of embodiment 112, wherein the real object comprises at least one of a person, an animal, a cell, a tissue, or a product, and the real scene comprises a scene encountered by the vehicle.
Example 114: the system of embodiment 113, wherein the discriminator is configured to classify the received image as being (i) an image of an actual person, an actual animal, an actual cell, an actual tissue, an actual product, or an actual scene encountered by the vehicle, or (ii) a composite image produced by the generator.
Example 115: the system of embodiment 113, wherein the vehicle comprises at least one of a motorcycle, an automobile, a truck, a train, a helicopter, an airplane, a submarine, a ship, or a drone.
Example 116: the system of embodiment 113, wherein the generator is configured to generate an image of a tissue or cell associated with at least one of a human disease, an animal disease, or a plant disease.
Example 117: the system of embodiment 116, wherein the generator is configured to generate an image of tissue or cells associated with a human disease, and the disease comprises at least one of cancer, parkinson's disease, sickle cell anemia, heart disease, cardiovascular disease, diabetes, chest disease, or skin disease.
Example 118: the system of embodiment 116, wherein the generator is configured to generate an image of a tissue or cell associated with the cancer, and the cancer comprises at least one of skin cancer, breast cancer, lung cancer, liver cancer, prostate cancer, or brain cancer.
Example 119: the system of embodiment 108, further comprising a random noise generator configured to generate random noise input to the generator, and the generator is configured to generate the first data set based on the random noise.
Example 120: a system, comprising:
a random noise generator configured to generate random noise; and
a generator configured to generate data based on random noise, wherein the generator includes an optical matrix processing unit.
Example 121: the system of embodiment 120, wherein the light matrix processing unit comprises at least one of: (i) the optical matrix multiplication unit of any one of embodiments 1 to 25, (ii) the passive diffractive optical component of any one of embodiments 33 to 52, 55 to 81, or (iii) the optical matrix processing unit of any one of embodiments 89 to 107.
Example 122: a system, comprising:
an optical circuit configured to perform a logic function (logic function) on two input signals, the optical circuit comprising:
a first directional coupler having two inputs configured to receive two input signals and two outputs;
a first pair (pair) of phase shifters configured to modify the phase of the signal at the two outputs of the first directional coupler;
A second directional coupler having two inputs configured to receive signals from the first pair of phase shifters and two outputs; and
a second pair of phase shifters configured to modify the phase of the signals at the two outputs of the second directional coupler.
Example 123: the system of embodiment 122, wherein the phase shifter is configured to cause the optical circuit to perform a rotation (rotation):
example 124: the system of embodiment 122 wherein when the input signals x1 and x2 are provided to both inputs of the first directional coupler, the phase shifter is configured to cause the optical circuit to perform the operations of:
example 125: the system of embodiment 124, wherein the optical circuit comprises a first photodetector configured to generate absolute values of signals from the second pair of phase shifters to cause the optical circuit to perform operations of:
example 126: the system of embodiment 125, wherein the optical circuit comprises a comparator configured to compare the output signal of the first photodetector to a threshold to generate a binary value to cause the optical circuit to generate the output:
example 127: the system of embodiment 125, wherein the optical circuit comprises a feedback mechanism (feedback mechanism) configured to cause an output signal of the photodetector to be fed back to an input of the first directional coupler and through the first directional coupler, the first pair of phase shifters, the second directional coupler, and the second pair of phase shifters and detected by the photodetector to cause the optical circuit to perform operations of:
It produces the outputs AND (x1, x2) AND OR (x1, x 2).
Example 128: the system of embodiment 125 wherein the optical circuit comprises:
a third directional coupler having two inputs configured to receive signals from the second pair of phase shifters and two outputs;
a third pair of phase shifters configured to modify the phase of the signal at the two outputs of the third directional coupler;
a fourth directional coupler having two inputs configured to receive signals from the third pair of phase shifters and two outputs;
a fourth pair of phase shifters configured to modify the phase of the signal at the two outputs of the fourth directional coupler; and
a second photodetector configured to generate an absolute value of the signal from the fourth pair of phase shifters to cause the optical circuit to perform the operations of:
it produces the outputs AND (x1, x2) AND OR (x1, x 2).
Example 129: the system of embodiment 122, comprising a Bitonic sorter (sorting function) configured to perform a sorting function of the Bitonic sorter using optical circuitry.
Example 130: the system of embodiment 122, comprising means configured to perform a hashing function using optical circuitry.
Example 131: the system of embodiment 130 wherein the hash function comprises a secure hash algorithm (SHA-2) 2.
Example 132: an apparatus, comprising:
a plurality of optical waveguides, wherein a set of a plurality of input values are encoded on respective optical signals carried by the optical waveguides;
a plurality of replica modules, and for each of at least two subsets of the one or more optical signals, a respective set of the one or more replica modules is configured to split the subset of the one or more optical signals into two or more replicas (copies) of the optical signals;
a plurality of multiplication modules, and for each of at least two copies of a first subset of the one or more optical signals, a respective multiplication module is configured to multiply the one or more optical signals of the first subset by one or more matrix element values using optical amplitude modulation, wherein at least one of the multiplication modules comprises an optical amplitude modulator comprising one input port and two output ports, and a pair of correlated optical signals is provided from the two output ports such that a difference between amplitudes of the correlated optical signals corresponds to a result of multiplying the input value by the signed matrix element value; and
One or more summation modules, and for the results of two or more multiplication modules, a respective one of the summation modules is configured to produce an electrical signal representing the sum of the results of the two or more multiplication modules.
Example 133: the apparatus of embodiment 132 wherein an input value in a set of multiple input values encoded on a corresponding optical signal represents an element of an input vector multiplied by a matrix comprising one or more matrix element values.
Example 134: the apparatus of embodiment 132 or 133 wherein a set of the plurality of output values is encoded on the corresponding electrical signal produced by the one or more summation modules, and wherein the output values in the set of the plurality of output values represent elements of an output vector produced by multiplying the input vector by the matrix.
Example 135: the apparatus of any of embodiments 132-134, wherein each optical signal carried by the optical waveguide comprises an optical wave having a common wavelength, the common wavelength being substantially the same for all optical signals.
Example 136: the apparatus of any one of embodiments 132 through 135, wherein the replica module comprises at least one replica module having an optical splitter that transmits a predetermined proportion of the power of the optical waves at an input port to a first output port and transmits the remaining proportion of the power of the optical waves at the input port to a second output port.
Example 137: the apparatus of embodiment 136 wherein the optical splitter comprises a waveguide optical splitter that transmits a predetermined proportion of the power of the optical wave guided by the input optical waveguide to the first output optical waveguide and transmits the remaining proportion of the power of the optical wave guided by the input optical waveguide to the second output optical waveguide.
Example 138: the apparatus of embodiment 137 wherein the guided mode of the input optical waveguide is adiabatically coupled to the guided mode of each of the first output optical waveguide and the second output optical waveguide.
Example 139: the apparatus of any of embodiments 136 to 138, wherein the optical splitter comprises a beam splitter comprising at least one surface that transmits a predetermined proportion of the power of the optical wave at the input port and reflects a remaining proportion of the power of the optical wave at the input port.
Example 140: the apparatus of embodiment 139 wherein at least one of the plurality of optical waveguides comprises an optical fiber coupled to an optical coupler, the optical coupler coupling a guided mode of the optical fiber to a free-space propagation mode.
Example 141: the apparatus of any one of embodiments 132-140, wherein the multiplication module comprises at least one coherence-sensitive multiplication module (coherent-sensitive multiplication module) configured to multiply the first subset of one or more optical signals by one or more matrix element values using optical amplitude modulation based on interference between optical waves, the optical waves having a coherence length that is at least as long as a propagation distance through the coherence-sensitive multiplication module.
Example 142: the apparatus of embodiment 141, wherein the coherence sensitive multiplication module comprises a mach-zehnder interferometer (MZI) that splits the optical waves guided by the input optical waveguide into a first optical waveguide arm (optical waveguide arm) of the MZI and a second optical waveguide arm of the MZI, the first optical waveguide arm comprising a phase shifter that produces a relative phase shift with respect to a phase delay of the second optical waveguide arm, and the MZI combines the optical waves from the first optical waveguide arm and the second optical waveguide arm into the at least one output optical waveguide.
Example 143: the apparatus of embodiment 142 wherein the MZI combines the optical waves from the first and second optical waveguide arms into each of the first and second output optical waveguides, the first photodetector receives the optical wave from the first output optical waveguide to produce a first photocurrent, the second photodetector receives the optical wave from the second output optical waveguide to produce a second photocurrent, and the result of the coherence-sensitive multiplication module includes a difference between the first photocurrent and the second photocurrent.
Example 144: the apparatus of any of embodiments 141 through 143, wherein the coherence sensitive multiplying module comprises one or more ring resonators (ring resonators) comprising at least one ring resonator coupled to the first optical waveguide and at least one ring resonator coupled to the second optical waveguide.
Example 145: the apparatus of embodiment 144 wherein the first photodetector receives the light wave from the first optical waveguide to produce a first photocurrent, the second photodetector receives the light wave from the second optical waveguide to produce a second photocurrent, and the result of the coherence sensitive multiplication module comprises a difference between the first photocurrent and the second photocurrent.
Example 146: the apparatus of any one of embodiments 132-145, wherein the multiplication module comprises at least one coherent-insensitive multiplication module configured to multiply the first subset of the one or more optical signals by the one or more matrix element values using optical amplitude modulation based on energy absorption within the optical waves.
Example 147: the apparatus of embodiment 146, wherein the coherent non-sensitive multiplication module comprises an electro-absorption modulator.
Example 148: the apparatus of any of embodiments 132-147, wherein the one or more summing modules comprises at least one summing module comprising: (1) two or more input conductors, each input conductor carrying an electrical signal in the form of an input current, the magnitude of the input current being representative of a respective result of a respective one of the multiplication modules, and (2) at least one output conductor carrying an electrical signal representative of a sum of the respective results in the form of an output current, the output current being proportional to the sum of the input currents.
Example 149: the apparatus of embodiment 148 wherein the two or more input conductors and the output conductor comprise wires that contact at one or more junctions between the wires and the output current is substantially equal to the sum of the input currents.
Example 150: the apparatus of embodiment 148 or 149 wherein the at least one first one of the input currents is provided in the form of at least one photocurrent generated by at least one photodetector receiving an optical signal generated by a first one of the multiplication modules.
Example 151: the apparatus of embodiment 150, wherein the first input current is provided as a difference between two photocurrents generated by different respective photodetectors that receive different respective optical signals generated by the first multiplication module.
Example 152: the apparatus of any of embodiments 132-151, wherein one of the copies of the first subset of one or more optical signals consists of a single optical signal, wherein one of the input values is encoded on the single optical signal.
Example 153: the apparatus of embodiment 152 wherein the multiplication module corresponding to the replica of the first subset multiplies the encoded input value by a single matrix element value.
Example 154: the apparatus of any of embodiments 132-153, wherein one of the copies of the first subset of one or more optical signals comprises more than one, and less than all, of the optical signals on which the plurality of input values are encoded.
Example 155: the apparatus of embodiment 154 wherein a multiplication module corresponding to a copy of the first subset multiplies the encoded input values by different respective matrix element values.
Example 156: the apparatus of embodiment 155 wherein different multiplication modules corresponding to different respective copies of the first subset of the one or more optical signals are included in different apparatuses, the different apparatuses in optical communication to transmit one of the copies of the first subset of the one or more optical signals between the different apparatuses.
Example 157: the apparatus of any one of embodiments 132-156, wherein at least one of two or more of the plurality of optical waveguides, two or more of the plurality of replica modules, two or more of the plurality of multiplication modules, and one or more summation modules is disposed on a substrate of a common apparatus.
Example 158: the apparatus of embodiment 157, wherein the apparatus performs a vector matrix multiplication, wherein the input vectors are provided as a set of optical signals and the output vectors are provided as a set of electrical signals.
Example 159: the apparatus of any one of embodiments 132 through 158, further comprising an accumulator that combines the input electrical signal corresponding to the output of the multiplication module or the summation module, wherein the input electrical signal is encoded using time domain encoding using on-off amplitude modulation within each of a plurality of time slots, and the accumulator produces the output electrical signal, the output electrical signal being encoded at more than two amplitude levels, the amplitude levels corresponding to different duty cycles of the time domain encoding over the plurality of time slots.
Example 160: the apparatus of any of embodiments 132-159, wherein each of two or more of the multiplication modules corresponds to a different subset of the one or more optical signals.
Example 161: the apparatus of any of embodiments 132-160, wherein for each copy of the second subset of one or more optical signals, different from the optical signals in the first subset of one or more optical signals, the apparatus further comprises a multiplication module configured to multiply the one or more optical signals of the second subset by one or more matrix element values using optical amplitude modulation.
Example 162: a method, comprising:
Encoding a set of multiple input values on respective optical signals;
for each of at least two subsets of one or more optical signals, using a respective set of one or more replica modules to divide the subset of one or more optical signals into two or more replicas of the optical signal;
for each of at least two copies of a first subset of the one or more optical signals, using a respective multiplication module to multiply the one or more optical signals of the first subset by one or more matrix element values using optical amplitude modulation, wherein at least one multiplication module comprises an optical amplitude modulator comprising one input port and two output ports, and a pair of correlated optical signals is provided from the two output ports such that a difference between the amplitudes of the correlated optical signals corresponds to a result of multiplying the input value by the signed matrix element value; and
for the results of the two or more multiplication modules, a summation module configured to generate an electrical signal is used, the electrical signal representing the sum of the results of the two or more multiplication modules.
Example 163: a method, comprising:
encoding a set of input values representing elements of an input vector on a respective optical signal;
Encoding a set of coefficients representing matrix elements as amplitude modulation levels of a set of optical amplitude modulators coupled to the optical signals, wherein at least one optical amplitude modulator comprising one input port and two output ports provides a pair of correlated optical signals from the two output ports such that a difference between amplitudes of the correlated optical signals corresponds to a result of multiplying an input value by a signed matrix element value; and
a set of output values representing elements of an output vector on respective electrical signals is encoded, wherein at least one of the electrical signals is in the form of a current whose magnitude corresponds to the sum of the respective elements of the input vector multiplied by the respective elements of a row (row) of the matrix.
Example 164: the method of embodiment 163 wherein the at least one optical signal is provided by a first optical waveguide and the first optical waveguide is coupled to an optical splitter that transmits a predetermined proportion of the power of the optical wave guided by the first optical waveguide to a second output optical waveguide and transmits the remaining proportion of the power of the optical wave guided by the first optical waveguide to a third optical waveguide.
Example 165: an apparatus, comprising:
a plurality of optical waveguides encoding a set of input values representing elements of an input vector on respective optical signals carried by the optical waveguides;
A set of optical amplitude modulators coupled to the optical signals, encoding a set of coefficients representing matrix elements as amplitude modulation levels, wherein at least one optical amplitude modulator comprising one input port and two output ports provides a pair of correlated optical signals from the two output ports such that a difference between amplitudes of the correlated optical signals corresponds to a result of multiplying an input value by a value of a signed matrix element; and
a plurality of summation modules encoding a set of output values representing elements of an output vector on respective electrical signals, wherein at least one of the electrical signals is in the form of a current whose magnitude corresponds to the sum of a respective element of an input vector multiplied by a respective element of a row (row) of the matrix.
Example 166: a method for multiplying an input vector by a given matrix includes:
encoding a set of input values representing elements of an input vector on respective ones of a set of optical signals;
coupling a first set of one or more devices to a first set of one or more waveguides that provide a first subset of the set of optical signals and producing a result of multiplying a first sub-matrix of a given matrix by a value encoded on the first subset of the set of optical signals;
coupling a second set of one or more devices to a second set of one or more waveguides that provide a second subset of the set of optical signals and producing a result of multiplying a second sub-matrix of the given matrix by values encoded on the second subset of the set of optical signals;
Coupling a third set of one or more devices to a third set of one or more waveguides that provide a copy of the first subset of the set of optical signals produced by the first optical splitter and produce a result of multiplying a third sub-matrix of the given matrix by values encoded on the first subset of the set of optical signals;
coupling a fourth set of one or more devices to a fourth set of one or more waveguides that provide copies of a second subset of the set of optical signals produced by the second optical splitter and produce a result of a fourth sub-matrix of the given matrix multiplied by values encoded on the second subset of the set of optical signals;
wherein the first, second, third and fourth sub-matrices connected together form a given matrix; and
wherein at least one output value representing an element of an output vector is encoded on an electrical signal, the output vector corresponding to the input vector multiplied by a given matrix, the electrical signal generated by a device in communication with the first set of one or more devices and the second set of one or more devices.
Example 167: the method of embodiment 166 wherein each pair of the first set of one or more devices, the second set of one or more devices, the third set of one or more devices, and the fourth set of one or more devices is mutually exclusive (mutuallyexclusive).
Example 168: an apparatus, comprising:
a first set of one or more devices configured to receive the first set of optical signals and produce a result of multiplying the first matrix by values encoded on the first set of optical signals;
a second set of one or more devices configured to receive the second set of optical signals and produce a result of the second matrix multiplied by values encoded on the second set of optical signals;
a third set of one or more devices configured to receive the third set of optical signals and produce a result of multiplying the third matrix by values encoded on the third set of optical signals;
a fourth set of one or more devices configured to receive the fourth set of optical signals and to generate a result of the fourth matrix multiplied by the values encoded on the fourth set of optical signals; and
configurable connection paths between two or more of the first set of one or more devices, the second set of one or more devices, the third set of one or more devices, or the fourth set of one or more devices,
wherein the first configuration of the configurable connection path is configured to (1) provide a copy of the first set of optical signals as at least one of the second set of optical signals, the third set of optical signals, or the fourth set of optical signals, and (2) provide one or more signals from the first set of one or more devices and one or more signals from the second set of one or more devices to a summing module, the summing module configured to produce an electrical signal representing a sum of values encoded on the signal received by the summing module.
Example 169: an apparatus, comprising:
a first set of one or more devices configured to receive the first set of optical signals and produce a result based on optical amplitude modulation of one or more optical signals of the first set of optical signals;
a second set of one or more devices configured to receive the second set of optical signals and produce a result based on optical amplitude modulation of one or more optical signals of the second set of optical signals;
a third set of one or more devices configured to receive the third set of optical signals and produce a result based on optical amplitude modulation of one or more optical signals of the third set of optical signals;
a fourth set of one or more devices configured to receive the fourth set of optical signals and produce a result based on optical amplitude modulation of one or more of the fourth set of optical signals; and
configurable connection paths between two or more of the first set of one or more devices, the second set of one or more devices, the third set of one or more devices, or the fourth set of one or more devices,
wherein the first configuration of the configurable connection path is configured to (1) provide a copy of the first set of optical signals as a third set of optical signals, or (2) provide one or more signals from the first set of one or more devices and one or more signals from the second set of one or more devices to a summing module, the summing module configured to produce an electrical signal representing a sum of values encoded on the signals received by the summing module.
Example 170: the apparatus of embodiment 169, wherein each pair of the first set of one or more apparatuses, the second set of one or more apparatuses, the third set of one or more apparatuses, and the fourth set of one or more apparatuses is mutually exclusive.
Example 171: the apparatus of embodiment 169 or 170, wherein the first configuration of the configurable connection path is configured to (1) provide a copy of the first set of optical signals as a third set of optical signals, and (2) provide one or more signals from the first set of one or more apparatuses and one or more signals from the second set of one or more apparatuses to a summing module, the summing module configured to produce an electrical signal representing a sum of values encoded on at least two different signals received by the summing module.
Example 172: the apparatus of any of embodiments 169-171, wherein a first configuration of the configurable connection paths is configured to provide a copy of the first set of optical signals as a third set of optical signals, and a second configuration of the configurable connection paths is configured to provide one or more signals from the first set of one or more devices and one or more signals from the second set of one or more devices to a summing module, the summing module configured to produce an electrical signal representing a sum of values encoded on signals received by the summing module.
Example 173: an apparatus, comprising:
a plurality of optical waveguides, wherein a set of a plurality of input values are encoded on respective optical signals carried by the optical waveguides;
a plurality of replica modules, for each of at least two subsets of the one or more optical signals, the plurality of replica modules comprising a respective set of one or more replica modules configured to divide the subset of the one or more optical signals into two or more replicas of the optical signal;
a plurality of multiplication modules, for each of the at least two copies of the first subset of one or more optical signals, the plurality of multiplication modules including a respective multiplication module configured to multiply the one or more optical signals of the first subset by one or more values using optical amplitude modulation; and
one or more summation modules, for the results of the two or more multiplication modules, the one or more summation modules comprising a summation module configured to produce an electrical signal representing a sum of the results of the two or more multiplication modules, wherein the result comprises at least one result encoded on the electrical signal, and the result is derived from a copy of the optical signal that propagates through no more than a single optical amplitude modulator before being converted into the electrical signal.
Example 174: a system, comprising:
a first unit configured to generate a plurality of modulator control signals;
a processor, comprising:
a light source configured to provide a plurality of light outputs;
a plurality of optical modulators coupled to the light source and the first unit, the plurality of optical modulators configured to generate an optical input vector by modulating a plurality of optical outputs provided by the light source based on a plurality of modulator control signals, the optical input vector comprising a plurality of optical signals; and
a matrix multiplication unit coupled to the plurality of optical modulators and the first unit, the matrix multiplication unit configured to convert an optical input vector into an analog output vector based on a plurality of weight control signals;
a second unit coupled to the matrix multiplication unit and configured to convert the analog output vector to a digital output vector; and
a controller comprising an integrated circuit configured to perform the following operations:
receiving an artificial neural network computation request, the artificial neural network computation request comprising an input data set, the input data set comprising a first numeric input vector;
receiving a first plurality of neural network weights; and
by a first unit, a first plurality of modulator control signals is generated based on a first digital input vector, and a first plurality of weight control signals is generated based on a first plurality of neural network weights.
Example 175: the system of embodiment 174, wherein the first unit comprises a digital-to-analog converter (DAC).
Example 176: the system of embodiment 174 or 175, wherein the second unit comprises an analog-to-digital converter (ADC).
Example 177: the system of any of embodiments 174-176, comprising a storage unit configured to store the data set and the plurality of neural network weights.
Example 178: the system of embodiment 177, wherein the integrated circuit of the controller is further configured to perform operations comprising storing the input data set and the first plurality of neural network weights in the memory unit.
Example 179: the system of any of embodiments 174-178, wherein the first unit is configured to generate a plurality of weight control signals.
Example 180: the system of any of embodiments 174-178, wherein the controller comprises an Application Specific Integrated Circuit (ASIC), an
Receiving the artificial neural network computation request includes receiving the artificial neural network computation request from a general purpose data processor.
Example 181: the system of any of embodiments 174 to 178, wherein the first unit, the processing unit, the second unit, and the controller are disposed on at least one of a multi-chip module or an integrated circuit, an
Receiving the artificial neural network computation request includes receiving the artificial neural network computation request from a second data processor, wherein the second data processor is external to the multi-chip module or integrated circuit, the second data processor is coupled to the multi-chip module or integrated circuit through a communication channel, and the processing unit is capable of processing data at a data rate that is at least an order of magnitude greater than a data rate of the communication channel.
Example 182: the system of embodiment 174, wherein the first unit, the processing unit, the second unit, and the controller are used in a photo-electric processing loop that repeats in a plurality of iterations, and the photo-electric processing loop comprises:
(1) at least a first light modulation operation based on at least one of the plurality of modulator control signals, and at least a second light modulation operation based on at least one of the weight control signals, and
(2) at least one of (a) an electrical summing operation or (b) an electrical storage operation.
Example 183: the system of embodiment 182, wherein the photo-electric processing cycle comprises an electrical storage operation, and the electrical storage operation is performed using a memory unit coupled to the controller,
wherein the operations performed by the controller further comprise storing the input data set and the first plurality of neural network weights in a memory unit.
Example 184: the system of embodiment 182, wherein the photo-processing cycle comprises an electrical summing operation, and the electrical summing operation is performed using an electrical summing module within the matrix multiplication unit,
wherein the electrical summation module is configured to generate currents corresponding to elements of an analog output vector representing a sum of respective elements of the optical input vector multiplied by respective neural network weights.
Example 185: the system of embodiment 182 wherein the photo-electric processing loop comprises at least one signal path on which no more than one first light modulation operation is performed in a single loop iteration based on at least one of the plurality of modulator control signals and no more than one second light modulation operation is performed in a single loop iteration based on at least one of the weight control signals.
Example 186: the system of embodiment 185 wherein the first light modulation operation is performed by one of a plurality of light modulators coupled to a light source of the light output and the matrix multiplication unit and the second light modulation operation is performed by a light modulator included in the matrix multiplication unit.
Example 187: the system of embodiment 182, wherein the electro-optical processing loop comprises at least one signal path on which no more than one electrical storage operation is performed in a single loop iteration.
Example 188: the system of embodiment 174, wherein the light source comprises a laser unit configured to generate a plurality of light outputs.
Example 189: the system of embodiment 174, wherein the matrix multiplication unit comprises:
an input waveguide array for receiving an optical input vector, and the optical input vector comprises a first array of optical signals;
an optical interference unit in optical communication with the input waveguide array for performing a linear transformation of the optical input vector into a second optical signal array; and
an array of output waveguides in optical communication with the optical interference unit for guiding the second array of optical signals, wherein at least one input waveguide in the array of input waveguides is in optical communication with each output waveguide in the array of output waveguides through the optical interference unit.
Example 190: the system of embodiment 189, wherein the optical interference unit comprises:
a plurality of interconnected Mach-Zehnder interferometers (MZIs), each of the plurality of interconnected MZIs comprising:
a first phase shifter configured to change a splitting ratio of the MZI; and
a second phase shifter configured to shift a phase of one output of the MZI,
wherein the first phase shifter and the second phase shifter are coupled to a plurality of weight control signals.
Example 191: the system of embodiment 174, wherein the matrix multiplication unit comprises:
a plurality of replica modules, wherein each replica module corresponds to a subset of the one or more optical signals of the optical input vector and is configured to split the subset of the one or more optical signals into two or more replicas of the optical signal;
a plurality of multiplication modules, wherein each multiplication module corresponds to a subset of the one or more optical signals and is configured to multiply the one or more optical signals of the subset by one or more matrix element values using optical amplitude modulation; and
one or more summation modules, wherein each summation module is configured to produce an electrical signal representing a sum of results of two or more of the multiplication modules.
Example 192: the system of embodiment 191 wherein the at least one multiplication module comprises an optical amplitude modulator, the optical amplitude modulator comprising an input port and two output ports, and a pair of correlated optical signals is provided from the two output ports such that a difference between the amplitudes of the correlated optical signals corresponds to a result of multiplying the input value by a value of a signed matrix element.
Example 193: the system of embodiment 191 or 192, wherein the matrix multiplication unit is configured to multiply the light input vector by a matrix comprising one or more matrix element values.
Example 194: the system of embodiment 193 wherein a set of the plurality of output values are encoded on the respective electrical signals generated by the one or more summation modules, and wherein the output values in the set of the plurality of output values represent elements of an output vector generated by multiplying the optical input vector by a matrix.
Example 195: the system of any of embodiments 174-194, wherein the system comprises a memory unit configured to store the input data set and the neural network weights, the second unit comprises an analog-to-digital conversion (ADC) unit, and the operations further comprise:
obtaining a first plurality of digital outputs from the ADC unit corresponding to the analog output vector of the matrix multiplication unit, the first plurality of digital outputs forming a first digital output vector;
performing a non-linear transformation on the first digital output vector to produce a first transformed digital output vector; and
the first transformed digital output vector is stored in a memory unit.
Example 196: the system of embodiment 195, wherein the system has a first cycle period defined as an elapsed time between the step of storing the input data set and the first plurality of neural network weights in the memory unit and the step of storing the first transformed digital output vector in the memory unit, and
Wherein the first cycle period is less than or equal to 1 ns.
Example 197: the system of embodiment 195 or 196, wherein the operations further comprise:
an artificial neural network output generated based on the first transformed digital output vector is output.
Example 198: the system of any of embodiments 195-197, wherein the first unit comprises a digital-to-analog conversion (DAC) unit, and the operations further comprise:
a second plurality of modulator control signals is generated by the DAC unit based on the first converted digital output vector.
Example 199: the system of any of embodiments 195-198, wherein the first unit comprises a digital-to-analog conversion (DAC) unit, the artificial neural network computation request further comprises a second plurality of neural network weights, and wherein the operations further comprise:
based on the obtaining of the first plurality of digital outputs, a second plurality of weight control signals is generated by the DAC unit based on the second plurality of neural network weights.
Example 200: the system of embodiment 199 wherein the first plurality of neural network weights and the second plurality of neural network weights correspond to different layers of the artificial neural network.
Example 201: the system of any of embodiments 195-200, wherein the first unit comprises a digital-to-analog conversion (DAC) unit and the input data set further comprises a second digital input vector, an
Wherein the operations further comprise:
generating, by the DAC unit, a second plurality of modulator control signals based on a second digital input vector;
obtaining a second plurality of digital outputs from the ADC unit corresponding to the analog output vector of the matrix multiplication unit, the second plurality of digital outputs forming a second digital output vector;
performing a non-linear transformation on the second digital output vector to produce a second transformed digital output vector;
storing the second transformed digital output vector in a storage unit; and
outputting an artificial neural network output generated based on the first transformed digital output vector and the second transformed digital output vector,
wherein the analog output vector of the matrix multiplication unit is generated by a second optical input vector generated based on a second plurality of modulator control signals, the second optical input vector being converted by the matrix multiplication unit based on the first-mentioned plurality of weight control signals.
Example 202: the system of any of embodiments 174-201, wherein the system comprises a memory unit configured to store the input data sets and the neural network weights, and the second unit comprises an analog-to-digital conversion (ADC) unit, and the system further comprises:
an analog nonlinear unit disposed between the matrix multiplication unit and the ADC unit, the analog nonlinear unit configured to receive a plurality of output voltages from the matrix multiplication unit, apply a nonlinear transfer function, and output a plurality of converted output voltages to the ADC unit,
Wherein the integrated circuit of the controller performs operations further comprising:
obtaining a first plurality of converted digital output voltages corresponding to the plurality of converted output voltages from the ADC unit, the first plurality of converted digital output voltages forming a first converted digital output vector; and
the first transformed digital output vector is stored in a memory unit.
Example 203: the system of any of embodiments 174-202, wherein the integrated circuit of the controller is configured to generate the first plurality of modulator control signals at a rate greater than or equal to 8 GHz.
Example 204: the system of any of embodiments 174-190, wherein the first unit comprises a digital-to-analog conversion (DAC) unit, the second unit comprises an analog-to-digital conversion (ADC) unit, and the matrix multiplication unit comprises:
a light matrix multiplication unit coupled to the plurality of light modulators and the DAC unit, the light matrix multiplication unit configured to convert a light input vector into a light output vector based on a plurality of weight control signals; and
a photo detection unit coupled to the light matrix multiplication unit and configured to generate a plurality of output voltages corresponding to the light output vectors.
Example 205: the system of embodiment 204, further comprising:
An analog storage unit disposed between the DAC unit and the plurality of light modulators, the analog storage unit configured to store an analog voltage and output the stored analog voltage; and
an analog nonlinear unit disposed between the photo detection unit and the ADC unit, the analog nonlinear unit configured to receive a plurality of output voltages from the photo detection unit, apply a nonlinear transfer function, and output a plurality of converted output voltages.
Example 206: the system of embodiment 205, wherein the analog memory cell comprises a plurality of capacitors.
Example 207: the system of embodiment 205 or 206, wherein the analog memory cell is configured to receive and store a plurality of converted output voltages of the analog nonlinear cell and output the stored plurality of converted output voltages to the plurality of optical modulators, an
The operations further comprise:
storing a plurality of converted output voltages of an analog non-linear unit in an analog storage unit based on generating a first plurality of modulator control signals and a first plurality of weight control signals;
outputting the stored converted output voltage through the analog memory cell;
obtaining a second plurality of converted digital output voltages from the ADC unit, the second plurality of converted digital output voltages forming a second converted digital output vector; and
The second transformed digital output vector is stored in the memory unit.
Example 208: the system of embodiment 204, wherein the system comprises a storage unit configured to store the input data set and the neural network weights, and the artificial neural network computes the requested input data set to comprise a plurality of digital input vectors,
wherein the light source is configured to generate a plurality of wavelengths,
wherein the plurality of light modulators includes:
an optical modulator group configured to generate a plurality of optical input vectors, each optical modulator group corresponding to one of a plurality of wavelengths and generating a respective optical input vector having a respective wavelength; and
an optical multiplexer configured to combine the plurality of optical input vectors into a combined optical input vector comprising a plurality of wavelengths,
wherein the photodetecting unit is further configured to demultiplex a plurality of wavelengths and generate a plurality of demultiplexed output voltages, an
Wherein the operations include:
obtaining a plurality of digital demultiplexed optical outputs from the ADC unit, the plurality of digital demultiplexed optical outputs forming a plurality of first digital output vectors, wherein each of the plurality of first digital output vectors corresponds to one of the plurality of wavelengths;
performing a non-linear transformation on each of the plurality of first digital output vectors to produce a plurality of transformed first digital output vectors; and
Storing a plurality of transformed first digital output vectors in a memory unit,
wherein each of the plurality of digital input vectors corresponds to one of the plurality of optical input vectors.
Example 209: the system of embodiment 174, wherein the system comprises a memory unit configured to store the input data set and the neural network weights, the second unit comprises an analog-to-digital conversion (ADC) unit, and the artificial neural network computation request comprises a plurality of digital input vectors,
wherein the light source is configured to generate a plurality of wavelengths,
wherein the plurality of light modulators includes:
an optical modulator group configured to generate a plurality of optical input vectors, each optical modulator group corresponding to one of a plurality of wavelengths and generating a respective optical input vector having a respective wavelength; and
an optical multiplexer configured to combine the plurality of optical input vectors into a combined optical input vector comprising a plurality of wavelengths, an
The operation comprises the following steps:
obtaining a first plurality of digital light outputs from the ADC unit corresponding to a light output vector, the light output vector comprising a plurality of wavelengths, the first plurality of digital light outputs forming a first digital output vector;
performing a non-linear transformation on the first digital output vector to produce a first transformed digital output vector; and
The first transformed digital output vector is stored in a memory unit.
Example 210: the system of any of embodiments 174-209, wherein the first unit comprises a digital-to-analog conversion (DAC) unit, the second unit comprises an analog-to-digital conversion (ADC) unit, and the DAC unit comprises:
a 1-bit DAC subunit configured to generate a plurality of 1-bit modulator control signals,
where the resolution of the ADC unit is 1 bit,
wherein the resolution of the first digital input vector is N bits, an
Wherein the operations include:
decomposing the first digital input vector into N1-bit input vectors, each of the N1-bit input vectors corresponding to one of the N bits of the first digital input vector;
generating, by a 1-bit DAC subunit, a sequence of N1-bit modulator control signals corresponding to N1-bit input vectors;
obtaining from the ADC unit a sequence of N digital 1-bit optical outputs corresponding to a sequence of N1-bit modulator control signals;
constructing an N-bit digital output vector from a sequence of N digital 1-bit optical outputs;
performing a non-linear transformation on the constructed N-bit digital output vector to produce a transformed N-bit digital output vector; and
the transformed N-bit digital output vector is stored in a memory unit.
Example 211: the system of any of embodiments 174-210, wherein the system comprises a storage unit configured to store the input data sets and the neural network weights, and the storage unit comprises:
a digital input vector memory configured to store a first digital input vector and comprising at least one SRAM; and
a neural network weight memory configured to store a plurality of neural network weights and including at least one DRAM.
Example 212: the system of any of embodiments 174-211, wherein the first unit comprises a digital-to-analog conversion (DAC) unit, the digital-to-analog conversion unit comprising:
a first DAC subunit configured to generate a plurality of modulator control signals; and
a second DAC subunit configured to generate a plurality of weight control signals,
wherein the first DAC sub-unit and the second DAC sub-unit are different.
Example 213: the system of any of embodiments 174-212, wherein the light source comprises:
a laser source configured to generate light; and
an optical power splitter configured to split light generated by the laser source into a plurality of optical outputs, wherein each of the plurality of optical outputs has substantially the same power.
Example 214: the system of any of embodiments 174-213, wherein the plurality of optical modulators comprises one of a MZI modulator, a ring resonance modulator, or an electro-absorption modulator.
Example 215: the system of embodiment 204, wherein the photodetecting unit comprises:
a plurality of photodetectors; and
a plurality of amplifiers configured to convert the photocurrent generated by the photodetector into a plurality of output voltages.
Example 216: the system as in any of embodiments 174-215, wherein the integrated circuit is an application specific integrated circuit.
Example 217: the system of any of embodiments 174 and 191-194, comprising a plurality of optical waveguides coupled between the optical modulator and the matrix multiplication unit, wherein the optical input vector comprises a set of multiple input values encoded on respective optical signals carried by the optical waveguides, and each optical signal carried by one of the optical waveguides comprises an optical wave having a common wavelength that is substantially the same for all of the optical signals.
Example 218: the system as in any of embodiments 191-194 and 217, wherein the replica module comprises at least one replica module having an optical splitter that transmits a predetermined proportion of the power of the optical wave at an input port to a first output port and transmits a remaining proportion of the power of the optical wave at the input port to a second output port.
Example 219: the apparatus of embodiment 218 wherein the optical splitter comprises a waveguide optical splitter that transmits a predetermined proportion of the power of the optical wave guided by the input optical waveguide to the first output optical waveguide and transmits the remaining proportion of the power of the optical wave guided by the input optical waveguide to the second output optical waveguide.
Example 220: the apparatus of embodiment 219 wherein the guided mode of the input optical waveguide is adiabatically coupled to the guided mode of each of the first output optical waveguide and the second output optical waveguide.
Example 221: the system as in any of embodiments 218-220, wherein the beam splitter comprises a beam splitter comprising at least one surface that transmits a predetermined proportion of the power of the optical wave at the input port and reflects a remaining proportion of the power of the optical wave at the input port.
Example 222: the system of any of embodiments 217-221, wherein at least one of the plurality of optical waveguides comprises an optical fiber coupled to an optical coupler, the optical coupler coupling a guided mode of the optical fiber to a free-space propagation mode.
Example 223: the system of any of embodiments 174, 191-194, and 217-222, wherein the multiplication module comprises at least one coherence sensitive multiplication module configured to multiply the first subset of one or more optical signals by one or more matrix element values using optical amplitude modulation based on interference between optical waves, the optical waves having a coherence length that is at least as long as a propagation distance through the coherence sensitive multiplication module.
Example 224: the apparatus of embodiment 223, wherein the coherence-sensitive multiplication module comprises a mach-zehnder interferometer (MZI) that splits the lightwaves guided by the input optical waveguide into a first optical waveguide arm of the MZI and a second optical waveguide arm of the MZI, the first optical waveguide arm comprising a phase shifter that produces a relative phase shift with respect to a phase delay of the second optical waveguide arm, and the MZI combines the lightwaves from the first optical waveguide arm and the second optical waveguide arm into the at least one output optical waveguide.
Example 225: the apparatus of embodiment 224 wherein the MZI combines the optical waves from the first and second optical waveguide arms into each of the first and second output optical waveguides, the first photodetector receives the optical wave from the first output optical waveguide to produce a first photocurrent, the second photodetector receives the optical wave from the second output optical waveguide to produce a second photocurrent, and the result of the coherence sensitive multiplication module comprises a difference between the first photocurrent and the second photocurrent.
Example 226: the system of any of embodiments 223-225, wherein the coherence sensitive multiplying module comprises one or more ring resonators comprising at least one ring resonator coupled to the first optical waveguide and at least one ring resonator coupled to the second optical waveguide.
Example 227: the apparatus of embodiment 226 wherein the first photodetector receives the light wave from the first optical waveguide to produce a first photocurrent, the second photodetector receives the light wave from the second optical waveguide to produce a second photocurrent, and the result of the coherence sensitive multiplication module comprises a difference between the first photocurrent and the second photocurrent.
Example 228: the system of any of embodiments 174, 191-194, and 217-227, wherein the multiplication module comprises at least one coherent insensitive multiplication module configured to multiply the first subset of the one or more optical signals by one or more matrix element values using optical amplitude modulation based on energy absorption within the optical wave.
Example 229: the apparatus of embodiment 228 wherein the coherent insensitive multiplication module comprises an electro-absorption modulator.
Example 230: the system of any of embodiments 174, 191-194, and 217-229, wherein the one or more summing modules comprises at least one summing module comprising: (1) two or more input conductors, each input conductor carrying an electrical signal in the form of an input current, the magnitude of the input current being representative of a respective result of a respective one of the multiplication modules, and (2) at least one output conductor carrying an electrical signal representative of a sum of the respective results in the form of an output current, the output current being proportional to the sum of the input currents.
Example 231: the apparatus of embodiment 230 wherein the two or more input conductors and the output conductor comprise wires that contact at one or more junctions between the wires and the output current is substantially equal to the sum of the input currents.
Example 232: the apparatus of embodiment 230 or 231 wherein at least a first one of the input currents is provided in the form of at least one photocurrent generated by at least one photodetector receiving an optical signal generated by a first one of the multiplication modules.
Example 233: the apparatus of embodiment 232 wherein the first input current is provided as a difference between two photocurrents produced by different respective photodetectors that receive different respective optical signals produced by the first multiplication module.
Example 234: the system of any of embodiments 174-233, wherein one of the copies of the first subset of one or more optical signals consists of a single optical signal, wherein one of the input values is encoded on the single optical signal.
Example 235: the apparatus of embodiment 234 wherein the multiplication module corresponding to the replica of the first subset multiplies the encoded input value by a single matrix element value.
Example 236: the system of any of embodiments 174, 191-194, and 217-235, wherein one of the copies of the first subset of one or more optical signals comprises more than one, and less than all, of the optical signals on which the plurality of input values are encoded.
Example 237: the apparatus of embodiment 236 wherein the multiplication module corresponding to the copy of the first subset multiplies the encoded input values by different respective matrix element values.
Example 238: the apparatus of embodiment 237 wherein different multiplication modules corresponding to different respective copies of the first subset of the one or more optical signals are included in different apparatuses, the different apparatuses in optical communication to transmit one of the copies of the first subset of the one or more optical signals between the different apparatuses.
Example 239: the system of any of embodiments 174, 191-194, and 217-238, wherein at least one of the two or more of the plurality of optical waveguides, the two or more of the plurality of replica modules, the two or more of the plurality of multiplication modules, and the one or more summation modules is disposed on a substrate of a common device.
Example 240: the apparatus of embodiment 239, wherein the apparatus performs a vector matrix multiplication, wherein the input vectors are provided as a set of optical signals and the output vectors are provided as a set of electrical signals.
Example 241: the system of any of embodiments 174, 191-194, and 217-240, further comprising an accumulator that combines the input electrical signal corresponding to the output of the multiplication module or the summation module, wherein the input electrical signal is encoded using time-domain coding using switching amplitude modulation within each of the plurality of time slots, and the accumulator generates the output electrical signal, the output electrical signal being encoded at more than two amplitude levels, the amplitude levels corresponding to different duty cycles of the time-domain coding over the plurality of time slots.
Example 242: the system of any of embodiments 174, 191-194, and 217-241, wherein each of two or more of the multiplication modules corresponds to a different subset of the one or more optical signals.
Example 243: the system of any of embodiments 174, 191-194, and 217-242, the apparatus further comprising, for each replica of the second subset of one or more optical signals, a multiplication module configured to multiply the one or more optical signals of the second subset by one or more matrix element values using optical amplitude modulation, different from the optical signals in the first subset of one or more optical signals.
Example 244: a system, comprising:
A storage unit configured to store the data set and a plurality of neural network weights;
a driver unit configured to generate a plurality of modulator control signals;
an optoelectronic processor comprising:
a light source configured to provide a plurality of light outputs;
a plurality of optical modulators coupled to the light source and the driver unit, the plurality of optical modulators configured to generate a light input vector by modulating a plurality of light outputs generated by the light source based on a plurality of modulator control signals;
a matrix multiplication unit coupled to the plurality of optical modulators and the driver unit, the matrix multiplication unit configured to convert an optical input vector into an analog output vector based on a plurality of weight control signals; and
a comparator unit coupled to the matrix multiplication unit and configured to convert the analog output vector into a plurality of digital 1-bit outputs; and
a controller comprising an integrated circuit configured to perform the following operations:
receiving an artificial neural network computation request comprising an input data set and a first plurality of neural network weights, wherein the input data set comprises a first digital input vector having an N-bit resolution;
storing the input data set and the first plurality of neural network weights in a memory unit;
Decomposing the first digital input vector into N1-bit input vectors, each of the N1-bit input vectors corresponding to one of the N bits of the first digital input vector;
generating, by a driver unit, a sequence of N1-bit modulator control signals corresponding to N1-bit input vectors;
obtaining from the comparator unit a sequence of N digital 1-bit outputs corresponding to the sequence of N1-bit modulator control signals;
constructing an N-bit digital output vector from the sequence of N digital 1-bit outputs;
performing a non-linear transformation on the constructed N-bit digital output vector to produce a transformed N-bit digital output vector; and
the transformed N-bit digital output vector is stored in a memory unit.
Example 245: the system of embodiment 244, wherein receiving an artificial neural network computation request comprises receiving an artificial neural network computation request from a general purpose computer (general purpose computer).
Example 246: the system of embodiment 244, wherein the driver unit is configured to generate a plurality of weight control signals.
Example 247: the system of embodiment 244, wherein the matrix multiplication unit comprises:
a light matrix multiplication unit coupled to the plurality of light modulators and the driver unit, the light matrix multiplication unit configured to convert a light input vector into a light output vector based on a plurality of weight control signals; and
A photo detection unit coupled to the light matrix multiplication unit and configured to generate a plurality of output voltages corresponding to the light output vectors.
Example 248: the system of embodiment 244, wherein the matrix multiplication unit comprises:
an input waveguide array for receiving an optical input vector;
an optical interference unit in optical communication with the input waveguide array for performing a linear transformation of the optical input vector into a second optical signal array; and
an array of output waveguides in optical communication with the optical interference unit for guiding the second array of optical signals, wherein at least one input waveguide in the array of input waveguides is in optical communication with each output waveguide in the array of output waveguides through the optical interference unit.
Example 249: the system of embodiment 248, wherein the optical interference unit comprises:
a plurality of interconnected Mach-Zehnder interferometers (MZIs), each of the plurality of interconnected MZIs comprising:
a first phase shifter configured to change a splitting ratio of the MZI; and
a second phase shifter configured to shift a phase of one output of the MZI,
wherein the first phase shifter and the second phase shifter are coupled to a plurality of weight control signals.
Example 250: the system of embodiment 244, wherein the matrix multiplication unit comprises:
A plurality of replica modules, for each of at least two subsets of one or more optical signals of the optical input vector, the plurality of replica modules comprising a respective set of one or more replica modules configured to divide the subset of one or more optical signals into two or more replicas of the optical signal;
a plurality of multiplication modules, for each of the at least two copies of the first subset of one or more optical signals, a respective multiplication module of the plurality of multiplication modules configured to multiply the one or more optical signals of the first subset by one or more matrix element values using optical amplitude modulation; and
one or more summation modules, for the results of the two or more multiplication modules, the one or more summation modules comprising a summation module configured to produce an electrical signal representing a sum of the results of the two or more multiplication modules.
Example 251: the system of embodiment 250, wherein the at least one multiplication module comprises an optical amplitude modulator comprising an input port and two output ports, and a pair of correlated optical signals is provided from the two output ports such that a difference between amplitudes of the correlated optical signals corresponds to a result of multiplying the input value by a value of an element of the signed matrix.
Example 252: the system of embodiment 250 or 251, wherein the matrix multiplication unit is configured to multiply the light input vector by a matrix comprising one or more matrix element values.
Example 253: the system of embodiment 252 wherein a set of the plurality of output values are encoded on the corresponding electrical signals generated by the one or more summation modules, and wherein the output values in the set of the plurality of output values represent elements of an output vector generated by multiplying the optical input vector by the matrix.
Example 254: a method for performing artificial neural network computations in a system having a matrix multiplication unit configured to convert an optical input vector to an analog output vector based on a plurality of weight control signals, the method comprising:
receiving an artificial neural network computation request comprising an input data set and a first plurality of neural network weights, wherein the input data set comprises a first numerical input vector;
storing the input data set and the first plurality of neural network weights in a memory unit;
generating a first plurality of modulator control signals based on the first digital input vector and a first plurality of weight control signals based on the first plurality of neural network weights;
Obtaining a first plurality of digital outputs corresponding to the output vectors of the matrix multiplication unit, the first plurality of digital outputs forming a first digital output vector;
performing, by a controller, a non-linear transformation on a first digital output vector to produce a first transformed digital output vector;
storing the first transformed digital output vector in a memory unit; and
an artificial neural network output generated based on the first transformed digital output vector is output by the controller.
Example 255: the method of embodiment 254 wherein receiving an artificial neural network computation request comprises receiving an artificial neural network computation request from a computer over a communications channel.
Example 256: the method of embodiment 254 or 255, wherein generating the first plurality of modulator control signals comprises generating the first plurality of modulator control signals by a digital-to-analog conversion (DAC) unit.
Example 257: the method of any one of embodiments 254 to 256, wherein deriving the first plurality of digital outputs comprises deriving the first plurality of digital outputs from an analog-to-digital conversion (ADC) unit.
Example 258: the method of embodiment 257, comprising:
applying a first plurality of modulator control signals to a plurality of optical modulators coupled to the light source and the DAC unit; and
A plurality of optical modulators are used to generate an optical input vector by modulating a plurality of optical outputs generated by the laser unit based on a plurality of modulator control signals.
Example 259: the method of embodiment 258, wherein the matrix multiplication unit is coupled to a plurality of optical modulators and DAC units, and the method comprises:
a matrix multiplication unit is used to convert the optical input vector into an analog output vector based on a plurality of weight control signals.
Example 260: the method of embodiment 259 wherein the ADC unit is coupled to a matrix multiplication unit, and the method comprises:
the analog output vector is converted into a first plurality of digital outputs using an ADC unit.
Example 261: the method of embodiment 259 or 260, wherein the matrix multiplication unit comprises an optical matrix multiplication unit coupled to the plurality of optical modulators and DAC units,
converting the light input vector into the analog output vector includes converting the light input vector into the light output vector based on the plurality of weight control signals using the light matrix multiplication unit, an
The method comprises the following steps: a plurality of output voltages corresponding to the light output vectors are generated using a photo-detection unit coupled to the optical matrix multiplication unit.
Example 262: the method of embodiment 254, comprising:
Receiving an optical input vector at an input waveguide array;
performing a linear transformation of the optical input vector into a second array of optical signals using an optical interference unit in optical communication with the input waveguide array; and
the second array of optical signals is guided using an array of output waveguides in optical communication with the optical interference unit, wherein at least one input waveguide in the array of input waveguides is in optical communication with each output waveguide in the array of output waveguides through the optical interference unit.
Example 263: the method of embodiment 262, wherein the optical interference unit comprises a plurality of interconnected mach-zehnder interferometers (MZIs), each of the plurality of interconnected MZIs comprising a first phase shifter and a second phase shifter, and the first phase shifter and the second phase shifter are coupled to the plurality of weight control signals, wherein
The method comprises the following steps:
changing the splitting ratio of the MZI using a first phase shifter, an
A second phase shifter is used to shift the phase of one output of the MZI.
Example 264: the method of embodiment 258, comprising:
for each of at least two subsets of one or more optical signals of the optical input vector, dividing the subset of one or more optical signals into two or more replicas of the optical signal using a respective set of one or more replica modules;
For each of the at least two copies of the first subset of one or more optical signals, using a respective multiplication module to multiply the one or more optical signals of the first subset by one or more matrix element values using optical amplitude modulation; and
for the results of the two or more multiplication modules, a summation module configured to generate an electrical signal is used, the electrical signal representing a sum of the results of the two or more multiplication modules.
Example 265: the method of embodiment 264 wherein the at least one multiplication module comprises an optical amplitude modulator, the optical amplitude modulator comprises an input port and two output ports, and a pair of correlated optical signals is provided from the two output ports such that a difference between amplitudes of the correlated optical signals corresponds to a result of multiplying an input value by a value of a signed matrix element.
Example 266: the method of embodiment 264 or 265 comprising multiplying the light input vector by a matrix comprising one or more matrix element values using a matrix multiplication unit.
Example 267: the method of embodiment 266, comprising encoding a set of multiple output values on respective electrical signals produced by one or more summation modules, an
The output values in the set of multiple output values are used to represent elements of an output vector, which is generated by multiplying the optical input vector by a matrix.
Example 268: a method, comprising:
providing input information in an electronic format;
converting at least a portion of the electronic input information into an optical input vector;
photoelectrically converting an optical input vector into an analog output vector based on matrix multiplication; and
a non-linear transformation is electronically applied to the analog output vector to provide output information in an electronic format.
Example 269: the method of embodiment 268, further comprising:
the electro-optical conversion, the photoelectric conversion, and the nonlinear conversion for the electrical application are repeated for new electronic input information corresponding to output information provided in an electronic format.
Example 270: the method of embodiment 269, wherein the matrix multiplication for the initial photoelectric conversion and the matrix multiplication for the repeated photoelectric conversion are the same and correspond to the same layer of the artificial neural network.
Example 271: the method of embodiment 269, wherein the matrix multiplication for the initial photoelectric conversion and the matrix multiplication for the repeated photoelectric conversion are different and correspond to different layers of the artificial neural network.
Example 272: the method of embodiment 268, further comprising:
repeating electro-optical conversion, and nonlinear transformation for electrical applications for different portions of the electronic input information,
Wherein the matrix multiplication for the initial photoelectric conversion and the matrix multiplication for the repeated photoelectric conversion are the same and correspond to the first layer of the artificial neural network.
Example 273: the method of embodiment 272, further comprising:
providing intermediate information in an electronic format based on electronic output information for a plurality of portions of electronic input information generated by a first layer of an artificial neural network; and
repeating the electro-optical conversion, the electro-optical conversion and the non-linear transformation for the electrical application for each of the different portions of the electrical intermediate information,
wherein the matrix multiplication for the initial photoelectric conversion and the matrix multiplication for the repeated photoelectric conversion associated with different parts of the electronic intermediate information are identical and correspond to the second layer of the artificial neural network.
Example 274: a system for performing artificial neural network computations, the system comprising:
a first unit configured to generate a plurality of vector control signals and generate a plurality of weight control signals;
a second unit configured to provide an optical input vector based on a plurality of vector control signals;
a matrix multiplication unit coupled to the second unit and the first unit, the matrix multiplication unit configured to convert the optical input vector into an output vector based on a plurality of weight control signals; and
A controller comprising an integrated circuit configured to perform the following operations:
receiving an artificial neural network computation request comprising an input data set and a first plurality of neural network weights, wherein the input data set comprises a first numerical input vector; and
generating, by a first unit, a first plurality of vector control signals based on a first digital input vector and a first plurality of weight control signals based on a first plurality of neural network weights;
wherein the first unit, the second unit, the matrix multiplication unit and the controller are used for a photo-electric processing cycle that is repeated in a plurality of iterations, and the photo-electric processing cycle comprises: (1) at least two light modulation operations, and (2) at least one of (a) an electrical summing operation or (b) an electrical storage operation.
Example 275: a method for performing artificial neural network computations, the method comprising:
providing input information in an electronic format;
converting at least a portion of the electronic input information into an optical input vector; and
converting an optical input vector to an output vector based on matrix multiplication using a set of neural network weights;
wherein the providing and converting are performed in a photoelectric processing loop, the photoelectric processing loop being repeated in a plurality of iterations using different respective sets of neural network weights and different respective input information, and the photoelectric processing loop comprising: (1) at least two light modulation operations, and (2) at least one of (a) an electrical summing operation or (b) an electrical storage operation.
Example 276: a computing system, comprising:
a first unit configured to generate a plurality of modulator control signals;
a processing unit comprising:
a light source or port configured to provide a plurality of light outputs;
a first set of optical modulators coupled to the optical source or port and the first cell, the optical modulators in the first set of optical modulators configured to generate an optical input vector by modulating a plurality of optical outputs provided by the optical source or port based on a plurality of digital input values corresponding to a first set of modulator control signals in the modulator control signals, the optical input vector comprising a plurality of optical signals; and
a matrix multiplication unit including a second set of light modulators, wherein the matrix multiplication unit is coupled to
A first unit, and the matrix multiplication unit is configured to transform the optical input vector into an analog output vector based on a plurality of digital weight values corresponding to a second set of modulator control signals of a plurality of modulator control signals applied to a second set of optical modulators,
wherein at least one optical modulator of at least one of the first set of optical modulators or the second set of optical modulators is configured to modulate the optical signal based on a first modulator control signal of the plurality of modulator control signals, and the first unit is configured to shape the first modulator control signal to include a bandwidth enhancement related to an amplitude variation associated with a corresponding variation of a continuous digital value corresponding to the first modulator control signal.
Example 277: the system of embodiment 276, further comprising:
a second unit coupled to the matrix multiplication unit and configured to convert the analog output vector to a digital output vector; and
a controller comprising an integrated circuit configured to perform the following operations:
receiving an artificial neural network computation request, the artificial neural network computation request comprising an input data set, the input data set comprising a first numeric input vector;
receiving a first plurality of neural network weights; and
by a first unit, a first plurality of modulator control signals is generated based on a first digital input vector, and a first plurality of weight control signals is generated based on a first plurality of neural network weights.
Example 278: the system of embodiment 276 or 277, wherein the first unit comprises a digital-to-analog converter (DAC).
Example 279: the system of embodiment 277, further comprising a storage unit configured to store the data set and the plurality of neural network weights.
Example 280: the system of embodiment 279, wherein the integrated circuit of the controller is further configured to perform operations comprising storing the input data set and the first plurality of neural network weights in a memory unit.
Example 281: the system as in any one of embodiments 277 through 280, wherein the controller comprises an Application Specific Integrated Circuit (ASIC), and
receiving the artificial neural network computation request includes receiving the artificial neural network computation request from a general purpose data processor.
Example 282: the system as in any one of embodiments 277 through 281, wherein the first unit, the processing unit, the second unit, and the controller are disposed on at least one of a multi-chip module or an integrated circuit, and
receiving the artificial neural network computation request includes receiving the artificial neural network computation request from a second data processor, wherein the second data processor is external to the multi-chip module or integrated circuit, the second data processor is coupled to the multi-chip module or integrated circuit through a communication channel, and the processing unit may process data at a data rate that is at least an order of magnitude greater than a data rate of the communication channel.
Example 283: the system as in any one of embodiments 277 through 282, wherein the first unit, the processing unit, the second unit, and the controller are used in a photo-electric processing loop that repeats in a plurality of iterations, the photo-electric processing loop comprising:
(1) at least a first light modulation operation based on at least one of the plurality of modulator control signals, and at least a second light modulation operation based on at least one of the weight control signals, and
(2) At least one of (a) an electrical summing operation or (b) an electrical storage operation.
Example 284: the system of embodiment 283, wherein the photo-electric processing cycle includes an electrical storage operation, and the electrical storage operation is performed using a memory unit coupled to the controller,
wherein the operations performed by the controller further comprise storing the input data set and the first plurality of neural network weights in a memory unit.
Example 285: the system of embodiment 283 or 284 wherein the photo-electric processing cycle comprises an electrical summing operation, and the electrical summing operation is performed using an electrical summing module within the matrix multiplication unit,
wherein the electrical summation module is configured to generate currents corresponding to elements of the analog output vector, the currents representing a sum of respective elements of the optical input vector multiplied by respective neural network weights.
Example 286: the system as in any one of embodiments 276-285, wherein the first modulator control signal comprises an analog signal associated with a plurality of predetermined amplitude levels, and each of the amplitude levels is associated with a different corresponding digital value.
Example 287: the system of embodiment 286, wherein the first modulator control signal comprises an analog signal associated with two predetermined amplitude levels, and each of the amplitude levels is associated with a different corresponding binary value.
Example 288: the system of embodiment 287, wherein the consecutive digital values comprise a plurality of consecutive binary values in a series of binary values.
Example 289: the system of embodiment 288, wherein the controller is configured to shape the first modulator control signal to include the bandwidth enhancement for the initial portion of the second time interval by increasing a magnitude of the amplitude variation between a first predetermined amplitude level associated with the first time interval and a second predetermined amplitude level associated with the second time interval.
Example 290: the system of embodiment 288 or 289, wherein a series of binary values is used to determine an amplitude level of a first modulator control signal used to modulate the optical signal according to a non-return-to-zero (NRZ) modulation pattern.
Example 291: the system as in any one of embodiments 288-290, wherein the first unit is configured to shape the first modulator control signal to include bandwidth enhancement by pumping current between the diode structure of the first modulator in the second set of light modulators and a capacitance connected in series between the diode structure and a circuit providing the first modulator control signal, and an amount of charge delivered by the pumping current is determined based at least in part on a constant voltage over a time period providing successive digital values.
Example 292: an apparatus, comprising:
a plurality of optical waveguides coupled to the first set of optical amplitude modulators, wherein a set of the plurality of input values is encoded on respective optical signals carried by the optical waveguides using the first set of optical amplitude modulators;
a plurality of replica modules, and for each of at least two subsets of the one or more optical signals, a corresponding set of the one or more replica modules is configured to split the subset of the one or more optical signals into two or more replicas of the optical signal;
a plurality of multiplication modules, each of the multiplication modules comprising an optical amplitude modulator of the second set of optical amplitude modulators, and for each of the at least two copies of the first subset of one or more optical signals, the corresponding multiplication module configured to multiply the one or more optical signals of the first subset by one or more matrix element values using the optical amplitude modulator of the second set of optical amplitude modulators; and
one or more summing modules, and for the results of two or more multiplying modules, a corresponding one of the summing modules is configured to produce an electrical signal representing the sum of the results of the two or more multiplying modules;
wherein at least one optical amplitude modulator of at least one of the first set of optical amplitude modulators or the second set of optical amplitude modulators is configured to modulate an optical signal with a modulation value using a power that monotonically increases with respect to an absolute value of the modulation value.
Example 293: the apparatus of embodiment 292 wherein at least one optical amplitude modulator of at least one of the first set of optical amplitude modulators or the second set of optical amplitude modulators comprises a coherence sensitive optical amplitude modulator configured to modulate an optical signal by a modulation value based on interference between a plurality of optical waves, the optical waves having a coherence length at least as long as a propagation distance through the coherence sensitive optical amplitude modulator.
Example 294: the apparatus of embodiment 293, wherein the coherence sensitive optical amplitude modulator comprises a mach-zehnder interferometer (MZI) that distributes the optical waves guided by the input optical waveguide to a first optical waveguide arm of the mach-zehnder interferometer and a second optical waveguide arm of the mach-zehnder interferometer, the first optical waveguide arm comprising an active phase shifter that produces a relative phase shift with respect to a phase delay of the second optical waveguide arm, and the mach-zehnder interferometer combines the optical waves from the first optical waveguide arm and the second optical waveguide arm into the at least one output optical waveguide.
Example 295: the apparatus of embodiment 294, wherein the power used to modulate the optical signal by the modulation value comprises power applied to an active phase shifter.
Example 296: the apparatus of embodiment 292 wherein an input value in a set of multiple input values encoded on a respective optical signal represents multiple elements of an input vector multiplied by a matrix comprising one or more matrix element values.
Example 297: the apparatus of embodiment 296, wherein a set of the plurality of output values is encoded on the corresponding electrical signals generated by the one or more summation modules, and wherein the output values in the set of the plurality of output values represent a plurality of elements of an output vector, the output vector generated by multiplying the input vector by the matrix.
Example 298: the apparatus of any of embodiments 292-297, wherein each of the optical signals carried by the optical waveguides includes optical waves having a common wavelength, the common wavelength being approximately the same for all of the optical signals.
Example 299: the apparatus of any one of embodiments 292-297, wherein the replica module comprises at least one replica module having an optical splitter, the optical splitter to transmit a predetermined proportion of the power of the optical wave at the input port of the replica module to a first output port of the replica module and to transmit a remaining proportion of the power of the optical wave at the input port of the replica module to a second output port of the replica module.
Example 300: the apparatus of embodiment 299 wherein the optical splitter comprises a waveguide optical splitter that transmits a predetermined proportion of the power of the lightwave guided by the input optical waveguide of the replica module to a first output optical waveguide of the replica module and transmits the remaining proportion of the power of the lightwave guided by the input optical waveguide of the replica module to a second output optical waveguide of the replica module.
Example 301: the apparatus of embodiment 300 wherein the guided mode of the input optical waveguide is adiabatically coupled to the guided mode of each of the first output optical waveguide and the second output optical waveguide.
Example 302: the apparatus of embodiment 299 or 230, wherein the optical splitter comprises a beam splitter comprising at least one surface that transmits a predetermined proportion of the power of the optical wave at the input port and reflects a remaining proportion of the power of the optical wave at the input port.
Example 303: the apparatus of embodiment 302 wherein at least one of the plurality of optical waveguides comprises an optical fiber coupled to an optical coupler, the optical coupler coupling a guided mode of the optical fiber to a free-space propagation mode.
Example 304: the apparatus as in any one of embodiments 292-303, wherein the multiplication module comprises at least one coherence sensitive optical amplitude modulator configured to multiply the one or more optical signals of the first subset by one or more matrix element values based on interference between optical waves, the optical waves having a coherence length at least as long as a propagation distance through the coherence sensitive optical amplitude modulator.
Example 305: the apparatus of embodiment 304 wherein the coherence sensitive optical amplitude modulator comprises a mach-zehnder interferometer that distributes the lightwaves guided by the input optical waveguide to a first optical waveguide arm of the mach-zehnder interferometer and a second optical waveguide arm of the mach-zehnder interferometer, the first optical waveguide arm comprising a phase shifter that produces a relative phase shift with respect to a phase delay of the second optical waveguide arm, and the mach-zehnder interferometer combines the lightwaves from the first optical waveguide arm and the second optical waveguide arm into the at least one output optical waveguide.
Example 306: the apparatus of embodiment 305 wherein the mach-zehnder interferometer combines a plurality of light waves from the first and second optical waveguide arms into each of the first and second output optical waveguides, the first photodetector receives the light wave from the first output optical waveguide to produce a first photocurrent, the second photodetector receives the light wave from the second output optical waveguide to produce a second photocurrent, and the result of the coherence sensitive optical amplitude modulator comprises a difference between the first photocurrent and the second photocurrent.
Example 307: the apparatus of any of embodiments 304-306, wherein the coherence sensitive optical amplitude modulator comprises one or more ring resonators comprising at least one ring resonator coupled to the first optical waveguide and at least one ring resonator coupled to the second optical waveguide.
Example 308: the apparatus of embodiment 307 wherein the first photodetector receives the light wave from the first optical waveguide to produce a first photocurrent, the second photodetector receives the light wave from the second optical waveguide to produce a second photocurrent, and the result of the coherently sensitive optical amplitude modulator comprises a difference between the first photocurrent and the second photocurrent.
Example 309: the apparatus of any one of embodiments 292 to 308, wherein the multiplication module comprises at least one coherent insensitive optical amplitude modulator configured to multiply the first subset of the one or more optical signals by one or more matrix element values based on energy absorption within the optical waves.
Example 310: the apparatus of embodiment 309 wherein the coherent non-sensitive optical amplitude modulator comprises an electro-absorption modulator.
Example 311: the apparatus as in any one of embodiments 292-310, wherein the one or more summing modules comprises at least one summing module comprising: (1) two or more input conductors, each of the input conductors carrying an electrical signal in the form of an input current, the magnitude of the input current representing a respective result of a respective one of the multiplication modules, and (2) at least one output conductor carrying an electrical signal in the form of an output current representing a sum of the respective results, the output current being proportional to the sum of the input currents.
Example 312: the apparatus of embodiment 311, wherein the two or more input conductors and the output conductor comprise wires that are in contact at one or more junctions between the wires, and the output current is approximately equal to a sum of the input currents.
Example 313: the apparatus of embodiment 311 or 312 wherein at least a first one of the input currents is provided in the form of at least one photocurrent generated by at least one photodetector that receives an optical signal generated by a first one of the multiplication modules.
Example 314: the apparatus of embodiment 313 wherein the first input current is provided as a difference between two photocurrents generated by different respective photodetectors that receive different respective optical signals generated by the first multiplication module.
Example 315: the apparatus as in any one of embodiments 292-314, wherein one of the copies of the first subset of one or more optical signals consists of a single optical signal on which one of the input values is encoded.
Example 316: the apparatus of embodiment 315 wherein the multiplication module corresponding to the replica of the first subset multiplies the encoded input value by a single matrix element value.
Example 317: the apparatus of any one of embodiments 292-316, wherein one of the copies of the first subset of one or more optical signals comprises more than one, and less than all, of the optical signals on which the plurality of input values are encoded.
Example 318: the apparatus of embodiment 317 wherein the multiplication module corresponding to the replica of the first subset multiplies the encoded input values by different respective matrix element values.
Example 319: the apparatus of embodiment 318 wherein different multiplication modules corresponding to different respective copies of the first subset of the one or more optical signals are included in different apparatuses, the different apparatuses in optical communication to transmit one of the copies of the first subset of the one or more optical signals between the different apparatuses.
Example 320: the apparatus of embodiment 319 wherein at least one of the two or more of the plurality of optical waveguides, the two or more of the plurality of replica modules, the two or more of the plurality of multiplication modules, and the one or more summation modules is disposed on a substrate of a common apparatus.
Example 321: the apparatus of embodiment 320 wherein the apparatus performs a vector matrix multiplication wherein input vectors are provided as a set of optical signals and output vectors are provided as a set of electrical signals.
Example 322: an apparatus as in any one of embodiments 292-321, further comprising an accumulator that integrates an input electrical signal corresponding to an output of the multiplication module or the summation module, wherein the input electrical signal is encoded using time-domain coding using switched amplitude modulation within each of a plurality of time slots, and the accumulator generates an output electrical signal that is encoded at more than two amplitude levels, the amplitude levels corresponding to different duty cycles of the time-domain coding over the plurality of time slots.
Example 323: the apparatus of any one of embodiments 292-322, wherein each of the two or more multiplication modules corresponds to a different subset of the one or more optical signals.
Example 324: the apparatus of any one of embodiments 292-323, further comprising a multiplication module for each replica of a second subset of one or more optical signals different from the optical signals in the first subset of one or more optical signals configured to multiply the one or more optical signals of the second subset by one or more matrix element values using optical amplitude modulation.
Example 325: a method, comprising:
encoding a set of multiple input values on a respective optical signal using a first set of optical amplitude modulators;
For each of at least two subsets of one or more optical signals, using a corresponding set of one or more replica modules to split the subset of one or more optical signals into two or more replicas of the optical signal;
for each of the at least two copies of the first subset of one or more optical signals, multiplying the one or more optical signals of the first subset by one or more matrix element values using an optical amplitude modulator of the second set of optical amplitude modulators using a corresponding multiplication module; and
for the results of the two or more multiplication modules, a summation module configured to generate an electrical signal is used, the electrical signal representing the sum of the results of the two or more multiplication modules,
wherein at least one optical amplitude modulator of at least one of the first set of optical amplitude modulators or the second set of optical amplitude modulators is configured to modulate an optical signal with a modulation value using a power that monotonically increases with respect to an absolute value of the modulation value.
Claims (38)
1. An optoelectronic computing system, comprising:
a first semiconductor die comprising a Photonic Integrated Circuit (PIC), the PIC comprising:
a plurality of optical waveguides, wherein a set of a plurality of input values are encoded on respective optical signals carried by the optical waveguides;
An optical replica distribution network comprising a plurality of optical splitters, wherein each optical splitter transmits half of the power of an input optical wave at an input port to each of two output ports; and
an array of optoelectronic circuit portions, each optoelectronic circuit portion receiving an optical wave from one of the output ports of the optical replica distribution network, and each optoelectronic circuit portion comprising:
at least one photodetector that detects at least one light wave from the photo-electric operation; and
at least one conductive line integrated in the PIC, the conductive line electrically coupled to the photodetector and electrically coupled to an electrical output port; and
a second semiconductor die comprising an Electronic Integrated Circuit (EIC), the EIC comprising:
a plurality of electrical input ports that receive respective electrical values;
wherein the first semiconductor die and the second semiconductor die are electrically coupled in a controlled collapse chip connection, wherein the electrical output port of the PIC is connected to one of the electrical input ports of the EIC.
2. The optoelectronic computing system of claim 1, wherein each optoelectronic circuit portion comprises:
an opto-electronic operational module that performs operations between (1) an optical value based on one of the input values scaled by the optical replication distribution network and (2) an electrical value provided by an electrical input port;
At least one photodetector that detects at least one light wave from the photovoltaic operation; and
at least one conductive line integrated in the PIC, the conductive line electrically coupled to the photodetector and electrically coupled to an electrical output port.
3. The optoelectronic computing system of claim 2, wherein the EIC further comprises a plurality of digital-to-analog converters (DACs) that provide electrical values to respective electrical output ports, and the electrical input port of the PIC is connected to the electrical output port of the EIC.
4. The optoelectronic computing system of claim 3, wherein the optical splitters are arranged as nodes in a binary tree arrangement connected by optical waveguides that are links in the binary tree arrangement.
5. The optoelectronic computing system of claim 4, wherein the optical replication distribution network includes a plurality of binary tree arrangements, each binary tree arrangement distributing a different one of the plurality of input values encoded on a respective optical signal.
6. The optoelectronic computing system of claim 4, wherein the lengths of light propagation between the roots of the binary tree arrangement and different optoelectronic circuit portions are all different from one another.
7. The optoelectronic computing system of claim 6, wherein the optical waveguides in the optical replica distribution network are arranged in the first semiconductor die to avoid crossing any optical waveguides in the optical replica distribution network.
8. The optoelectronic computing system of claim 7, wherein the optoelectronic circuit portion is arranged in a substantially straight plurality of lines on the first semiconductor die.
9. The optoelectronic computing system of claim 8, wherein each of the plurality of lines are optically coupled to each other by one or more optical waveguides in the light replication distribution network.
10. The optoelectronic computing system of claim 2, wherein a portion of the wires integrated in the PIC connect the photodetector to a junction between wires from different optoelectronic circuit portions.
11. The optoelectronic computing system of claim 2, wherein the optoelectronic operations module comprises a mach-zehnder interferometer configured to perform a multiplication operation between (1) the optical value based on one of the input values scaled by the optical replica distribution network and (2) the electrical value provided by the electrical input port.
12. The optoelectronic computing system of claim 2, wherein the EIC further comprises a transimpedance amplifier having an input electrically coupled to an electrical output port of the PIC.
13. An optoelectronic computing system, comprising:
a first semiconductor die comprising a Photonic Integrated Circuit (PIC), the PIC comprising:
a plurality of optical waveguides, wherein a set of a plurality of input values are encoded on respective optical signals carried by the optical waveguides;
an optical replication distribution network comprising a plurality of optical splitters or directional couplers; and
an array of optoelectronic circuit portions, each optoelectronic circuit portion receiving an optical wave from one of the output ports of the optical replica distribution network, and each optoelectronic circuit portion comprising:
at least one photodetector that detects at least one light wave from the photo-electric operation; and
at least one conductive line integrated in the PIC, the conductive line electrically coupled to the photodetector and electrically coupled to an electrical output port; and
a second semiconductor die comprising an Electronic Integrated Circuit (EIC), the EIC comprising:
a plurality of electrical input ports that receive respective electrical values;
wherein the first semiconductor die and the second semiconductor die are electrically coupled in a controlled collapse chip connection, wherein the electrical output port of the PIC is connected to one of the electrical input ports of the EIC.
14. An optoelectronic computing system according to claim 13, wherein each optical splitter transmits half of the power of an input optical wave at an input port to each of two output ports.
15. The optoelectronic computing system of claim 13, wherein the optical replication distribution network comprises a cascade of directional couplers.
16. The optoelectronic computing system as set forth in claim 13, wherein each optoelectronic circuit portion includes:
an opto-electronic operational module that performs operations between (1) an optical value based on one of the input values scaled by the optical replication distribution network and (2) an electrical value provided by an electrical input port;
at least one photodetector that detects at least one light wave from the photovoltaic operation; and
at least one conductive line integrated in the PIC, the conductive line electrically coupled to the photodetector and electrically coupled to an electrical output port.
17. The optoelectronic computing system of claim 16, wherein the EIC further comprises a plurality of digital-to-analog converters (DACs) that provide electrical values to respective electrical output ports, and the electrical input port of the PIC is connected to the electrical output port of the EIC.
18. The optoelectronic computing system of claim 17, wherein the optical splitters are arranged as nodes in a binary tree arrangement connected by optical waveguides that are links in the binary tree arrangement.
19. The optoelectronic computing system of claim 18, wherein the optical replication distribution network includes a plurality of binary tree arrangements, each binary tree arrangement distributing a different one of the plurality of input values encoded on a respective optical signal.
20. The optoelectronic computing system of claim 18, wherein the lengths of light propagation between the roots and different optoelectronic circuit portions of the binary tree arrangement are all different from one another.
21. The optoelectronic computing system of claim 20, wherein the optical waveguides in the optical replica distribution network are arranged in the first semiconductor die to avoid crossing any optical waveguides in the optical replica distribution network.
22. The optoelectronic computing system of claim 21, wherein the optoelectronic circuit portion is arranged in a substantially straight plurality of lines on the first semiconductor die.
23. The optoelectronic computing system of claim 22, wherein each of the plurality of lines are optically coupled to each other by one or more optical waveguides in the light replication distribution network.
24. The optoelectronic computing system of claim 16, wherein a portion of the wires integrated in the PIC connect the photodetector to a junction between wires from different optoelectronic circuit portions.
25. The optoelectronic computing system of claim 16, wherein the optoelectronic operations module comprises a mach-zehnder interferometer configured to perform a multiplication operation between (1) an optical value based on one of the input values scaled by the optical replica distribution network and (2) an electrical value provided by an electrical input port.
26. The optoelectronic computing system of claim 16, wherein the EIC further comprises a transimpedance amplifier having an input electrically coupled to an electrical output port of the PIC.
27. An optoelectronic computing system, comprising:
a first semiconductor die comprising a Photonic Integrated Circuit (PIC), the PIC comprising:
a plurality of optical waveguides, wherein a set of a plurality of input values are encoded on respective optical signals carried by the optical waveguides;
an optical replica distribution network comprising a plurality of optical splitters, wherein each optical splitter is configured to transmit a portion of the power of an input optical wave at an input port to each of two output ports, and each of the output ports of the optical replica distribution network provides a portion of the input optical wave carrying an optical signal encoding one of the input values scaled by the same scale; and
An array of optoelectronic circuit portions, each optoelectronic circuit portion receiving an optical wave from one of the output ports of the optical replica distribution network, and each optoelectronic circuit portion comprising:
at least one photodetector that detects at least one light wave from the photo-electric operation; and
at least one conductive line integrated in the PIC, the conductive line electrically coupled to the photodetector and electrically coupled to an electrical output port; and
a second semiconductor die comprising an Electronic Integrated Circuit (EIC), the EIC comprising:
a plurality of electrical input ports that receive respective electrical values;
wherein the first semiconductor die and the second semiconductor die are electrically coupled in a controlled collapse chip connection, wherein the electrical output port of the PIC is connected to one of the electrical input ports of the EIC.
28. The optoelectronic computing system as set forth in claim 27, wherein each optoelectronic circuit portion includes:
an opto-electronic operational module that performs operations between (1) an optical value based on one of the input values scaled by the optical replication distribution network and (2) an electrical value provided by an electrical input port;
at least one photodetector that detects at least one light wave from the photovoltaic operation; and
At least one conductive line integrated in the PIC, the conductive line electrically coupled to the photodetector and electrically coupled to an electrical output port.
29. The optoelectronic computing system of claim 28, wherein the EIC further comprises a plurality of digital-to-analog converters (DACs) providing electrical values to respective electrical output ports, and the electrical input port of the PIC is connected to the electrical output port of the EIC.
30. An optoelectronic computing system according to claim 29, wherein the plurality of optical splitters are configured to transmit half of the power of an input optical wave at an input port to each of two output ports, and the optical splitters are arranged as nodes in a binary tree arrangement connected by optical waveguides as links in the binary tree arrangement.
31. The optoelectronic computing system of claim 30, wherein the optical replica distribution network comprises a plurality of binary tree arrangements, each binary tree arrangement distributing a different one of the plurality of input values encoded on a respective optical signal, and the proportion by which respective input values are scaled in different binary tree arrangements is the same.
32. The optoelectronic computing system of claim 30, wherein the lengths of light propagation between the roots of the binary tree arrangement and different optoelectronic circuit portions are all different from one another.
33. The optoelectronic computing system of claim 32, wherein the optical waveguides in the optical replica distribution network are arranged in the first semiconductor die to avoid crossing any optical waveguides in the optical replica distribution network.
34. The optoelectronic computing system of claim 33, wherein the optoelectronic circuit portion is arranged in a substantially straight plurality of lines on the first semiconductor die.
35. The optoelectronic computing system of claim 34, wherein the plurality of lines are optically coupled to each other by one or more optical waveguides in the optical replication distribution network.
36. The optoelectronic computing system of claim 28, wherein a portion of the wires integrated in the PIC connect the photodetector to a junction between wires from different optoelectronic circuit portions.
37. The optoelectronic computing system of claim 28, wherein the optoelectronic operations module comprises a mach-zehnder interferometer configured to perform a multiplication operation between (1) an optical value based on one of the input values scaled by the optical replica distribution network and (2) an electrical value provided by an electrical input port.
38. The optoelectronic computing system of claim 28, wherein the EIC further comprises a transimpedance amplifier having an input electrically coupled to an electrical output port of the PIC.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201962820562P | 2019-03-19 | 2019-03-19 | |
| US62/820,562 | 2019-03-19 | ||
| US16/703,278 US11507818B2 (en) | 2018-06-05 | 2019-12-04 | Optoelectronic computing systems |
| US16/703,278 | 2019-12-04 | ||
| PCT/US2020/023674 WO2020191217A1 (en) | 2019-03-19 | 2020-03-19 | Optoelectronic computing systems |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112912900A true CN112912900A (en) | 2021-06-04 |
Family
ID=72521231
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202080005363.8A Pending CN112912900A (en) | 2019-03-19 | 2020-03-19 | Photoelectric computing system |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP3942482A4 (en) |
| CN (1) | CN112912900A (en) |
| TW (2) | TWI741533B (en) |
| WO (1) | WO2020191217A1 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| TW202201165A (en) | 2022-01-01 |
| TWI819368B (en) | 2023-10-21 |
| WO2020191217A1 (en) | 2020-09-24 |
| TWI741533B (en) | 2021-10-01 |
| EP3942482A4 (en) | 2022-12-28 |
| TW202103063A (en) | 2021-01-16 |
| EP3942482A1 (en) | 2022-01-26 |
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