CN112909170A - MIM capacitor and method for manufacturing the same - Google Patents
MIM capacitor and method for manufacturing the same Download PDFInfo
- Publication number
- CN112909170A CN112909170A CN202110209085.4A CN202110209085A CN112909170A CN 112909170 A CN112909170 A CN 112909170A CN 202110209085 A CN202110209085 A CN 202110209085A CN 112909170 A CN112909170 A CN 112909170A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- layer
- mim capacitor
- metal
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 107
- 238000000034 method Methods 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 150
- 239000002184 metal Substances 0.000 claims abstract description 150
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000005530 etching Methods 0.000 claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 239000000463 material Substances 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 229910052755 nonmetal Inorganic materials 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 230000003667 anti-reflective effect Effects 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 10
- 238000001259 photo etching Methods 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 263
- 238000000206 photolithography Methods 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides an MIM capacitor and a manufacturing method thereof, which are applied to the technical field of semiconductors. The invention provides a manufacturing method of an MIM capacitor, which divides a dielectric layer of the MIM capacitor in the prior art into two layers (a first dielectric layer and a second dielectric layer) by a layer of structure, so that the first dielectric layer positioned on the surface of the first metal layer can be used as an etching stop layer of the MIM capacitor etching process in the process of etching the second metal layer and the second dielectric layer to form the MIM capacitor, thereby ensuring the integrity of the first metal layer, ensuring the flatness of the surface of the dielectric layer covered on the surface of the first metal layer and avoiding the problem of photoresist coated on the edge of a substrate in the subsequent photoetching process.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a metal-insulator-metal (MIM) capacitor and a method for manufacturing the same.
Background
In the manufacture of semiconductor integrated circuits, MIM (Metal-Insulator-Metal) capacitors are integrated in Metal interconnects in the back-end, which can reduce chip area and parasitic capacitance, and gradually replace poly-Insulator-poly (PIP) capacitors and Metal-oxide-silicon (MOS) capacitors, and thus are widely used in memories, radio frequency and analog/mixed signal integrated circuits.
In the prior art, the structure of the MIM capacitor is a sandwich structure consisting of three thin films, namely a metal film, an insulator film and a metal film, and the specific formation of the MIM capacitor includes the following steps: providing a substrate; forming a first metal layer on the substrate; forming a dielectric layer of a material, such as silicon nitride, on the first metal layer; a second metal layer, such as a titanium layer, is formed over the capacitor dielectric layer. And the first metal layer and the second metal layer are respectively used as a lower polar plate and an upper polar plate of the formed MIM capacitor. And etching the second metal layer and the dielectric layer of the upper electrode plate by adopting a photoetching process so as to form the MIM capacitor in a partial area of the substrate. However, in the prior art, in order to protect the first metal layer as the lower plate from being etched in the etching process of the second metal layer and the dielectric layer, it is necessary that the dielectric layer with the remaining thickness is on the surface of the first metal layer in the etching process of the second metal layer and the dielectric layer.
However, due to the characteristics of the etching process, the dielectric layer remaining on the surface of the first metal layer after the second metal layer and a part of the dielectric layer are dry-etched has a problem of inconsistent thickness, for example, the thickness of the dielectric layer on the surface of the edge region of the first metal layer (or the substrate) is greater than the thickness of the dielectric layer covering the surface of the central region thereof, and thus, in the subsequent photolithography process, the photoresist coated on the edge of the substrate is separated. In addition, the dielectric layer with a thicker thickness on the surface of the edge region of the substrate can cause a higher optical effect, thereby increasing the risk of failure of the edge pattern of the wafer and reducing the product yield of the MIM capacitor.
Disclosure of Invention
The invention aims to provide an MIM capacitor and a manufacturing method thereof, which aim to solve the problem that the product yield of the MIM capacitor is reduced due to inconsistent thickness of a dielectric layer remained on the surface of a first metal layer in the prior art.
In order to solve the above technical problem, the present invention provides a method for manufacturing an MIM capacitor, including:
providing a semiconductor substrate with a capacitance area and a non-capacitance area, and at least forming a first metal layer to cover the capacitance area;
forming a first dielectric layer, wherein the first dielectric layer covers the surface of the first metal layer of the capacitor area, extends to cover the non-capacitor area, and has a flat top surface;
sequentially forming a second dielectric layer and a second metal layer on the surface of the first dielectric layer;
and taking the first dielectric layer as an etching stop layer, sequentially etching and removing the second metal layer and the second dielectric layer on the non-capacitance region, and forming at least one MIM capacitor on the capacitance region, wherein the MIM capacitor comprises the first metal layer, the first dielectric layer, the second dielectric layer and the second metal layer which are sequentially stacked from bottom to top.
Optionally, the thickness of the first dielectric layer is less than
The thickness of the second dielectric layer is less than
Optionally, the material of the first dielectric layer may include a dielectric antireflection material containing at least one element of nitrogen, silicon, oxygen, and carbon.
Alternatively, the first dielectric layer may be formed using a chemical vapor deposition process or a spin-on process or a physical vapor deposition process.
Optionally, the material of the second dielectric layer may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.
Optionally, after forming the first dielectric layer and before forming the second dielectric layer, the method may further include:
and carrying out planarization treatment on the upper surface of the first dielectric layer.
Optionally, the first metal layer and the second metal layer comprise at least one of a metal, a conductive metal oxide, a conductive metal nitride, a conductive metal carbide, and a conductive nonmetal.
Optionally, the metal is one or more of copper, aluminum and titanium, and the nonmetal includes at least one of silicon, germanium and carbon.
Optionally, the second metal layer and the second dielectric layer may be etched by a dry etching process.
Based on the manufacturing method of the MIM capacitor, the present invention also provides an MIM capacitor, including:
a semiconductor substrate including a capacitive region and a non-capacitive region;
the first metal layer is at least positioned on the surface of the semiconductor substrate of the capacitance area and is used as a lower polar plate of the MIM capacitor;
the first dielectric layer is at least positioned on the surface of the first metal layer of the capacitor area;
the second dielectric layer is positioned on the surface of the first metal layer in the capacitance area and forms a dielectric layer of the MIM capacitor together with the first dielectric layer;
and the second metal layer is positioned on the surface of the second dielectric layer and is used as an upper polar plate of the MIM capacitor.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
the invention provides a manufacturing method of an MIM capacitor, which divides a dielectric layer of the MIM capacitor in the prior art into two layers (a first dielectric layer and a second dielectric layer) by a layer of structure, so that the first dielectric layer positioned on the surface of the first metal layer can be used as an etching stop layer of the MIM capacitor etching process in the process of etching a second metal layer and the second dielectric layer to form the MIM capacitor, thereby ensuring the integrity of the first metal layer, ensuring the flatness of the surface of the dielectric layer covered on the surface of the first metal layer and avoiding the problem of photoresist coated on the edge of a semiconductor substrate in the subsequent photoetching process.
Furthermore, because the laminated structure formed by the first dielectric layer and the second dielectric layer is used as the dielectric layer of the MIM capacitor, the capacitance value of the MIM capacitor can be adjusted by respectively adjusting the thicknesses of the first dielectric layer and the second dielectric layer, and the thickness of the first dielectric layer is reduced while the capacitance value of the MIM capacitor meets the design requirement, so that the problem that the exposure and development of photoresist coated on the first dielectric layer are insufficient to cause the failure risk of a semiconductor substrate graph in the subsequent photoetching process due to the thicker thickness of the first dielectric layer is avoided, the reliability of the whole device is improved, and the yield of products is ensured.
Drawings
FIG. 1 is a schematic diagram of a prior art MIM capacitor;
fig. 2 is a schematic flow chart illustrating a method for fabricating a MIM capacitor according to an embodiment of the present invention;
fig. 3a to 3c are schematic structural diagrams of a manufacturing method of an MIM capacitor according to an embodiment of the present invention during a manufacturing process thereof.
Wherein the reference numbers are as follows:
100-a semiconductor substrate; 110 — a first metal layer;
120/120' -dielectric layer; 130-a second metal layer;
140-an antireflective dielectric layer; 200-a semiconductor substrate;
210-a first metal layer; 220-a first dielectric layer;
230-a second dielectric layer; 240-a second metal layer;
A-MIM capacitance; 211 — a first metal layer;
212-second metal layer.
Detailed Description
As described in the background, in the conventional method for forming the MIM capacitor, the substrate 100 is first provided; forming a first metal layer 110 on the substrate 100; forming a dielectric layer 120 made of silicon oxide or silicon nitride on the first metal layer 110; a second metal layer 130, such as a titanium nitride layer, is formed on the dielectric layer 120. The first metal layer 110 and the second metal layer 130 then serve as the lower plate and the upper plate, respectively, of the formed MIM capacitor. Then, the second metal layer 130 and the dielectric layer 120 of the upper plate are etched by using a photolithography etching process to form the MIM capacitor in a partial region of the substrate 100. However, in the prior art, in order to protect the first metal layer 110 as the bottom plate from being etched during the etching process of the second metal layer 130 and the dielectric layer 120, it is necessary that the dielectric layer 120' with the remaining thickness is on the surface of the first metal layer 110 during the etching process of the second metal layer 130 and the dielectric layer 120, as shown in fig. 1.
However, due to the characteristics of the etching process, the dielectric layer 120 ' remaining on the surface of the first metal layer 110 after the second metal layer 130 and a portion of the dielectric layer 120 are dry-etched has a problem of inconsistent thickness, for example, the thickness of the dielectric layer 120 ' on the surface of the edge region of the first metal layer 110 (or the substrate 100) is greater than the thickness of the dielectric layer 120 ' covering the surface of the center region thereof, and thus the photoresist coated on the edge of the substrate 100 is separated in the subsequent photolithography process. Moreover, the thicker dielectric layer 120' on the surface of the edge region of the substrate 100 may cause a higher optical effect, thereby increasing the risk of wafer edge pattern failure and reducing the product yield of the MIM capacitor.
Therefore, the invention provides an MIM capacitor and a manufacturing method thereof, which aim to solve the problem that the product yield of the MIM capacitor is reduced due to inconsistent thickness of a dielectric layer remained on the surface of a first metal layer in the prior art.
Referring to fig. 2, fig. 2 is a schematic flow chart illustrating a method for fabricating a MIM capacitor according to an embodiment of the present invention; the manufacturing method of the MIM capacitor can comprise the following steps:
step S100, providing a semiconductor substrate with a capacitance area and a non-capacitance area, and forming at least a first metal layer to cover the capacitance area;
step S200, forming a first dielectric layer, wherein the first dielectric layer covers the surface of the first metal layer of the capacitor region, extends to cover the non-capacitor region, and has a flat top surface;
step S300, forming a second dielectric layer and a second metal layer on the surface of the first dielectric layer in sequence;
and step S400, taking the first dielectric layer as an etching stop layer, sequentially etching and removing the second metal layer and the second dielectric layer on the non-capacitance area, and forming at least one MIM capacitor on the capacitance area. The MIM capacitor comprises a first metal layer, a first dielectric layer, a second dielectric layer and a second metal layer which are sequentially stacked from bottom to top.
The dielectric layer of the MIM capacitor in the prior art is divided into two layers (the first dielectric layer and the second dielectric layer) by one layer, so that the first dielectric layer positioned on the surface of the first metal layer can be used as an etching stop layer of the MIM capacitor etching process in the process of etching the second metal layer and the second dielectric layer to form the MIM capacitor, the integrity of the first metal layer is ensured, the flatness of the surface of the dielectric layer covering the surface of the first metal layer is ensured, and the problem that photoresist coated on the edge of a semiconductor substrate is separated in the subsequent photoetching process is avoided.
The following describes the manufacturing method of the MIM capacitor according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 3a to 3c are schematic structural diagrams of a manufacturing method of an MIM capacitor according to an embodiment of the present invention during a manufacturing process thereof.
In step S100, referring to fig. 3a specifically, a semiconductor substrate 200 is provided, where the semiconductor substrate 200 includes a capacitor region 201 and a non-capacitor region 202, and at least a first metal layer 210 is formed to cover the capacitor region 201. Illustratively, in fig. 3 provided in the embodiment of the present invention, the first metal layer 210 is formed on the entire surface of the semiconductor substrate including the capacitor region 201 and the non-capacitor region 202, it is to be understood that, in other embodiments, the first metal layer 210 may also be formed only on the surface of the semiconductor substrate 200 corresponding to the capacitor region 201, and the present invention is not limited to this specifically. In the following embodiments of the present invention, the method for manufacturing the MIM capacitor according to the present invention will be described by taking the example of forming the first metal layer 210 on the entire surface of the semiconductor substrate 200.
The material of the semiconductor substrate 200 may be a material known to those skilled in the art, such as silicon, silicon germanium, silicon carbide, etc. Illustratively, the semiconductor substrate 200 in the embodiment of the present invention is a silicon substrate. The semiconductor substrate 200 may have a MOS transistor, a metal interconnection structure, and the like formed therein. When a metal interconnection structure is formed in the semiconductor substrate 200, the metal interconnection structure may include a plurality of copper interconnection metal wiring layers, a metal interconnection layer of tantalum, titanium nitride, or the like. In addition, the metal interconnection layers of copper, tantalum, titanium nitride and the like in the metal interconnection structure can be used as metal layer materials of an upper electrode plate and a lower electrode plate of the MIM capacitor.
In this embodiment, a metal layer having a single-layer structure or a multi-layer composite structure may be separately formed on the surface of the semiconductor substrate 200 having the MOS transistor formed therein as a lower plate of the MIM capacitor. When the lower plate of the MIM capacitor is of a double-layer structure, in the prior art, when the lower plate of the MIM capacitor is of a double-layer structure, a metal layer in the lower plate, which is directly adjacent to the dielectric layer, and the dielectric layer both contain nitrides, so that when the MIM capacitor is formed by etching the dielectric layer and the metal layer of the lower plate by a dry method, the dielectric layer cannot be completely etched by the dry etching without affecting the integrity of the first metal layer located below the dielectric layer, thereby causing the technical problems as described in the background art. Therefore, based on this problem, the present inventors have studied the technical means described in the present invention.
It is understood that, when the lower plate of the MIM capacitor is a single-layer structure, as long as the single-layer metal layer serving as the lower plate and the dielectric layer located thereon both contain nitride, the technical problem to be solved by the present invention also exists, and the present invention is not particularly limited thereto.
Illustratively, the present invention employs a metal layer (first metal layer 210) having a double-layer structure as a lower plate of the MIM capacitor. The first metal layer 210 may include a first metal layer 211 and a second metal layer 212. The material of the first metal layer 211 may include at least one of a metal, a conductive metal oxide, a conductive metal nitride, a conductive metal carbide, and a conductive nonmetal. The material of the second metal layer 212 at least includes metal nitride. Wherein the metal may be one or more of copper, aluminum and titanium.
In step S200, referring to fig. 3b specifically, a first dielectric layer 220 is formed, the first dielectric layer 220 covers the surface of the first metal layer 210 of the capacitor region 201 and extends to cover the surface of the first metal layer 210 of the non-capacitor region 202, and the top surface of the first dielectric layer 220 is flat.
The first dielectric layer material may include a dielectric antireflection material, the dielectric antireflection material may include at least one element selected from nitrogen, silicon, oxygen, and carbon, and the formation process may be a chemical vapor deposition process, a spin coating process, or a physical vapor deposition process.
In this embodiment, after the first dielectric layer 210 is formed on the surface of the first metal layer 210, the flatness of the upper surface of the first dielectric layer 210 can be ensured by performing planarization treatment on the upper surface of the first dielectric layer 210, so as to avoid the problem of separation of the photoresist coated on the edge of the semiconductor substrate in the subsequent photolithography process.
In step S300, with continued reference to fig. 3b, a second dielectric layer 230 and a second metal layer 240 are sequentially formed.
Wherein the material of the second dielectric layer 230 may include silicon nitride, silicon oxide and silicon oxynitrideAnd the thickness of the first dielectric layer 220 may be less than
The thickness of the second dielectric layer 230 may be less than
In this embodiment, the second dielectric layer 230 and the second metal layer 240 may be formed on the entire surface of the first dielectric layer 220, and then, the second dielectric layer 230 and the second metal layer 240 are etched by using an etching process, so as to remove all of the second dielectric layer 230 and the second metal layer 240 on the surface of the first dielectric layer 210 in the non-capacitance region 202 while forming at least one MIM capacitor structure in the capacitance region.
In other embodiments, the non-capacitance region 202 may be shielded, and then a second dielectric layer 230 and a second metal layer 240 are formed on the surface of the first dielectric layer 220 of the capacitance region 201, and then the second dielectric layer 230 and the second metal layer 240 in the capacitance region 201 are etched in the following step S400, so as to form at least one MIM capacitance structure in the capacitance region.
Alternatively, the first metal layer 210 and the second metal layer 220 may include at least one of a metal, a conductive metal oxide, a conductive metal nitride, a conductive metal carbide, and a conductive nonmetal.
In step S400, referring to fig. 3c specifically, with the first dielectric layer 220 as an etching stop layer, the second metal layer 240 and the second dielectric layer 230 on the non-capacitance region 202 are sequentially etched and removed, and at least one MIM capacitor a is formed on the capacitance region 201. The MIM capacitor a includes a first metal layer 210, a first dielectric layer 220, a second dielectric layer 230, and a second metal layer 240 stacked in sequence from bottom to top.
In this embodiment, a dry etching process may be used to etch the second metal layer 240 and the second dielectric layer 230 to the first dielectric layer 220. In the manufacturing method of the MIM capacitor provided by the invention, the dielectric layer of the MIM capacitor in the prior art is divided into two layers (the first dielectric layer 220 and the second dielectric layer 230) by one layer, so that the first dielectric layer 220 positioned on the surface of the first metal layer 210 can be used as an etching stop layer of the MIM capacitor etching process in the process of etching the second metal layer 240 and the second dielectric layer 230 to form the MIM capacitor, the integrity of the first metal layer 210 is protected, the flatness of the surface of the dielectric layer covered on the surface of the first metal layer 210 is ensured, and the problem that photoresist coated on the edge of a semiconductor substrate is separated in the subsequent photoetching process is avoided.
In addition, the present invention provides a MIM capacitor manufactured based on the MIM capacitor manufacturing method as described above, including:
a semiconductor substrate 200, wherein the semiconductor substrate 200 comprises a capacitance region 201 and a non-capacitance region 202;
a first metal layer 210 at least on the surface of the semiconductor substrate 200 and serving as a lower plate of the MIM capacitor;
a first dielectric layer 220 at least on the surface of the first metal layer 210;
a second dielectric layer 230 located on the surface of the first metal layer 210 in the capacitance region 201 and forming a dielectric layer of the MIM capacitor with the first dielectric layer 220;
and a second metal layer 240 on the surface of the second dielectric layer 230 and serving as an upper plate of the MIM capacitor.
In summary, the present invention provides a method for manufacturing an MIM capacitor, in which a dielectric layer of the MIM capacitor in the prior art is divided into two layers (a first dielectric layer and a second dielectric layer) by a layer of structure, so that in a process of forming the MIM capacitor by performing an etching process on a second metal layer and a second dielectric layer, the first dielectric layer on the surface of the first metal layer can be used as an etching stop layer of the MIM capacitor etching process, thereby protecting the integrity of the first metal layer, ensuring the flatness of the surface of the dielectric layer covering the surface of the first metal layer, and avoiding the problem of photoresist coated on the edge of the semiconductor substrate being separated in a subsequent photolithography process.
Furthermore, because the laminated structure formed by the first dielectric layer and the second dielectric layer is used as the dielectric layer of the MIM capacitor, the capacitance value of the MIM capacitor can be adjusted by respectively adjusting the thicknesses of the first dielectric layer and the second dielectric layer, and the thickness of the first dielectric layer is reduced while the capacitance value of the MIM capacitor meets the design requirement, so that the problem that the exposure and development of photoresist coated on the first dielectric layer are insufficient to cause the failure risk of a semiconductor substrate graph in the subsequent photoetching process due to the thicker thickness of the first dielectric layer is avoided, the reliability of the whole device is improved, and the yield of products is ensured.
It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.
Claims (10)
1. A method of fabricating a MIM capacitor, comprising:
providing a semiconductor substrate with a capacitance area and a non-capacitance area, and at least forming a first metal layer to cover the capacitance area;
forming a first dielectric layer, wherein the first dielectric layer covers the surface of the first metal layer of the capacitor area, extends to cover the non-capacitor area, and has a flat top surface;
sequentially forming a second dielectric layer and a second metal layer on the surface of the first dielectric layer;
and taking the first dielectric layer as an etching stop layer, sequentially etching and removing the second metal layer and the second dielectric layer on the non-capacitance region, and forming at least one MIM capacitor on the capacitance region, wherein the MIM capacitor comprises the first metal layer, the first dielectric layer, the second dielectric layer and the second metal layer which are sequentially stacked from bottom to top.
2. The method of manufacturing the MIM capacitor according to claim 1 wherein the first dielectric layer has a thickness less than
The thickness of the second dielectric layer is less than
3. The method of claim 1, wherein the material of the first dielectric layer comprises a dielectric antireflective material comprising at least one element selected from the group consisting of nitrogen, silicon, oxygen, and carbon.
4. The method of claim 1, wherein the first dielectric layer is formed using a chemical vapor deposition process or a spin-on process or a physical vapor deposition process.
5. The method of claim 1, wherein the material of the second dielectric layer comprises at least one of silicon nitride, silicon oxide, and silicon oxynitride.
6. The method of fabricating the MIM capacitor according to claim 1 wherein after forming the first dielectric layer and before forming the second dielectric layer, the method further comprises:
and carrying out planarization treatment on the upper surface of the first dielectric layer.
7. The method of manufacturing the MIM capacitor according to claim 1 wherein the first metal layer and the second metal layer comprise at least one of a metal, a conductive metal oxide, a conductive metal nitride, a conductive metal carbide, and a conductive non-metal.
8. The method of claim 7, wherein the metal is one or more of copper, aluminum, and titanium, and the non-metal comprises at least one of silicon, germanium, and carbon.
9. The method of manufacturing the MIM capacitor according to claim 1 wherein the second metal layer and the second dielectric layer are etched using a dry etch process.
10. A MIM capacitor manufactured based on the MIM capacitor manufacturing method according to any one of claims 1 to 9, comprising:
a semiconductor substrate including a capacitive region and a non-capacitive region;
the first metal layer is at least positioned on the surface of the semiconductor substrate of the capacitance area and is used as a lower polar plate of the MIM capacitor;
the first dielectric layer is at least positioned on the surface of the first metal layer of the capacitor area;
the second dielectric layer is positioned on the surface of the first metal layer in the capacitance area and forms a dielectric layer of the MIM capacitor together with the first dielectric layer;
and the second metal layer is positioned on the surface of the second dielectric layer and is used as an upper polar plate of the MIM capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110209085.4A CN112909170A (en) | 2021-02-24 | 2021-02-24 | MIM capacitor and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110209085.4A CN112909170A (en) | 2021-02-24 | 2021-02-24 | MIM capacitor and method for manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112909170A true CN112909170A (en) | 2021-06-04 |
Family
ID=76108147
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110209085.4A Pending CN112909170A (en) | 2021-02-24 | 2021-02-24 | MIM capacitor and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112909170A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115132662A (en) * | 2022-07-06 | 2022-09-30 | 重庆中科渝芯电子有限公司 | Optimization integration method for simulating high-stress edge effect in BiCMOS (bipolar complementary metal oxide semiconductor) process and high-linearity double-polycrystal capacitor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010010955A1 (en) * | 1999-01-04 | 2001-08-02 | Taiwan Semiconductor Manufacturing Company | High performance MIM (MIP) ic capacitor process |
| CN110931373A (en) * | 2019-12-11 | 2020-03-27 | 武汉新芯集成电路制造有限公司 | Semiconductor device and manufacturing method thereof |
| CN111211092A (en) * | 2018-11-22 | 2020-05-29 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| CN111816607A (en) * | 2019-04-12 | 2020-10-23 | 德克萨斯仪器股份有限公司 | Method for etching metal interconnection layer |
-
2021
- 2021-02-24 CN CN202110209085.4A patent/CN112909170A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010010955A1 (en) * | 1999-01-04 | 2001-08-02 | Taiwan Semiconductor Manufacturing Company | High performance MIM (MIP) ic capacitor process |
| CN111211092A (en) * | 2018-11-22 | 2020-05-29 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| CN111816607A (en) * | 2019-04-12 | 2020-10-23 | 德克萨斯仪器股份有限公司 | Method for etching metal interconnection layer |
| CN110931373A (en) * | 2019-12-11 | 2020-03-27 | 武汉新芯集成电路制造有限公司 | Semiconductor device and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115132662A (en) * | 2022-07-06 | 2022-09-30 | 重庆中科渝芯电子有限公司 | Optimization integration method for simulating high-stress edge effect in BiCMOS (bipolar complementary metal oxide semiconductor) process and high-linearity double-polycrystal capacitor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6977198B2 (en) | Metal-insulator-metal (MIM) capacitor and fabrication method for making the same | |
| US9865582B2 (en) | Integrated thinfilm resistor and MIM capacitor with a low serial resistance | |
| KR970013366A (en) | Method for manufacturing semiconductor integrated circuit device | |
| US7602599B1 (en) | Metal-metal capacitor and method of making the same | |
| US7592220B2 (en) | Capacitance process using passivation film scheme | |
| US6319767B1 (en) | Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique | |
| US7557003B2 (en) | MIM capacitor manufacturing method | |
| US20070235788A1 (en) | Poly-Insulator-Poly Capacitor and Fabrication Method for Making the Same | |
| US7595525B2 (en) | Integrated circuit capacitor having antireflective dielectric | |
| US7508023B2 (en) | Capacitor structure and fabricating method thereof | |
| US20040014331A1 (en) | Semiconductor device with capacitor and process for manufacturing the device | |
| CN112909170A (en) | MIM capacitor and method for manufacturing the same | |
| US7544580B2 (en) | Method for manufacturing passive components | |
| JPH11145387A (en) | Semiconductor device and manufacture thereof | |
| US20020182794A1 (en) | Method of making stacked MIMCap between Cu dual-damascene levels | |
| JP3820003B2 (en) | Thin film capacitor manufacturing method | |
| US7745343B1 (en) | Method for fabricating semiconductor device with fuse element | |
| US7713816B2 (en) | Semiconductor device and method for fabricating the same | |
| US20070075395A1 (en) | Capacitor of a semiconductor device | |
| US6503823B1 (en) | Method for manufacturing capacitor elements on a semiconductor substrate | |
| US6809334B2 (en) | Semiconductor integrated circuit device, and method of manufacturing the same | |
| US20030173672A1 (en) | Semiconductor devices and methods for manufacturing the same | |
| JP3221398B2 (en) | Capacitive element and method of manufacturing the same | |
| US6610603B2 (en) | Method of manufacturing a capacitor | |
| US20120211866A1 (en) | Metal-insulator-metal capacitor and a method of fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |