CN112908940A

CN112908940A - Embedded substrate

Info

Publication number: CN112908940A
Application number: CN202110014492.XA
Authority: CN
Inventors: 吕文隆
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2021-01-06
Filing date: 2021-01-06
Publication date: 2021-06-04

Abstract

The present invention provides an embedded substrate, comprising: a wafer located in a dielectric material of a buried substrate; and a thermoelectric generator disposed beside the wafer in the dielectric material, the p-type electrode and the n-type electrode of the thermoelectric generator being connected in series. The embedded substrate provided by the invention improves the heat dissipation of the embedded substrate.

Description

Embedded substrate

Technical Field

Embodiments of the present invention relate to a buried substrate.

Background

Embedded chip components are widely used in the semiconductor field, and the variety of chips is various. The heat dissipation problem is particularly important when high heat generating chips are embedded. For the chip embedded in the substrate, the heat source is conducted in the direction of metal, and the current technical scheme cannot effectively solve the heat extraction problem of the functional chip.

Disclosure of Invention

In view of the problems in the related art, an object of the present invention is to provide an embedded substrate to improve heat dissipation of the embedded substrate.

To achieve the above object, the present invention provides a buried substrate comprising: a wafer located in a dielectric material of a buried substrate; and a thermoelectric generator disposed beside the wafer in the dielectric material, the p-type electrode and the n-type electrode of the thermoelectric generator being connected in series.

In an embodiment, further comprising: a first line structure over the wafer and the thermoelectric generator, the first line structure including a pad on a surface of the buried substrate and a first via through the dielectric material to electrically connect the thermoelectric generator to the pad.

In an embodiment, the thermoelectric generator includes a second via extending in a lateral direction, the lateral direction being a direction in which the p-type electrode and the n-type electrode extend, the first via contacting the second via.

In an embodiment, the second through hole is a portion of a cylinder extending in a transverse direction, a top surface of the portion being parallel to a generatrix of the cylinder, the first through hole being in contact with the top surface and perpendicular to the top surface.

In an embodiment, a ratio of a maximum thickness of the second via hole to a maximum width of the second via hole, which is a diameter of the cylinder and is in a range of 5 μm to 20 μm, is in a range of 1/3 to 1/2 in a cross section perpendicular to the lateral direction.

In an embodiment, the diameter of the first via hole becomes smaller from the pad to the thermoelectric generator.

In an embodiment, a plurality of thermoelectric generators are arranged around the wafer, as viewed from the top view.

In an embodiment, the thermoelectric generator includes a plurality of p-type electrodes and a plurality of n-type electrodes, the plurality of p-type electrodes being located under the plurality of n-type electrodes in a one-to-one correspondence.

In an embodiment, the top surface of the hot spot generator is higher than the top surface of the wafer.

In an embodiment, the outermost p-type and n-type electrodes of the thermoelectric generator are connected to a metal plate on the side remote from the wafer.

Drawings

Fig. 1 to 9 are sectional views showing an intermediate process of forming a line structure according to an embodiment of the present application.

Fig. 10 to 20 are sectional views illustrating an intermediate process of forming a TEG according to an embodiment of the present application.

Fig. 21 to 38 are sectional views showing an intermediate process of forming a buried substrate according to an embodiment of the present application.

Fig. 39-50 show structural schematics of a buried substrate according to various embodiments of the present application.

Detailed Description

In order to better understand the spirit of the embodiments of the present application, the following further description is given in conjunction with some preferred embodiments of the present application.

Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.

As used herein, the terms "substantially", "substantially" and "about" are used to describe and illustrate minor variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation that is less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are considered to be "substantially" identical if the difference between the two numerical values is less than or equal to ± 10% (e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%) of the mean of the values.

In this specification, unless specified or limited otherwise, relative terms such as: terms of "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing figures. These relative terms are for convenience of description only and do not require that the present application be constructed or operated in a particular orientation.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.

Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.

In the design of the substrate, the thermal non-uniformity between the thermal effect region and the non-thermal effect region is prone to warp problems and crack problems from warping. In the invention, the thermal point generator (TEG) is arranged in the embedded chip structure, the TEG generates a temperature difference by electric energy, and the position close to the embedded chip is a low-temperature position, so that the heat generated by the chip can be conducted to the TEG from two sides. The thermoelectric generator (TEG) of the present application addresses heat dissipation by converting thermal energy to electrical energy, thereby providing a heat transfer effect (instead of a heat sink).

The embedded substrate of the present application is explained in detail below with reference to the drawings.

Referring to fig. 1, a first seed layer 12 is formed on a carrier 10. In an embodiment, the first seed layer 12 may be formed by a Physical Vapor Deposition (PVD) process.

Referring to fig. 2, a first mask layer 20 is formed on the first seed layer 12, the first mask layer 20 may include a Photoresist (PR) material, and an exposure process 21 is performed to cure the first mask layer 20.

Referring to fig. 3, the first mask layer 20 is patterned and a first metal layer 30 is formed in the patterned first mask layer 20.

Referring to fig. 4, the patterned first mask layer 20 is removed, and the first seed layer 20 is etched using the first metal layer 30 as a mask so that the first seed layer 20 has the same pattern as the first metal layer 30.

Referring to fig. 5, a first dielectric layer 50 is formed overlying the first metal layer 30 and the first seed layer 20. In an embodiment, the first dielectric layer 50 may include a Polyamide (PA) material, and the first dielectric layer 50 is subjected to an exposure process 51 for curing.

Referring to fig. 6, an opening is formed in the first dielectric layer to expose the first metal layer 30, and a second seed layer 60 is formed in the opening and on the first dielectric layer 50.

Referring to fig. 7, a second mask layer 70 is formed on the second seed layer 60. The second mask layer 70 may include a Photoresist (PR) material, and an exposure process 71 is performed to cure the second mask layer 70.

Referring to fig. 8, the second mask layer 70 is patterned to expose the second seed layer 60. And a second metal layer 80 is formed on the exposed second seed layer 60.

Referring to fig. 9, the patterned second mask layer 70 is removed, and the second seed layer 60 is etched using the second metal layer 80 as a mask so that the second seed layer 60 has the same pattern as the second metal layer 80. To form a first line structure 90 on the first carrier 10.

Referring to fig. 10, a first plate 100 is provided. In an embodiment, the first plate 100 includes metallic aluminum.

Referring to fig. 11, a second dielectric layer 110 is formed to cover the first plate 100. In an embodiment, the second dielectric layer 110 may include a Polyamide (PA) material, and the exposure process 111 is performed on the second dielectric layer 110 to cure.

Referring to fig. 12, the second dielectric layer 110 is subjected to a patterning process. So as to form a first opening 121, a second opening 122 and a third opening 123 which are adjacent in sequence. The first thermoelectric material 124 is filled into the first opening 121 using the third mask 120 and the pressing tool 125, wherein the opening of the third mask 120 is aligned with the first opening 121.

Referring to fig. 13, the second thermoelectric material 134 is filled into the second opening 122 using the fourth mask 130 and the pressing tool 125, wherein the opening of the fourth mask 130 is aligned with the second opening 122. In an embodiment, the first thermoelectric material 124 is a P-type material and the second thermoelectric material 125 is an N-type material. In other embodiments, the first thermoelectric material 124 is an N-type material and the second thermoelectric material 125 is a P-type material.

Referring to fig. 14, a third sub-layer 140 is formed in the third opening 123 and on the second dielectric layer 110. In an embodiment, the third sub-layer 140 may be formed by a Physical Vapor Deposition (PVD) process.

Referring to fig. 15, a fifth mask layer 150 is formed on the third sub-layer 140, the fifth mask layer 150 may include a Photoresist (PR) material, and an exposure process 151 is performed to cure the fifth mask layer 150.

Referring to fig. 16, the fifth mask layer 150 is patterned to expose the third sub-layer 140. And a third metal layer 160 is formed on the exposed third sub-layer 140.

Referring to fig. 17, the patterned fifth mask layer 150 is removed, and the third seed layer 140 is etched using the third metal layer 160 as a mask so that the third seed layer 140 has the same pattern as the third metal layer 160. To form a second line structure 170.

Referring to fig. 18, a third dielectric layer 180 is formed overlying the second line structure 170. In an embodiment, the third dielectric layer 180 may include a Polyamide (PA) material, and the exposure process 181 is performed on the third dielectric layer 180 to cure.

Referring to fig. 19, the steps of forming thermoelectric materials in the dielectric layer are repeated to form a plurality of circuit structures similar to the second circuit structure 170, resulting in a thermoelectric generator (TEG) structure 190.

Referring to fig. 20, a cutting process 212 is performed on the TEG structure to obtain a singulated TEG 200. The dicing process 212 exposes the third seed layer 140 and the third metal layer 160 to form the second via 202.

Referring to fig. 21, a second carrier 210 is provided, and a wafer 212 is placed on the second carrier 210 using a chuck 214, with a vacuum between the chuck 214 and the wafer 212 during chucking.

Referring to fig. 22, the TEG200 is placed on the second carrier 210 and beside the wafer 210.

Referring to fig. 23, an encapsulation layer 230 is formed on the wafer 210 and the TEG200, and the first carrier 10 and the first line structure 90 are placed on the wafer 210 and the TEG200 in a flip-chip manner.

Referring to fig. 24, the first circuit structure 90 is bonded to the encapsulation layer 230, removing the first carrier 10. 50 referring to fig. 25, a laser process 250 is performed on the first line structure 90 to form an opening as shown in fig. 26, wherein a portion of the opening exposes the second via 202 of the TEG200, a portion of the opening exposes the wafer pad 262 of the wafer 212, and a portion of the opening exposes the second seed layer 60 of the first line structure 90. A fourth sub-layer 260 is formed in the opening and on the first line structure 90.

Referring to fig. 27, a sixth mask layer 270 is formed on the fourth sub-layer 260, the sixth mask layer 270 may include a Photoresist (PR) material, and an exposure process 271 is performed to cure the sixth mask layer 270.

Referring to fig. 28, the sixth mask layer 270 is patterned to expose the fourth sub-layer 260. And a fourth metal layer 280 is formed on the exposed fourth sub-layer 260.

Referring to fig. 29, the patterned sixth mask layer 270 is removed, and the fourth sub-layer 260 is etched using the fourth metal layer 280 as a mask so that the fourth sub-layer 260 has the same pattern as the fourth metal layer 280 to form the first via 290.

Referring to fig. 30, the second carrier 210 is removed.

Referring to fig. 31, a fifth seed layer 310 is formed on the surface exposed after the second carrier 210 is removed.

Referring to fig. 32, a seventh mask layer 320 is formed on the fifth seed layer 310, the seventh mask layer 320 may include a Photoresist (PR) material, and an exposure process 321 is performed to cure the seventh mask layer 320.

Referring to fig. 33, the seventh mask layer 320 is patterned to expose the fifth seed layer 310. And a fifth metal layer 330 is formed on the exposed fifth seed layer 310.

Referring to fig. 34, the patterned seventh mask layer 320 is removed, and the fifth seed layer 310 is etched using the fifth metal layer 330 as a mask so that the fifth seed layer 310 has the same pattern as the fifth metal layer 330. A fourth dielectric layer 340 is formed overlying the fifth metal layer 330. In an embodiment, the fourth dielectric layer 340 may include a Polyamide (PA) material, and the exposure process 341 is performed on the fourth dielectric layer 340 to cure.

Referring to fig. 35, an opening is formed in the fourth dielectric layer 340 to expose the fifth metal layer 330, and a sixth seed layer 350 is formed in the opening and on the fourth dielectric layer 340.

Referring to fig. 36, an eighth mask layer 360 is formed on the sixth seed layer 350. The eighth mask layer 360 may include a Photoresist (PR) material, and an exposure process 361 is performed to cure the eighth mask layer 360.

Referring to fig. 37, the eighth mask layer 360 is patterned to expose the sixth seed layer 350. And a sixth metal layer 370 is formed on the exposed sixth seed layer 350.

Referring to fig. 38, the patterned eighth mask layer 360 is removed, and the sixth seed layer 350 is etched using the sixth metal layer 370 as a mask so that the sixth seed layer 350 has the same pattern as the sixth metal layer 370. The buried substrate 3800 of the embodiments of the present application is ultimately formed. In an embodiment, the total thickness of the buried substrate 3800 is less than 100 μm.

Referring to fig. 39, in contrast to the buried substrate 3800 shown in fig. 38, the sub-substrate 390 is also included beneath the TEG200 of the buried substrate 3900.

Referring to fig. 40, compared to fig. 38, the TEG200 in the buried substrate 3800 shown in fig. 38 includes a single cell, and the TEG200 of the buried substrate 4000 includes a plurality of cells.

Referring to fig. 41, the buried substrate 4100 connects the wafer 212 and the first line layer 90 using bumps 410. In an embodiment, the bumps 410 comprise micro bumps or solder.

Referring to fig. 42, the buried substrate 4200 also electrically connects the first via 290 and the TEG200 using a wire 420.

Referring to the top view shown in fig. 43A-43B, wherein, in the embodiment shown in fig. 43A, the TEG200 is a block structure disposed around the wafer 212. In the embodiment shown in FIG. 43B, the TEG200 is a ring-like structure surrounding the wafer 212. Among them, the encapsulation layer 230 may include an organic dielectric, for example, bismaleimide triazine resin (BT), Ajinomotobuild-up film (ABF), polyimide (polyimide, PI), a photosensitive epoxy resin and/or a non-photosensitive liquid and/or a dry film including a fiber; a dielectric comprising fibers; inorganic substances, such as oxides (SiOx, SiNx, TaOx), glass, silicon, ceramic materials, and the like.

Referring to fig. 44, the buried substrate 4400 includes the chip 212 placed laterally.

Referring to fig. 45, a buried substrate 4500 includes a plurality of chips 212.

Referring to fig. 46, a buried substrate 4600 includes a plurality of TEGs 200 side by side.

The present invention provides an embedded substrate 3800, referring to fig. 38, including: a wafer 212 located in the dielectric material (encapsulation layer 230) of the buried substrate 3800; thermoelectric generator 200, disposed beside wafer 212 in a dielectric material, p-type and n-type electrodes of thermoelectric generator 200 are connected in series. Referring to fig. 47, an enlarged view of the electrodes of the TEG200 is shown, wherein the p-type electrode is formed from the first thermoelectric material 124 and the n-type electrode is formed from the second thermoelectric material 125. In an embodiment, the thermoelectric generator 200 includes a plurality of p-type electrodes and a plurality of n-type electrodes, the plurality of p-type electrodes being located under the plurality of n-type electrodes in a one-to-one correspondence. In an embodiment, the outermost p-type and n-type electrodes of the thermoelectric generator are connected to a metal plate (first plate 100) on the side away from the wafer. Wherein the arrangement of the p-type electrodes and the n-type electrodes in the TEG200 is connected in series. Wherein the heat generates electrical energy through the plurality of p-type electrodes and the plurality of n-type electrodes.

In an embodiment, further comprising: a first line structure 90 over the wafer 212 and thermoelectric generator 200, the first line structure 90 including a pad 291 (portions of the fourth sub-layer 260 and the fourth metal layer 280 exposed on the upper surface of the line layer 90) on the surface of the buried substrate, and a first via 290 passing through the dielectric material to electrically connect the thermoelectric generator to the pad.

In an embodiment, referring to fig. 48, the thermoelectric generator 200 includes a second through hole 202 extending in a lateral direction, which is a direction in which the p-type electrode and the n-type electrode extend, and the first through hole 290 contacts the second through hole 202.

In an embodiment, referring to fig. 49, the second through hole 202 is a portion of a cylinder extending in a lateral direction, a top surface of the portion is parallel to a generatrix of the cylinder, and the first through hole 290 is in contact with and perpendicular to the top surface. In the embodiment, in the cross section perpendicular to the lateral direction, the ratio of the maximum thickness 202t of the second via 202 to the maximum width of the second via 202 is in the range between 1/3 and 1/2, the maximum width being the diameter D of the cylinder and being in the range of 5 μm to 20 μm. In an embodiment, the diameter of the first via 290 becomes smaller from the pad to the thermoelectric generator 200. In an embodiment, the diameter 290d of the bottom portion of the first via 290 is in the range of 5 μm to 200 μm.

In an embodiment, the top surface of the thermoelectric generator 200 is higher than the top surface of the wafer 212. In an embodiment, a plurality of thermoelectric generators 200 are disposed around the wafer 212, as viewed from the top view. Referring to fig. 50, a plurality of TEGs 200, a chip 212, a substrate body 500, and a via structure in the substrate body 500 are included. Several organic materials are used for the substrate body 500, the encapsulation layer 230, such as ABF, PI, BT, resin and/or epoxy, etc.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A buried substrate, comprising:

a wafer located in a dielectric material of the buried substrate;

a thermoelectric generator disposed in the dielectric material beside the wafer, a p-type electrode and an n-type electrode of the thermoelectric generator being connected in series.

2. The embedded substrate of claim 1, further comprising:

a first line structure over the wafer and the thermoelectric generator, the first line structure including a pad at a surface of the buried substrate and a first via through the dielectric material to electrically connect the thermoelectric generator to the pad.

3. The buried substrate of claim 2, wherein the thermoelectric generator includes a second via extending in a lateral direction, the lateral direction being a direction in which the p-type electrode and the n-type electrode extend, the first via contacting the second via.

4. The buried substrate of claim 3, wherein the second via is a portion of a cylinder extending in the lateral direction, a top surface of the portion being parallel to a generatrix of the cylinder, the first via being in contact with the top surface and perpendicular to the top surface.

5. The buried substrate of claim 4, wherein, in a cross section perpendicular to the lateral direction, a ratio of a maximum thickness of the second via to a maximum width of the second via, which is a diameter of the cylinder and is in a range of 5 μm to 20 μm, is in a range of 1/3 to 1/2.

6. The buried substrate of claim 2, wherein a diameter of the first via becomes smaller from the pad to the thermoelectric generator.

7. The buried substrate of claim 1, wherein a plurality of the thermoelectric generators are disposed around the wafer as viewed from a top view.

8. The buried substrate of claim 1, wherein the thermoelectric generator comprises a plurality of the p-type electrodes and a plurality of the n-type electrodes, the plurality of p-type electrodes being located under the plurality of n-type electrodes in a one-to-one correspondence.

9. The buried substrate of claim 1, wherein a top surface of the hot spot generator is higher than a top surface of the wafer.

10. The buried substrate of claim 1, wherein the p-type electrode and the n-type electrode on the outermost side of the thermoelectric generator are connected with a metal plate on a side away from the wafer.