CN112907437A - Method and device for running multiple 3D processes, electronic equipment and storage medium - Google Patents
Method and device for running multiple 3D processes, electronic equipment and storage medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
Abstract
The embodiment of the application provides a method and a device for running a plurality of 3D processes, electronic equipment and a storage medium, which are applied to the electronic equipment, wherein the electronic equipment comprises a Central Processing Unit (CPU) and a Graphics Processing Unit (GPU), and the method comprises the following steps: allocating exclusive use right of a GPU for the 3D processes through the CPU; after a target 3D process obtains an exclusive use right of a GPU, synchronizing a pre-stored hardware state to the GPU through the CPU, wherein the hardware state is a hardware state corresponding to the target 3D process; and executing the atomic rendering operation corresponding to the target 3D process through the GPU. According to the embodiment of the application, the GPU is obtained through competition, the hardware state is synchronous, and atomic rendering is executed, so that the running process of a plurality of 3D processes is realized.
Description
Technical Field
The present application relates to image processing technologies, and in particular, to a method and an apparatus for running multiple 3D processes, an electronic device, and a storage medium.
Background
A Graphics Processing Unit (GPU), also called a display core, a visual processor, and a display chip, is a microprocessor that is specially used in a personal computer, a workstation, a game machine, and some mobile devices (such as a tablet pc and a smart phone), and performs operations related to images and Graphics. The GPU reduces the dependence of the display card on a Central Processing Unit (CPU), performs a part of work originally belonging to the CPU, and particularly during 3D graphics processing, the core technology adopted by the GPU comprises cubic environment material mapping and vertex mixing, texture compression and concave-convex mapping, a dual-texture four-pixel 256-bit rendering engine and the like.
When the GPU performs 3D graphics processing, there are usually a plurality of different 3D application processes that all require the GPU to perform processing, and in this case, how the GPU performs processing on the processes of the plurality of 3D applications is a technical problem that needs to be solved at present.
Disclosure of Invention
The embodiment of the application provides a method and a device for running a plurality of 3D processes, electronic equipment and a storage medium, which are used for running and processing the processes of a plurality of 3D applications.
According to a first aspect of embodiments of the present application, there is provided a method for running multiple 3D processes, which is applied to an electronic device including a central processing unit CPU and a graphics processing unit GPU, the method including:
allocating exclusive use right of a GPU for the 3D processes through the CPU;
after a target 3D process obtains an exclusive use right of a GPU, synchronizing a pre-stored hardware state to the GPU through the CPU, wherein the hardware state is a hardware state corresponding to the target 3D process;
and executing the atomic rendering operation corresponding to the target 3D process through the GPU.
According to a second aspect of the embodiments of the present application, there is provided a method for running multiple 3D processes, where the method is applied to a central processing unit CPU of an electronic device, the electronic device further includes a graphics processing unit GPU, and the method includes:
allocating exclusive use right of the GPU to a plurality of 3D processes;
after the target 3D process obtains the exclusive use right of the GPU, synchronizing a pre-stored hardware state to the GPU to enable the GPU to execute the atomic rendering operation corresponding to the target 3D process, wherein the hardware state is the hardware state corresponding to the target 3D process.
According to a third aspect of the embodiments of the present application, there is provided a multiple 3D process running apparatus applied to an electronic device, the apparatus including:
the exclusive right distribution module is used for distributing exclusive right of use of the GPU to the 3D processes through the CPU;
the synchronization module is used for synchronizing a pre-stored hardware state to the GPU through the CPU after the target 3D process obtains the exclusive use right of the GPU, wherein the hardware state is the hardware state corresponding to the target 3D process;
and the rendering module is used for executing the atomic rendering operation corresponding to the target 3D process through the GPU.
According to a fourth aspect of the embodiments of the present application, there is provided a multiple 3D process running apparatus applied to a CPU of an electronic device, where the electronic device further includes a GPU, and the apparatus includes:
the exclusive right distribution module is used for distributing exclusive right of use of the GPU to the 3D processes through the CPU;
and the synchronization module is used for synchronizing a pre-stored hardware state to the GPU through the CPU after the target 3D process obtains the exclusive use right of the GPU, so that the GPU executes the atomic rendering operation corresponding to the target 3D process, wherein the hardware state is the hardware state corresponding to the target 3D process.
According to a fifth aspect of embodiments of the present application, there is provided an electronic apparatus, including: a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, the processor and the memory communicating over the bus when the electronic device is operating, the machine-readable instructions when executed by the processor performing a plurality of 3D process execution methods.
According to a sixth aspect of embodiments of the present application, there is provided a storage medium having stored thereon a computer program which, when executed by a processor, performs a plurality of 3D process execution methods.
The embodiment of the application provides a method and a device for running a plurality of 3D processes, electronic equipment and a storage medium, which are applied to the electronic equipment, wherein the electronic equipment comprises a Central Processing Unit (CPU) and a Graphics Processing Unit (GPU), and the method comprises the following steps: allocating exclusive use right of a GPU for the 3D processes through the CPU; after a target 3D process obtains an exclusive use right of a GPU, synchronizing a pre-stored hardware state to the GPU through the CPU, wherein the hardware state is a hardware state corresponding to the target 3D process; and executing the atomic rendering operation corresponding to the target 3D process through the GPU. According to the embodiment of the application, the GPU is obtained through competition, the hardware state is synchronous, and atomic rendering is executed, so that the running process of a plurality of 3D processes is realized.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a schematic view of an electronic device according to an embodiment of the present disclosure;
fig. 2 is a flowchart of a 3D process running method according to an embodiment of the present disclosure;
fig. 3 is a flowchart illustrating sub-steps of step S11 according to an embodiment of the present disclosure;
fig. 4 is a schematic operation diagram of 3D processes provided in an embodiment of the present application;
fig. 5 is a functional block diagram of a plurality of 3D process running apparatuses according to an embodiment of the present application;
fig. 6 is a second schematic diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In the process of implementing the present application, the inventor finds that a Graphics Processing Unit (GPU), also called a display core, a visual processor, and a display chip, is a microprocessor specially used in a personal computer, a workstation, a game machine, and some mobile devices (such as a tablet computer, a smart phone, etc.) for performing operations related to images and Graphics. The GPU reduces the dependence of the display card on a Central Processing Unit (CPU), performs a part of work originally belonging to the CPU, and particularly during 3D graphics processing, the core technology adopted by the GPU comprises cubic environment material mapping and vertex mixing, texture compression and concave-convex mapping, a dual-texture four-pixel 256-bit rendering engine and the like.
When the GPU performs 3D graphics processing, there are usually a plurality of different 3D application processes that all require the GPU to perform processing, and in this case, how the GPU performs processing on the processes of the plurality of 3D applications is a technical problem that needs to be solved at present.
In order to solve the above problem, an embodiment of the present application provides a method and an apparatus for running multiple 3D processes, an electronic device and a storage medium, where the method is applied to an electronic device, the electronic device includes a central processing unit CPU and a graphics processing unit GPU, and the method includes: allocating exclusive use right of a GPU for the 3D processes through the CPU; after a target 3D process obtains an exclusive use right of a GPU, synchronizing a pre-stored hardware state to the GPU through the CPU, wherein the hardware state is a hardware state corresponding to the target 3D process; and executing the atomic rendering operation corresponding to the target 3D process through the GPU. According to the embodiment of the application, the GPU is obtained through competition, the hardware state is synchronous, and atomic rendering is executed, so that the running process of a plurality of 3D processes is realized.
The scheme in the embodiment of the present application may be implemented by using various computer languages, for example, C language, object-oriented programming language C + +, and JavaScript.
In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following further detailed description of the exemplary embodiments of the present application with reference to the accompanying drawings makes it clear that the described embodiments are only a part of the embodiments of the present application, and are not exhaustive of all embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
Referring to fig. 1, fig. 1 is a schematic view of an electronic device 10 according to an embodiment of the present disclosure. In the present embodiment, the electronic device 10 includes a processor 11, the processor 11 includes a CPU111 and a GPU112, and the CPU111 and the GPU112 are communicatively connected. Optionally, in this embodiment, the model of the GPU112 may be the chip JM 7200.
The method for running the multiple 3D processes provided by the embodiment of the application is applied to the electronic device 10, and the electronic device 10 realizes the step of running the multiple 3D processes through the CPU111 or the GPU 112.
A plurality of 3D process execution methods provided in the embodiments of the present application are described below with reference to the accompanying drawings.
Referring to fig. 2, fig. 2 is a flowchart of a 3D process running method according to an embodiment of the present disclosure.
In this embodiment, the method includes:
in step S11, the CPU allocates exclusive use rights of the GPU to the plurality of 3D processes.
Step S12, after the target 3D process obtains the exclusive use right of the GPU, synchronizing the pre-stored hardware state to the GPU by the CPU.
And the hardware state is the hardware state corresponding to the target 3D process.
Step S13, the GPU performs an atomic rendering operation corresponding to the target 3D process.
In the above steps, when each 3D process performs hardware rendering, it is necessary to first obtain an exclusive use right of the GPU112, so as to implement mutually exclusive access of the GPU 112. Therefore, when running multiple 3D processes, the CPU111 needs to allocate an exclusive use right of the GPU112 to one target 3D process of the multiple 3D processes, which means that only the target 3D process can use the GPU 112. After the target 3D process obtains the exclusive use right of the GPU112, the CPU111 synchronizes the hardware state of the target 3D process pre-stored in the memory to the GPU112, so that the GPU112 can execute the atomic rendering operation corresponding to the target 3D process.
When the GPU is JM7200, the chip JM7200 runs a plurality of 3D processes through time division multiplexing, and the illusion that each process monopolizes one GPU is formed. The driver of the chip JM7200 maintains a hardware state in the memory of the electronic device 10, and defines a minimum schedulable atomic rendering operation, and when starting an atomic rendering, the driver of the chip JM7200 ensures that the hardware state in the memory of the electronic device 10 is consistent with actual hardware, so that after the target 3D process obtains the exclusive use right of the GPU112, the CPU111 synchronizes the hardware state of the target 3D process pre-stored in the memory to the GPU 112.
It should be noted that, after performing the atomic rendering of one target 3D process, steps S11 to S13 are repeated to allocate the exclusive right of use of the GPU112 to the next target 3D process, and the atomic rendering is performed.
Optionally, in this embodiment, the atomic rendering refers to an uninterruptable set of GPU commands, the atomicity of which is determined by the hardware characteristics of the GPU 112. The GPU112 is driven to implement mutually exclusive access of processes by a kernel-mode mutually exclusive lock, so as to ensure that GPU commands corresponding to atomic rendering are not interrupted.
Optionally, in this embodiment, after the target 3D process obtains the exclusive use right of the GPU, the method for running the multiple 3D processes further includes: and locking the GPU through the CPU.
Optionally, in this example, in step S13, after the GPU executes the atomic rendering operation corresponding to the target 3D process, the method for running the multiple 3D processes further includes: and unlocking the GPU through the CPU.
In the above steps, in order to ensure that the atomic rendering process is not interrupted by other programs, after a target 3D process obtains the exclusive use right of the GPU112, the GPU112 may be locked by a kernel-state mutual exclusion lock, and after the atomic rendering of the target 3D process is completed, the GPU112 is unlocked. After unlocking, other 3D processes may continue to contend for exclusive use of GPU 112.
Alternatively, a set of { gljProLock, gljProUnlock } pairs that are successfully locked and unlocked may be treated as one atomic rendering operation in the GPU's driver code.
Optionally, in this embodiment, a scheduling problem may be involved when multiple 3D processes run by time-sharing multiplexing, and if multiple 3D processes compete for the exclusive use right of the GPU112 together, a target 3D process that finally obtains the exclusive use right needs to be determined by the scheduling policy of the CPU 111.
Referring to fig. 3, fig. 3 is a flowchart illustrating a sub-step of step S11 according to an embodiment of the present disclosure. In the present embodiment, step S11 includes the following sub-steps:
step S111, acquiring the priority of each 3D process.
And step S112, allocating the exclusive use right of the GPU to the target 3D process with the highest priority according to the priority of each 3D process.
In the above steps, one scheduling policy of the CPU111 may be to allocate the exclusive right of use of the GPU112 to the target 3D process with the highest priority by the priority of each 3D process.
For example, if there are A, B, C, D four different 3D processes, where the priority of the a process is highest, then the exclusive use of GPU112 is first assigned to the a process so that GPU112 can perform the atomic rendering operations corresponding to the a process. After the a process is executed, the process with the highest priority is selected at B, C, D, and the process is assigned the exclusive right of use of the GPU 112.
Optionally, in this embodiment, before executing each 3D process, the hardware state required for executing each 3D process is also pre-stored in the memory of the electronic device 10, so as to be synchronized into the GPU112 subsequently. Therefore, the method for running the plurality of 3D processes further includes: and pre-storing the hardware state of each 3D process into a memory.
Specifically, the step of pre-storing the hardware state of each 3D process in the memory includes:
acquiring the context state gl _ state of each 3D process through the CPU 111; and converting the context state gl _ state of each 3D process into a corresponding hardware state jmgpu _ hwstate through the CPU, and storing the hardware state jmgpu _ hwstate in the memory.
The above embodiments will be described with reference to the drawings. Referring to fig. 4, fig. 4 is a schematic operation diagram of 3D processes provided in the embodiment of the present application. In fig. 4, there are 3 OpenGL applications (i.e., ubgears in fig. 4) waiting for GPU112 to execute simultaneously.
In the user space (i.e., Userapace in fig. 4), each OpenGL application (ubgears) needs to pre-store a piece of software context state (i.e., gl _ state) in the memory, then convert it into a hardware context state (i.e., jmgpu _ hwstate), and store it in the memory.
Since GPU112 can only execute one 3D process at a time, 3 OpenGL applications (ubgears) need to contend for exclusive use of GPU112, i.e., obtain a kernel-mode exclusive lock. The CPU111 may determine a contention winner according to the priority of each OpenGL application (ubgears), and the contention winner may obtain the exclusive use right of the GPU112, and obtain one atomic rendering time slice of the GPU 112. Then, the CPU111 synchronizes the hardware state corresponding to the contention winner pre-stored in the memory to the GPU112, and the GPU112 can execute the atomic rendering after obtaining the hardware state.
Optionally, in this embodiment, step S13 specifically includes:
after receiving a JMGPUREG _ FRAME _ START instruction, starting an atomic rendering operation; upon receiving the JMGPUREG _ FRAME _ END instruction, the atomic rendering operation is ended.
In the above steps, one atomic rendering refers to a group of commands JMGPUREG _ FRAME _ START to JMGPUREG _ FRAME _ END from a hardware characteristic point of view. When the GPU112 receives the JMGPUREG _ FRAME _ START instruction, an atomic rendering operation may be started, and the atomic rendering operation may be ended when the JMGPUREG _ FRAME _ END instruction is received.
That is, after the GPU completes executing the JMGPUREG _ FRAME _ END instruction, indicating that the atomic rendering is finished, the GPU sends a completion signal to notify the CPU that the unlocking operation can be performed on the GPU 112.
Optionally, in this embodiment, step S12 specifically includes:
directly writing the hardware state into an annular buffer register of the GPU through the CPU; or the CPU writes the hardware state into the CPU annular buffer and informs the GPU so that the GPU can actively acquire the hardware state.
To sum up, the embodiment of the present application provides a method and an apparatus for operating multiple 3D processes, an electronic device and a storage medium, which are applied to an electronic device, where the electronic device includes a central processing unit CPU and a graphics processing unit GPU, and the method includes: allocating exclusive use right of a GPU for the 3D processes through the CPU; after a target 3D process obtains an exclusive use right of a GPU, synchronizing a pre-stored hardware state to the GPU through the CPU, wherein the hardware state is a hardware state corresponding to the target 3D process; and executing the atomic rendering operation corresponding to the target 3D process through the GPU. According to the embodiment of the application, the GPU is obtained through competition, the hardware state is synchronous, and atomic rendering is executed, so that the running process of a plurality of 3D processes is realized.
Optionally, an embodiment of the present application further provides a method for running multiple 3D processes, which is applied to a CPU of the electronic device 10, and the method includes:
allocating exclusive use right of the GPU to a plurality of 3D processes;
after the target 3D process obtains the exclusive use right of the GPU, synchronizing a pre-stored hardware state to the GPU to enable the GPU to execute the atomic rendering operation corresponding to the target 3D process, wherein the hardware state is the hardware state corresponding to the target 3D process.
It should be noted that the specific implementation steps of the multiple 3D process running method applied to the CPU of the electronic device 10 are the same as those of the multiple 3D process running method applied to the electronic device 10, and are not described herein again.
Referring to fig. 5, fig. 5 is a functional block diagram of a plurality of 3D process running apparatuses 110 according to an embodiment of the present disclosure. In this embodiment, the plurality of 3D process execution apparatuses 110 include:
an exclusive right allocation module 1101, configured to allocate, by the CPU, an exclusive right of use of the GPU to the plurality of 3D processes.
The synchronization module 1102 is configured to synchronize, by the CPU, a pre-stored hardware state to the GPU after the target 3D process obtains an exclusive use right of the GPU, where the hardware state is a hardware state corresponding to the target 3D process.
A rendering module 1103, configured to execute, by the GPU, an atomic rendering operation corresponding to the target 3D process.
Optionally, an embodiment of the present application further provides a device for running multiple 3D processes, which is applied to a CPU of an electronic device, where the electronic device further includes a GPU, and the device includes:
the exclusive right distribution module is used for distributing exclusive right of use of the GPU to the 3D processes through the CPU;
and the synchronization module is used for synchronizing a pre-stored hardware state to the GPU through the CPU after the target 3D process obtains the exclusive use right of the GPU, so that the GPU executes the atomic rendering operation corresponding to the target 3D process, wherein the hardware state is the hardware state corresponding to the target 3D process.
Referring to fig. 6, fig. 6 is a second schematic view of the electronic device 10 according to the embodiment of the present disclosure. In the present embodiment, the electronic device 10 includes: a processor 11, a memory 12 and a bus 13, wherein the memory 12 stores machine-readable instructions executable by the processor 11, when the electronic device 10 is running, the processor 11 and the memory 12 communicate with each other through the bus 13, and when the machine-readable instructions are executed by the processor 11, the method for running a plurality of 3D processes provided by the embodiments of the present application is performed.
The embodiment of the application also provides a storage medium, wherein a computer program is stored on the storage medium, and when the computer program is executed by a processor, the method for executing the multiple 3D processes provided by the embodiment of the application is executed.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (16)
1. A method for running a plurality of 3D processes is applied to an electronic device, wherein the electronic device comprises a Central Processing Unit (CPU) and a Graphics Processing Unit (GPU), and the method comprises the following steps:
allocating exclusive use right of a GPU for the 3D processes through the CPU;
after a target 3D process obtains an exclusive use right of a GPU, synchronizing a pre-stored hardware state to the GPU through the CPU, wherein the hardware state is a hardware state corresponding to the target 3D process;
and executing the atomic rendering operation corresponding to the target 3D process through the GPU.
2. The method of claim 1, wherein after the target 3D process obtains exclusive use of the GPU, the method further comprises:
and locking the GPU through the CPU.
3. The method of claim 2, wherein after the target 3D process performs the atomic rendering operation, the method further comprises:
and unlocking the GPU through the CPU.
4. The method according to claim 1, wherein the performing, by the GPU, the atomic rendering operation corresponding to the target 3D process comprises:
acquiring the priority of each 3D process;
and allocating the exclusive use right of the GPU to a target 3D process with the highest priority according to the priority of each 3D process.
5. The method according to claim 1, further comprising the step of pre-storing the hardware state of each 3D process in a memory, the step comprising:
acquiring a context state gl _ state of each 3D process through the CPU;
and converting the context state gl _ state of each 3D process into a corresponding hardware state jmgpu _ hwstate through the CPU, and storing the hardware state jmgpu _ hwstate in a memory.
6. The method of claim 5, wherein synchronizing, by the CPU, pre-stored hardware states to the GPU comprises:
directly writing the hardware state into an annular buffer register of the GPU, or;
and writing the hardware state into an annular buffer of the CPU, and informing the GPU to enable the GPU to actively acquire the hardware state.
7. The method according to claim 1, wherein performing, by the GPU, an atomic rendering operation corresponding to the target 3D process comprises:
after receiving a JMGPUREG _ FRAME _ START instruction, initiating an atomic rendering operation;
upon receiving the JMGPUREG _ FRAME _ END instruction, the atomic rendering operation is ended.
8. A method for running a plurality of 3D processes is applied to a Central Processing Unit (CPU) of an electronic device, the electronic device further comprises a Graphics Processing Unit (GPU), and the method comprises the following steps:
allocating exclusive use right of the GPU to a plurality of 3D processes;
after the target 3D process obtains the exclusive use right of the GPU, synchronizing a pre-stored hardware state to the GPU to enable the GPU to execute the atomic rendering operation corresponding to the target 3D process, wherein the hardware state is the hardware state corresponding to the target 3D process.
9. The method of claim 8, wherein after the target 3D process obtains exclusive use of the GPU, the method further comprises:
and locking the GPU.
10. The method of claim 9, wherein after the target 3D process performs the atomic rendering operation, the method further comprises:
and unlocking the GPU.
11. The method according to claim 8, further comprising the step of pre-storing the hardware state of each 3D process in a memory, the step comprising:
acquiring a context state gl _ state of each 3D process;
and converting the context state gl _ state of each 3D process into a corresponding hardware state jmgpu _ hwstate, and storing the hardware state jmgpu _ hwstate in an internal memory.
12. The method of claim 8, wherein synchronizing the pre-stored hardware state to the GPU comprises:
directly writing the hardware state into an annular buffer register of the GPU, or;
and writing the hardware state into an annular buffer of the CPU, and informing the GPU to enable the GPU to actively acquire the hardware state.
13. A plurality of 3D process running devices, which are applied to electronic equipment, the device comprises:
the exclusive right distribution module is used for distributing exclusive right of use of the GPU to the 3D processes through the CPU;
the synchronization module is used for synchronizing a pre-stored hardware state to the GPU through the CPU after the target 3D process obtains the exclusive use right of the GPU, wherein the hardware state is the hardware state corresponding to the target 3D process;
and the rendering module is used for executing the atomic rendering operation corresponding to the target 3D process through the GPU.
14. A plurality of 3D process running devices, which are applied to a CPU of an electronic device, wherein the electronic device further comprises a GPU, and the device comprises:
the exclusive right distribution module is used for distributing exclusive right of use of the GPU to the 3D processes through the CPU;
and the synchronization module is used for synchronizing a pre-stored hardware state to the GPU through the CPU after the target 3D process obtains the exclusive use right of the GPU, so that the GPU executes the atomic rendering operation corresponding to the target 3D process, wherein the hardware state is the hardware state corresponding to the target 3D process.
15. An electronic device, comprising: a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, the processor and the memory communicating over the bus when the electronic device is operating, the machine-readable instructions when executed by the processor performing the method of any of claims 1-7.
16. A storage medium, having stored thereon a computer program which, when executed by a processor, performs the method according to any one of claims 1-7.
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