CN112905366A - Operation control method and device of simulation model and electronic equipment - Google Patents
Operation control method and device of simulation model and electronic equipment Download PDFInfo
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- CN112905366A CN112905366A CN202110453694.4A CN202110453694A CN112905366A CN 112905366 A CN112905366 A CN 112905366A CN 202110453694 A CN202110453694 A CN 202110453694A CN 112905366 A CN112905366 A CN 112905366A
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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Abstract
The application discloses an operation control method and device of a simulation model and electronic equipment, wherein the method comprises the following steps: obtaining a simulation project to be simulated and operated, wherein the simulation project comprises a plurality of simulation models; starting a plurality of simulation processes under the condition that the simulation projects contain simulation models with different bit width parameters, so that each simulation process respectively carries out simulation operation on the corresponding simulation model to obtain a project simulation result of the simulation project; the simulation models with different bit width parameters respectively correspond to different simulation processes, the transmission of simulation data is carried out between the simulation processes through a memory area, and the simulation data at least comprises a model simulation result obtained by carrying out simulation operation on the simulation models.
Description
Technical Field
The present application relates to the field of simulation technologies, and in particular, to a method and an apparatus for controlling operation of a simulation model, and an electronic device.
Background
Simulation models created by modeling systems with different bit widths have different bit widths, such as 16-bit, 32-bit or even 64-bit simulation model FMU (Functional Mock-Up Unit) packaged based on FMI (Functional Mock-Up Interface) protocol.
In the simulation project, the situation that simulation models with multiple bit widths exist simultaneously may be included, and in order to implement joint simulation operation of simulation models with different bit widths, the situation that data interaction between simulation models with different bit widths may have low interaction efficiency may exist, thereby resulting in low simulation efficiency.
Therefore, a technical solution for improving the simulation efficiency when implementing the simulation operation of the simulation models with different bit width parameters coexisting in the same simulation project is needed.
Disclosure of Invention
In view of the above, the present application provides an operation control method and apparatus for a simulation model, and an electronic device, including:
an operation control method of a simulation model includes:
obtaining a simulation project to be simulated and operated, wherein the simulation project comprises a plurality of simulation models;
starting a plurality of simulation processes under the condition that the simulation projects contain simulation models with different bit width parameters, so that each simulation process respectively carries out simulation operation on the corresponding simulation model to obtain a project simulation result of the simulation project;
the simulation models with different bit width parameters respectively correspond to different simulation processes, the transmission of simulation data is carried out between the simulation processes through a memory area, and the simulation data at least comprises a model simulation result obtained by carrying out simulation operation on the simulation models.
In the method, preferably, the memory area is used for caching corresponding simulation data of any simulation process in a simulation operation process, so that any other simulation process reads the simulation data in the memory area.
In the method, preferably, the simulation data read by the simulation process in the memory area is: and the memory area is provided with simulation data in operation incidence relation with the simulation process.
In the above method, preferably, the memory area is created by a first simulation process of the plurality of simulation processes;
wherein the first simulation process is further to: after the memory area is created, transmitting area address information of the memory area to a second simulation process in the plurality of simulation processes, so that the second simulation process receives the area address information, and the second simulation process caches second simulation data corresponding to the second simulation process in the memory area based on the area address information.
In the above method, preferably, a first simulation process of the plurality of simulation processes is further configured to: storing a first model simulation result obtained by performing simulation operation on a first simulation model corresponding to the first simulation process in the memory area, so that a second simulation process in the multiple simulation processes reads the first model simulation result in the memory area and performs simulation operation on a second simulation model corresponding to the second simulation process according to the first model simulation result to obtain a project simulation result of the simulation project;
wherein the second simulation process is further to: and storing the project simulation result of the simulation project into the memory area, so that the first simulation process reads the project simulation result of the simulation project in the memory area and outputs the project simulation result.
In the above method, preferably, a first simulation process of the plurality of simulation processes is further configured to: and reading a second model simulation result obtained by performing simulation operation on a second simulation model corresponding to a second simulation process by the second simulation process in the plurality of simulation processes in the memory area, and performing simulation operation on a first simulation model corresponding to the first simulation process according to the second model simulation result to obtain a project simulation result of the simulation project and output the project simulation result.
In the method, preferably, after the project simulation result of the simulation project is obtained, any simulation process in the plurality of simulation processes is further used to release the memory area.
In the above method, preferably, when the simulation operation of the simulation item is finished, a first simulation process of the plurality of simulation processes is further configured to: and closing other simulation processes except the first simulation process in the plurality of simulation processes.
An operation control device of a simulation model, comprising:
the simulation system comprises a project obtaining unit, a simulation unit and a simulation unit, wherein the project obtaining unit is used for obtaining a simulation project to be simulated and operated, and the simulation project comprises a plurality of simulation models;
the process starting unit is used for starting a plurality of simulation processes under the condition that the simulation projects contain simulation models with different bit width parameters, so that each simulation process respectively carries out simulation operation on the corresponding simulation model to obtain a project simulation result of the simulation project;
the simulation models with different bit width parameters respectively correspond to different simulation processes, the transmission of simulation data is carried out between the simulation processes through a memory area, and the simulation data at least comprises a model simulation result obtained by carrying out simulation operation on the simulation models.
An electronic device, comprising:
the memory is used for storing an application program and data generated by the running of the application program;
a processor for executing the application to implement: obtaining a simulation project to be simulated and operated, wherein the simulation project comprises a plurality of simulation models; starting a plurality of simulation processes under the condition that the simulation projects contain simulation models with different bit width parameters, so that each simulation process respectively carries out simulation operation on the corresponding simulation model to obtain a project simulation result of the simulation project; the simulation models with different bit width parameters respectively correspond to different simulation processes, the transmission of simulation data is carried out between the simulation processes through a memory area, and the simulation data at least comprises a model simulation result obtained by carrying out simulation operation on the simulation models.
According to the technical scheme, after a simulation project to be subjected to simulation operation and including a plurality of simulation models is obtained, different simulation processes are started to respectively perform simulation operation on the simulation models with corresponding bit width parameters based on the simulation models with different bit width parameters included in the simulation project, so that a project simulation result of the simulation project is obtained, and in the process, transmission of simulation data such as a model simulation result is realized among the different simulation processes through a memory area. Therefore, when the simulation operation of the simulation models with different bit width parameters coexisting in the same simulation project is realized, the data interaction efficiency in the simulation operation is improved by utilizing the characteristic of high memory reading speed, and the aim of improving the simulation efficiency is fulfilled.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a flowchart of an operation control method of a simulation model according to an embodiment of the present application;
FIG. 2 is a schematic diagram illustrating interaction between two emulation processes in an embodiment of the present application;
fig. 3 is a schematic structural diagram of an operation control device of a simulation model according to a second embodiment of the present application;
fig. 4 is a schematic structural diagram of an electronic device according to a third embodiment of the present application;
5-6 are schematic diagrams of interaction between a master process and a slave process when the application is applied to a server with 32-bit FMUs and 64-bit FMUs for simulation operation respectively;
FIG. 7 is a schematic flow chart of the present application for simulation operations performed by a server with 32-bit and 64-bit FMUs.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, a flowchart of an implementation of an operation control method of a simulation model provided in an embodiment of the present application is shown, where the method may be applied to an electronic device capable of performing data processing, such as a computer or a server. The technical scheme in the embodiment is mainly used for improving the data interaction efficiency among simulation models while realizing the simulation operation of the simulation projects of the simulation models containing different bit width parameters, thereby improving the simulation operation rate.
Specifically, the method in this embodiment may include the following steps:
step 101: and acquiring a simulation project to be simulated and operated.
The simulation project includes a plurality of simulation models, and the simulation model may be a simulation model encapsulated based on a standard protocol, for example, an FMU (Functional Mock-Up Unit) simulation model encapsulated based on an FMI (Functional Mock-Up Interface) protocol.
Specifically, the simulation project can be understood as: the method comprises the simulation system engineering of various meta-models to be operated, wherein the meta-models are simulation models in simulation projects.
In a specific implementation, in this embodiment, a simulation project including a simulation model to be operated may be loaded on an implemented simulation platform, for example, an application program of the simulation platform is first opened, a simulation system project including a plurality of FMU simulation models, which is required and has been created in advance, is manually selected on a loading interactive interface of the simulation platform, that is, the simulation project is clicked to open the simulation system project, so as to implement loading of the simulation system project.
Step 102: and judging whether the simulation item contains simulation models with different bit width parameters, and executing the step 103 if the simulation item contains the simulation models with different bit width parameters.
Specifically, in this embodiment, the bit width parameters of the multiple simulation models included in the simulation project may be obtained, and then the bit width parameters are compared, so as to determine whether the simulation project includes the simulation models with different bit width parameters.
The bit width refers to a data amount that can be transmitted by the memory or the video memory at one time, the bit width parameter refers to a system bit width parameter of the modeling system when the simulation model is modeled, and the bit width parameter of each simulation model may be the same or different, that is, each simulation model may be created based on the modeling system with different system bit widths. Specifically, the bit width parameter may have 16 bits, 32 bits, or 64 bits, etc.
For example, in this embodiment, after the simulation item is loaded on the simulation platform, the bit width parameter of each simulation model in the simulation item is obtained, and then, whether the simulation models included in the simulation item correspond to the same bit width parameter or correspond to a plurality of different bit width parameters is determined by comparing and classifying the bit width parameters. For example, there are 3 simulation models in the simulation project, and bit width parameters of the 3 simulation models are all 32 bits, at this time, the simulation models in the simulation project correspond to the same bit width parameter; for another example, there are 4 simulation models in the simulation project, and the bit width parameters of the 4 simulation models are all 64 bits, at this time, the simulation models in the simulation project correspond to the same bit width parameter; for another example, there are 5 simulation models in the simulation project, and 2 of the 5 simulation models have a bit width parameter of 32 bits, and the other 3 simulation models have a bit width parameter of 64 bits, at this time, there are two bit width parameters in the simulation models included in the simulation project.
Step 103: and starting a plurality of simulation processes, so that each simulation process respectively carries out simulation operation on the corresponding simulation model to obtain a project simulation result of the simulation project.
The simulation processes are transmitted by the memory area, and specifically, the simulation data at least comprises a model simulation result obtained by performing simulation operation on the simulation model.
It should be noted that a process refers to a running activity of a program in a computer on a certain data set, is a basic unit for resource allocation and scheduling of a system, and is a basis of an operating system structure. The simulation operation is a process of establishing an equivalent mathematical model, compiling a simulation program on a computer, compiling and running.
In specific implementation, in this embodiment, simulation processes of simulation models respectively corresponding to different bit width parameters are started, and then the simulation processes are used to perform simulation operation on one or more simulation models having corresponding bit width parameters, and in the process of performing simulation operation on the simulation models having corresponding bit width parameters, the simulation operation of the simulation models needs to be performed based on model operation results of other simulation models, so that transmission of respective model simulation results is performed between the simulation models through a memory area, thereby implementing joint simulation operation between different simulation models in a simulation project, and finally obtaining a project simulation result of the simulation project.
For example, two simulation models are respectively a simulation model with a bit width parameter of 32 bits and a simulation model with a bit width parameter of 64 bits in the acquired simulation project, two simulation processes are correspondingly started, one simulation process is used for executing simulation operation on the simulation model with the bit width parameter of 32 bits, the other simulation process is used for executing simulation operation on the simulation model with the bit width parameter of 64 bits, and the two simulation processes utilize a memory area for transmitting a model simulation result, so that the two simulation processes can realize the simulation operation on the corresponding simulation models based on the transmitted model operation results of other simulation models, thereby realizing joint simulation operation between the two simulation models and obtaining a project simulation result of the simulation project;
or, the acquired simulation project comprises three simulation models, namely a simulation model with a bit width parameter of 32 bits and two simulation models with a bit width parameter of 64 bits, and two simulation processes are correspondingly started, wherein one simulation process is used for executing simulation operation on the simulation model with the bit width parameter of 32 bits, the other simulation process is used for executing simulation operation on the simulation models with the bit width parameter of 64 bits, and the two simulation processes utilize the memory area for transmitting the simulation result of the models, so that the two simulation processes can realize the simulation operation on the corresponding simulation models based on the transmitted model operation results of other simulation models, thereby realizing the joint simulation operation between the two simulation models and obtaining the project simulation result of the simulation project;
or, the acquired simulation project includes three simulation models, which are respectively a simulation model with a bit width parameter of 16 bits, a simulation model with a bit width parameter of 32 bits and a simulation model with a bit width parameter of 64 bits, and three simulation processes are correspondingly started, one simulation process is used for executing simulation operation on the simulation model with a bit width parameter of 16 bits, one simulation process is used for executing simulation operation on the simulation model with a bit width parameter of 32 bits, the other simulation process is used for executing simulation operation on the simulation model with a bit width parameter of 64 bits, the three simulation processes utilize a memory area to transmit model simulation results, so that the three simulation processes can realize the simulation operation on the basis of the transmitted model operation results of other simulation models when performing the simulation operation on the respective corresponding simulation models, thereby realizing the joint simulation operation among a plurality of simulation models, to obtain a project simulation result of the simulation project.
According to the above scheme, in the operation control method of the simulation model provided in the first embodiment of the present application, after the simulation project to be subjected to the simulation operation and including the plurality of simulation models is obtained, different simulation processes are started to perform the simulation operation on the simulation models having the corresponding bit width parameters respectively based on the simulation models having the different bit width parameters included in the simulation project, so as to obtain the project simulation result of the simulation project, and in this process, the transmission of the simulation data, such as the model simulation result, is realized between the different simulation processes through the memory area. It can be seen that, in the present embodiment, corresponding simulation processes are started for simulation models with different bit width parameters in a simulation project to perform corresponding simulation operation processing and output a project simulation result, and meanwhile, a memory area is used in the simulation operation processing to implement data transmission between the simulation processes, so that in the present embodiment, data interaction between the processes for performing simulation operation on the simulation models with different bit width parameters is implemented by using the memory area, and finally a project simulation result of the simulation project is obtained.
In a specific implementation, the memory area for implementing transmission of the simulation data in this embodiment may be a region pre-partitioned in a memory of the electronic device for implementing simulation operation of the simulation project, or the memory area for implementing transmission of the simulation data in this embodiment may be a region partitioned in the memory of the electronic device in real time according to transmission requirements of the simulation data, such as data size and the like.
Based on this, the memory area partitioned in this embodiment may be used to cache the simulation data corresponding to any simulation process in the simulation operation process, so that any other simulation process reads the simulation data in the memory area.
Taking a simulation model with two bit width parameters in a simulation project as an example, the memory area divided in the embodiment is used for caching corresponding first simulation data of a first simulation process in two simulation processes in a simulation operation process, so that a second simulation process in the two simulation processes reads the stored first simulation data in the memory area; in addition, the memory area divided in this embodiment is used to cache corresponding second simulation data of a second simulation process in the two simulation processes in the simulation operation process, so that a first simulation process in the two simulation processes reads the stored second simulation data in the memory area, as shown in fig. 2.
Specifically, the simulation data read by the simulation process in the memory area may be: and simulation data which has operation association relation with the simulation process in the memory area. The simulation data having an operation association relationship with the simulation process may be understood as simulation data required for the simulation process to perform the simulation operation, such as a model operation result obtained by performing the simulation operation on another simulation process.
Taking a simulation model with two bit width parameters in a simulation project as an example, the memory area divided in the embodiment is used for caching corresponding first simulation data of a first simulation process in two simulation processes in a simulation operation process, so that a second simulation process in the two simulation processes reads simulation data related to the simulation operation of the second simulation process in the stored first simulation data in the memory area; in addition, the memory area divided in this embodiment is used to cache the second simulation data corresponding to the second simulation process in the simulation operation process in the two simulation processes, so that the first simulation process in the two simulation processes reads the simulation data related to the simulation operation performed by the first simulation process in the saved second simulation data in the memory area.
For example, two simulation models are respectively a simulation model with a bit width parameter of 32 bits and a simulation model with a bit width parameter of 64 bits in the acquired simulation project, two simulation processes are correspondingly started, one simulation process is used for executing simulation operation on the simulation model with the bit width parameter of 32 bits, the other simulation process is used for executing simulation operation on the simulation model with the bit width parameter of 64 bits, and each simulation process respectively caches a corresponding model simulation result in the simulation operation process on the simulation model in a memory area, so that other simulation processes can read a required model simulation result from the memory area for the simulation operation on the corresponding simulation model, thereby realizing joint simulation operation between the two simulation models to obtain a project simulation result of the simulation project;
or, the acquired simulation project comprises three simulation models, namely a simulation model with a bit width parameter of 32 bits and two simulation models with a bit width parameter of 64 bits, and two corresponding simulation processes are started, wherein one simulation process is used for executing simulation operation on the simulation model with the bit width parameter of 32 bits, the other simulation process is used for executing simulation operation on the simulation models with the bit width parameter of 64 bits, and each simulation process caches a corresponding model simulation result in the simulation operation process on the simulation model in the memory area, so that other simulation processes can read a required model simulation result from the memory area for the simulation operation on the corresponding simulation model, thereby realizing joint simulation operation between the two simulation models and obtaining a project simulation result of the simulation project;
or, the acquired simulation project includes three simulation models, which are respectively a simulation model with a bit width parameter of 16 bits, a simulation model with a bit width parameter of 32 bits and a simulation model with a bit width parameter of 64 bits, and three simulation processes are correspondingly started, one simulation process is used for executing simulation operation on the simulation model with a bit width parameter of 16 bits, one simulation process is used for executing simulation operation on the simulation model with a bit width parameter of 32 bits, the other simulation process is used for executing simulation operation on the simulation model with a bit width parameter of 64 bits, each simulation process respectively caches a corresponding model simulation result in the simulation operation process on the simulation model in the memory area, so that other simulation processes can read a required model simulation result from the memory area for simulation operation on the corresponding simulation model, therefore, joint simulation operation among the simulation models is realized, and a project simulation result of the simulation project is obtained.
In an implementation manner, the memory area may be created by a first simulation process in the multiple simulation processes, at this time, the first simulation process is a main process, such as a simulation process corresponding to a 64-bit simulation model, and the first simulation process may cache first simulation data corresponding to the first simulation process in the process of performing simulation operation on the first simulation process in the memory area, so that a second simulation process in the multiple simulation processes may read, in the memory area, simulation data having an operation association relationship with the second simulation process in the first simulation data.
Based on this, the first simulation process is further configured to: after the memory area is created, the area address information of the memory area is transmitted to a second simulation process in the multiple simulation processes, so that the second simulation process receives the area address information, and second simulation data corresponding to the second simulation process is cached in the memory area based on the area address information, so that the first simulation process can read simulation data which has an operation association relationship with the first simulation process in the second simulation data in the memory area.
In a specific implementation, a first simulation process of the multiple simulation processes may be further configured to: storing a first model simulation result obtained by performing simulation operation on a first simulation model corresponding to a first simulation process in a memory area, so that a second simulation process in the plurality of simulation processes reads the first model simulation result in the memory area and performs simulation operation on a second simulation model corresponding to the second simulation process according to the first model simulation result to obtain a project simulation result of a simulation project;
wherein the second simulation process is further to: and storing the project simulation result of the simulation project into a memory area, so that the first simulation process serving as the main process reads the project simulation result of the simulation project in the memory and outputs the project simulation result. For example, the first simulation process may transmit the project simulation result to an interactive interface, such as a UI interface, through an interface between the first simulation process and the interactive interface on the simulation platform, so as to perform subsequent processing according to the project simulation result, for example, outputting data such as a corresponding table or an image on the UI interface.
It should be noted that "first" and "second" in the first emulation process and the second emulation process are used to distinguish two different master-slave processes.
That is to say, the project simulation result in this embodiment is generated by the second simulation process, and after the second simulation process as the slave process performs the final simulation operation on the corresponding second simulation model according to the first model simulation result corresponding to the first simulation process, the finally output project simulation result of the simulation project is cached in the memory area, so that the first simulation process as the master process reads the project simulation result from the memory area, and the first simulation process as the master process outputs the project simulation result.
Alternatively, the first emulation process of the plurality of emulation processes may be further configured to: and reading a second model simulation result obtained by carrying out simulation operation on a second simulation model corresponding to a second simulation process by a second simulation process in the plurality of simulation processes in the memory area, and carrying out simulation operation on a first simulation model corresponding to a first simulation process according to the second model simulation result to obtain a project simulation result of the simulation project and outputting the project simulation result.
That is, after the first simulation process as the main process performs the final simulation operation on the corresponding first simulation model according to the second model simulation result corresponding to the second simulation process, the finally obtained project simulation result of the simulation project is output.
In another implementation manner, the memory area may be created by a second simulation process in the multiple simulation processes, at this time, the second simulation process is a main process, such as a simulation process corresponding to the 32-bit simulation model, and the second simulation process may cache second simulation data corresponding to the second simulation process in the simulation operation process in the memory area, so that a first simulation process in the multiple simulation processes may read, in the memory area, simulation data having an operation association relationship with the first simulation process in the second simulation data.
Based on this, the second simulation process is further configured to: after the memory area is created, the area address information of the memory area is transmitted to a first simulation process in the multiple simulation processes, so that the first simulation process receives the area address information, and first simulation data corresponding to the first simulation process are cached in the memory area based on the area address information, so that a second simulation process can read simulation data which are in the first simulation data and have an operation association relationship with the second simulation process in the memory area.
In a specific implementation, a second simulation process of the multiple simulation processes may be further configured to: storing a second model simulation result obtained by performing simulation operation on a second simulation model corresponding to a second simulation process in the memory area, so that a first simulation process in the plurality of simulation processes reads the second model simulation result in the memory area and performs simulation operation on the first simulation model corresponding to the first simulation process according to the second model simulation result to obtain a project simulation result of the simulation project;
wherein the first simulation process is further to: and storing the project simulation result of the simulation project into a memory area, so that a second simulation process serving as a main process reads the project simulation result of the simulation project in the memory and outputs the project simulation result. For example, the second simulation process may also transmit the project simulation result to an interactive interface, such as a UI interface, through an interface with the interactive interface on the simulation platform, so as to perform subsequent processing according to the project simulation result, for example, outputting data such as a corresponding table or an image on the UI interface.
That is to say, the project simulation result in this embodiment is generated by the first simulation process, and after the first simulation process serving as the slave process performs the final simulation operation on the corresponding first simulation model according to the second model simulation result corresponding to the second simulation process, the project simulation result of the finally output simulation project is cached in the memory area, so that the second simulation process serving as the master process reads the project simulation result from the memory area, and the second simulation process serving as the master process outputs the project simulation result.
Alternatively, the second simulation process of the plurality of simulation processes may be further configured to: reading a first model simulation result obtained by carrying out simulation operation on a first simulation model corresponding to a first simulation process by a first simulation process in the plurality of simulation processes in the memory area, and carrying out simulation operation on a second simulation model corresponding to a second simulation process according to the first model simulation result so as to obtain a project simulation result of the simulation project and outputting the project simulation result.
That is, after the second simulation process as the main process performs the final simulation operation on the corresponding second simulation model according to the first model simulation result corresponding to the first simulation process, the finally obtained project simulation result of the simulation project is output.
In an implementation manner, in this embodiment, after the project simulation result of the simulation project is obtained, any simulation process in the multiple simulation processes is further used to release the memory area. That is, the memory area may be released by any simulation process after the simulation project is completed by the simulation operation, so that the released memory space may be used for other purposes.
For example, after the second simulation process serving as the slave process caches the finally output item simulation result of the simulation item in the memory area, so that the first simulation process serving as the master process can release the memory area after reading the item simulation result from the memory area, or the second simulation process releases the memory area after the first simulation process reads the item simulation result from the memory area;
or after the first simulation process serving as the main process reads the second model simulation result corresponding to the second simulation process from the memory area and performs the final simulation operation on the corresponding first simulation model according to the second model simulation result, the memory area can be released except for outputting the finally obtained project simulation result of the simulation project, or after the first simulation process reads the second model simulation result corresponding to the second simulation process from the memory area, the memory area is released by the second simulation process.
Further, in this embodiment, when the simulation operation of the simulation item is finished, the first simulation process in the plurality of simulation processes is further configured to: and closing other simulation processes except the first simulation process in the plurality of simulation processes. For example, after the simulation operation of the simulation item is completed, the first simulation process as the master process collects the second simulation process as the slave process. Finally, in this embodiment, the first simulation process is closed, so as to achieve the purpose of releasing the process resources.
Referring to fig. 3, a schematic structural diagram of an operation control apparatus for a simulation model according to a second embodiment of the present application is provided, where the apparatus may be applied to an electronic device capable of performing data processing, such as a computer or a server. The technical scheme in the embodiment is mainly used for improving the data interaction efficiency among simulation models while realizing the simulation operation of the simulation projects of the simulation models containing different bit width parameters, thereby improving the simulation operation rate.
Specifically, the apparatus in this embodiment may include the following units:
the project obtaining unit 301 is configured to obtain a simulation project to be subjected to simulation operation, where the simulation project includes multiple simulation models;
a process starting unit 302, configured to start a plurality of simulation processes when simulation models with different bit width parameters are included in a simulation project, so that each simulation process performs simulation operation on its corresponding simulation model, so as to obtain a project simulation result of the simulation project;
the simulation models with different bit width parameters respectively correspond to different simulation processes, the transmission of simulation data is carried out between the simulation processes through a memory area, and the simulation data at least comprises a model simulation result obtained by carrying out simulation operation on the simulation models.
It can be known from the foregoing solution that, in the operation control device for a simulation model according to the second embodiment of the present application, after a simulation project to be subjected to simulation operation and including a plurality of simulation models is obtained, based on simulation models with different bit width parameters included in the simulation project, different simulation processes are started to perform simulation operation on the simulation models with the corresponding bit width parameters, respectively, so as to obtain a project simulation result of the simulation project, and in this process, transmission of simulation data, such as a model simulation result, is realized between the different simulation processes through a memory area. It can be seen that, in the present embodiment, corresponding simulation processes are started for simulation models with different bit width parameters in a simulation project to perform corresponding simulation operation processing and output a project simulation result, and meanwhile, a memory area is used in the simulation operation processing to implement data transmission between the simulation processes, so that in the present embodiment, data interaction between the processes for performing simulation operation on the simulation models with different bit width parameters is implemented by using the memory area, and finally a project simulation result of the simulation project is obtained.
In one implementation manner, the memory area is configured to cache simulation data corresponding to any simulation process in a simulation operation process, so that any other simulation process reads the simulation data in the memory area.
Specifically, the simulation data read by the simulation process in the memory area is: and the memory area is provided with simulation data in operation incidence relation with the simulation process.
In one implementation, the memory region is created by a first simulation process of the plurality of simulation processes;
wherein the first simulation process is further to: after the memory area is created, transmitting area address information of the memory area to a second simulation process in the plurality of simulation processes, so that the second simulation process receives the area address information, and the second simulation process caches second simulation data corresponding to the second simulation process in the memory area based on the area address information.
Further, the first emulation process of the plurality of emulation processes is further configured to: storing a first model simulation result obtained by performing simulation operation on a first simulation model corresponding to the first simulation process in the memory area, so that a second simulation process in the multiple simulation processes reads the first model simulation result in the memory area and performs simulation operation on a second simulation model corresponding to the second simulation process according to the first model simulation result to obtain a project simulation result of the simulation project;
wherein the second simulation process is further to: and storing the project simulation result of the simulation project into the memory area, so that the first simulation process reads the project simulation result of the simulation project in the memory area and outputs the project simulation result.
Or, the first simulation process of the plurality of simulation processes is further configured to: and reading a second model simulation result obtained by performing simulation operation on a second simulation model corresponding to a second simulation process by the second simulation process in the plurality of simulation processes in the memory area, and performing simulation operation on a first simulation model corresponding to the first simulation process according to the second model simulation result to obtain a project simulation result of the simulation project and output the project simulation result.
In one implementation, after the project simulation result of the simulation project is obtained, any simulation process of the plurality of simulation processes is further configured to release the memory area.
In one implementation, in a case that the simulation operation of the simulation project is finished, the first simulation process of the plurality of simulation processes is further configured to: and closing other simulation processes except the first simulation process in the plurality of simulation processes.
It should be noted that, for the specific implementation of each unit in the present embodiment, reference may be made to the corresponding content in the foregoing, and details are not described here.
Referring to fig. 4, a schematic structural diagram of an electronic device according to a third embodiment of the present application is provided, where the electronic device may be an electronic device capable of performing data processing, such as a computer or a server. The technical scheme in the embodiment is mainly used for improving the data interaction efficiency among simulation models while realizing the simulation operation of the simulation projects of the simulation models containing different bit width parameters, thereby improving the simulation operation rate.
Specifically, the electronic device in this embodiment may include the following structure:
a memory 401 for storing an application program and data generated by the application program;
a processor 402 for executing an application to implement: acquiring a simulation project to be simulated and operated, wherein the simulation project comprises a plurality of simulation models; starting a plurality of simulation processes under the condition that the simulation projects contain simulation models with different bit width parameters, so that each simulation process respectively carries out simulation operation on the corresponding simulation model to obtain a project simulation result of the simulation project; the simulation models with different bit width parameters respectively correspond to different simulation processes, the transmission of simulation data is carried out between the simulation processes through a memory area, and the simulation data at least comprises a model simulation result obtained by carrying out simulation operation on the simulation models.
According to the scheme, after the simulation project to be subjected to simulation operation and including the multiple simulation models is obtained, different simulation processes are started to respectively perform simulation operation on the simulation models with the corresponding bit width parameters based on the simulation models with the different bit width parameters included in the simulation project, so that a project simulation result of the simulation project is obtained, and in the process, transmission of simulation data such as a model simulation result is achieved among the different simulation processes through a memory area. It can be seen that, in the present embodiment, corresponding simulation processes are started for simulation models with different bit width parameters in a simulation project to perform corresponding simulation operation processing and output a project simulation result, and meanwhile, a memory area is used in the simulation operation processing to implement data transmission between the simulation processes, so that in the present embodiment, data interaction between the processes for performing simulation operation on the simulation models with different bit width parameters is implemented by using the memory area, and finally a project simulation result of the simulation project is obtained.
Taking the combined simulation of the FMUs with two bit widths of 32 bits and 64 bits in the same simulation project on the server as an example, the technical scheme of the application aims to realize that: when the 32-bit FMU model and the 64-bit FMU model are subjected to combined simulation operation, mixed real-time simulation operation of the 32-bit FMU and the 64-bit FMU in the same simulation system is achieved, the correctness of a simulation result is guaranteed, meanwhile, the maximization of the simulation operation speed is achieved in the simulation operation of the 32-bit FMU and the 64-bit FMU in a coexistence mode, and the simulation efficiency is greatly improved.
In a specific implementation, after the simulation tool is loaded, the simulation tool communicates with a simulation operation engine process (also referred to as a "simulation engine") through a transmission Control protocol (tcp) (transmission Control protocol) module. The simulation engine is used for realizing the simulation operation of the simulation model, and the operation result is transmitted back to the simulation tool in real time through the TCP module.
On the basis of the above scheme, in the technical scheme of the application, the maximization of the operation speed during the joint simulation of the 32-bit FMU and the 64-bit FMU is realized by sharing the memory read-write address among multiple processes, and the problem of low simulation speed is solved. Specifically, in the technical scheme of the application, a main engine (SE-master) process running a 64-bit FMU and a slave engine (SE-slave) process running a 32-bit FMU share a memory address, as shown in fig. 5, a method of reading and writing simulation data to be interacted on the shared memory address greatly improves the data exchange speed between 32-bit 64-bit FMU, and thus greatly improves the speed of joint simulation.
In another implementation manner, the master engine may run a 32-bit FMU, and the slave engine may run a 64-bit FMU, as shown in fig. 6, and all the solutions formed are within the protection scope of the present application.
With reference to the flowchart shown in fig. 7, a specific implementation flow for implementing the multi-FMU joint simulation in the present application is as follows:
firstly, after a simulation system project is loaded in a simulation tool and a user starts simulation, the simulation tool identifies whether the 32-bit FMU and 64-bit FMU combined simulation exists in the simulation project. If the simulation system engineering with 32-bit 64-bit FMU coexists, the method is operated according to the following steps:
1) starting an SE-master process;
2) the SE-master process creates a section of memory address for subsequent data interaction with the slave process;
3) the SE-master process pulls up the SE-slave process and informs the SE-slave process of the address of the shared memory and all 32-bit FMU information in the simulation engineering;
4) the SE-master process uses the initialization data to carry out the operation of 64-bit FMU;
5) the SE-master process writes the operation result of the 64-bit fmu into the shared memory address;
6) the SE-slave process carries out simulation operation of the 32-bit FMU, reads an operation result of the 64-bit FMU from the shared memory address according to the connection relation to serve as an input value of the 32-bit FMU of the process, and writes the operation result into the shared memory address;
7) the SE-master process reads the operation result of the SE-slave according to the connection relation and uses the operation result as the input of a 64-bit FMU to carry out the simulation operation of the next beat;
8) the SE-master process transmits all FMU (32-bit/64-bit FMU) operation results of the beat back to the simulation tool;
and repeating the steps 4) to 8) until the simulation is finished.
And after the simulation is finished, the SE-master process or the SE-slave process reclaims the shared memory, and the SE-master process terminates the recovery of the SE-slave process.
To sum up, in the technical scheme of the application, data interaction between processes is realized through inter-process shared memory addresses, and the condition that the data interaction between the processes is lower due to the difference from tcp communication realization is different, so that the operation speed is maximized when the 32-bit 64-bit FMU is subjected to combined simulation, and the efficiency of simulation software is greatly improved. For example, in a 32-bit and 64-bit fmu combined simulation project, the simulation time length is 10000s, the simulation step length is 0.05s, the scheme for realizing data interaction between processes by tcp communication needs to run for 10000s at the maximum speed, the technical scheme of the application only needs to run for 305s at the maximum speed, and the simulation result is correct.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. An operation control method of a simulation model, comprising:
obtaining a simulation project to be simulated and operated, wherein the simulation project comprises a plurality of simulation models;
starting a plurality of simulation processes under the condition that the simulation projects contain simulation models with different bit width parameters, so that each simulation process respectively carries out simulation operation on the corresponding simulation model to obtain a project simulation result of the simulation project;
the simulation models with different bit width parameters respectively correspond to different simulation processes, the transmission of simulation data is carried out between the simulation processes through a memory area, and the simulation data at least comprises a model simulation result obtained by carrying out simulation operation on the simulation models.
2. The method according to claim 1, wherein the memory area is used for caching corresponding simulation data of any simulation process in a simulation operation process, so that any other simulation process reads the simulation data in the memory area.
3. The method of claim 2, wherein the emulation data read by the emulation process in the memory region is: and the memory area is provided with simulation data in operation incidence relation with the simulation process.
4. The method of claim 2, wherein the memory region is created by a first emulation process of the plurality of emulation processes;
wherein the first simulation process is further to: after the memory area is created, transmitting area address information of the memory area to a second simulation process in the plurality of simulation processes, so that the second simulation process receives the area address information, and the second simulation process caches second simulation data corresponding to the second simulation process in the memory area based on the area address information.
5. The method of claim 1 or 2, wherein the first emulation process of the plurality of emulation processes is further configured to: storing a first model simulation result obtained by performing simulation operation on a first simulation model corresponding to the first simulation process in the memory area, so that a second simulation process in the multiple simulation processes reads the first model simulation result in the memory area and performs simulation operation on a second simulation model corresponding to the second simulation process according to the first model simulation result to obtain a project simulation result of the simulation project;
wherein the second simulation process is further to: and storing the project simulation result of the simulation project into the memory area, so that the first simulation process reads the project simulation result of the simulation project in the memory area and outputs the project simulation result.
6. The method of claim 1 or 2, wherein the first emulation process of the plurality of emulation processes is further configured to: and reading a second model simulation result obtained by performing simulation operation on a second simulation model corresponding to a second simulation process by the second simulation process in the plurality of simulation processes in the memory area, and performing simulation operation on a first simulation model corresponding to the first simulation process according to the second model simulation result to obtain a project simulation result of the simulation project and output the project simulation result.
7. The method of claim 1 or 2, wherein any of the plurality of simulation processes is further configured to release the memory region after obtaining the project simulation result of the simulation project.
8. The method of claim 1 or 2, wherein in the event that the simulation operation of the simulation project ends, the first simulation process of the plurality of simulation processes is further configured to: and closing other simulation processes except the first simulation process in the plurality of simulation processes.
9. An operation control device of a simulation model, comprising:
the simulation system comprises a project obtaining unit, a simulation unit and a simulation unit, wherein the project obtaining unit is used for obtaining a simulation project to be simulated and operated, and the simulation project comprises a plurality of simulation models;
the process starting unit is used for starting a plurality of simulation processes under the condition that the simulation projects contain simulation models with different bit width parameters, so that each simulation process respectively carries out simulation operation on the corresponding simulation model to obtain a project simulation result of the simulation project;
the simulation models with different bit width parameters respectively correspond to different simulation processes, the transmission of simulation data is carried out between the simulation processes through a memory area, and the simulation data at least comprises a model simulation result obtained by carrying out simulation operation on the simulation models.
10. An electronic device, comprising:
the memory is used for storing an application program and data generated by the running of the application program;
a processor for executing the application to implement: obtaining a simulation project to be simulated and operated, wherein the simulation project comprises a plurality of simulation models; starting a plurality of simulation processes under the condition that the simulation projects contain simulation models with different bit width parameters, so that each simulation process respectively carries out simulation operation on the corresponding simulation model to obtain a project simulation result of the simulation project; the simulation models with different bit width parameters respectively correspond to different simulation processes, the transmission of simulation data is carried out between the simulation processes through a memory area, and the simulation data at least comprises a model simulation result obtained by carrying out simulation operation on the simulation models.
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