CN112886963B - Variable parameter sine jitter signal injection method for error rate test equipment - Google Patents
Variable parameter sine jitter signal injection method for error rate test equipment Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D30/00—Reducing energy consumption in communication networks
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Abstract
The invention relates to a variable parameter sine jitter signal injection method for error rate test equipment, which belongs to the technical field of integrated circuits, wherein a code pattern generating part of the error rate test equipment comprises a point frequency source, a direct frequency synthesizer I, an FPGA controller, a direct frequency synthesizer II, a phase discriminator, a high-speed operational amplifier, a voltage-controlled oscillator, a frequency divider and a code pattern generator, and the variable parameter sine jitter signal injection method adopts the equipment and comprises the following steps: the point frequency source is divided into two paths to provide reference clock signals; the FPGA controller respectively sends control signals to the two direct frequency synthesizers to enable the two direct frequency synthesizers to output sinusoidal signals; summing a sinusoidal signal output by the first direct frequency synthesizer and a phase-discriminated voltage in the phase-locked loop; and then the output signal of the voltage-controlled oscillator is sent to the code pattern generator, and the output of the phase-locked loop is connected to the output jitter signal of the code pattern generator, so that the problems that the parameters of the jitter signal generated in the prior art are relatively constant and the amplitude control effect is not ideal are solved.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a variable parameter sine jitter signal injection method for bit error rate test equipment.
Background
Jitter is defined as the short-term deviation of a signal from its ideal time position at a particular time and can be characterized by the peak-to-peak value of the positional deviation over a specified frequency range. Jitter is one of the core contents of signal integrity tests of digital systems, and is the most important measurement parameter of clock and serial signals.
For bit error rate testing equipment, it is often necessary to verify how tolerant the transmission system under test is to bad signals. Therefore, the bit error rate test equipment is required to be capable of generating a bad signal with controllable jitter frequency and amplitude and sending the bad signal to a receiving end of a tested transmission system, and then observing the tolerance capability of the bad signal through the eye diagram or the bit error rate change of an oscilloscope. The process of generating the accurate controllable bad signal by the bit error rate test equipment is jitter injection.
In the prior art, a method of changing the jitter frequency by multiplying a jitter signal by a frequency multiplier is adopted for jitter injection to generate different jitter signals, parameters are relatively constant, the control effect of the amplitude is not ideal, and improvement is needed.
Disclosure of Invention
The invention provides a variable parameter sine jitter signal injection method for bit error rate test equipment, and aims to solve the problems that the parameters of jitter signals generated in the prior art are relatively constant and the amplitude control effect is not ideal.
A code pattern generating part of the bit error rate testing device comprises a point frequency source, a first direct frequency synthesizer, an FPGA controller, a second direct frequency synthesizer, a phase discriminator, a high-speed operational amplifier, a voltage-controlled oscillator, a frequency divider and a code pattern generator.
The dot frequency source is used for respectively providing reference clocks for the first direct frequency synthesizer and the second direct frequency synthesizer.
And the FPGA controller respectively sends control word signals to the direct frequency synthesizer I and the direct frequency synthesizer II to carry out frequency control and phase control.
And the direct frequency synthesizer II, the phase discriminator, the high-speed operational amplifier, the voltage-controlled oscillator and the frequency divider form a phase-locked loop to generate a first clock source.
The first direct frequency synthesizer is used as a second clock source, connected with the phase-locked loop through the high-speed operational amplifier and mainly used for providing a modulation signal.
The signal is modulated by adjusting the locking voltage of the voltage-controlled oscillator, and the output of the phase-locked loop is connected to the code pattern generator to output a jitter signal.
Further, modulating the signal by adjusting the locking voltage of the voltage controlled oscillator comprises the following steps:
designing an adder circuit through a high-speed operational amplifier;
after the modulation signal is shaped, the voltage is locked and summed through an adder circuit and a phase-locked loop;
and the modulation is carried out on the voltage control pin of the voltage-controlled oscillator to realize the modulation of the output frequency of the phase-locked loop.
Further, the phase-locked loop locking voltage is related to the selected voltage-controlled oscillator model and the frequency band output by the phase-locked loop.
Further, both the first and second direct frequency synthesizers employ direct frequency synthesizers with 32-bit frequency resolution and 12-bit amplitude resolution.
Furthermore, the sampling clock of the point frequency source adopts 2.5GHz, and the corresponding frequency resolution is 2.5GHz/2320.6Hz, amplitude resolution 1/212And introducing the modulation signal into the output signal after the phase-locked loop is performed, wherein the frequency of the modulation signal is 0.2 mV.
Further, if the output frequency of the direct frequency synthesizer one and the output frequency of the direct frequency synthesizer two are more than 400MHz, the direct frequency synthesizers with frequency resolution higher than 32 bits and amplitude resolution higher than 12 bits are selected.
The invention also provides a variable parameter sine jitter signal injection method for the error rate test equipment, which adopts the error rate test equipment and comprises the following steps:
s1: the point frequency source provides a reference clock signal for the first direct frequency synthesizer and the second direct frequency synthesizer respectively, and the frequency of the reference clock signal is related to the frequency range of the final output signal and the parameters of the frequency divider;
s2: the FPGA controller sends a control signal to the first direct frequency synthesizer to enable the first direct frequency synthesizer to output a jitter frequency fjitterAmplitude of VrmsOf sinusoidal signals, VrmsThe calculation formula of (2) is as follows:
in the above formula, AppIs the jitter amplitude in units of UI; f. ofjitterJitter frequency in MHz; s is the voltage control sensitivity of the voltage controlled oscillator, and the unit is MHz/V; 0.45 is a normalized frequency modulation constant;
s3: the FPGA controller sends a control signal to the direct frequency synthesizer IISo that its output frequency is f1Amplitude of V1Of sinusoidal signal f1The calculation formula of (2) is as follows:
in the above formula, fBClock frequency corresponding to code rate, unit MHz; n is the frequency division coefficient of the frequency divider; amplitude V1The value of (c) depends on the effective amplitude input range of the phase detector in the circuit;
s4: through an equivalent low-noise addition circuit of the high-speed operational amplifier, a sinusoidal signal output by the direct frequency synthesizer I is summed with a phase discrimination voltage in a phase-locked loop consisting of the direct frequency synthesizer II, the phase discriminator, the voltage-controlled oscillator and the frequency divider, so that jitter injection of an output signal of the voltage-controlled oscillator can be realized;
s5: the output signal of the voltage-controlled oscillator is sent to the code pattern generator as a clock signal generated by the code pattern generator, the jitter characteristic of the clock signal can be transmitted to the output signal of the code pattern generator, and the loop output of the phase-locked loop is connected to the code pattern generator to output the jitter signal;
at this point, the injection of the variable parameter sine jitter signal is completed.
Further, the frequency of the reference clock signal is 2.5GHz, which is related to the frequency range of the final output signal and the parameters of the frequency divider.
Further, the point frequency source in S1 provides a reference clock equal to or greater than 2.5 times the output frequency of the direct frequency synthesizer.
Furthermore, the frequency range of the output clock signal of the voltage-controlled oscillator in the S1 is 8GHz to 16GHz, the frequency division coefficient of the frequency divider is configured to be 25 to 50 correspondingly, the frequency of the output signal of the direct frequency synthesizer two is 320MHz, and the reference clock provided by the dot frequency source is greater than or equal to 800 MHz.
Further, the amplitude V in S31The value of (A) is constant at 0.5V.
Further, the frequency range of the clock signal output by the voltage-controlled oscillator in S5 is 8GHz to 16GHz, and if clock signals of other frequency bands are required, the clock signal can be obtained by performing frequency multiplication or frequency division on the signal.
The beneficial technical effects obtained by the invention are as follows:
the jitter injection method which takes the frequency modulation technology as the core and takes the high-speed digital control as the assistance is adopted, the sine jitter injection effect which has long amplitude time interval and variable parameters in the effective jitter frequency range is realized, the jitter injection function requirement of the error rate testing equipment can be effectively met, and the problems that the jitter signal parameters generated by the prior art are relatively constant and the amplitude control effect is not ideal are solved.
Drawings
FIG. 1 is a block diagram of a code pattern generation section according to an embodiment of the present invention.
Detailed Description
The following detailed description of the present invention is provided in conjunction with the accompanying drawings, and specific details such as specific system configurations, model numbers, technical parameters, etc., set forth in the following description are set forth merely to provide a better understanding of the present invention, and are not intended to limit the scope of the invention. In addition, those that should be known and understood by those skilled in the art will not be described in detail herein.
The structure of the code pattern generating part of the error rate testing device is shown in figure 1, and the error rate testing device realizes the injection of the variable parameter sine jitter signal of the code element signal by using a local oscillator signal generator with frequency modulation input to provide a local oscillator clock for the code pattern generator. The generation of a jitter signal source is realized through two clock modulations, and a first clock source generates a high-frequency clock signal; the second clock source generates a relatively low frequency clock signal for modulating the first clock source; the modulated signal is sent to the code pattern generator as local oscillator clock, and the code pattern generator outputs jitter signal.
The code pattern generating part in this embodiment includes a point frequency source 1, a first direct frequency synthesizer 2, an FPGA controller 3, a second direct frequency synthesizer 4, a phase detector 5, a high-speed operational amplifier 6, a Voltage Controlled Oscillator (VCO)7, a frequency divider 8, and a code pattern generator 9.
The dot frequency source 1 is used to provide reference clocks for the direct frequency synthesizer one 2 and the direct frequency synthesizer two 4, respectively.
And the FPGA controller 3 respectively sends control word signals to the first direct frequency synthesizer 2 and the second direct frequency synthesizer 4 to carry out frequency control and phase control.
And the direct frequency synthesizer II 4, the phase discriminator 5, the high-speed operational amplifier 6, the voltage-controlled oscillator 7 and the frequency divider 8 form a phase-locked loop to generate a first clock source.
The direct frequency synthesizer one 2 is used as a second clock source, connected with the phase-locked loop through the high-speed operational amplifier 6, and is mainly used for providing a modulation signal.
The method is characterized in that a mode of adjusting the locking voltage of a voltage-controlled oscillator 7 is adopted to modulate signals, a specific implementation mode is that an adder circuit is designed through a high-speed operational amplifier 6, after the modulation signals are shaped, the adder circuit and the locking voltage of a phase-locked loop are summed, and then the sum is loaded to a voltage control pin of the voltage-controlled oscillator 7, so that the modulation of the output frequency of the phase-locked loop is realized. Connecting the phase locked loop output to the pattern generator 9 may output a jitter signal. Wherein the phase-locked loop locking voltage is related to the selected type of voltage-controlled oscillator 7 and the frequency band output by the phase-locked loop.
Because the precision required for the jitter frequency and amplitude is high, in this embodiment, a direct frequency synthesizer with 32-bit frequency resolution and 12-bit amplitude resolution is used to generate the modulation signal, and if the sampling clock of the dot frequency source 1 is 2.5GHz, the corresponding frequency resolution is 2.5GHz/2320.6Hz, amplitude resolution 1/212The high-precision adjustment resolution can be realized by 0.2mV, and the modulation signal is introduced into the output signal after the phase-locked loop. If the direct frequency synthesizer meets the requirement that the output frequency is larger than 400MHz, the direct frequency synthesizer with higher frequency resolution and amplitude resolution can also meet the application requirement.
A variable parameter sine jitter signal injection method for bit error rate test equipment comprises the following steps:
s1: the dot frequency source 1 provides reference clock signals for the direct frequency synthesizer one 2 and the direct frequency synthesizer two 4 respectively, the frequency of the reference clock signal in the embodiment is 2.5GHz, and the frequency of the reference clock signal is related to the frequency range of the final output signal and the parameters of the frequency divider;
in this embodiment, the frequency range of the clock signal output by the voltage-controlled oscillator 7 is 8GHz to 16GHz, the frequency division coefficient of the frequency divider is configured to be 25 to 50 correspondingly, the frequency of the output signal of the direct frequency synthesizer two 4 is 320MHz, and according to the principle that the output frequency of the direct frequency synthesizer is not greater than 0.4 times of the input clock, that is, the reference clock provided by the dot frequency source 1 is greater than or equal to 800MHz according to the principle that the output frequency of the dot frequency source 1 is greater than or equal to 2.5 times of the output frequency of the direct frequency synthesizer, the frequency of the output signal of the direct frequency synthesizer one 2 is lower, so the reference clock provided by the dot frequency source 1 for the direct frequency synthesizer two 4 is also applicable to the direct frequency synthesizer one 2.
S2: the FPGA controller 3 sends a control signal to the direct frequency synthesizer I2 to enable the output frequency of the direct frequency synthesizer I to be fjitterAmplitude of VrmsOf the sinusoidal signal. Wherein f isjitterFor dithering frequency, VrmsThe calculation formula of (2) is as follows:
in the above formula, AppIs the jitter amplitude in units of UI (unit interval, 1UI corresponds to the duration of one bit of the data signal); f. ofjitterJitter frequency in MHz; s is the voltage control sensitivity of the voltage controlled oscillator 7, and the unit is MHz/V; 0.45 is a normalized frequency modulation constant;
s3: the FPGA controller 3 sends a control signal to the direct frequency synthesizer II 4 to enable the output frequency of the direct frequency synthesizer II to be f1Amplitude of V1Of the sinusoidal signal. Wherein, in this embodiment V1Constant at 0.5V, which depends on the effective amplitude input range of the phase detector in the circuit, different phase detectors require difference in input signal amplitude, f1The calculation formula of (2) is as follows:
in the above formula, fBClock frequency corresponding to code rate, unit MHz; n is the frequency division coefficient of the frequency divider;
s4: through an equivalent low-noise addition circuit of the high-speed operational amplifier 6, a sinusoidal signal output by the direct frequency synthesizer I2 is summed with a phase discrimination voltage in a phase-locked loop consisting of the direct frequency synthesizer II 4, the phase discriminator 5, the voltage-controlled oscillator 7 and the frequency divider 8, so that jitter injection of an output signal of the voltage-controlled oscillator 7 can be realized;
s5: the output signal of the voltage-controlled oscillator 7 is sent to the code pattern generator 9 as the clock signal generated by the code pattern generator 9, the jitter characteristic of the clock signal can be transmitted to the output signal of the code pattern generator 9, and the phase-locked loop output is connected to the code pattern generator (9) and can output the jitter signal;
at this point, the injection of the variable parameter sine jitter signal is completed.
In this embodiment, the frequency range of the clock signal output by the voltage-controlled oscillator 7 is 8GHz to 16GHz, and if clock signals of other frequency bands are required, the clock signal can be obtained by performing frequency multiplication or frequency division on the signal.
The beneficial technical effects obtained by the specific embodiment are as follows:
the method adopts a jitter injection method which takes a frequency modulation technology as a core and takes high-speed digital control as assistance to realize sine jitter injection effects that the amplitude is not less than 10UI within the jitter frequency range of 1 kHz-10 kHz and not less than 0.125UI within the jitter frequency range of 10 kHz-1 MHz, can effectively meet the jitter injection function requirement of error rate testing equipment, has variable parameters, and solves the problems of relatively constant jitter signal parameters and unsatisfactory amplitude control effect in the prior art.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent replacements, improvements, etc. within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (12)
1. The bit error rate test equipment is characterized in that a code pattern generating part of the bit error rate test equipment comprises a point frequency source (1), a direct frequency synthesizer I (2), an FPGA controller (3), a direct frequency synthesizer II (4), a phase discriminator (5), a high-speed operational amplifier (6), a voltage-controlled oscillator (7), a frequency divider (8) and a code pattern generator (9);
the point frequency source (1) is used for respectively providing reference clocks for the direct frequency synthesizer I (2) and the direct frequency synthesizer II (4);
the FPGA controller (3) respectively sends control word signals to the direct frequency synthesizer I (2) and the direct frequency synthesizer II (4) to carry out frequency control and phase control;
the direct frequency synthesizer II (4), the phase discriminator (5), the high-speed operational amplifier (6), the voltage-controlled oscillator (7) and the frequency divider (8) form a phase-locked loop to generate a first clock source;
the direct frequency synthesizer I (2) is used as a second clock source, is connected with the phase-locked loop through a high-speed operational amplifier (6) and is mainly used for providing a modulation signal;
the signal is modulated by adjusting the locking voltage of a voltage-controlled oscillator (7), and the output of a phase-locked loop is connected to a code pattern generator (9) to output a jitter signal.
2. A bit error rate test device according to claim 1, characterized in that said modulating the signal by adjusting the lock voltage of the voltage controlled oscillator (7) comprises the steps of:
designing an adder circuit through a high-speed operational amplifier (6);
after the modulation signal is shaped, the voltage is locked and summed through an adder circuit and a phase-locked loop;
and the voltage is loaded to a voltage control pin of a voltage-controlled oscillator (7) to realize the modulation of the output frequency of the phase-locked loop.
3. A bit error rate test apparatus as claimed in claim 2, wherein the phase locked loop locking voltage is related to the selected type of voltage controlled oscillator (7) and the frequency band of the phase locked loop output.
4. A bit error rate test apparatus according to claim 3, wherein the direct frequency synthesizer one (2) and the direct frequency synthesizer two (4) both use direct frequency synthesizers with 32-bit frequency resolution and 12-bit amplitude resolution.
5. A bit error rate test device according to claim 4, characterized in that the sampling clock of the point frequency source (1) is 2.5GHz, and the corresponding frequency resolution is 2.5GHz/2320.6Hz, amplitude resolution 1/212And introducing the modulation signal into the output signal after the phase-locked loop is performed, wherein the frequency of the modulation signal is 0.2 mV.
6. A bit error rate test apparatus according to claim 3, wherein the direct frequency synthesizer one (2) and the direct frequency synthesizer two (4) are selected to have a frequency resolution higher than 32 bits and an amplitude resolution higher than 12 bits if the output frequency is larger than 400 MHz.
7. A method for injecting a variable parameter sinusoidal jitter signal for a bit error rate test device, characterized in that the bit error rate test device according to any one of claims 1 to 6 is adopted, and the method comprises the following steps:
s1: the dot frequency source (1) respectively provides a reference clock signal for the direct frequency synthesizer I (2) and the direct frequency synthesizer II (4), and the frequency of the reference clock signal is related to the frequency range of the final output signal and the parameters of the frequency divider;
s2: the FPGA controller (3) sends a control signal to the direct frequency synthesizer I (2) to enable the direct frequency synthesizer I to output a jitter frequency fjitterAmplitude of VrmsOf sinusoidal signals, VrmsThe calculation formula of (2) is as follows:
in the above formula, AppIs the jitter amplitude in units of UI; f. ofjitterJitter frequency in MHz; s is the voltage control sensitivity of the voltage controlled oscillator (7), and the unit is MHz/V; 0.45 is a normalized frequency modulation constant;
s3: the FPGA controller (3) sends a control signal to the direct frequency synthesizer II (4) to enable the output frequency of the direct frequency synthesizer II to be f1Amplitude of V1Sinusoidal signal of (f)1The calculation formula of (2) is as follows:
in the above formula, fBClock frequency corresponding to code rate, unit MHz; n is the frequency division coefficient of the frequency divider; amplitude V1The value of (c) depends on the effective amplitude input range of the phase detector in the circuit;
s4: through a low-noise addition circuit equivalent to a high-speed operational amplifier (6), a sinusoidal signal output by a direct frequency synthesizer I (2) is summed with a phase discrimination voltage in a phase-locked loop consisting of a direct frequency synthesizer II (4), a phase discriminator (5), a voltage-controlled oscillator (7) and a frequency divider (8), so that jitter injection of an output signal of the voltage-controlled oscillator (7) can be realized;
s5: the output signal of the voltage-controlled oscillator (7) is sent to the code pattern generator (9) as the clock signal generated by the code pattern generator, the jitter characteristic of the clock signal can be transmitted to the output signal of the code pattern generator (9), and the phase-locked loop output is connected to the code pattern generator (9) and can output the jitter signal;
at this point, the injection of the variable parameter sine jitter signal is completed.
8. The method of claim 7, wherein the reference clock signal has a frequency of 2.5GHz depending on the frequency range of the final output signal and the parameters of the frequency divider.
9. The method according to claim 8, wherein in step S1, the reference clock provided by the dot frequency source (1) is equal to or greater than 2.5 times the output frequency of the direct frequency synthesizer.
10. The method according to claim 9, wherein in S1, the frequency range of the output clock signal of the voltage controlled oscillator (7) is 8GHz to 16GHz, the division factor of the frequency divider is configured to be 25 to 50 correspondingly, the frequency of the output signal of the direct frequency synthesizer two (4) is 320MHz, and the reference clock provided by the dot frequency source is greater than or equal to 800 MHz.
11. The method of claim 10, wherein in S3, the amplitude V is set to be smaller than the amplitude V of the sinusoidal jitter signal1The value of (A) is constant at 0.5V.
12. The method according to claim 11, wherein in S5, the frequency range of the output clock signal of the voltage controlled oscillator (7) is 8 GHz-16 GHz, and the output clock signal can be obtained by frequency doubling or frequency division if clock signals in other frequency bands are required.
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| CN114024636B (en) * | 2022-01-07 | 2022-04-15 | 中星联华科技（北京）有限公司 | Jitter injection method, device and storage medium |
| CN114499511B (en) * | 2022-01-14 | 2023-03-28 | 中星联华科技（北京）有限公司 | Jitter signal injection device, system and method suitable for code pattern generator |
| CN114430262B (en) * | 2022-01-14 | 2023-03-28 | 中星联华科技（北京）有限公司 | Phase adjusting device, system and method suitable for code pattern generator |
| CN114594825B (en) * | 2022-03-28 | 2024-04-12 | 深圳市爱普泰科电子有限公司 | System and method for generating jittered clock signal |
| CN117375642B (en) * | 2023-12-06 | 2024-04-02 | 杭州长川科技股份有限公司 | Signal transmitting device, tester and signal output method thereof |
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