CN112885843A - Display substrate, manufacturing method thereof and display device - Google Patents
Display substrate, manufacturing method thereof and display device Download PDFInfo
- Publication number
- CN112885843A CN112885843A CN201911203895.8A CN201911203895A CN112885843A CN 112885843 A CN112885843 A CN 112885843A CN 201911203895 A CN201911203895 A CN 201911203895A CN 112885843 A CN112885843 A CN 112885843A
- Authority
- CN
- China
- Prior art keywords
- line
- sub
- display substrate
- pixel
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 205
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 230000005540 biological transmission Effects 0.000 claims abstract description 105
- 230000008054 signal transmission Effects 0.000 claims abstract description 76
- 229910052751 metal Inorganic materials 0.000 claims description 75
- 239000002184 metal Substances 0.000 claims description 75
- 239000003990 capacitor Substances 0.000 claims description 32
- 238000003860 storage Methods 0.000 claims description 25
- 239000010409 thin film Substances 0.000 claims description 25
- 230000003071 parasitic effect Effects 0.000 claims description 17
- 230000006698 induction Effects 0.000 claims description 10
- 230000008878 coupling Effects 0.000 claims description 9
- 238000010168 coupling process Methods 0.000 claims description 9
- 238000005859 coupling reaction Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 2
- 230000008439 repair process Effects 0.000 abstract description 13
- 239000010410 layer Substances 0.000 description 100
- 238000005452 bending Methods 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000002159 abnormal effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 230000001154 acute effect Effects 0.000 description 2
- 230000007123 defense Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- -1 region Substances 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention provides a display substrate, a manufacturing method thereof and a display device, wherein the display substrate comprises a grid line extending along a first direction and a data line extending along a second direction, and the grid line and the data line are intersected to form a plurality of sub-pixel regions; the grid line comprises first transmission sections and second transmission sections which are alternately arranged, wherein the second transmission sections comprise at least two signal transmission lines, each signal transmission line is respectively connected with two adjacent first transmission sections in the first direction, and the orthographic projection of the data line on the substrate base plate and the orthographic projection of the signal transmission line on the substrate base plate have a superposition area; the data line includes a first portion and a second portion extending in a second direction, and a third portion connecting the first portion and the second portion, and the extending direction of the third portion forms an angle with the second direction. The display substrate, the manufacturing method thereof and the display device provided by the invention can reduce the layout difficulty of the repair structure in the display substrate and improve the manufacturing efficiency of the display device.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display substrate, a manufacturing method thereof and a display device.
Background
With the continuous progress of technology and the improvement of living standard, the demand of display is continuously increasing, and in order to meet the demand of consumers, many manufacturers have designed 8K or even higher resolution display devices.
In the related art, as PPI (number of pixels possessed per inch of screen) in the display device is higher and higher, space inside the display device is smaller and smaller, and signal lines are inevitably more and more densely gathered. This may cause the spatial design of a repair structure (repair) for improving the yield of the product to be very difficult.
Disclosure of Invention
Embodiments of the present invention provide a display substrate, a method for manufacturing the same, and a display device, so as to alleviate the problem that spatial design of a repair structure is very difficult in a high PPI display device in the related art.
In order to solve the above technical problems, the present invention provides the following technical solutions:
in a first aspect, an embodiment of the present invention provides a display substrate, including a gate line extending along a first direction and a data line extending along a second direction, where the first direction and the second direction intersect, and the gate line and the data line intersect to form a plurality of sub-pixel regions; wherein the content of the first and second substances,
the at least one grid line comprises first transmission sections and second transmission sections which are alternately arranged, wherein the second transmission sections comprise at least two signal transmission lines, each signal transmission line is respectively connected with two adjacent first transmission sections in the first direction, and the orthographic projection of the at least one data line on the substrate base plate and the orthographic projection of the at least one signal transmission line of the at least one grid line on the substrate base plate have a superposition area;
at least one data line comprises a first part and a second part extending along the second direction, and a third part connecting the first part and the second part, wherein the extending direction of the third part forms an included angle with the second direction.
Further, a display unit in the display substrate includes a first sub-pixel, a second sub-pixel and a third sub-pixel which are sequentially arranged along the first direction, wherein two first data lines are arranged between the first sub-pixel and the second sub-pixel, a second data line is arranged between the second sub-pixel and the third sub-pixel, the second data line includes a first portion and a second portion which extend along the second direction, and a third portion which connects the first portion and the second portion, and an included angle exists between the extending direction of the third portion and the second direction.
Further, a width of the third portion of the second data line in a direction perpendicular to an extending direction thereof is greater than a width of the second portion of the second data line in the first direction.
Further, the capacitor and the transistor in the first sub-pixel are arranged symmetrically to the capacitor and the transistor in the second sub-pixel.
Further, at least one first portion of the second data line is located on the same straight line extending along the second direction, at least one second portion of the second data line is located on the same straight line extending along the second direction, and the first portion and the second portion of the second data line are located on different straight lines respectively.
Further, the second transmission section comprises a first sub-transmission section and a second sub-transmission section, and the orthographic projection of the first sub-transmission section on the substrate base plate and the orthographic projection of the two first data lines on the substrate base plate have an overlapping region; an overlapping region exists between the orthographic projection of the second sub-transmission segment on the substrate base plate and the orthographic projection of the second data line on the substrate base plate.
Furthermore, an induction line extending along the second direction is further arranged on one side, far away from the second sub-pixel, of the third sub-pixel.
Further, the second transmission section comprises a third sub-transmission section, and the orthographic projection of the third sub-transmission section on the substrate base plate and the orthographic projection of the induction line on the substrate base plate have a coincidence region.
Further, the sensing line includes a first portion and a second portion, and a width of the first portion of the sensing line in the first direction is different from a width of the second portion of the sensing line in the first direction.
Further, an orthographic projection of the first part of the sensing line on the substrate base plate and an orthographic projection of the grid line on the substrate base plate have a superposition area; the second part of the induction line is positioned between two adjacent first parts in the second direction and respectively connects the two adjacent first parts.
Further, the width of the first portion of the sensing line in the first direction is smaller than the width of the second portion of the sensing line in the first direction.
Furthermore, an auxiliary electrode line extending along the second direction is further arranged on one side, away from the second sub-pixel, of the third sub-pixel.
Further, the orthographic projection of the third sub-transmission section on the substrate base plate also has an overlapping area with the orthographic projection of the auxiliary electrode line on the substrate base plate.
Further, the auxiliary electrode line includes a first portion and a second portion, and a width of the first portion of the auxiliary electrode line in the first direction is different from a width of the second portion of the auxiliary electrode line in the first direction.
Further, an orthographic projection of the first part of the auxiliary electrode line on the substrate and an orthographic projection of the grid line on the substrate have an overlapping area; the second portion of the auxiliary electrode line is located between and connects two adjacent first portions in the second direction, respectively.
Further, a width of the first portion of the auxiliary electrode line in the first direction is smaller than a width of the second portion of the auxiliary electrode line in the first direction.
Furthermore, a power line extending along the second direction is further disposed on a side of the first sub-pixel away from the second sub-pixel.
Further, the second transmission section comprises a fourth sub-transmission section, and an orthographic projection of the fourth sub-transmission section on the substrate base plate and an orthographic projection of the power supply line on the substrate base plate have a coincidence region.
Further, the power supply line includes a first portion and a second portion, and a width of the first portion of the power supply line in the first direction is different from a width of the second portion of the power supply line in the first direction.
Further, an orthographic projection of the first part of the power line on the substrate and an orthographic projection of the grid line on the substrate have an overlapping region; the second part of the power line is positioned between two adjacent first parts in the second direction and respectively connects the two adjacent first parts.
Further, a width of the first portion of the power line in the first direction is smaller than a width of the second portion of the auxiliary electrode line in the first direction.
Further, each sub-pixel region includes a pixel driving circuit including a first transistor, a second transistor, a third transistor, a storage capacitor, and a light emitting element;
the control electrode of the first transistor is connected with a first grid line, the first electrode of the first transistor is connected with a data line, and the second electrode of the first transistor is connected with the first polar plate of the storage capacitor;
the control electrode of the second transistor is connected with a second grid line, the first electrode of the second transistor is connected with the touch sensing line, and the second electrode of the second transistor is connected with the second plate of the storage capacitor;
a control electrode of the third transistor is connected to a second electrode of the first transistor, a first electrode of the third transistor is connected to a power supply line, and a second electrode of the third transistor is connected to the light-emitting element.
Furthermore, an insulating layer is arranged between the first polar plate of the storage capacitor and the second polar plate of the storage capacitor, the second polar plate comprises two sub-polar plates which are parallel to each other and electrically connected, the first polar plate is arranged between the two sub-polar plates of the second polar plate, and the two sub-polar plates are respectively provided with parts which are opposite to the first polar plate.
Further, the sub-pixel region includes a thin film transistor array layer on the substrate, the thin film transistor array layer includes a light-shielding pattern, a buffer layer covering the light-shielding pattern, an active layer on the buffer layer, a gate metal layer on the active layer and the buffer layer, an insulating layer covering the buffer layer, the active layer, and the gate metal layer, and a metal pattern on the insulating layer.
Furthermore, the first pole of the first transistor comprises a first via hole arranged in the thin film transistor array layer, and the first via hole penetrates through the insulating layer to enable the first metal part in the metal pattern to be connected with the active layer; the second pole of the first transistor comprises a second through hole arranged in the thin film transistor array layer, and the second through hole penetrates through the insulating layer, so that a second metal part in the metal pattern is respectively connected with the active layer and the gate metal layer.
Furthermore, the first pole of the second transistor comprises a third via hole which is arranged in the thin film transistor array layer, and the third via hole penetrates through the insulating layer, so that a third metal part in the metal pattern is connected with the active layer; the second pole of the second transistor comprises a fourth via hole and a fifth via hole which are arranged in the thin film transistor array layer, the fourth via hole penetrates through the insulating layer to enable a fourth metal portion in the metal pattern to be connected with the active layer, the fifth via hole penetrates through the insulating layer and the buffer layer, and the fourth metal portion is connected with the shading pattern through the fifth via hole.
Furthermore, the first pole of the third transistor comprises a sixth via hole opened in the thin film transistor array layer, and the sixth via hole penetrates through the insulating layer, so that a fifth metal part in the metal pattern is connected with the active layer; the second pole of the third transistor comprises a seventh via hole and an eighth via hole which are arranged in the thin film transistor array layer, the seventh via hole penetrates through the insulating layer, so that a sixth metal part in the metal pattern is connected with the active layer, the eighth via hole penetrates through the insulating layer and the buffer layer, and the sixth metal part is connected with the shading pattern through the eighth via hole.
Further, the first gate line is located between the first via and the sixth via.
Further, the first sub-transmission section is located in an area surrounded by the first via hole and the sixth via hole of the first sub-pixel and the first via hole and the sixth via hole of the second sub-pixel.
Further, the second sub-transmission section is located in an area surrounded by the first via hole and the sixth via hole of the second sub-pixel and the first via hole and the sixth via hole of the third sub-pixel.
Further, the second gate line is located between the fourth via and the eighth via.
Further, the resistance values of different data lines are all approximately equal.
Furthermore, the capacitance values of the parasitic capacitances generated by the coupling of different data lines with any other signal line are approximately equal, and the number of the parasitic capacitances generated by the coupling of different data lines with other signal lines is approximately equal.
In a second aspect, an embodiment of the present invention further provides a display device, including the display substrate as described above.
In a third aspect, an embodiment of the present invention further provides a method for manufacturing a display substrate, where the method includes:
providing a substrate base plate;
forming grid lines extending along a first direction on the substrate, wherein at least one grid line comprises first transmission sections and second transmission sections which are alternately arranged, each second transmission section comprises at least two signal transmission lines, and each signal transmission line is respectively connected with two adjacent first transmission sections in the first direction;
and forming data lines extending along a second direction on the substrate base plate, wherein an orthographic projection of at least one data line on the substrate base plate and an orthographic projection of the second transmission segment on the substrate base plate have an overlapping region, the at least one data line comprises a first part and a second part extending along the second direction and a third part connecting the first part and the second part, and the extending direction of the third part forms an included angle with the second direction.
In the technical scheme provided by the invention, each second transmission section comprises at least two signal transmission lines as a repair structure, so that when one signal transmission line and a Data line are in Short circuit (DGS for Short), the signal transmission line can be cut off, the Data signal can be ensured to be smoothly transmitted in the Data line, the grid scanning signal can be ensured to be smoothly transmitted in the other signal transmission lines, and the yield of the display device is improved. And through bending at least one data line, the space capable of accommodating the second transmission section can be reserved in the high-PPI display device, the layout difficulty of the second transmission section in the display substrate is reduced, and the manufacturing efficiency of the display device is improved. Therefore, the technical scheme provided by the invention can reduce the layout difficulty of the repair structure in the display substrate and improve the manufacturing efficiency of the display device.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a display substrate according to an embodiment of the invention;
FIG. 2 is a schematic structural diagram of two adjacent pixel units in the same row in FIG. 1;
FIG. 3 is a schematic structural diagram of the data line 120B in FIG. 2;
FIG. 4 is a cross-sectional view of the second transport section of FIG. 2 taken in a second direction;
FIG. 5 is a schematic diagram of a pixel driving circuit in a display substrate according to another embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view of the line and via locations of FIG. 2;
FIG. 7 is a cross-sectional view taken along line I-I' of FIG. 6;
FIG. 8 is a cross-sectional view taken along line II-II' of FIG. 6;
FIG. 9 is a schematic diagram illustrating the position of the parasitic capacitor in FIG. 2;
fig. 10 is a manufacturing method of a display substrate according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the related art, as PPI (number of pixels possessed per inch of screen) in the display device is higher and higher, space inside the display device is smaller and smaller, and signal lines are inevitably more and more densely gathered. This may cause the spatial design of a repair structure (repair) for improving the yield of the product to be very difficult.
Embodiments of the present invention provide a display substrate and a display device, which can solve the problem that the spatial design of the repair structure is very difficult in the high PPI display device in the related art.
The embodiment of the invention provides a display substrate, as shown in fig. 1 to 3, including a gate line 110 extending along a first direction and a data line 120 extending along a second direction, where the first direction and the second direction intersect, and the gate line 110 and the data line 120 intersect to form a plurality of sub-pixel regions 130; at least one gate line 110 includes first transmission segments 111 and second transmission segments 112 arranged alternately, where the second transmission segment 112 includes at least two signal transmission lines 1121, each signal transmission line 1121 is respectively connected to two adjacent first transmission segments 111 in the first direction, and an orthogonal projection of at least one data line 120 on a substrate and an orthogonal projection of one signal transmission line 1121 of at least one gate line 110 on the substrate have an overlapping region;
at least one data line 120 includes a first portion 121 and a second portion 122 extending along the second direction, and a third portion 123 connecting the first portion 121 and the second portion 122, wherein the extending direction of the third portion 123 forms an angle with the second direction 122.
In the embodiment of the invention, each second transmission section is used as a repair structure and comprises at least two signal transmission lines, so that when one signal transmission line and the data line generate short circuit DGS, the signal transmission line can be cut off, the data signals are ensured to be transmitted in the data line smoothly, the grid scanning signals are ensured to be transmitted in the other signal transmission lines smoothly, and the yield of the display device is improved. And through bending at least one data line, the space capable of accommodating the second transmission section can be reserved in the high-PPI display device, the layout difficulty of the second transmission section in the display substrate is reduced, and the manufacturing efficiency of the display device is improved. Therefore, the technical scheme provided by the invention can reduce the layout difficulty of the repair structure in the display substrate and improve the manufacturing efficiency of the display device.
In the embodiment of the present invention, one display unit in the display substrate may be a three-color pixel including a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B), as shown in fig. 2; other color sub-pixels such as a white sub-pixel and a yellow sub-pixel may be included.
In the embodiment of the present invention, the first direction is a horizontal direction in fig. 2 (i.e., a row direction of the pixel arrangement), and the second direction is a vertical direction in fig. 2 (i.e., a column direction of the pixel arrangement).
As shown in fig. 3, each gate line 110 includes a plurality of first transmission segments 111 and a plurality of second transmission segments 112, and the first transmission segments 111 and the second transmission segments 112 are alternately arranged and commonly transmit the same gate scan signal. The number of the signal transmission lines 1121 in the plurality of second transmission segments 112 may be uniform, for example: each second transmission segment 112 includes two signal transmission lines 1121, as shown in fig. 2; the number of signal transmission lines 1121 in the plurality of second transmission segments 112 may also be different, for example: a portion of the second transmission segment 112 includes two signal transmission lines and a portion of the second transmission segment 112 includes three signal transmission lines.
Taking an example that each second transmission segment 112 includes two signal transmission lines 1121, the cross-sectional view of the second transmission segment 112 taken along the second direction in fig. 2 is shown in fig. 4, and includes two signal transmission lines 1121 for transmitting gate scanning signals.
The second transmission segment 112 is designed to prevent the gate line 110 and the data line 120 from being short-circuited DGS and prevent the gate scan signal and the data signal from being transmitted abnormally after DGS, and when one signal transmission line in one second transmission segment 112 is short-circuited with the data line 120, the data line 120 can be recovered to normally transmit the data signal by cutting off the signal transmission line with the short-circuit, and the gate scan signal can be normally transmitted through other signal transmission lines.
The plurality of data lines 120 may be arranged with a row of sub-pixels spaced from each other, in which case, the number of the second transmission segments 112 in each gate line 110 is equal to the number of the data lines 120, that is, the orthographic projections of the plurality of second transmission segments 112 of one gate line 110 on the substrate are overlapped with the orthographic projections of the plurality of data lines on the substrate in a one-to-one correspondence.
The data line 120 includes a first portion 121 and a second portion 122 extending in the second direction, and a third portion 123 extending at an angle to the second direction. The bending angle of the third portion 123 relative to the second direction, that is, the included angle between the extending direction of the third portion 123 and the second defense line, is an acute angle.
In the embodiment of the present invention, in order to enable the second transmission segment 112 to be disposed between two sub-pixels, at least one data line is bent to make a space for the layout of the second transmission segment 112 free, so as to reduce the difficulty in the layout of the second transmission segment 112 in the display substrate and improve the manufacturing efficiency of the display device.
Further, as shown in fig. 2, the display unit in the display substrate includes a first sub-pixel 131, a second sub-pixel 132, and a third sub-pixel 133 sequentially arranged along the first direction, wherein two first data lines 120A are disposed between the first sub-pixel 131 and the second sub-pixel 132, and one second data line 120B is disposed between the second sub-pixel 132 and the third sub-pixel 133, wherein as shown in fig. 3, the second data line 120B includes a first portion 121 and a second portion 122 extending along the second direction, and a third portion 123 connecting the first portion 121 and the second portion 122, and an extending direction of the third portion 123 forms an angle with the second direction.
The data lines in this embodiment are arranged in such a way that two of the three continuous data lines are close to each other, and another data line is separated from the two data lines by one column of sub-pixels, and each display unit includes only 3 sub-pixels.
As shown in fig. 2, the second transmission segment 112 includes a first sub-transmission segment 112-1 and the second sub-transmission segment 112-2, and a first transmission segment 111 is located between the first sub-transmission segment 112-1 and the second sub-transmission segment 112-2. The first sub-transmission segment 112-1 includes at least two signal transmission lines 1121, wherein each signal transmission line 1121 is connected to two first transmission segments 111 adjacent to the first sub-transmission segment 112-1 in the first direction. The second sub-transmission segment 112-2 includes at least two signal transmission lines 1121, wherein each signal transmission line 1121 is connected to two first transmission segments 111 adjacent to the second sub-transmission segment 112-2 in the first direction.
An overlapping region exists between the orthographic projection of the first sub-transmission segment 112-1 on the substrate and the orthographic projections of the two first data lines 120A on the substrate, so that the DGS between the gate line 110 and at least one of the two first data lines 120A close to each other can be avoided; an overlapping region exists between the orthographic projection of the second sub-transmission segment 112-2 on the substrate and the orthographic projection of one second data line 120B on the substrate, so that the DGS between the one gate line 110 and the second data line 120B which is separately arranged can be avoided.
In this case, the number of the second transmission segments 112 in each gate line 110 is equal to 2/3 of the number of the data lines 120, and it can be seen that the structure shown in fig. 2 can reduce the number of the second transmission segments 112 compared to the former, thereby optimizing the spatial layout of the display substrate and reducing the manufacturing cost of the display substrate.
An orthogonal projection of at least one data line 120 on the substrate and an orthogonal projection of one signal transmission line 1121 of at least one gate line 110 on the substrate have an overlapping region, and specifically, it can be understood that an orthogonal projection of any data line 120 on the substrate and an orthogonal projection of at least two signal transmission lines in one second transmission segment 112 of the gate line 110 on the substrate have an overlapping region. As shown in fig. 2, in the two first data lines 120A disposed close to each other, an orthogonal projection of one of the two first data lines 120A on the substrate has an overlapping region with an orthogonal projection of one signal transmission line 1121 of the gate line 110 on the substrate, and an orthogonal projection of the other one of the two first data lines 120A on the substrate has an overlapping region with an orthogonal projection of the one signal transmission line 1121 of the same gate line 110 on the substrate.
As shown in fig. 3, the first portion 121 of the data line 120 is substantially parallel to the second portion 122, and both ends of the third portion 123 are connected to the first portion 121 and the second portion 122, respectively, so that the data signal is smoothly transmitted. Taking the transmission of the data signal from the first portion 121 to the second portion 122 as an example: it can be understood that the data line is bent from the end position of the first portion 121 to the beginning of the second portion 122, wherein the bent portion is the third portion 123.
The number of the first portion 121, the second portion 122, and the third portion 123 may be multiple, so that one data line 120 is bent at multiple positions, thereby making a layout space for the second transmission segments 112 distributed in multiple rows.
Further, a width of the third portion 123 of the second data line 120B in a direction perpendicular to an extending direction thereof is greater than a width of the second portion 122 of the second data line 120B in the first direction.
Since the second data line 120B is a bent and extended data line, and the length thereof is greater than that of the first data line 120A, so that the resistance of the second data line 120B is greater than that of the first data line 120A, by designing the width of the third portion 123 of the second data line 120B in the direction perpendicular to the extending direction thereof to be greater than that of the second portion 122 of the second data line 120B in the first direction, the resistance of the second data line 120B can be reduced as a whole, and thus the resistance difference between the first data line 120A and the second data line 120 can be reduced, and the delay difference of the data signal on the first data line 120A and the second data line 120 respectively can be reduced.
Further, as shown in fig. 2, the capacitor and the transistor in the first subpixel 131 are symmetrically disposed with respect to the capacitor and the transistor in the second subpixel 132.
Because the two first data lines 120A corresponding to the first sub-pixel 131 and the second sub-pixel 132 are located between the first sub-pixel 131 and the second sub-pixel 132, by symmetrically arranging the capacitor and the transistor in the first sub-pixel 131 and the capacitor and the transistor in the second sub-pixel 132, it can be ensured that the interface of the first sub-pixel 131 connected to the first data line 120A is close to the side where the second sub-pixel 132 is located, and the interface of the second sub-pixel 132 connected to the first data line 120A is close to the side where the first sub-pixel 131 is located, so that the structural design is simplified while signal connection is ensured, an additional internal structure of the sub-pixel is not required to be designed, and the manufacturing time of the display substrate is saved.
Further, as shown in fig. 3, at least one first portion 121 of the second data line 120B is located on a same straight line extending along the second direction, at least one second portion 122 of the second data line 120B is located on a same straight line extending along the second direction, and the first portion and the second portion of the second data line 120B are located on different straight lines.
In this way, the second data line 120B can be directionally extended between the straight line where the first portion 121 is located and the straight line where the second portion 122 is located, so as to be conveniently matched with the sub-pixels distributed in the array, improve the regularity of signal transmission of the display substrate, and simplify the difficulty of signal control of the display substrate.
In an alternative embodiment, as shown in fig. 2, a sensing line 140 extending along the second direction is further disposed on a side of the third sub-pixel 131 away from the second sub-pixel 132.
In this embodiment, the display substrate integrates a touch sensing function, and the sensing lines 140 are used for determining a touch position of a user when the user touches the display substrate with a finger. Specifically, the sensing line 140 is used to detect the capacitance of each touch electrode of the display substrate, and when the capacitance value of the capacitance in a partial area is detected to be changed, the area is determined as the position touched by the user. Of course, the sensing line 140 can also determine the touch position by detecting the resistance, which is not limited herein.
Further, as shown in fig. 2, the second transmission segment 112 includes a third sub-transmission segment 112-3, and an orthographic projection of the third sub-transmission segment 112-3 on the substrate base has a coincidence region with an orthographic projection of the sensing line 140 on the substrate base.
The third sub-transmission segment 112-3 includes at least two signal transmission lines 1121, wherein each signal transmission line 1121 is connected to two first transmission segments 111 adjacent to the third sub-transmission segment 112-3 in the first direction.
An overlapping region exists between the orthographic projection of the third sub-transmission section 112-3 on the substrate and the orthographic projection of the induction line 140 on the substrate, when a short circuit occurs between one signal transmission line 1121 in the third sub-transmission section 112-3 and the induction line 140, the induction line 140 can be recovered by cutting off the signal transmission line 1121 with the short circuit, so that the induction signal is normally transmitted, meanwhile, the gate scanning signal can also be normally transmitted from other signal transmission lines, and the abnormal transmission condition of the gate scanning signal and the induction signal is avoided.
In this embodiment, the third sub-transmission segment 112-3 can be used to prevent the gate line 110 and the sensing line 140 from being short-circuited, thereby improving the production yield of the display device.
The sensing line 140 includes a first portion 141 and a second portion 142, and a width of the first portion 141 of the sensing line 140 in the first direction is different from a width of the second portion 142 of the sensing line 140 in the first direction, so as to adapt to a layout space in which the data line 120 is bent.
Specifically, an orthogonal projection of the first portion 141 of the sensing line 140 on the substrate and an orthogonal projection of the gate line 110 on the substrate have an overlapping region; the second portion 142 of the sensing line 140 is located between two adjacent first portions 141 in the second direction and respectively connects the two adjacent first portions 141.
Since the orthographic projection of the sensing line 140 on the substrate coincides with the orthographic projection of the third sub-transmission segment 112-3 of the gate line 110 on the substrate, and the third sub-transmission segment 112-3 comprises at least two signal transmission lines 1121, the volume occupied by the third sub-transmission segment 112-3 is large, so that in order to make up the layout space of the third sub-transmission segment 112-3, the width of the first portion 141 of the sensing line 140 in the first direction is designed to be smaller than the width of the second portion 142 of the sensing line 140 in the first direction.
It should be noted that, when the width of the sensing line 140 conforms to the current endurance performance, the sensing line may be designed to have different widths in the first direction without affecting the touch performance of the display substrate.
In another alternative embodiment, as shown in fig. 2, an auxiliary electrode line 150 extending along the second direction is further disposed on a side of the third sub-pixel 133 away from the second sub-pixel 132.
In this embodiment, the display substrate further includes an auxiliary electrode line 150, and the auxiliary electrode line 150 is connected to the cathode in the display substrate to reduce the resistance of the cathode, so as to reduce the voltage Drop (IR Drop, a phenomenon that the voltage drops or rises on the power supply and the ground network in the integrated circuit) of the display substrate, and improve the display effect of the display device.
Further, the orthographic projection of the third sub-transmission segment 112-3 on the substrate base plate also has an overlapping area with the orthographic projection of the auxiliary electrode line 150 on the substrate base plate.
An overlapping area exists between the orthographic projection of the third sub-transmission section 112-3 on the substrate and the orthographic projection of the auxiliary electrode line 150 on the substrate, when a short circuit occurs between one signal transmission line 1121 of the third sub-transmission section 112-3 and the auxiliary electrode line 150, the auxiliary electrode line 150 can be recovered by cutting off the signal transmission line 1121 with the short circuit, so that the induction signal is normally transmitted, the gate scanning signal can be normally transmitted from other signal transmission lines, and the abnormal transmission condition of the gate scanning signal and the auxiliary electric signal is avoided.
In this embodiment, the third sub-transmission segment 112-3 can be used to prevent the gate line 110 and the auxiliary electrode line 150 from being short-circuited, thereby improving the production yield of the display device.
Under the condition that the display substrate simultaneously comprises the sensing line 140 and the auxiliary electrode line 150, the orthographic projection of the third sub-transmission section 112-3 on the substrate can be simultaneously superposed with the orthographic projection of the sensing line 140 on the substrate and the orthographic projection of the auxiliary electrode line 150 on the substrate, that is, one third sub-transmission section 112-3 can avoid the short circuit between the gate line 110 and the sensing line 140 and/or between the gate line 110 and the auxiliary electrode line 150, so that the production yield of the display device is improved. In addition, the number of the third sub-transmission segments 112-3 can be reduced, so that the material of the gate line 110 is saved, the space occupied by the gate line 110 is reduced, and the space design of the display substrate is optimized.
Further, as shown in fig. 2, the auxiliary electrode line 150 includes a first portion 151 and a second portion 152, and a width of the first portion 151 of the auxiliary electrode line 150 in the first direction is different from a width of the second portion 152 of the auxiliary electrode line 150 in the first direction, so as to adapt to a layout space where the data line 120 is bent.
Specifically, an orthogonal projection of the first portion 151 of the auxiliary electrode line 150 on the substrate has an overlapping region with an orthogonal projection of the gate line 110 on the substrate; the second portion 152 of the auxiliary electrode line 150 is located between two adjacent first portions 141 in the second direction and respectively connects the two adjacent first portions 151.
Since the orthographic projection of the auxiliary electrode line 150 on the substrate coincides with the orthographic projection of the third sub-transmission segment 112-3 of the gate line 110 on the substrate, and the third sub-transmission segment 112-3 includes at least two signal transmission lines 1121, the volume occupied by the third sub-transmission segment 112-3 is large, so that in order to make up the layout space of the third sub-transmission segment 112-3, the width of the first portion 151 of the auxiliary electrode line 150 in the first direction is designed to be smaller than the width of the second portion 152 of the auxiliary electrode line 150 in the first direction.
When the width of the auxiliary electrode line 150 is in accordance with the current resistance performance, the auxiliary electrode line may be designed to have a different width in the first direction.
In another alternative embodiment, as shown in fig. 2, a side of the first sub-pixel 131 away from the second sub-pixel 132 is further provided with a power line 160 extending along the second direction.
In this embodiment, the display substrate further includes a power line 160, and the power line 160 is used for providing a high-level signal to the electrode in the sub-pixel region to charge the electrode, so as to complete the normal light emission of the sub-pixel region.
Further, the second transmission segment 112 includes a fourth sub-transmission segment 112-4, and an orthogonal projection of the fourth sub-transmission segment 112-4 on the substrate has a coincidence region with an orthogonal projection of the power line 160 on the substrate.
The fourth sub transmission segment 112-4 includes at least two signal transmission lines 1121, wherein each signal transmission line 1121 is connected to two first transmission segments 111 adjacent to the fourth sub transmission segment 112-4 in the first direction.
When a short circuit occurs between one signal transmission line 1121 of the fourth sub-transmission segment 112-4 and the power line 160, the power line 160 can be recovered by cutting off the short-circuited signal transmission line 1121, so that a high-level signal can be normally transmitted, and meanwhile, a gate scanning signal can be normally transmitted from other signal transmission lines, thereby avoiding the occurrence of abnormal transmission of the gate scanning signal and the high-level signal.
In this embodiment, the fourth sub-transmission segment 112-4 can be used to prevent the gate line 110 and the power line 160 from being shorted, thereby improving the production yield of the display device.
Further, the power line 160 includes a first portion 161 and a second portion 162, and a width of the first portion 161 of the power line 160 in the first direction is different from a width of the second portion 162 of the power line 160 in the first direction to fit a layout space where the data line 120 is bent.
Specifically, an orthogonal projection of the first portion 161 of the power line 160 on the substrate and an orthogonal projection of the gate line 110 on the substrate have an overlapping region; the second portion 162 of the power line 160 is located between two adjacent first portions 161 in the second direction and respectively connects the two adjacent first portions 161.
Since the orthographic projection of the power line 160 on the substrate coincides with the orthographic projection of the fourth sub-transmission segment 112-4 of the gate line 110 on the substrate, and the fourth sub-transmission segment 112-4 comprises at least two signal transmission lines 1121, the volume occupied by the fourth sub-transmission segment 112-4 is large, so that in order to make up the layout space of the fourth sub-transmission segment 112-4, the width of the first portion 161 of the power line 160 in the first direction is designed to be smaller than the width of the second portion of the power line 160 in the first direction 162.
When the width of the power line 160 is in accordance with the current endurance, the power line may be designed to have different widths in the first direction without affecting the touch performance of the display substrate.
In this embodiment, the positions of the sensing line 140, the auxiliary electrode line 150 and the power line 160 are all described by the positional relationship in the pixel unit composed of the first sub-pixel 131, the second sub-pixel 132 and the third sub-pixel 133 in fig. 2. In an actual display substrate, the positions of the sensing lines, the auxiliary electrode lines and the power lines are not completely applicable to other pixel units, such as: the sensing line and the auxiliary electrode line may be located at a side where the two sub-pixels close to each other are far from the separately disposed sub-pixels, and the power line is located at a side where the separately disposed sub-pixels are far from the two sub-pixels close to each other.
In another alternative embodiment, as shown in fig. 5, each sub-pixel region includes a pixel driving circuit 134 including a first transistor T1, a second transistor T2, a third transistor T3, a storage capacitor Cst, and a light emitting element EL;
a control electrode of the first transistor T1 is connected to a first gate line G1, a first electrode of the first transistor T1 is connected to a Data line Data, and a second electrode of the first transistor T1 is connected to a first plate of the storage capacitor Cst;
a control electrode of the second transistor T2 is connected to a second gate line G2, a first electrode of the second transistor T2 is connected to the sensing line 140, and a second electrode of the second transistor T2 is connected to the second plate of the storage capacitor Cst;
a control electrode of the third transistor T3 is connected to the second electrode of the first transistor T1, a first electrode of the third transistor T3 is connected to the power supply line 160, and a second electrode of the third transistor T3 is connected to the light emitting element EL.
In this embodiment, the pixel driving circuit is designed by 3T1C, and the sub-pixels can achieve both the display function and the touch sensing function by time-sharing driving.
In the display period, the first gate line G1 provides a turn-on signal to the first transistor T1, turning on between the first pole of the first transistor T1 and the second pole of the first transistor T1; the second gate line G2 provides a turn-off signal to the second transistor T2 to turn off between the first electrode of the second transistor T2 and the second electrode of the second transistor T2, so that the data signal in the data line Date can be written into the storage capacitor Cst to drive the light emitting element EL to emit light.
In the sensing period, the first gate line G1 provides a turn-off signal to the first transistor T1, turning off between the first pole of the first transistor T1 and the second pole of the first transistor T1; the second gate line G2 provides a turn-on signal to the second transistor T2 to turn on the first electrode of the second transistor T2 and the second electrode of the second transistor T2, so that the sensing signal in the sensing line 140 can be written into the storage capacitor Cst to detect whether there is a touch on the screen.
The pixel driving circuit may further include an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC), and the two switches (S1 and S2) are respectively used to control the connection between the ADC and the DAC and the sensing line 140, so as to help the sensing line 140 to implement the touch sensing function.
Further, as shown in fig. 5, an insulating layer is disposed between the first plate 410 of the storage capacitor Cst and the second plate 420 of the storage capacitor Cst, the second plate includes two sub-plates (421 and 422) that are parallel to each other and electrically connected, the first plate 410 is disposed between the two sub-plates (421 and 422) of the second plate 420, and the two sub-plates (421 and 422) respectively have portions facing the first plate 410.
In this embodiment, the storage capacitor Cst is made of three substantially parallel plates.
The second plate 420 of the storage capacitor Cst is set as two sub-plates (421 and 422) parallel to each other, and the sub-plates are respectively opposite to the first plate, and when the total area of the opposite surfaces of the first plate 410 and the second plate 420 is equal to the total area of the opposite surfaces of the two layers of plates in the related art, the size of the storage capacitor Cst can be reduced under the condition that the storage capacitance value is not changed, so that the size of a Gate Driver on Array (GOA for short) circuit is reduced, and the internal space of the high PPI device is convenient to optimize.
The second plate 420 of the storage capacitor Cst is configured as two sub-plates (421 and 422) parallel to each other, and the total area of the first plate 410 and the second plate 420 facing each other can be doubled without changing the size of the storage capacitor Cst, so as to increase the storage capacitance of the storage capacitor Cst.
In an alternative embodiment, as shown in fig. 7 and 8, fig. 7 is a sectional view taken along line i-i 'of fig. 6, fig. 8 is a sectional view taken along line ii-ii' of fig. 6, and fig. 6 is the same as fig. 2. The sub-pixel region 130 includes a thin film transistor array layer 710 on the substrate 700, the thin film transistor array layer 710 including a light-shielding pattern 711, a buffer layer 712 covering the light-shielding pattern, an active layer 713 on the buffer layer 712, a gate metal layer (including the first gate line G1 and the second gate line G2 in fig. 6) on the active layer 713 and the buffer layer 712, an insulating layer 714 covering the buffer layer 712, the active layer 713, and the gate metal layer, and a metal pattern 715 on the insulating layer 714.
In this embodiment, the light-shielding pattern 711 is used to shield light from one side of the substrate 700, so as to prevent the light from affecting the active layer 713 and reducing the performance of each transistor, wherein the buffer layer 712 covering the light-shielding pattern 711 can provide a flat surface for the active layer 713.
The thin film transistor array layer 710 may include a first transistor T1, a second transistor T2, and a third transistor T3 as shown in fig. 5. The metal pattern 715 may include a plurality of metal portions separated from each other, the active layer 712 includes a plurality of active segments, and two metal portions are connected to the same active segment in the active layer 712 through vias to form a first pole or a second pole in the transistor. The active layer 712 may be formed of Indium Gallium Zinc Oxide (IGZO).
In addition, as shown in fig. 7, the sub-pixel region further includes a protective layer 716 covering the metal pattern 715, a resin layer 717 covering the protective layer 716, and an anode 718 covering a portion of the resin layer 717, wherein the sub-pixel region further includes a via Z penetrating through the protective layer 716 and the resin layer 717, and the anode 718 is connected to the metal pattern 715 through the via Z.
In addition, the sub-pixel region further includes a cathode 719, and a light emitting layer 720 between the anode 718 and the cathode 719. A pixel defining layer 721 is further included between the light emitting layers 720 in two adjacent sub-pixel regions for insulating the light emitting layers 720 in the two sub-pixel regions from each other.
As shown in fig. 7, the first pole of the first transistor T1 includes a first via a opened in the thin film transistor array layer 710, and the first via a penetrates through the insulating layer 714 to connect the first metal portion 7151 of the metal pattern 715 with the active layer 713; the second pole of the first transistor T1 includes a second via B opened in the thin film transistor array layer 710, and the second via B penetrates the insulating layer 714, so that the second metal portion 7152 in the metal pattern is connected to the active layer 713 and the gate metal layer, respectively.
In this embodiment, it can be seen from fig. 6 that the first metal portion 7151 is connected to the data line 120, and it can be seen from fig. 7 that the first via a penetrates the insulating layer 714 to connect the first metal portion 7151 to the first active segment 7131. It can be seen from fig. 7 that the second via B penetrates the insulating layer 714 to connect the second metal portion 7152 with the first active segment 7131 and the first gate line G1. The orthographic projections of the first via a and the second via B on the substrate base 700 are both located inside the orthographic projection of the first active segment 7131 on the substrate base 700. The orthographic projection of the second metal portion 7152 on the substrate base 700 covers the orthographic projection of the first gate line G1 on the substrate base 700.
When the first gate line G1 provides a high level signal, the first electrode (the first metal part 7151) of the first transistor T1 and the second electrode (the second metal part 7152) of the first transistor T1 are turned on, thereby transmitting a data signal to the second electrode of the first transistor T1.
As shown in fig. 7, the first pole of the second transistor T2 includes a third via C opened in the thin film transistor array layer 710, and the third via C penetrates through the insulating layer 714 to connect the third metal portion 7153 of the metal pattern 715 with the active layer 713; the second pole of the second transistor T2 includes a fourth via D and a fifth via E opened in the thin film transistor array layer 710, the fourth via D penetrates the insulating layer 714 to connect the fourth metal portion 7154 of the metal pattern 715 with the active layer 713, the fifth via E penetrates the insulating layer 714 and the buffer layer 712, and the fourth metal portion 7154 is connected with the light-shielding pattern 711 through the fifth via E.
It can be seen from fig. 7 that a third via C extends through the insulating layer 714 connecting the third metal portion 7153 with the second active segment 7132. It can be seen from fig. 7 that a fourth via D penetrates the insulating layer 714 to connect the fourth metal portion 7154 with the second active segment 7132, and a fifth via E penetrates the insulating layer 714 and the buffer layer 712. Wherein, the orthographic projection of the third via C on the substrate base plate 700, the orthographic projection of the fourth via D on the substrate base plate 700 and the orthographic projection of the second gate line G2 on the substrate base plate are all located within the orthographic projection of the second active segment 7132 on the substrate base plate 700.
When the second gate line G2 provides a high-level signal, the first pole (the third metal portion 7153) of the second transistor T2 and the second pole (the fourth metal portion 7154) of the second transistor T2 are turned on, thereby transmitting the sensing signal to the second pole of the second transistor T2.
As shown in fig. 8, the first pole of the third transistor T3 includes a sixth via F opened in the thin film transistor array layer 710, and the sixth via F penetrates through the insulating layer 714 to connect the fifth metal portion 7155 of the metal pattern 715 with the active layer 713; the second pole of the third transistor T3 includes a seventh via G and an eighth via H opened in the thin film transistor array layer 710, the seventh via G penetrates the insulating layer 714 to connect the sixth metal portion 7156 of the metal pattern 715 to the active layer 713, the eighth via H penetrates the insulating layer 714 and the buffer layer 712, and the sixth metal portion 7156 is connected to the light-shielding pattern 711 through the eighth via H.
It can be seen from fig. 6 that the fifth metal portion 7155 is connected to the power supply line 160, and from fig. 8 that a sixth via F penetrates the insulating layer 714 to connect the fifth metal portion 7155 to the third active segment 7133. As can be seen from fig. 7, the seventh via G penetrates the insulating layer 714 to connect the sixth metal portion 7156 to the third active segment 7133, and the eighth via H penetrates the insulating layer 714 and the buffer layer 712 to connect the sixth metal portion 7156 to the light-shielding pattern 711. Wherein, the orthographic projection of the sixth via hole F on the substrate base plate and the orthographic projection of the seventh via hole G on the substrate base plate are both located in the orthographic projection of the third active segment 7133 on the substrate base plate.
When the high level signal is supplied from the first gate line G1 and transmitted to the control electrode of the third transistor T3, the first electrode (the fifth metal portion 7155) of the third transistor T3 and the second electrode (the sixth metal portion 7156) of the third transistor T3 are turned on, so that the high level signal is transmitted to the second electrode of the third transistor T3 and charges the light emitting element EL.
As shown in fig. 6, the first gate line G1 is located between the first via a and the sixth via F.
As shown in fig. 6, the first sub-transmission segment 112-1 is located in an area surrounded by the first via a and the sixth via F of the first sub-pixel 131 and the first via a and the sixth via F of the second sub-pixel 132.
As shown in fig. 6, the second sub-transmission segment 112-2 is located in an area surrounded by the first via a and the sixth via F of the second sub-pixel 132 and the first via a and the sixth via F of the third sub-pixel 133.
In addition, as shown in fig. 6, the second gate line G2 is located between the fourth via D and the eighth via H.
Further, the resistance values of the different data lines 120 are all substantially equal.
In this embodiment, all the data lines 120 may be bent (i.e. include the third portion 123 having an included angle between the extending direction and the second direction), or only some of the data lines may be bent, and in any case, the resistance values of different data lines 120 are substantially equal.
The resistance of the data line 120 is calculated as: r ═ Rs × (L/W), where Rs is the unit resistance, Rs in the same process and same material, L is the total length of the data line, and W is the average width of the data line.
When all the data lines 120 are bent, the resistance values of all the data lines can be uniform by uniform the extension length of the data lines 120 and the width of each portion.
In the case where only a portion of the data lines are bent, since the length of the bent data lines is longer than the length of the straight data lines, the average width of the bent data lines needs to be larger than the average width of the straight data lines, so that the resistance of the bent data lines is equal to the resistance of the straight data lines. Specifically, the average width of the data lines may be increased by increasing the width of the third portion 123.
In this embodiment, the resistance values of all the data lines 120 in the display substrate are uniform, so that the phenomenon of transmission delay of part of data signals due to different resistances of the data lines can be avoided, and the display effect of the display device is improved.
Further, the capacitance values of the parasitic capacitances generated by the coupling of different data lines 120 and any other signal line are equal, and the number of the parasitic capacitances generated by the coupling of different data lines 120 and other signal lines is equal.
As shown in fig. 9, the data line 120 may couple with the surrounding signal lines during the process of transmitting the data signal to generate parasitic capacitance, for example: one data line 120 is coupled to each signal transmission line 1121 of the second transmission segment 112, which has an overlapping region between the orthographic projection of the data line on the substrate and the orthographic projection of the data line on the substrate, and generates a parasitic capacitance (the solid line frame in fig. 9 is the position of the parasitic capacitance), and when the display substrate further includes other signal lines, which have overlapping regions between the orthographic projection of the data line on the substrate and the orthographic projection of the data line on the substrate, the data line 120 is coupled to each signal line of the signal lines and generates a parasitic capacitance.
The magnitude of the parasitic capacitance is related to the area of the overlapping region where the orthographic projection of the signal line on the substrate and the orthographic projection of the data line 120 on the substrate overlap each other, and when the areas of the overlapping regions are equal, the parasitic capacitances generated are also equal. In this embodiment, the areas of the overlapping areas of the orthographic projection of the data line 120 on the substrate and the orthographic projection of different signal lines on the substrate are all equal, that is, the capacitance values of the parasitic capacitances generated by the data line 120 and different signal lines are all equal.
In the present embodiment, the capacitance values of the parasitic capacitances generated by coupling each data line 120 with any other signal line are equal, and the number of the parasitic capacitances generated by coupling different data lines 120 with other signal lines is equal, so that the total capacitance values of the parasitic capacitances generated by coupling different data lines 120 are equal.
Thus, when the gate line 110 enables the sub-pixels in the same row to write the data signals, the delay time of the data signals of the sub-pixels is the same, the time for writing the data signals of the sub-pixels is the same, and the display effect of the display device is ensured. For example: when gray scale display is carried out (the same gray scale data is written into the same row of sub-pixels), the same charging voltage of the sub-pixels in the same row can be ensured.
The embodiment of the invention also provides a display device which comprises the display substrate.
The display device may be a display, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, etc.
An embodiment of the present invention further provides a method for manufacturing a display substrate, as shown in fig. 10, the method includes:
step 901: providing a substrate base plate;
step 902: forming grid lines extending along a first direction on the substrate, wherein at least one grid line comprises first transmission sections and second transmission sections which are alternately arranged, each second transmission section comprises at least two signal transmission lines, and each signal transmission line is respectively connected with two adjacent first transmission sections in the first direction;
step 903: and forming data lines extending along a second direction on the substrate base plate, wherein an orthographic projection of at least one data line on the substrate base plate and an orthographic projection of the second transmission segment on the substrate base plate have an overlapping region, the at least one data line comprises a first part and a second part extending along the second direction and a third part connecting the first part and the second part, and the extending direction of the third part forms an included angle with the second direction.
In the embodiment of the invention, each second transmission section is used as a repair structure and comprises at least two signal transmission lines, so that when one signal transmission line and the data line generate short circuit DGS, the signal transmission line can be cut off, the data signals are ensured to be transmitted in the data line smoothly, the grid scanning signals are ensured to be transmitted in the other signal transmission lines smoothly, and the yield of the display device is improved. And through bending at least one data line, the space capable of accommodating the second transmission section can be reserved in the high-PPI display device, the layout difficulty of the second transmission section in the display substrate is reduced, and the manufacturing efficiency of the display device is improved. Therefore, the technical scheme provided by the invention can reduce the layout difficulty of the repair structure in the display substrate and improve the manufacturing efficiency of the display device.
In the embodiment of the present invention, one display unit in the display substrate may be a three-color pixel including a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B), as shown in fig. 2; other color sub-pixels such as a white sub-pixel and a yellow sub-pixel may be included.
In the embodiment of the present invention, the first direction is a horizontal direction (i.e., a row direction of the pixel arrangement) in fig. 2, and the second direction is a vertical direction (i.e., a column direction of the pixel arrangement) in fig. 3.
As shown in fig. 2, each gate line 110 includes a plurality of first transmission segments 111 and a plurality of second transmission segments 112, and the first transmission segments 111 and the second transmission segments 112 are alternately arranged and commonly transmit the same gate scan signal. The number of the signal transmission lines 1121 in the plurality of second transmission segments 112 may be uniform, for example: each second transmission segment 112 includes two signal transmission lines 1121, as shown in fig. 2; the number of signal transmission lines 1121 in the plurality of second transmission segments 112 may also be different, for example: a portion of the second transmission segment 112 includes two signal transmission lines and a portion of the second transmission segment 112 includes three signal transmission lines.
Taking an example that each second transmission segment 112 includes two signal transmission lines 1121, the cross-sectional view of the second transmission segment 112 taken along the second direction in fig. 2 is shown in fig. 4, and includes two signal transmission lines 1121 for transmitting gate scanning signals.
The second transmission segment 112 is designed to prevent the gate line 110 and the data line 120 from being short-circuited DGS and prevent the gate scan signal and the data signal from being transmitted abnormally after DGS, and when one signal transmission line in one second transmission segment 112 is short-circuited with the data line 120, the data line 120 can be recovered to normally transmit the data signal by cutting off the signal transmission line with the short-circuit, and the gate scan signal can be normally transmitted through other signal transmission lines.
The plurality of data lines 120 may be arranged with a row of sub-pixels spaced from each other, in which case, the number of the second transmission segments 112 in each gate line 110 is equal to the number of the data lines 120, that is, the orthographic projections of the plurality of second transmission segments 112 of one gate line 110 on the substrate are overlapped with the orthographic projections of the plurality of data lines on the substrate in a one-to-one correspondence.
The data line 120 includes a first portion 121 and a second portion 122 extending in the second direction, and a third portion 123 extending at an angle to the second direction. The bending angle of the third portion 123 relative to the second direction, that is, the included angle between the extending direction of the third portion 123 and the second defense line, is an acute angle.
In the embodiment of the present invention, in order to enable the second transmission segment 112 to be disposed between two sub-pixels, at least one data line is bent to make a space for the layout of the second transmission segment 112 free, so as to reduce the difficulty in the layout of the second transmission segment 112 in the display substrate and improve the manufacturing efficiency of the display device.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (35)
1. A display substrate comprises a grid line extending along a first direction and a data line extending along a second direction, wherein the first direction and the second direction are crossed, and the grid line and the data line are crossed to enclose a plurality of sub-pixel regions; wherein the content of the first and second substances,
the at least one grid line comprises first transmission sections and second transmission sections which are alternately arranged, wherein the second transmission sections comprise at least two signal transmission lines, each signal transmission line is respectively connected with two adjacent first transmission sections in the first direction, and the orthographic projection of the at least one data line on the substrate base plate and the orthographic projection of the at least one signal transmission line of the at least one grid line on the substrate base plate have a superposition area;
at least one data line comprises a first part and a second part extending along the second direction, and a third part connecting the first part and the second part, wherein the extending direction of the third part forms an included angle with the second direction.
2. The display substrate according to claim 1, wherein the display unit in the display substrate comprises a first sub-pixel, a second sub-pixel and a third sub-pixel which are sequentially arranged along the first direction, wherein two first data lines are arranged between the first sub-pixel and the second sub-pixel, one second data line is arranged between the second sub-pixel and the third sub-pixel, the second data line comprises a first portion and a second portion which extend along the second direction, and a third portion which connects the first portion and the second portion, and the extending direction of the third portion forms an included angle with the second direction.
3. The display substrate according to claim 2, wherein a width of the third portion of the second data line in a direction perpendicular to an extending direction thereof is larger than a width of the second portion of the second data line in the first direction.
4. The display substrate according to claim 2, wherein the capacitor and the transistor in the first subpixel are arranged symmetrically to the capacitor and the transistor in the second subpixel.
5. The display substrate according to claim 2, wherein at least one first portion of the second data line is located on a same straight line extending in the second direction, at least one second portion of the second data line is located on a same straight line extending in the second direction, and the first portion and the second portion of the second data line are located on different straight lines.
6. The display substrate according to claim 2, wherein the second transmission segment comprises a first sub transmission segment and a second sub transmission segment, and an orthographic projection of the first sub transmission segment on the substrate and an orthographic projection of the two first data lines on the substrate are overlapped; an overlapping region exists between the orthographic projection of the second sub-transmission segment on the substrate base plate and the orthographic projection of the second data line on the substrate base plate.
7. The display substrate according to claim 2, wherein a side of the third sub-pixel away from the second sub-pixel is further provided with a sensing line extending along the second direction.
8. The display substrate of claim 7, wherein the second transmission segment comprises a third sub-transmission segment, and an orthographic projection of the third sub-transmission segment on the substrate and an orthographic projection of the sensing line on the substrate have a coincidence region.
9. The display substrate according to claim 7, wherein the sensing lines comprise a first portion and a second portion, and a width of the first portion of the sensing lines in the first direction is different from a width of the second portion of the sensing lines in the first direction.
10. The display substrate of claim 9, wherein an orthographic projection of the first portion of the sensing line on the substrate and an orthographic projection of the gate line on the substrate have an overlapping region; the second part of the induction line is positioned between two adjacent first parts in the second direction and respectively connects the two adjacent first parts.
11. The display substrate of claim 10, wherein a width of the first portion of the sensing line in the first direction is smaller than a width of the second portion of the sensing line in the first direction.
12. The display substrate according to claim 8, wherein a side of the third sub-pixel away from the second sub-pixel is further provided with an auxiliary electrode line extending along the second direction.
13. The display substrate according to claim 12, wherein an orthogonal projection of the third sub-transmission segment on the substrate further has an overlapping area with an orthogonal projection of the auxiliary electrode line on the substrate.
14. The display substrate according to claim 12, wherein the auxiliary electrode lines comprise a first portion and a second portion, and a width of the first portion of the auxiliary electrode lines in the first direction is different from a width of the second portion of the auxiliary electrode lines in the first direction.
15. The display substrate according to claim 14, wherein an orthogonal projection of the first portion of the auxiliary electrode line on the substrate has an overlapping area with an orthogonal projection of the gate line on the substrate; the second portion of the auxiliary electrode line is located between and connects two adjacent first portions in the second direction, respectively.
16. The display substrate according to claim 15, wherein a width of the first portion of the auxiliary electrode line in the first direction is smaller than a width of the second portion of the auxiliary electrode line in the first direction.
17. The display substrate according to claim 2, wherein a side of the first sub-pixel away from the second sub-pixel is further provided with a power line extending along the second direction.
18. The display substrate of claim 17, wherein the second transmission segment comprises a fourth sub-transmission segment, and an orthogonal projection of the fourth sub-transmission segment on the substrate has an overlapping region with an orthogonal projection of the power line on the substrate.
19. The display substrate according to claim 17, wherein the power supply line comprises a first portion and a second portion, and wherein a width of the first portion of the power supply line in the first direction is different from a width of the second portion of the power supply line in the first direction.
20. The display substrate of claim 19, wherein an orthographic projection of the first portion of the power line on the substrate has an overlapping area with an orthographic projection of the gate line on the substrate; the second part of the power line is positioned between two adjacent first parts in the second direction and respectively connects the two adjacent first parts.
21. The display substrate according to claim 20, wherein a width of the first portion of the power supply line in the first direction is smaller than a width of the second portion of the auxiliary electrode line in the first direction.
22. The display substrate of claim 7,
each sub-pixel region includes a pixel driving circuit including a first transistor, a second transistor, a third transistor, a storage capacitor, and a light emitting element;
the control electrode of the first transistor is connected with a first grid line, the first electrode of the first transistor is connected with a data line, and the second electrode of the first transistor is connected with the first polar plate of the storage capacitor;
the control electrode of the second transistor is connected with a second grid line, the first electrode of the second transistor is connected with the sensing line, and the second electrode of the second transistor is connected with the second plate of the storage capacitor;
a control electrode of the third transistor is connected to a second electrode of the first transistor, a first electrode of the third transistor is connected to a power supply line, and a second electrode of the third transistor is connected to the light-emitting element.
23. The display substrate of claim 22, wherein an insulating layer is disposed between the first plate of the storage capacitor and the second plate of the storage capacitor, the second plate comprises two sub-plates parallel to each other and electrically connected to each other, the first plate is disposed between the two sub-plates of the second plate, and the two sub-plates respectively have portions facing the first plate.
24. The display substrate of claim 23, wherein the sub-pixel region comprises a thin film transistor array layer on the substrate, the thin film transistor array layer comprising a light-shielding pattern, a buffer layer covering the light-shielding pattern, an active layer on the buffer layer, a gate metal layer on the active layer and the buffer layer, an insulating layer covering the buffer layer, the active layer, and the gate metal layer, and a metal pattern on the insulating layer.
25. The display substrate according to claim 24, wherein the first electrode of the first transistor comprises a first via hole opened in the thin film transistor array layer, the first via hole penetrating the insulating layer to connect a first metal portion of the metal pattern with an active layer; the second pole of the first transistor comprises a second through hole arranged in the thin film transistor array layer, and the second through hole penetrates through the insulating layer, so that a second metal part in the metal pattern is respectively connected with the active layer and the gate metal layer.
26. The display substrate according to claim 25, wherein the first electrode of the second transistor comprises a third via hole opened in the thin film transistor array layer, the third via hole penetrating the insulating layer to connect a third metal portion in the metal pattern with the active layer; the second pole of the second transistor comprises a fourth via hole and a fifth via hole which are arranged in the thin film transistor array layer, the fourth via hole penetrates through the insulating layer to enable a fourth metal portion in the metal pattern to be connected with the active layer, the fifth via hole penetrates through the insulating layer and the buffer layer, and the fourth metal portion is connected with the shading pattern through the fifth via hole.
27. The display substrate according to claim 26, wherein the first pole of the third transistor comprises a sixth via hole opened in the thin film transistor array layer, the sixth via hole penetrating the insulating layer to connect a fifth metal portion in the metal pattern with the active layer; the second pole of the third transistor comprises a seventh via hole and an eighth via hole which are arranged in the thin film transistor array layer, the seventh via hole penetrates through the insulating layer, so that a sixth metal part in the metal pattern is connected with the active layer, the eighth via hole penetrates through the insulating layer and the buffer layer, and the sixth metal part is connected with the shading pattern through the eighth via hole.
28. The display substrate of claim 27, wherein the first gate line is located between the first via and the sixth via.
29. The display substrate of claim 28, wherein the first sub-transmission segment is located in an area surrounded by the first via hole and the sixth via hole of the first sub-pixel and the first via hole and the sixth via hole of the second sub-pixel.
30. The display substrate of claim 28, wherein the second sub-transmission segment is located in an area surrounded by the first via hole and the sixth via hole of the second sub-pixel and the first via hole and the sixth via hole of the third sub-pixel.
31. The display substrate of claim 27, wherein the second gate line is located between the fourth via and the eighth via.
32. The display substrate of claim 1, wherein the resistance values of the different data lines are substantially equal.
33. The display substrate of claim 1, wherein the capacitance of the parasitic capacitance generated by the coupling of different data lines with any other signal line is substantially equal, and the number of the parasitic capacitance generated by the coupling of different data lines with other signal lines is substantially equal.
34. A display device comprising the display substrate according to any one of claims 1 to 33.
35. A method for manufacturing a display substrate, the method comprising:
providing a substrate base plate;
forming grid lines extending along a first direction on the substrate, wherein at least one grid line comprises first transmission sections and second transmission sections which are alternately arranged, each second transmission section comprises at least two signal transmission lines, and each signal transmission line is respectively connected with two adjacent first transmission sections in the first direction;
and forming data lines extending along a second direction on the substrate base plate, wherein an orthographic projection of at least one data line on the substrate base plate and an orthographic projection of the second transmission segment on the substrate base plate have an overlapping region, the at least one data line comprises a first part and a second part extending along the second direction and a third part connecting the first part and the second part, and the extending direction of the third part forms an included angle with the second direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911203895.8A CN112885843A (en) | 2019-11-29 | 2019-11-29 | Display substrate, manufacturing method thereof and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911203895.8A CN112885843A (en) | 2019-11-29 | 2019-11-29 | Display substrate, manufacturing method thereof and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112885843A true CN112885843A (en) | 2021-06-01 |
Family
ID=76038841
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911203895.8A Pending CN112885843A (en) | 2019-11-29 | 2019-11-29 | Display substrate, manufacturing method thereof and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112885843A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115460326A (en) * | 2021-06-08 | 2022-12-09 | 京东方科技集团股份有限公司 | Display panel, scanning method, electronic device, and storage medium |
-
2019
- 2019-11-29 CN CN201911203895.8A patent/CN112885843A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115460326A (en) * | 2021-06-08 | 2022-12-09 | 京东方科技集团股份有限公司 | Display panel, scanning method, electronic device, and storage medium |
| CN115460326B (en) * | 2021-06-08 | 2024-05-31 | 京东方科技集团股份有限公司 | Display panel, scanning method, electronic device, and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11086439B2 (en) | Display panel with metal mesh units and display apparatus | |
| US20230376150A1 (en) | Touch display device | |
| CN115662351B (en) | Display panel and display device | |
| US11963405B2 (en) | Display, display panel, and electronic terminal | |
| CN210575037U (en) | Display panel and display device | |
| CN103649889A (en) | Display device | |
| CN110164359B (en) | Display panel and display device | |
| CN111384136B (en) | Display panel and display device | |
| CN210271564U (en) | Display substrate and display device | |
| CN111900192A (en) | Display panel and display device | |
| US11561634B2 (en) | Display module, fabrication method thereof and display device | |
| CN210628309U (en) | Display substrate and display device | |
| CN111158533A (en) | Detection substrate and display device | |
| CN114175133B (en) | Display panel, manufacturing method thereof and display device | |
| US11526226B2 (en) | Touch control display screen and electronic device | |
| WO2024113781A1 (en) | Display panel and display apparatus | |
| CN212277199U (en) | Display panel and display device | |
| CN112885843A (en) | Display substrate, manufacturing method thereof and display device | |
| CN218383922U (en) | Touch display structure and display device | |
| US11416099B2 (en) | Touch display panel and touch display device comprising the same | |
| CN114361186A (en) | Display substrate and display device | |
| CN109801943B (en) | Display panel and display device | |
| CN114207696A (en) | Display panel, manufacturing method thereof and display device | |
| US20230217779A1 (en) | Transparent touch display device | |
| US11822748B2 (en) | Touch display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |