CN112885281B

CN112885281B - Display drive circuit, display drive chip and electronic equipment

Info

Publication number: CN112885281B
Application number: CN202110107221.9A
Authority: CN
Inventors: 兰永城
Original assignee: Vivo Mobile Communication Co Ltd
Current assignee: Vivo Mobile Communication Co Ltd
Priority date: 2021-01-26
Filing date: 2021-01-26
Publication date: 2022-11-11
Anticipated expiration: 2041-01-26
Also published as: CN112885281A

Abstract

The application discloses display drive circuit, display drive chip and electronic equipment belongs to the display circuit field. The display drive circuit includes: the demodulation module is used for receiving a clock signal and image data sent by the processor, demodulating the image data to obtain a processed image and outputting a line scanning signal according to the clock signal; the counting comparison module is used for receiving the line scanning signals and obtaining actual line effective scanning time according to the line scanning signals, and the counting comparison module outputs a time sequence adjustment signal according to the difference value of the actual line effective scanning time and the standard line effective scanning time; and the time sequence adjusting module is used for receiving the time sequence adjusting signal and outputting a time sequence driving signal according to the time sequence adjusting signal, wherein the time sequence driving signal is used for driving a display to display the processed image.

Description

Display drive circuit, display drive chip and electronic equipment

Technical Field

The application belongs to the field of display circuits, and particularly relates to a display driving circuit, a display driving chip and an electronic device.

Background

For example, when a display of a Mobile phone is in operation, it interferes with the receiving sensitivity of RF modules such as GSM, 4G, wiFi, GPS, etc., most of the Interference causes radiation or coupling Interference caused by Mobile phone MIPI (Mobile Industry Processor Interface) data transmission, and in the face of this problem, the prior art adopts a frequency hopping mechanism and a frequency spreading mechanism of MIPI to solve the problem, and by adjusting the MIPI CLK frequency, the Interference energy of the original default frequency point is reduced, so as to improve or solve the problem of radio frequency Interference.

However, in the process of implementing the present application, the inventors found that at least the following problems exist in the prior art: taking a touch and display driver integrated touch panel function (TDDI) embedded In an In-cell display module as an example, the module display timing and touch timing of the TDDI are time division multiplexed, when the MIPI adopts a frequency hopping or spread spectrum mechanism, a Line (Line) time THS of MIPI transmission data changes, and since the total scanning time In one Line is a fixed value, discontinuous or overlapped parts occur In the display and touch timing of the TDDI display module, thereby bringing about the problem of no flash screen or touch function.

Content of application

The embodiment of the application aims to provide a display driving circuit, a display driving chip and electronic equipment, which can solve the problem that a display module flickers or is not functional in touch control.

In order to solve the technical problem, the present application is implemented as follows:

in a first aspect, an embodiment of the present application provides a display driving circuit, including:

a first input end of the demodulation module is used for receiving a clock signal sent by a processor, a second input end of the demodulation module is used for receiving image data sent by the processor, the demodulation module demodulates the image data to obtain a processed image, and a line scanning signal is output according to the clock signal;

a first input end of the counting comparison module is connected with a first output end of the demodulation module, the counting comparison module is used for receiving the line scanning signal and obtaining the effective scanning time of an actual line according to the line scanning signal, and the counting comparison module outputs a time sequence adjusting signal according to the difference value of the effective scanning time of the actual line and the effective scanning time of a standard line; and (c) a second step of,

and a first input end of the time sequence adjusting module is connected with an output end of the counting comparison module, the time sequence adjusting module is used for receiving the time sequence adjusting signal and outputting a time sequence driving signal according to the time sequence adjusting signal, and the time sequence driving signal is used for driving a display to display the processed image.

In a second aspect, an embodiment of the present application provides a display driver chip, which is characterized in that, the display driver chip includes a housing, a substrate and a display driver circuit in the first aspect, the housing is provided with a first pin, a second pin, a third pin and a fourth pin, the display driver circuit is integrated on the substrate, the substrate and the display driver circuit are packaged in the housing, a first input end of a demodulation module is connected with the first pin, a second input end of the demodulation module is connected with the second pin, an output end of a timing adjustment module is connected with the third pin, and an output end of the display information driver module is connected with the fourth pin.

In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor, a display, a scan driving circuit, and the display driving chip of the second aspect or the display driving circuit of any one of the third aspects;

the output end of the processor is connected with the input end of the display driving chip, the first output end of the display driving chip is connected to the first input end of the display, the first output end of the display driving chip is the output end of the display information driving module, the second output end of the display driving chip is connected to the input end of the scanning driving circuit, the second output end of the display driving chip is the output end of the time sequence adjusting module, the output end of the scanning driving circuit is connected to the second input end of the display,

the processor is used for outputting a clock signal and image data to the demodulation module of the display driving chip;

the display driving chip is used for outputting a time sequence driving signal to the scanning driving circuit according to the received clock signal and the image data and outputting a processed image to the display;

the scanning driving circuit is used for driving the display to execute an instruction for displaying an image according to the time sequence driving signal;

the display is used for displaying the processed image.

In the embodiment of the application, the counting comparison module is used for calculating the effective scanning time of the lines in the line scanning signals to obtain the effective scanning time of the actual lines, then the effective scanning time of the actual lines is compared with the standard effective scanning time to obtain the difference value of the effective scanning time and the standard effective scanning time, and the time sequence adjusting signal is generated by using the difference value, so that the effective scanning time of the actual lines is corrected by using the time sequence adjusting signal to enable the effective scanning time of the actual lines to be consistent with the standard effective scanning time.

Drawings

Fig. 1 is a schematic circuit diagram of a display driving circuit provided in this embodiment;

fig. 2 is a schematic structural diagram of a count comparison module according to this embodiment;

FIG. 3 is a timing diagram of a control signal and image data of a count comparison module according to this embodiment;

fig. 4 is a schematic structural diagram of a display driver chip provided in this embodiment;

fig. 5 is a schematic circuit structure diagram of an electronic device provided in this embodiment;

fig. 6 is a schematic diagram of a hardware structure of another electronic device provided in this embodiment.

In the figure: the display driving circuit comprises a display driving chip 100, a demodulation module 101, a count comparison module 102, a timing adjustment module 103, a line buffer 104, a display information driving module 105, a substrate 106, a housing 107, a counter 1021, a memory 1022, a comparator 1023, a processor 200, a scan driving circuit 201 and a display 202.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application are capable of operation in sequences other than those illustrated or described herein. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.

The display driving circuit, the display driving chip and the electronic device provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings through specific embodiments and application scenarios thereof.

Referring to fig. 1 and 5, the present embodiment provides a display driving circuit including: the device comprises a demodulation module 101, a count comparison module 102 and a timing adjustment module 103, wherein the demodulation module 101 is configured to receive a clock signal and image data sent by the receiving processor 200 shown in fig. 5, and demodulate the clock signal and the image data, and the clock signal is configured to display the image data on a display according to a corresponding clock. For example, the DATA transmission between the demodulation module 101 and the processor 200 uses a Mobile Industry Processor Interface (MIPI) alliance, the clock signal may be MIPI CLK, the image DATA may be MIPI DATA, the demodulation module 101 may be a decoder, the demodulation module 101 converts the received MIPI CLK and MIPI DATA into digital signals to implement circuit control, and in an alternative example, the demodulation module 101 converts the MIPI CLK into a line scan signal HSYNC and a frame scan signal VSYNC, demodulates the MIPI DATA into a continuous multi-frame image, and stores the continuous multi-frame image. When the display is displaying, every time a new line is to be displayed and scanning is to be performed, the processor will send out a horizontal Synchronization signal, namely, a horizontal Synchronization signal HSYNC (horizontal Synchronization), and after one frame of picture is drawn and before the next frame is to be drawn, the processor will send out a Vertical Synchronization signal, namely, a Vertical Synchronization signal VSYNC (Vertical Synchronization), to refresh the display at a fixed frequency.

In this embodiment, a first input end of the demodulation module 101 is configured to receive a clock signal sent by the processor 200, a second input end of the demodulation module 101 is configured to receive image data sent by the processor, the demodulation module 101 demodulates the image data to obtain a processed image, and outputs a line scan signal according to the clock signal. For example, a first input terminal of the demodulation module 101 receives the MIPI CLK, a second input terminal of the demodulation module 101 receives the MIPI DATA, outputs the line scanning signal HSYNC to the count comparison module 102 according to the MIPI CLK, and outputs the multi-frame image to the line buffer 104 for buffering according to the MIPI DATA. Referring to fig. 3, HOST MIPI in fig. 3 is a frame image buffered in a line buffer, where each frame image is composed of a plurality of lines of pixels (L1, L2 \8230; ln), and the display is controlled to scan each line one by one according to a line scanning signal HSYNC, so as to display a frame image on the display.

It should be noted that, in order to solve the problems mentioned in the background art, the present embodiment is provided with a count comparison module 102, a first input end of the count comparison module 102 is connected to a first output end of the demodulation module 101, the count comparison module 102 is configured to receive the line scanning signal HSYNC and obtain an actual line effective scanning time according to the HSYNC, and the count comparison module 102 outputs the timing adjustment signal according to a difference between the actual line effective scanning time and the standard line effective scanning time. The count comparison module 102 is used for calculating the effective scanning time of the line in the line scanning signal to obtain the effective scanning time of the actual line, then the effective scanning time of the actual line is compared with the effective scanning time of the standard to obtain the difference value of the effective scanning time and the standard effective scanning time, the difference value is used for generating a time sequence adjusting signal, and therefore the effective scanning time of the actual line is corrected by the time sequence adjusting signal, so that the effective scanning time of the actual line is consistent with the effective scanning time of the standard, and the problem of screen flicker or touch non-functional caused by frequency spreading or frequency hopping in MIPI data transmission is avoided.

In this embodiment, the line scan signal may be a pulse sequence of HSYNC in fig. 3, where scanning time THS is a line effective scanning time, HBP and HFP are idle times occupied by a falling edge and a rising edge of a line, and if one frame of image data includes n lines, n lines of THS are provided, and scanning is performed one by one according to the n lines of THS, thereby displaying one frame of image. The actual effective scan time is the effective scan time obtained by the demodulation module 101 from the received clock signal.

In this embodiment, a first input end of the timing adjusting module 103 is connected to an output end of the count comparing module 102, and the timing adjusting module 103 is configured to receive a timing adjusting signal and output a timing driving signal according to the timing adjusting signal, where the timing driving signal is used to drive a display to display a processed image. The count comparison module 102 outputs a timing adjustment signal, which may be a correction signal, to correct the actual effective scanning time received by the timing adjustment module 103, so as to output a timing driving signal to drive the display 202 to display the processed image, thereby avoiding the phenomena of image dislocation and screen flashing. For example, the timing adjustment signal may be Y in fig. 1, and THS of the output timing driving signal in the present embodiment is the same as or consistent with the standard effective scan time.

In an alternative example, referring to fig. 2, the count comparing module 102 includes a counter 1021, a memory 1022 and a comparator 1023, the counter 1021 has a first input terminal, the first input terminal of the counter 1021 is the first input terminal of the count comparing module 102, an output terminal of the counter 1021 is connected to an input terminal of the memory, an output terminal of the memory 1022 is connected to an input terminal of the comparator 1023, and an output terminal of the comparator 1023 is the output terminal of the count comparing module 102. For example, referring to fig. 1, a first input terminal of the count comparator 1023 and a first input terminal of the count comparison module 102 are both configured to receive the HSYNC line scan signal, an output terminal of the count comparator 1023 is connected to the memory 1022, and the memory 1022 is connected to the comparator 1023.

The counter 1021 is used for recording the line active scanning time of each line in the line scanning signal, and outputting the line active scanning time of each line as the actual line active scanning time to the memory 1022. While the counter 1021 is also arranged to receive a count clock CLK REF which triggers its own operation, the count is incremented by one each time a high level of CLK REF is received to ensure that its counter 1021 operates normally.

The memory 1022 is used for saving the actual line effective scanning time from the counter 1021 and outputting the actual line effective scanning time to the comparator 1023, and the memory 1022 is used for storing the standard line effective scanning time, which can be preset according to the model of the intelligent terminal. For example, in the case that the intelligent terminal device transmits data through the MIPI bus in the normal operation mode, that is, the MIPI interface is in the non-frequency hopping or spread spectrum mode, the clock signal transmitted by the processor is acquired, the number of lines of the line scanning signal in one frame image period in the clock signal and the line effective scanning time of each line are acquired, and the average value of the line effective scanning times is output according to the number of lines of the line scanning signal in one frame image period and the line effective scanning time, that is, the average value of all THS is calculated.

The comparator 1023 outputs a timing adjustment signal according to the actual line effective scanning time and the standard line effective scanning time. For example, the comparator 1023 subtracts the actual line effective scanning time from the standard line effective scanning time to obtain a difference value therebetween, and obtains a comparison result therebetween, thereby generating a corresponding control signal so that the actual line effective scanning time is the same as the standard line effective scanning time.

It should be noted that the counter 1021 calculates the effective scanning time of each line in the scanning signal, and the accuracy is corrected for the THS of each line, so that the accuracy can be improved. In addition, the counter 1021 of the embodiment can also be used to record the effective line scanning time of each line in the line scanning signal and the number of lines of the line scanning signal in one frame of image period, and output the average value of the effective line scanning time in one frame of image period as the actual effective line scanning time to the memory, so as to improve the calculation speed. Referring to fig. 2, the time of the THS row n of the signal of the enable terminal EN of the counter 1021 in fig. 2, that is, THS1, THS2, 8230, THSn, is recorded, the time values of THS1, THS2, 8230, THSn are added, the average value of the effective scanning time of the row is obtained according to the row number n, and the average value is output to the memory as the effective scanning time of the actual row. The memory 1022 stores the actual effective scanning time and outputs the actual effective scanning time to the comparator 1023, and the comparator 1023 outputs the timing adjustment signal according to the actual effective scanning time and the standard effective scanning time. Specifically, the functions of the memory 1022 and the comparator 1023 are described above, and are not described herein again to avoid redundancy.

In this embodiment, the first input terminal of the counter 1021 is an enable terminal for driving the count comparison module 102 to operate, and referring to fig. 1 or fig. 2, the first input terminal of the counter 1021 and the first input terminal of the count comparison module 102 are enable terminals EN. The input of the enable terminal is HSYNC, the enable terminal is active at high level, the counter 1021 enables to start counting within the time of HSYNC signal THS, and since the input terminal of the enable terminal is connected with an inverter, referring to signal HSYNC and signal EN in fig. 2, when the HSYNC signal is low level at THS time, the enable terminal is high level, the counter 1021 starts counting, thereby obtaining the number of lines of the line scanning signal.

In this embodiment, a second output end of the demodulation module 101 is connected to a second input end of the count comparison module 102, and is configured to output the frame scanning signal to the count comparison module 102, where the second input end of the count comparison module 102 is a reset end. For example, the second output terminal of the demodulation module 101 outputs the frame scanning signal VSYNC to the reset terminal RST of the count comparison module 102, and since the input of the reset terminal is provided with an inverter and the reset terminal is active low, referring to fig. 3, when VSYNC is high, RST is low, so that the count comparison module 102 is controlled by VSYNC to reset after the end of each frame image display, i.e. a reset period is one image period.

In a practical example, the count comparison module 102 may also be used in a Global System for Mobile Communications (GSM) System for avoiding a display module flickering problem caused by a frequency change due to network transmission, for example, the count comparison module 102 of the embodiment may be disposed between the GSM and the display module, so that the output actual effective scanning time is consistent with the standard effective scanning time.

Referring to fig. 1, the display driving circuit in this embodiment further includes a line buffer 104 and a display information driving module 105, and a third output terminal of the demodulation module 101 is connected to an input terminal of the line buffer 104, and is configured to output the demodulated image to the line buffer 104. The buffer is a container for registering data of a specific basic type, and is used for registering a linear finite sequence of elements of the specific basic type, and besides contents, basic attributes of the buffer also comprise capacity, limitation and position. For example, the Line Buffer (Line Buffer) 104 of the present embodiment stores therein the image data L1, L2 \8230; ln, and the image display timing of the image data on a per-Line basis, and the image data of each Line may be arranged Line by Line according to the image display timing to sequentially compose a complete frame of image data.

The first output end of the line buffer 104 is connected to the input end of the display information driving module 105, and is used for outputting the image data in the line buffer 104 to the display information driving module 105. The display information driving module 105 is configured to output the image data stored in the line buffer 104 to the display information driving module 105, and drive the display 202 to display the specific image data, for example, the display information driving module 105 may be a source driver (source driver), and transmits the digital image display data (S1 \8230; sn) in the line buffer 104 to the display 202 line by line, and converts the digital signal into an analog driving voltage, so as to drive the display 202 to display an image.

A second output terminal of the line buffer 104 is connected to a second input terminal of the timing adjustment module 103, and is configured to output an image display timing sequence corresponding to the clock signal to the timing adjustment module 103. The timing adjustment signal generated by the count comparison module 102 in this embodiment is used to correct the actual effective scanning time, and since the image display timing of the image data is not only registered in the line buffer 104 but also obtained according to the clock signal received by the demodulation module 101, that is, the image display timing is consistent with the line scanning signal demodulated by the demodulation module 101, the image display timing in the line buffer 104 can be sent to the timing adjustment module 103, so as to correct the image display timing according to the timing adjustment signal.

In this embodiment, the timing adjustment module 103 corrects the image display timing according to the timing adjustment signal and outputs a timing driving signal. THE timing adjustment module 103 can be a GOA (GATE ON that array) timing controller, and is used for outputting a timing driving signal to control THE time when THE GOA driving circuit turns ON each pixel (GATE) in turn, i.e. THE time required for THE display 202 to scan each pixel once. The image elements in one frame of image period include G1, 8230Gn, and the number of image elements in one frame of image period is equal to the number of lines of one frame of image data.

The comparator 1023 of this embodiment is further configured to output a low level timing adjustment signal when the actual line effective scanning time is greater than the standard line effective scanning time, where a duration of the low level timing adjustment signal is a difference between the actual line effective scanning time and the standard line effective scanning time, so as to reduce a time duration of THS, and make the actual line effective scanning time equal to the standard line effective scanning time; under the condition that the actual line effective scanning time is less than the standard line effective scanning time, outputting a high-level time sequence adjusting signal, wherein the duration of the high-level time sequence adjusting signal is the difference between the actual line effective scanning time and the standard line effective scanning time, so that the THS duration is increased, and the actual line effective scanning time is equal to the standard line effective scanning time; and under the condition that the actual effective scanning time of the line is equal to the standard effective scanning time of the line, indicating that the actual effective scanning time of the line at the moment is equal to the standard effective scanning time of the line, and stopping outputting the timing sequence adjusting signal. For example, assuming that the difference between the actual line effective scanning time and the standard line effective scanning time is Δ T, when Δ T >0, the timing adjustment signal Y outputs a low pulse width, that is, a low level is maintained for Δ T duration, thereby reducing the duration of THS; when the time sequence is less than 0, the time sequence adjusting signal Y outputs high pulse width, namely, the high level keeps the time length of the time sequence, thereby increasing the time length of the THS; when Δ T =0, the output of the timing adjustment signal Y is stopped, and the high impedance is maintained.

In this embodiment, the count comparison module 102 is utilized to calculate the effective scanning time of a line in the line scanning signal to obtain the effective scanning time of an actual line, then the effective scanning time of the actual line is compared with the standard effective scanning time to obtain a difference value between the effective scanning time of the actual line and the standard effective scanning time, and the difference value is utilized to generate the timing sequence adjustment signal, so that the effective scanning time of the actual line is corrected by the timing sequence adjustment signal to make the effective scanning time of the actual line consistent with the standard effective scanning time.

The present embodiment provides a display driving chip 100, referring to fig. 4, the display driving chip 100 includes a housing 107, a substrate 106 and the display driving circuit in the foregoing embodiments, the housing 107 is provided with a first pin, a second pin, a third pin and a fourth pin, the display driving circuit is integrated on the substrate 106, the substrate 106 and the display driving circuit are packaged in the housing 107, a first input end of a demodulation module 101 of the display driving circuit is connected with the first pin, a second input end of the demodulation module 101 is connected with the second pin, an output end of a timing adjustment module 103 is connected with the third pin, and an output end of a display information driving module 105 is connected with the fourth pin. The substrate 106 may be a PCB, the display driving circuit is integrated on the substrate 106 by way of circuit connection and soldering pins, and the substrate 106 and the display driving circuit are packaged in the housing 107, thereby playing a role in protecting the display driving circuit. The first pin, the second pin, the third pin and the fourth pin of the housing 107 are used for electrically connecting the driving chip with an external device.

In a possible example, referring to fig. 5, the display driver chip 100 is configured to receive a clock signal and image data sent by a processor, demodulate the image data to obtain a processed image, and output a line scan signal according to the clock signal; obtaining actual effective scanning time of a line according to the line scanning signal, and outputting a time sequence adjusting signal according to the difference value of the actual effective scanning time of the line and the standard effective scanning time of the line; and outputting a timing driving signal according to the timing adjustment signal, wherein the timing driving signal is used for driving the display 202 to display the processed image.

The display driver chip 100 of this embodiment can utilize the count comparison module 102 to calculate the effective scanning time of a line in a line scanning signal to obtain the effective scanning time of an actual line, compare the effective scanning time of the actual line with the standard effective scanning time to obtain a difference between the effective scanning time of the actual line and the standard effective scanning time, and generate a timing adjustment signal by using the difference, so as to correct the effective scanning time of the actual line by using the timing adjustment signal, so that the effective scanning time of the actual line is consistent with the standard effective scanning time, and under the condition of not depending on theoretical calculation and engineering application point detection, the problem of screen flicker or non-functional touch due to frequency spreading or frequency hopping in MIPI data transmission can be fundamentally solved.

The present embodiment provides an electronic device, and referring to fig. 5, the electronic device may be a mobile electronic device, and the mobile electronic device includes a processor 200, a display 202, a scan driving circuit 201, and the display driving chip 100 or the display driving circuit of the above embodiments. The output end of the processor is connected to the input end of the display driver chip 100, the first output end of the display driver chip 100 is connected to the first input end of the display 202, the first output end of the display driver chip 100 is the output end of the display information driver module 105, the second output end of the display driver chip 100 is connected to the input end of the scan driver circuit 201, the second output end of the display driver chip 100 is the output end of the timing adjustment module 103, and the output end of the scan driver circuit 201 is connected to the second input end of the display 202.

In one possible example, the processor 200 is configured to output the clock signal and the image data to the demodulation module 101 of the display driving chip 100; the display driver chip 100 is configured to output a timing driving signal to the scan driver circuit 201 and output a processed image to the display 202 according to the received clock signal and image data; the scan driving circuit 201 is used for driving the display 202 to execute an instruction for displaying an image according to the timing driving signal; display 202 is used to show the processed image.

The electronic device of this embodiment can utilize the count comparison module 102 to calculate the effective scanning time of a line in the line scanning signal to obtain the effective scanning time of an actual line, compare the effective scanning time of the actual line with the effective scanning time of a standard to obtain a difference between the effective scanning time of the actual line and the effective scanning time of the standard, and generate the timing adjustment signal by using the difference, so as to correct the effective scanning time of the actual line by using the timing adjustment signal, so that the effective scanning time of the actual line is consistent with the effective scanning time of the standard, and under the condition of not depending on theoretical calculation and engineering application point detection, the problem of screen flicker or touch reactive function caused by frequency spreading or frequency hopping in MIPI data transmission can be fundamentally solved.

Optionally, referring to fig. 6, an electronic device 1000 according to the embodiment of the present application may further include a processor 1010, a memory 1009, and a program or an instruction stored in the memory 1009 and capable of running on the processor 1010, where the program or the instruction is executed by the processor 1010 to implement each process of the embodiment of the display driver chip 100, and may achieve the same technical effect, and no further description is provided here to avoid repetition.

It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and the non-mobile electronic devices described above.

Fig. 6 is a schematic diagram of a hardware structure of an electronic device implementing an embodiment of the present application.

The electronic device 1000 includes, but is not limited to: the display driver chip 100, the radio frequency unit 1001, the network module 1002, the audio output unit 1003, the input unit 1004, the sensor 1005, the display unit 1006, the user input unit 1007, the interface unit 1008, the memory 1009, the processor 1010, and the like in the above embodiments.

Those skilled in the art will appreciate that the electronic device 1000 may further comprise a power supply (e.g., a battery) for supplying power to the various components, and the power supply may be logically connected to the processor 1010 through a power management system, so as to implement functions of managing charging, discharging, and power consumption through the power management system. Drawing (A)6The electronic device structures shown in the figures do not constitute limitations of the electronic device, and the electronic device may include more or less components than those shown in the figures, or some components may be combined, or different component arrangements may be provided, which are not described in detail herein.

The network module 1002 is configured to implement data communication between the processor and the display driver chip 100 in the foregoing embodiments.

A processor 1010 for transmitting a clock signal and image data to the display driving chip 100.

The display unit 1006 is used for displaying the processed image according to the timing driving signal of the display driving chip 100.

It should be understood that in the embodiment of the present application, the input Unit 1004 may include a Graphics Processing Unit (GPU) 10041 and a microphone 10042, and the Graphics Processing Unit 10041 processes image data of still pictures or videos obtained by an image capturing device (such as a camera) in a video capturing mode or an image capturing mode. The display unit 1006 may include a display panel 10061, and the display panel 10061 may be configured in the form of a liquid crystal display 202, an organic light emitting diode, or the like. The user input unit 1007 includes a touch panel 10071 and other input devices 10072. The touch panel 10071 is also referred to as a touch screen. The touch panel 10071 may include two parts, a touch detection device and a touch controller. Other input devices 10072 may include, but are not limited to, a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which are not described in detail herein. The memory 1009 may be used to store software programs as well as various data, including but not limited to application programs and operating systems. Processor 1010 may integrate an application processor that handles primarily operating systems, user interfaces, applications, etc. and a modem processor that handles primarily wireless communications. It will be appreciated that the modem processor described above may not be integrated into processor 1010.

The embodiments of the present application further provide a readable storage medium, where a program or an instruction is stored on the readable storage medium, and when the program or the instruction is executed by a processor, the process of the foregoing embodiments is implemented, and the same technical effect can be achieved, and in order to avoid repetition, details are not repeated here.

The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and so on.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one of 8230, and" comprising 8230does not exclude the presence of additional like elements in a process, method, article, or apparatus comprising the element.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present application or portions thereof that contribute to the prior art may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present application.

While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A display driver circuit, comprising:

a count comparison module, a first input end of which is connected with a first output end of the demodulation module, the count comparison module being configured to receive the line scanning signal and obtain an actual line effective scanning time according to the line scanning signal, and the count comparison module outputting a timing adjustment signal according to a difference between the actual line effective scanning time and a standard line effective scanning time; and the number of the first and second groups,

a timing sequence adjusting module, a first input end of which is connected with an output end of the counting comparison module, the timing sequence adjusting module being configured to receive the timing sequence adjusting signal and output a timing sequence driving signal according to the timing sequence adjusting signal, wherein the timing sequence driving signal is configured to drive a display to display the processed image;

wherein the actual line effective scanning time includes a line effective scanning time of each line in the line scanning signal or an average value of the line effective scanning times within one frame of image period.

2. The display drive circuit according to claim 1,

the counting comparison module comprises a counter, a memory and a comparator, the counter is provided with a first input end, the first input end of the counter is the first input end of the counting comparison module, the output end of the counter is connected with the input end of the memory, the output end of the memory is connected with the input end of the comparator, and the output end of the comparator is the output end of the counting comparison module;

the counter is used for recording the effective scanning time of each line in the line scanning signal and outputting the effective scanning time of each line as the effective scanning time of the actual line to the memory,

the memory is used for saving the actual effective scanning time of the line and outputting the actual effective scanning time of the line to the comparator, and the memory is used for storing the standard effective scanning time of the line;

and the comparator outputs the time sequence adjusting signal according to the actual line effective scanning time and the standard line effective scanning time.

3. The display driver circuit according to claim 1,

the counter is used for recording the effective scanning time of each line in the line scanning signals and the number of lines of the line scanning signals in one frame of image period, and outputting the average value of the effective scanning time of the lines in one frame of image period to the memory as the effective scanning time of the actual lines;

the memory is used for saving the actual line effective scanning time and outputting the actual line effective scanning time to the comparator, and the memory is used for storing the standard line effective scanning time;

4. The display driving circuit according to claim 2 or 3, wherein the first input terminal of the counter is an enable terminal for driving the count comparison module to operate.

5. The display drive circuit according to claim 1,

and the second output end of the demodulation module is connected with the second input end of the counting comparison module and is used for outputting a frame scanning signal to the counting comparison module, and the second input end of the counting comparison module is a reset end.

6. The display driver circuit according to claim 1, wherein the circuit further comprises:

the third output end of the demodulation module is connected with the input end of the line buffer and is used for outputting the demodulated image to the line buffer;

the first output end of the line buffer is connected with the input end of the display information driving module and is used for outputting the image data in the line buffer to the display information driving module;

and the second output end of the line buffer is connected with the second input end of the time sequence adjusting module and is used for outputting the image display time sequence corresponding to the clock signal to the time sequence adjusting module.

7. The display driving circuit according to claim 6, wherein the timing adjustment module outputs a timing driving signal according to the timing adjustment signal, and comprises: and correcting the image display time sequence according to the time sequence adjusting signal, and outputting a time sequence driving signal.

8. The display drive circuit according to claim 2,

the comparator is further configured to output a low level timing adjustment signal when the actual line effective scanning time is greater than the standard line effective scanning time, where a duration of the low level timing adjustment signal is a difference between the actual line effective scanning time and the standard line effective scanning time;

under the condition that the actual line effective scanning time is less than the standard line effective scanning time, outputting a high-level time sequence adjusting signal, wherein the duration of the high-level time sequence adjusting signal is the difference value between the actual line effective scanning time and the standard line effective scanning time;

and when the actual line effective scanning time is equal to the standard line effective scanning time, stopping outputting the timing adjustment signal.

9. A display driving chip, comprising a housing, a substrate and the display driving circuit of any one of claims 1 to 8, wherein the housing is provided with a first pin, a second pin, a third pin and a fourth pin, the display driving circuit is integrated on the substrate, the substrate and the display driving circuit are packaged in the housing, the first input terminal of the demodulation module is connected to the first pin, the second input terminal of the demodulation module is connected to the second pin, the output terminal of the timing adjustment module is connected to the third pin, and the output terminal of the display information driving module is connected to the fourth pin.

10. An electronic device, comprising a processor, a display, a scan driving circuit, and the display driving chip of claim 9;

the display is used for displaying the processed image.