CN112882754B - Function calling method and processor - Google Patents
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- CN112882754B CN112882754B CN201911205836.4A CN201911205836A CN112882754B CN 112882754 B CN112882754 B CN 112882754B CN 201911205836 A CN201911205836 A CN 201911205836A CN 112882754 B CN112882754 B CN 112882754B
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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Abstract
The application provides a function calling method and a processor. In the method, firstly, a first processor determines a second processor to which the function to be operated belongs, and the first processor acquires various information of multi-level pointer parameters and sends the information to the second processor through a first network message; then, the second processor receives the first network message sent by the first processor, analyzes the first network message and acquires various information of the multi-level pointer parameters; secondly, reconstructing the multi-stage pointer parameters according to various information of the analyzed multi-stage pointer parameters and information of the functions to be operated; and finally, the second processor returns the calling result and the result of running the function to be run to the first process through the second network message. The method can effectively solve the problem that the traditional function calling method can not realize the function calling which comprises multi-level pointer parameters and is across processors.
Description
Technical Field
The embodiment of the application relates to the technical field of computers, in particular to a function calling method and a processor.
Background
In a computing device, there may be multiple processors. The plurality of processors cooperate to implement computing functionality of the computing device. Typically, during the running of a program by one processor, the need to call functions in other processors arises.
In conventional function call methods, the processor only supports the call of functions containing shaping parameters, string parameters, and single level pointer parameters. Wherein all pointer variables in the single level pointer parameter point to addresses.
Since the data length of these parameters is known, when the processor a determines that these functions need to be called, the processor B may directly notify the data length of the parameters included in the functions to the processor B, and the processor B may allocate a memory address for the parameters according to the obtained data length, so as to run the functions. After the processor B runs the function to obtain the running result, the running result is notified to the processor A, so that the processor A can complete the function call.
However, some functions may involve multiple levels of pointer parameters, where at least one pointer variable points to the other pointer variable, and the addresses of the two processors are independent. Obviously, even if the processor a sends the multi-level pointer parameters to the processor B by adopting the method, the processor B cannot determine the pointing relation of the pointer variables in the multi-level pointer parameters, and thus cannot run the function containing the multi-level pointer parameters. Thus, the above-described conventional function call method is employed to implement a function call including multiple levels of pointer parameters across processors.
Therefore, there is a need in the art to propose a function call method including multiple levels of pointer parameters that can be implemented across processors.
Disclosure of Invention
The embodiment of the invention provides a function calling method for realizing cross-processor function calling containing multi-layer pointer parameters.
The specific technical scheme provided by the embodiment of the invention is as follows:
in a first aspect, an embodiment of the present application provides a function calling method, which may be applied to a computing device having a plurality of processors, and specifically includes the following steps:
the first processor determines a second processor to which a function to be run belongs;
the first processor determines that the function to be operated contains multi-level pointer parameters, wherein the multi-level pointer parameters contain a plurality of pointer variables, and at least one pointer variable in the plurality of pointer variables points to other pointer variables;
the first processor acquires the structure information of the multi-level pointer parameters and stores the structure information into a cache with continuous addresses; wherein the structural information is used to characterize: the multi-level pointer parameter comprises the number of pointer variables, the variable information of each pointer variable and the pointing relation among the pointer variables; the variable information of any pointer variable comprises the length and the head address of the pointer variable;
The first processor acquires the number of pointer variables contained in the multi-level pointer parameter and variable information of each pointer variable from the structure information;
the first processor sends a first network message to the second processor, wherein the first network message comprises: the structure information of the multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, the variable information of each pointer variable and the information of the function to be operated;
the first processor receives a second network message sent by the second processor, wherein the second network message comprises an operation result of the second processor on the function to be operated.
According to the method, when the function call containing the multi-level pointer parameters is carried out between the two processors, the first processor stores the related contents of the called multi-level pointer parameters in the first network message according to the corresponding format, the first processor sends the first network message to the second processor, the second processor analyzes the first network message so as to execute the function call and returns the call execution result to the first processor through the second network message, and therefore the cross-processor function call containing the multi-level pointer parameters is effectively realized.
In one possible implementation manner, the first processor determines that the function to be executed includes multiple levels of pointer parameters, and the method includes:
when the first processor determines that the length of the specified parameter is greater than or equal to the set length, the first processor determines that the multi-stage pointer parameter is contained in the function to be operated.
By the method, the first processor can determine pointer parameters contained in the function to be operated as multi-level pointer parameters.
In one possible implementation, the pointing relationship between pointer variables includes:
the number of pointing relationships between pointer variables;
the pointing relationship between each pointer variable contains the identity and address offset of the source pointer variable and the identity and address offset of the destination pointer variable.
In a second aspect, embodiments of the present application also provide a function call method applied to a computing device having a plurality of processors, the method comprising:
the second processor receives a first network message sent by the first processor, wherein the first network message comprises: the method comprises the steps of structural information of multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, variable information of each pointer variable and information of a function to be operated; wherein the structural information is used to characterize: the multi-level pointer parameter comprises the number of pointer variables, the variable information of each pointer variable and the pointing relation among the pointer variables; the variable information of any pointer variable comprises the length and the head address of the pointer variable; the second processor stores the structural information of the multi-level pointer parameters into a cache with continuous addresses;
The second processor determines the absolute address offset of each pointer variable in the multi-level pointer parameter according to the number of pointer variables contained in the multi-level pointer parameter contained in the first network message and the variable information of each pointer variable;
the second processor calculates the address of the source pointer variable and the address of the destination pointer variable in the pointing relation between each pointer variable according to the pointing relation between the pointer variables in the structural information of the multi-level pointer parameters and the absolute address offset of each pointer variable;
the second processor assigns addresses of target pointer variables in the pointing relation among the pointer variables to a source pointer, and reconstructs the multi-level pointer parameters according to the structural information of the multi-level pointer parameters;
the second processor operates the function to be operated according to the information of the function to be operated and the reconstructed multi-level pointer parameters to obtain an operation result;
and the second processor sends a second network message to the first processor, wherein the second network message contains the operation result.
In one possible implementation, the pointing relationship between the pointer variables includes:
The number of pointing relationships between pointer variables;
the pointing relationship between each pointer variable contains the identity and address offset of the source pointer variable and the identity and address offset of the destination pointer variable.
In one possible implementation manner, the second processor calculates, according to a pointing relationship between pointer variables in the structural information of the multi-level pointer parameters and an absolute address offset of each pointer variable, an address of a source pointer variable and an address of a destination pointer variable in the pointing relationship between each pointer parameter, including:
the second processor takes the first address of the structural information of the multi-level pointer parameter in the cache as the first address of the multi-level pointer parameter;
and the second processor calculates the address of the source pointer variable and the address of the destination pointer variable in the pointing relation between each pointer variable according to the head address of the multi-level pointer parameter and the absolute address offset of each pointer variable.
In a third aspect, the present application provides a first processor for use in a computing device having a plurality of processors, comprising:
the storage unit is used for caching data;
a processing unit, configured to determine a second processor to which the function to be executed belongs; determining that the function to be operated contains multi-level pointer parameters, wherein the multi-level pointer parameters contain a plurality of pointer variables, and at least one pointer variable of the plurality of pointer variables points to other pointer variables; acquiring the structural information of the multi-level pointer parameters, and storing the structural information into a continuous address cache in the storage unit; wherein the structural information is used to characterize: the multi-level pointer parameter comprises the number of pointer variables, the variable information of each pointer variable and the pointing relation among the pointer variables; the variable information of any pointer variable comprises the length and the head address of the pointer variable; acquiring the number of pointer variables contained in the multi-level pointer parameters and the variable information of each pointer variable from the structure information;
A communication unit, configured to send a first network message to the second processor, where the first network message includes: the structure information of the multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, the variable information of each pointer variable and the information of the function to be operated; and receiving a second network message sent by the second processor, wherein the second network message comprises an operation result of the second processor on the function to be operated.
In one possible implementation manner, the processing unit is specifically configured to, when determining that the function to be executed includes multiple levels of pointer parameters: when the first processor determines that the length of the specified parameter is greater than or equal to the set length, the first processor determines that the multi-stage pointer parameter is contained in the function to be operated.
In one possible implementation, the pointing relationship between pointer variables includes: the number of pointing relationships between pointer variables; the pointing relationship between each pointer variable contains the identity and address offset of the source pointer variable and the identity and address offset of the destination pointer variable.
In a fourth aspect, the present application provides a second processor for use in a computing device having a plurality of processors, comprising:
the storage unit is used for caching data;
the communication unit is configured to receive a first network message sent by the first processor, where the first network message includes: the method comprises the steps of structural information of multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, variable information of each pointer variable and information of a function to be operated; wherein the structural information is used to characterize: the multi-level pointer parameter comprises the number of pointer variables, the variable information of each pointer variable and the pointing relation among the pointer variables; the variable information of any pointer variable comprises the length and the head address of the pointer variable;
the processing unit is used for storing the structural information of the multi-level pointer parameters into the continuous address cache in the storage unit, and determining the absolute address offset of each pointer variable in the multi-level pointer parameters according to the number of pointer variables contained in the multi-level pointer parameters and the variable information of each pointer variable contained in the first network message; calculating the address of a source pointer variable and the address of a destination pointer variable in the pointing relation between each pointer variable according to the pointing relation between the pointer variables in the structural information of the multi-level pointer parameters and the absolute address offset of each pointer variable; assigning addresses of target pointer variables in the pointing relation among the pointer variables to a source pointer, and reconstructing the multi-level pointer parameters according to the structural information of the multi-level pointer parameters; operating the function to be operated according to the information of the function to be operated and the reconstructed multi-stage pointer parameters to obtain an operation result;
The communication unit is further configured to send a second network message to the first processor, where the second network message includes the operation result.
In one possible implementation, the pointing relationship between the pointer variables includes: the number of pointing relationships between pointer variables; the pointing relationship between each pointer variable contains the identity and address offset of the source pointer variable and the identity and address offset of the destination pointer variable.
In one possible implementation manner, the processing unit is specifically configured to, when calculating the address of the source pointer variable and the address of the destination pointer variable in the pointing relationship between each pointer variable according to the pointing relationship between the pointer variables in the structure information of the multi-level pointer parameter and the absolute address offset of each pointer variable:
taking the first address of the structural information of the multi-level pointer parameter in the cache as the first address of the multi-level pointer parameter; and calculating the address of the source pointer variable and the address of the destination pointer variable in the pointing relation between each pointer variable according to the head address of the multi-level pointer parameter and the absolute address offset of each pointer variable.
In a fifth aspect, embodiments of the present application provide a computing device configured to perform the units of the steps of the above aspects.
In a sixth aspect, embodiments of the present application provide a computer readable storage medium storing a computer program, which when executed on an electronic device, causes the electronic device to perform the method provided in each or any one of the possible implementations described above.
In a seventh aspect, embodiments of the present application provide a computer program which, when run on a computer, causes the computer to perform the method provided in each of the above aspects or any one of the possible implementations.
In an eighth aspect, embodiments of the present application provide a chip for reading a computer program stored in a memory, and performing the method involved in the above aspects.
Drawings
FIG. 1 is a block diagram of a computing device provided in an embodiment of the present application;
FIG. 2 is a flowchart of a method for invoking a function according to an embodiment of the present application;
fig. 3 is a block diagram of a processor a according to an embodiment of the present application;
fig. 4 is a block diagram of a processor B according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings, wherein it is apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The embodiment of the application provides a function calling method and device, which are used for solving the problem of function calling which comprises multiple stages of pointer parameters and is used for crossing processors. The method and the device described in the present application are based on the same inventive concept, and because the principles of solving the problems by the method and the device are similar, the implementation of the device and the method can be referred to each other, and the repetition is not repeated.
In the technical scheme of the embodiment of the application, when a first processor in a computing device determines that a function to be executed in the program belongs to a second processor in the computing device in the process of executing the program, and the function to be executed contains multi-stage pointer parameters, the first processor can send structural information of the multi-stage pointer parameters, the number and information of pointer variables contained in the multi-stage pointer parameters, and information of the function to be executed to the second processor through a first network message; in this way, after receiving the first network message, the second processor can reconstruct the multi-level pointer parameters according to various information therein and operate the function to be operated, thereby obtaining an operation result; finally, the second processor returns the operation result to the first processor through the second network message. This approach may enable cross-processor function calls that contain multiple levels of pointer parameters.
Some of the terms in the embodiments of the present application are explained below to facilitate understanding by those skilled in the art.
1. The computing device is a device with a computing function. In the embodiment of the application, the computing device is a device that realizes a computing function through cooperation of a plurality of processors. Currently, some examples of computing devices are: computers, notebooks, smartphones, base stations, etc.
The multiple processors in the computing device may be located in the same board card or may be located in different board cards, which is not limited in this application.
Alternatively, there is one processor a among the plurality of processors, and the program executed by the processor a may include functions belonging to other processors (for example, the processor B). When the processor a is running the program, the function needs to be called at the processor a to ensure the running of the program.
By way of example, the processor a may be a master processor that performs the main computing functions of the computer, including executing application code, and the processor B may be referred to as a slave processor that is used to assist the master processor.
2. A function refers to a piece of program code that is grouped together to perform a certain calculation and generate a result. Wherein the function may comprise at least one parameter. The types of parameters may be, but are not limited to: shaping parameters, string parameters, single level pointer parameters, multi-level pointer parameters, etc.
Wherein all pointer variables in the single level pointer parameter point to addresses.
3. The multi-level pointer parameter comprises a plurality of pointer variables, and at least one pointer variable points to other pointer variables.
For example: * P, where p is a pointer variable, and the combination indicates that this pointer variable points to an address of a pointer variable.
For another example, the pointer structure of the multi-level pointer parameter is multi-level nested. For example: defining a pointer variable q of a T-type, wherein T is q; ≡ (int) q; ≡int q, the variable q is referred to as the secondary pointer variable of base type int.
4. A plurality of, at least two.
In addition, it should be understood that in the description of this application, the words "first," "second," and the like are used merely for distinguishing between the descriptions and not for indicating or implying any relative importance or order.
Embodiments of the present application will be specifically described below with reference to the accompanying drawings.
The present application provides a block diagram of a computing device to which a function call method may be applied. Referring to fig. 1, the computing device 100 includes: a communication unit 101, a plurality of processors 102 (e.g., processor a and processor B shown in the figure), a memory 103, a display unit 105, and an input unit 106. The various constituent elements of the computing device 100 are described in detail below in conjunction with FIG. 1.
The communication unit 101 is used to enable communication interactions of the computing device 100 with other devices. Alternatively, the communication unit 101 may include: the system comprises a wireless communication module, a mobile communication module and a communication interface. Wherein the wireless communication module and the mobile communication module include an antenna for implementing the wireless communication function of the computing device 100; the communication interface is capable of plugging in a cable for implementing wired communication functions of the computing device.
The mobile communication module may provide a solution for wireless communication including 2G/3G/4G/5G, etc. as applied on a computing device. The mobile communication module can receive electromagnetic waves by the antenna, filter, amplify and the like the received electromagnetic waves, and transmit the electromagnetic waves to the modem processor for demodulation. The mobile communication module can amplify the signal modulated by the modulation and demodulation processor and convert the signal into electromagnetic waves to radiate through the antenna. In some embodiments, at least some of the functional modules of the mobile communication module may be disposed in the processor 102. In some embodiments, at least some of the functional modules of the mobile communication module may be provided in the same device as at least some of the modules of the processor 102.
The wireless communication module may provide solutions for wireless communication including wireless local area network (wireless local area networks, WLAN) (e.g., wireless fidelity (wireless fidelity, wi-Fi) network), bluetooth (BT), global navigation satellite system (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), near field wireless communication technology (near field communication, NFC), infrared technology (IR), etc. for application on an electronic device. The wireless communication module may be one or more devices that integrate at least one communication processing module. The wireless communication module receives electromagnetic waves via the antenna 2, modulates the electromagnetic wave signals, filters the electromagnetic wave signals, and transmits the processed signals to the processor 102. The wireless communication module may also receive a signal to be transmitted from the processor 102, frequency modulate and amplify the signal, and convert the signal into electromagnetic waves to radiate the electromagnetic waves through the antenna 2.
And the communication interface is used for realizing physical connection with other devices. Optionally, the communication interface is connected with the communication interfaces of the other devices through a cable, so as to realize data transmission between the computing device 100 and the other devices.
The plurality of processors 102 are control centers of the computing device 100, and may connect the components using various interfaces or lines, run an operating system, execute software programs and/or modules stored in the memory 103, and call stored data, and execute processes of various functions or processes within the computing device 100, so as to implement various services based on the computing device 100.
In this embodiment, the number of the plurality of processors 102 is not limited to two, but may be more than two. Wherein either processor may call a function in the other processor. Optionally, one master processor exists among the plurality of processors 102, and the other processors are slave processors. The master processor may call functions belonging to the slave processor during the running of the program. Communication interactions may be performed between any two processors of the plurality of processors 102, transmitting network messages to enable cross-processor function calls.
A buffer 1021 is also provided in each of the plurality of processors 102 for buffering instructions and data of the processor. In some embodiments, the buffer 1021 in the processor is a cache memory. The register 1021 may hold instructions or data that the processor has just used or recycled. If the processor needs to reuse the instruction or data, it can be called directly from the cache 1021. Repeated access is avoided, and the waiting time of the processor is reduced, so that the efficiency of the system is improved.
In the embodiment of the application, any processor may store a function, a parameter in the function, and related information of the parameter in an internal memory thereof during the execution of the program.
The display unit 105 is used for a user interface. The display unit 105 may also be referred to as a display panel or screen. The display unit may employ a liquid crystal display (liquid crystal display, LCD), an organic light-emitting diode (OLED), an active-matrix organic light emitting diode (AMOLED), a flexible light-emitting diode (flex), a mini, a Micro-OLED, a quantum dot light-emitting diode (quantum dot light emitting diodes, QLED), or the like.
The input unit 106 may be used to receive character information and instructions input by a user. Alternatively, the input unit 106 may include a touch screen 1061 and other input devices (e.g., function keys).
The touch screen 1061 is configured to collect information corresponding to a touch operation of a user, and the processor 102 executes a corresponding command after receiving the information. Alternatively, the touch screen 1061 may be implemented using various types of resistive, capacitive, infrared, and surface acoustic waves. For example, a user may initiate a function of environmental activity awareness through the touch screen 1061. The touch screen may be coupled with the display panel as a touch display screen.
Those skilled in the art will appreciate that the architecture of the computing device shown in fig. 1 is not limiting of the computing device, and that embodiments of the present application provide a computing device that may include more or fewer components than shown, or may combine certain components, or may be a different arrangement of components.
Embodiments of the present application provide a method of function invocation that is suitable for use in a computing device 100 as shown in fig. 1. The first processor and the second processor involved in the following method may be any two processors of the plurality of processors 102 in the computing device 100, such as processor a and processor B. Referring to fig. 2, the flow of the method includes:
s201: and the first processor determines a second processor to which a function to be operated belongs in the program in the process of operating the program.
Illustratively, the remote call function prototype in the first processor is as follows:
the dstsfield is a processor to which a function to be executed belongs, namely a second processor, u32Cmd is a cross-processor call function command word, osp_addr_val represents different processor bit widths, u32 is defined when 32 bits are defined, u64 is defined when 64 bits are defined, arg represents a user-specified parameter, and u32Arglen is the length of different types of parameters.
S202: the first processor determines that the function to be run contains multiple levels of pointer parameters. The multi-level pointer parameter comprises a plurality of pointer variables, and at least one pointer variable points to other pointer variables.
In one embodiment, the first processor may perform S202 by:
first, it is determined that the function to be run contains a specified parameter.
And then, determining whether the function to be operated contains multi-stage pointer parameters according to the length of the designated parameters in the function to be operated.
Optionally, when the first processor determines that the length of the specified parameter in the function to be executed is greater than or equal to a set length, it is determined that the function to be executed includes the multi-level pointer parameter. Wherein, the set length can take a value of 2048.
The description will be continued taking the remote call function prototype as an example.
The first processor may determine whether the setting parameter in the function to be run includes a multi-level pointer parameter by determining the u32Arglen value size:
first case: when the length u32Arglen of the parameter is 0, the first processor determines that the parameter type is integer data.
Second case: when the parameter is greater than 0 and less than 2047 in length, then the first processor determines that the parameter type is single level pointer data.
Third case: when the length of the parameter is equal to 2048, then the first processor determines that the parameter type is multi-level pointer data.
S203: the first processor acquires the structure information of the multi-level pointer parameters in the function to be operated, and stores the structure information into a cache with continuous addresses; wherein the structural information is used to characterize: the multi-level pointer parameter comprises the number of pointer variables, the variable information of each pointer variable and the pointing relation among the pointer variables; the variable information of any one pointer variable contains the length and the head address of the pointer variable.
In one embodiment, the first processor may obtain the structural information of the multi-level pointer parameter in the function to be executed through a preset function. The structure information may be represented by the global variable g_streospioctl argpatch. The specific structure is as follows:
specifically, the specific structure of the information osp_stru_rioctl_arg_info of the pointer variable may include:
(1) Format of 64bit data
(2) Format of 32bit data
As can be seen from the above two formats, the variable information of any pointer variable includes the length and the head address of the pointer variable, and can be compatible with 32-bit and 64-bit data.
Specifically, the pointing relationship of pointer variables may be embodied by osp_stru_rioctl_ptr_info:
the osp_stru_rioct_ptr_info structure records the pointing relation between each pointer variable, specifically including the identifier and address offset of the source pointer variable and the identifier and address offset of the destination pointer variable.
From the above description, the structural information of the multi-level pointer parameter can be used to characterize: the multi-level pointer parameter comprises the number of pointer variables, the variable information of each pointer variable and the pointing relation among the pointer variables; the variable information of any one pointer variable contains the length and the head address of the pointer variable.
Optionally, the structural information of the multi-level pointer parameter may be stored in the address-consecutive buffer 1021.
S204: the first processor acquires the number of pointer variables contained in the multi-level pointer parameter and variable information of each pointer variable from the structure information. The information which can be acquired by the first processor is also stored in a cache which is continuous with the structure information address.
Through S203 and S204, the first processor may expand the pointing relationship of the multi-level pointer parameter and tile the pointing relationship into a segment of address-continuous cache.
S205: the first processor sends a first network message to the second processor through the first network message, wherein the first network message comprises the following components: the structure information of the multi-level pointer parameter, the number of pointer variables contained in the multi-level pointer parameter, the variable information of each pointer variable, and the information of the function to be executed. The second processor receives the first network message sent by the first processor.
In one embodiment, the first processor may send the first network message to a second processor over a communication interface. Alternatively, the communication interface may be defined as:
OSP_STATUS Osp_Register_Rioct1_Hook(u32 u32Cmd,
void *pArg,
OSP_STRU_RIOCTL_ARG_PAT CH*pstruArgPatch)
s206: the second processor determines an absolute address offset of each pointer variable in the multi-level pointer parameter according to the number of pointer variables contained in the multi-level pointer parameter contained in the first network message and variable information of each pointer variable.
And after receiving the first network message, the second processor stores the structural information of the multi-level pointer parameters into a cache memory with continuous addresses. Then, according to the number of pointer variables contained in the multi-level pointer parameter contained in the first network message and the variable information of each pointer variable, determining the absolute address offset of each pointer variable in the multi-level pointer parameter. Alternatively, the second processor may determine by:
The second processor can sort all pointer variables according to the order from small to large according to the first address of the pointer variable in each pointer variable information; determining that the absolute address offset of the first pointer variable is 0; the second processor then determines the absolute address offset of the second pointer variable as the length of the first pointer variable; the absolute offset address of the third pointer variable is the sum of the length of the first pointer variable and the length of the second pointer variable, and so on, so as to determine the absolute offset address of each pointer variable in the multi-level pointer parameter.
Through S206, the second processor may determine an absolute offset address of each pointer variable in the multi-level pointer parameter, so as to facilitate subsequent calculation of an address of a source pointer variable and an address of a destination pointer variable in a pointing relationship between each pointer variable.
S207: and the second processor calculates the address of the source pointer variable and the address of the destination pointer variable in the pointing relation between each pointer variable according to the pointing relation between the pointer variables in the structural information of the multi-level pointer parameters and the absolute address offset of each pointer variable.
The specific steps of the second processor executing S207 are as follows:
a1: the second processor takes the first address of the structural information of the multi-level pointer parameter in the cache as the first address of the multi-level pointer parameter.
a2: and the second processor calculates the address of the source pointer variable and the address of the destination pointer variable in the pointing relation between each pointer variable according to the head address of the multi-level pointer parameter and the absolute address offset of each pointer variable.
Alternatively, the second processor may perform step a2 by the following algorithm:
b1: the second processor determines a source pointer variable and a destination pointer variable in a pointing relation between the first pointer variables according to the structural information of the multi-level pointer parameters;
b2: the second processor determining an absolute address offset of the source pointer variable and an address offset of the destination pointer variable;
b3: the second processor takes the sum of the head address determined in a1 and the absolute address offset of the source pointer variable as the address of the source pointer variable; the second processor takes the sum of the head address determined in a1 and the absolute address offset of the destination pointer variable as the address of the destination pointer variable;
b4: the second processor repeats the above steps to determine the address of the source pointer variable and the address of the destination pointer variable in the pointing relationship between the next pointer variables until the address of the source pointer variable and the address of the destination pointer variable in the pointing relationship between each pointer variable are determined.
Through S207, the second processor performs reorganization of the multi-level pointer parameters according to the determined address of the source pointer variable and the address of the destination pointer variable in the pointing relationship between each pointer variable in the multi-level pointer parameters.
S208: and the second processor assigns the address of the target pointer variable in the pointing relation between each pointer variable to the source pointer, and reconstructs the multi-level pointer parameters according to the structural information of the multi-level pointer parameters.
Through S208, the second processor reorganizes pointer parameters tiled in a section of address continuous buffer memory in the second processor according to the structure information of the multi-level pointer parameters, so as to realize the reconstruction of the multi-level pointer parameters.
S209: and the second processor operates the function to be operated according to the information of the function to be operated and the reconstructed multi-level pointer parameter to obtain an operation result.
S210: and the second processor sends a second network message to the first processor, wherein the second network message contains the operation result.
S211: and the first processor receives the second network message from the second processor to obtain the operation result of the function to be operated, and then continues to operate the program according to the operation result.
In the method, when a first processor in a computing device determines that a function to be executed in the program belongs to a second processor in the computing device in the process of executing the program and the function to be executed contains multi-stage pointer parameters, the first processor can send structure information of the multi-stage pointer parameters, the number and information of pointer variables contained in the multi-stage pointer parameters and the information of the function to be executed to the second processor through a first network message; in this way, after receiving the first network message, the second processor can reconstruct the multi-level pointer parameters according to various information therein and operate the function to be operated, thereby obtaining an operation result; finally, the second processor returns the operation result to the first processor through the second network message. This approach may enable cross-processor function calls that contain multiple levels of pointer parameters.
Based on the above embodiments, the present embodiments provide a first processor 300, where the first processor 300 is applied to a computing device having a plurality of processors, and referring to fig. 3, the first processor 300 includes: a storage unit 301, a processing unit 302, a communication unit 303, wherein:
a storage unit 301 for buffering data.
A processing unit 302, configured to determine a second processor to which the function to be executed belongs; determining that the function to be operated contains multi-level pointer parameters, wherein the multi-level pointer parameters contain a plurality of pointer variables, and at least one pointer variable of the plurality of pointer variables points to other pointer variables; acquiring the structural information of the multi-level pointer parameters, and storing the structural information into a continuous address cache in the storage unit; wherein the structural information is used to characterize: the multi-level pointer parameter comprises the number of pointer variables, the variable information of each pointer variable and the pointing relation among the pointer variables; the variable information of any pointer variable comprises the length and the head address of the pointer variable; and acquiring the number of pointer variables contained in the multi-level pointer parameters and the variable information of each pointer variable from the structure information.
A communication unit 303, configured to send a first network message to the second processor, where the first network message includes: the structure information of the multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, the variable information of each pointer variable and the information of the function to be operated; and receiving a second network message sent by the second processor, wherein the second network message comprises an operation result of the second processor on the function to be operated.
Optionally, when determining that the function to be executed includes multiple levels of pointer parameters, the processing unit 302 is specifically configured to: when the first processor determines that the length of the specified parameter is greater than or equal to the set length, the first processor determines that the multi-stage pointer parameter is contained in the function to be operated.
Specifically, the pointing relationship between pointer variables includes: the number of pointing relationships between pointer variables; the pointing relationship between each pointer variable contains the identity and address offset of the source pointer variable and the identity and address offset of the destination pointer variable.
Based on the above embodiments, the present application further provides a second processor 400, where the second processor 400 is applied to a computing device having a plurality of processors, and referring to fig. 4, the first processor 400 includes: a storage unit 401, a processing unit 402, a communication unit 403, wherein:
a storage unit 401 for caching data.
A communication unit 403, configured to receive a first network message sent by the first processor, where the first network message includes: the method comprises the steps of structural information of multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, variable information of each pointer variable and information of a function to be operated; wherein the structural information is used to characterize: the multi-level pointer parameter comprises the number of pointer variables, the variable information of each pointer variable and the pointing relation among the pointer variables; the variable information of any one pointer variable contains the length and the head address of the pointer variable.
A processing unit 402, configured to store the structure information of the multi-level pointer parameters in a cache with continuous addresses in the storage unit, and determine an absolute address offset of each pointer variable in the multi-level pointer parameters according to the number of pointer variables included in the multi-level pointer parameters and variable information of each pointer variable included in the first network message; calculating the address of a source pointer variable and the address of a destination pointer variable in the pointing relation between each pointer variable according to the pointing relation between the pointer variables in the structural information of the multi-level pointer parameters and the absolute address offset of each pointer variable; assigning addresses of target pointer variables in the pointing relation among the pointer variables to a source pointer, and reconstructing the multi-level pointer parameters according to the structural information of the multi-level pointer parameters; and operating the function to be operated according to the information of the function to be operated and the reconstructed multi-stage pointer parameters to obtain an operation result.
The communication unit 403 is further configured to send a second network message to the first processor, where the second network message includes the operation result.
Specifically, the pointing relationship between the pointer variables includes: the number of pointing relationships between pointer variables; the pointing relationship between each pointer variable contains the identity and address offset of the source pointer variable and the identity and address offset of the destination pointer variable.
Optionally, the processing unit 402 is specifically configured to, when calculating the address of the source pointer variable and the address of the destination pointer variable in the pointing relationship between each pointer variable according to the pointing relationship between the pointer variables in the structure information of the multi-level pointer parameter and the absolute address offset of each pointer variable:
taking the first address of the structural information of the multi-level pointer parameter in the cache as the first address of the multi-level pointer parameter; and calculating the address of the source pointer variable and the address of the destination pointer variable in the pointing relation between each pointer variable according to the head address of the multi-level pointer parameter and the absolute address offset of each pointer variable.
Based on the above embodiments, the present application provides a computing device for performing the units of the steps in the above embodiments.
Based on the above embodiments, the present application provides a computer-readable storage medium having stored therein computer instructions that, when executed by a computer, cause the computer to execute a function calling method provided in the above embodiments.
Based on the above embodiments, the present application further provides a chip for reading and executing the computer program stored in the memory, so as to implement a function calling method provided in the above embodiments. It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.
Claims (14)
1. A function call method applied to a computing device having a plurality of processors, the method comprising:
the first processor determines a second processor to which a function to be run belongs;
the first processor determines that the function to be operated contains multi-level pointer parameters, wherein the multi-level pointer parameters contain a plurality of pointer variables, and at least one pointer variable in the plurality of pointer variables points to other pointer variables;
the first processor acquires the structure information of the multi-level pointer parameters and stores the structure information into a cache with continuous addresses; wherein the structural information is used to characterize: the multi-level pointer parameter comprises the number of pointer variables, the variable information of each pointer variable and the pointing relation among the pointer variables; the variable information of any pointer variable comprises the length and the head address of the pointer variable;
the first processor acquires the number of pointer variables contained in the multi-level pointer parameter and variable information of each pointer variable from the structure information;
the first processor sends a first network message to the second processor, wherein the first network message comprises: the structure information of the multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, the variable information of each pointer variable and the information of the function to be operated;
The first processor receives a second network message sent by the second processor, wherein the second network message comprises an operation result of the second processor on the function to be operated.
2. The method of claim 1, wherein the first processor determining that the function to be run contains multi-level pointer parameters comprises:
when the first processor determines that the length of the specified parameter is greater than or equal to the set length, the first processor determines that the multi-stage pointer parameter is contained in the function to be operated.
3. The method of claim 1, wherein the pointing relationship between pointer variables comprises:
the number of pointing relationships between pointer variables;
the pointing relationship between each pointer variable contains the identity and address offset of the source pointer variable and the identity and address offset of the destination pointer variable.
4. A function call method applied to a computing device having a plurality of processors, the method comprising:
the second processor receives a first network message sent by the first processor, wherein the first network message comprises: the method comprises the steps of structural information of multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, variable information of each pointer variable and information of a function to be operated; wherein the structural information is used to characterize: the multi-level pointer parameter comprises the number of pointer variables, the variable information of each pointer variable and the pointing relation among the pointer variables; the variable information of any pointer variable comprises the length and the head address of the pointer variable; the second processor stores the structural information of the multi-level pointer parameters into a cache with continuous addresses;
The second processor determines the absolute address offset of each pointer variable in the multi-level pointer parameter according to the number of pointer variables contained in the multi-level pointer parameter contained in the first network message and the variable information of each pointer variable;
the second processor calculates the address of the source pointer variable and the address of the destination pointer variable in the pointing relation between each pointer variable according to the pointing relation between the pointer variables in the structural information of the multi-level pointer parameters and the absolute address offset of each pointer variable;
the second processor assigns addresses of target pointer variables in the pointing relation among the pointer variables to a source pointer, and reconstructs the multi-level pointer parameters according to the structural information of the multi-level pointer parameters;
the second processor operates the function to be operated according to the information of the function to be operated and the reconstructed multi-level pointer parameters to obtain an operation result;
and the second processor sends a second network message to the first processor, wherein the second network message contains the operation result.
5. The method of claim 4, wherein the pointing relationship between pointer variables comprises:
The number of pointing relationships between pointer variables;
the pointing relationship between each pointer variable contains the identity and address offset of the source pointer variable and the identity and address offset of the destination pointer variable.
6. The method of claim 4, wherein the second processor calculating the address of the source pointer variable and the address of the destination pointer variable in the pointing relationship between each pointer variable based on the pointing relationship between the pointer variables in the structure information of the multi-level pointer parameter, the absolute address offset of each pointer variable, comprises:
the second processor takes the first address of the structural information of the multi-level pointer parameter in the cache as the first address of the multi-level pointer parameter;
and the second processor calculates the address of the source pointer variable and the address of the destination pointer variable in the pointing relation between each pointer variable according to the head address of the multi-level pointer parameter and the absolute address offset of each pointer variable.
7. A first processor for application to a computing device having a plurality of processors, comprising:
the storage unit is used for caching data;
a processing unit, configured to determine a second processor to which the function to be executed belongs; determining that the function to be operated contains multi-level pointer parameters, wherein the multi-level pointer parameters contain a plurality of pointer variables, and at least one pointer variable of the plurality of pointer variables points to other pointer variables; acquiring the structural information of the multi-level pointer parameters, and storing the structural information into a continuous address cache in the storage unit; wherein the structural information is used to characterize: the multi-level pointer parameter comprises the number of pointer variables, the variable information of each pointer variable and the pointing relation among the pointer variables; the variable information of any pointer variable comprises the length and the head address of the pointer variable; acquiring the number of pointer variables contained in the multi-level pointer parameters and the variable information of each pointer variable from the structure information;
A communication unit, configured to send a first network message to the second processor, where the first network message includes: the structure information of the multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, the variable information of each pointer variable and the information of the function to be operated; and receiving a second network message sent by the second processor, wherein the second network message comprises an operation result of the second processor on the function to be operated.
8. The first processor of claim 7, wherein the processing unit, when determining that the function to be executed includes a multi-level pointer parameter, is specifically configured to:
when the first processor determines that the length of the specified parameter is greater than or equal to the set length, the first processor determines that the multi-stage pointer parameter is contained in the function to be operated.
9. The first processor of claim 7, wherein the pointing relationship between pointer variables comprises:
the number of pointing relationships between pointer variables;
the pointing relationship between each pointer variable contains the identity and address offset of the source pointer variable and the identity and address offset of the destination pointer variable.
10. A second processor for application to a computing device having a plurality of processors, comprising:
the storage unit is used for caching data;
the communication unit is configured to receive a first network message sent by the first processor, where the first network message includes: the method comprises the steps of structural information of multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, variable information of each pointer variable and information of a function to be operated; wherein the structural information is used to characterize: the multi-level pointer parameter comprises the number of pointer variables, the variable information of each pointer variable and the pointing relation among the pointer variables; the variable information of any pointer variable comprises the length and the head address of the pointer variable;
the processing unit is used for storing the structural information of the multi-level pointer parameters into the continuous address cache in the storage unit; determining the absolute address offset of each pointer variable in the multi-level pointer parameter according to the number of pointer variables contained in the multi-level pointer parameter contained in the first network message and the variable information of each pointer variable; calculating the address of a source pointer variable and the address of a destination pointer variable in the pointing relation between each pointer variable according to the pointing relation between the pointer variables in the structural information of the multi-level pointer parameters and the absolute address offset of each pointer variable; assigning addresses of target pointer variables in the pointing relation among the pointer variables to a source pointer, and reconstructing the multi-level pointer parameters according to the structural information of the multi-level pointer parameters; operating the function to be operated according to the information of the function to be operated and the reconstructed multi-stage pointer parameters to obtain an operation result;
The communication unit is further configured to send a second network message to the first processor, where the second network message includes the operation result.
11. The second processor of claim 10, wherein the pointing relationship between the pointer variables comprises:
the number of pointing relationships between pointer variables;
the pointing relationship between each pointer variable contains the identity and address offset of the source pointer variable and the identity and address offset of the destination pointer variable.
12. The second processor of claim 10, wherein the processing unit, when calculating the address of the source pointer variable and the address of the destination pointer variable in the pointing relationship between each pointer variable based on the pointing relationship between the pointer variables in the structure information of the multi-level pointer parameter, the absolute address offset of each pointer variable, is specifically configured to:
taking the first address of the structural information of the multi-level pointer parameter in the cache as the first address of the multi-level pointer parameter; and calculating the address of the source pointer variable and the address of the destination pointer variable in the pointing relation between each pointer variable according to the head address of the multi-level pointer parameter and the absolute address offset of each pointer variable.
13. A computing device, comprising:
a first processor for performing the method of any of claims 1-3;
a second processor for performing the method of any of claims 4-6.
14. A computer readable storage medium, characterized in that the computer readable storage medium has stored therein a computer program which, when run on an electronic device, causes the electronic device to perform the method according to any of claims 1-6.
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| CN103135964A (en) * | 2011-12-05 | 2013-06-05 | 联想(北京)有限公司 | Method and electronic equipment of calling function across instruction set |
| CN106649084A (en) * | 2016-09-14 | 2017-05-10 | 腾讯科技（深圳）有限公司 | Function call information obtaining method and apparatus, and test device |
| JP2019144857A (en) * | 2018-02-21 | 2019-08-29 | 富士通株式会社 | Information processing device, compiling method, and compiling program |
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| CN103135964A (en) * | 2011-12-05 | 2013-06-05 | 联想(北京)有限公司 | Method and electronic equipment of calling function across instruction set |
| CN106649084A (en) * | 2016-09-14 | 2017-05-10 | 腾讯科技（深圳）有限公司 | Function call information obtaining method and apparatus, and test device |
| JP2019144857A (en) * | 2018-02-21 | 2019-08-29 | 富士通株式会社 | Information processing device, compiling method, and compiling program |
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