CN112882722A - Compiling method, chip, computer readable medium - Google Patents
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Abstract
The present disclosure provides a compiling method for a chip, the chip including a plurality of processing cores, the method including: acquiring fault processing core information of the chip; and mapping an algorithm compiling result to the processing core without the fault of the chip according to the fault processing core information of the chip. The disclosure also provides a chip and a computer readable medium.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a compiling method for a chip, and a computer-readable medium.
Background
A chip (e.g., an artificial intelligence chip) may be composed of one or more processors, and one processor usually integrates multiple complete computing engines (or processing cores), and multiple processing cores in one processor and processing cores of different processors may cooperate with each other to jointly complete a task.
In an actual production process, some processing cores of a chip often fail due to manufacturing reasons and the like, and the failed processing cores cannot execute an algorithm (or cannot map the algorithm to the failed processing cores).
In a scenario (e.g., a cloud computing center) using a multi-chip architecture, when a chip for handling a core fault exists in the multi-chip architecture, the chip may not be used, and even the entire chip of the multi-chip architecture needs to be discarded, which increases the manufacturing cost of the chip.
Disclosure of Invention
The present disclosure provides a compiling method for a chip, and a computer-readable medium.
In a first aspect, the present disclosure provides a compiling method, where the compiling method is applied to a chip, where the chip includes a plurality of processing cores, and the compiling method includes: acquiring fault processing core information of the chip; and mapping an algorithm compiling result to the processing core without the fault of the chip according to the fault processing core information of the chip.
In a second aspect, the present disclosure provides a chip comprising: a plurality of processing cores; the information module is used for acquiring fault processing core information of the chip; and the compiling module is used for mapping the algorithm compiling result to the processing core without the fault of the chip according to the fault processing core information of the chip.
In a third aspect, the present disclosure provides a computer readable medium having stored thereon a computer program, wherein the computer program, when executed by a processing core, implements the compiling method described above.
In the compiling method for a chip, the chip and the computer readable medium provided by the disclosure, the chip acquires the fault handling core information of the chip, and maps the algorithm compiling result to the processing core of the chip without fault according to the acquired fault handling core information of the chip. Because the algorithm compiling result is mapped to the processing core of the chip which is not in fault, the processing core of the chip which is in fault can not be mapped with the algorithm compiling result, namely the processing core of the chip which is in fault does not need to execute the algorithm compiling result, the algorithm compiling result can be executed by the chip, the condition that the chip can not be used is avoided, the utilization rate of chip resources is improved, and the manufacturing cost of the chip is reduced.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure and not to limit the disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:
fig. 1 is a flowchart of a compiling method for a chip according to an embodiment of the disclosure;
fig. 2 is a flowchart of another compiling method for a chip according to an embodiment of the disclosure;
FIG. 3 is a flowchart of a portion of steps of another compiling method for a chip according to an embodiment of the disclosure;
FIG. 4 is a flowchart of another compiling method for a chip according to an embodiment of the disclosure;
FIG. 5 is a flowchart of a portion of steps of another compiling method for a chip according to an embodiment of the disclosure;
FIG. 6 is a flowchart of a portion of steps of another compiling method for a chip according to an embodiment of the disclosure;
fig. 7 is a schematic diagram of a compiling method for a chip according to an embodiment of the disclosure;
fig. 8 is a schematic diagram of a compiling method for a chip according to an embodiment of the disclosure;
fig. 9 is a block diagram of a chip according to an embodiment of the disclosure.
Detailed Description
To facilitate a better understanding of the technical aspects of the present disclosure, exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, wherein various details of the embodiments of the present disclosure are included to facilitate an understanding, and they should be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
Embodiments of the present disclosure and features of embodiments may be combined with each other without conflict.
As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 is a flowchart of a compiling method for a chip according to an embodiment of the disclosure.
Referring to fig. 1, an embodiment of the present disclosure provides a compiling method, which is used for a chip.
The chip refers to a chip (such as a many-core chip or a multi-core chip) integrating a plurality of processing cores, that is, one chip has a plurality of processing cores.
The compiling method specifically comprises the following steps:
s101, acquiring fault processing core information of the chip.
The chip has a Unit with computing capability, such as an ARM (Advanced RISC Machine) or an APU (Accelerated Processing Unit) of the chip, to obtain the fault Processing core information of the chip.
The failure processing core refers to a processing core which fails or cannot be used temporarily for various reasons in a chip, such as a processing core which fails due to manufacturing reasons, a processing core which fails during use, a processing core which cannot be used temporarily due to overheating, error, and the like.
Because the routing of the processing core of the chip is not easy to fail, although the failed processing core does not have the computing capability (such as the capability of running the executable file corresponding to the algorithm), the failed processing core still has the routing function at a high probability and can still transmit information.
The fault handling core information refers to information of a fault handling core of the chip, such as the number of the fault handling cores of the chip, absolute coordinates of the fault handling cores on the chip, an ID (Identity Document), and the like.
After a chip is manufactured and produced, the absolute coordinates, ID and other information of each processing core are determined, and before the chip is shipped, the information of the chip is written into an efuse (one-time programmable memory) of the chip.
The efuse stored information of the chip includes basic information of the chip: such as the power supply voltage available to the chip, the version number of the chip, the date of manufacture, etc. After the production of the chip is completed, the chip is tested, and when the chip is tested, fault processing core information (such as the number of fault processing cores, absolute coordinates of the fault processing cores in the chip, ID and the like) of the chip can be acquired and can also be written into efuse of the chip.
The ARM or APU of the chip can acquire the fault processing core information of the chip by reading the efuse (one-time programmable memory) of the chip.
And S102, mapping the algorithm compiling result to a processing core without a fault of the chip according to the fault processing core information of the chip.
After the ARM or the APU of the chip acquires the fault processing core information of the chip, the algorithm compiling result is mapped to the processing core of the chip without fault according to the fault processing core information of the chip.
And the algorithm compiling result is a compiling result obtained by compiling the algorithm to be compiled corresponding to the chip.
The algorithm to be compiled corresponding to the chip is an algorithm to be implemented on the chip, the algorithm to be compiled is a problem solving method and a problem solving flow, and is a section of logic, and the chip is a physical device for actually executing the problem solving method and the problem solving flow.
The chip realizes the algorithm to be compiled by operating an executable file (such as a binary executable file) which corresponds to the algorithm to be compiled and can be executed by the chip, the process of converting the algorithm to be compiled into the executable file is the process of compiling the algorithm to be compiled, the executable file which can be executed by the chip is the algorithm compiling result, the step of compiling the algorithm to be compiled to obtain the algorithm compiling result can be completed by a server connected with the chip, and the server sends the algorithm compiling result to the chip after obtaining the algorithm compiling result.
Since the chip is a chip integrating a plurality of processing cores, and it is the processing core of the chip that finally executes the algorithm compilation result (i.e., the executable file), after the algorithm compilation result is obtained, the algorithm compilation result needs to be mapped to the processing core of the chip.
The ARM or the APU of the chip already acquires the fault processing core information of the chip, so that the algorithm compiling result can be mapped to the processing core without the fault of the chip according to the acquired fault processing core information of the chip in the process of mapping the algorithm compiling result to the chip.
Because the algorithm compiling result is mapped to the processing core of the chip which is not in fault, the processing core of the chip which is in fault can not be mapped with the algorithm compiling result, namely the processing core of the chip which is in fault does not need to execute the algorithm compiling result, the algorithm compiling result can be executed by the chip, the condition that the chip can not be used is avoided, the utilization rate of chip resources is improved, and the manufacturing cost of the chip is reduced.
Fig. 2 is a flowchart of a part of steps of another compiling method for a chip according to an embodiment of the disclosure.
Referring to fig. 2, another compiling method for a chip provided in the embodiment of the present disclosure specifically includes:
s201, acquiring fault processing core information of the chip.
The ARM or APU of the chip obtains the fault processing core information of the chip by reading the efuse of the chip, wherein the fault processing core information comprises the number of fault processing cores and the absolute coordinates of the fault processing cores.
S202, grouping algorithm compiling results according to the number of the chip fault processing cores, and obtaining grouping results to be mapped.
The ARM or APU of the chip groups (or folds) the algorithm compiling results according to the number of the fault processing cores of the chip, namely, the algorithm compiling results are divided into compiling results (namely, grouping results to be mapped) which are executed by a certain number of processing cores which do not have faults.
The algorithm compiling result may be a compiling result executed by a plurality of (e.g. a first number) processing cores, and in general, the first number is greater than the number of non-failing processing cores of the chip, so that the ARM or APU of the chip groups the compiling results executed by the first number of processing cores according to the number of non-failing processing cores in the chip, and the compiling results divided into the same group are executed by one non-failing processing core of the chip.
If the algorithm compiling result is an executable file executed by 500 processing cores, and the chip has 100 processing cores, including 6 failed processing cores and 94 non-failed processing cores, the ARM or APU of the chip groups the algorithm compiling result, and divides the algorithm compiling result into 94 groups, and the executable file in each group is executed by one non-failed processing core, that is, the to-be-mapped grouping result may be an executable file executed by the 94 non-failed processing cores.
And S203, mapping the grouping result to be mapped to the processing core with the non-fault chip.
And the ARM or APU of the chip maps the grouping result to be mapped to the processing core corresponding to the absolute coordinate determined by the chip according to the absolute coordinate of the fault processing core of the chip.
The grouping result to be mapped is to group the algorithm compiling result according to the number of the fault processing cores, the algorithm compiling result is only divided into the compiling result which can be executed by a plurality of non-fault processing cores, and the execution of each grouping by which non-fault processing core of the chip is not determined, therefore, after the grouping result to be mapped is obtained, the ARM or APU of the chip maps each grouping in the grouping result to be mapped to one non-fault processing core of the chip according to the absolute coordinates of the fault processing core of the chip.
If the chip has 100 processing cores, including 6 failed processing cores and 94 non-failed processing cores, the grouping result to be mapped is a compiling result executed by the 94 processing cores, and the process of mapping the grouping result to be mapped to the non-failed processing cores of the chip is to allocate a processing core corresponding to a determined absolute coordinate to each grouping of the grouping result to be mapped, for example, a compiling result executed by a non-failed processing core with an absolute coordinate of (1,1) as a first grouping of the grouping result to be mapped, a compiling result executed by a non-failed processing core with a second grouping of (1,2) as a second grouping of the grouping result to be mapped, and the like.
In the process of actually executing the compiling result, the processing core with the absolute coordinate of (1,1) executes the partial operation corresponding to the processing core in the executable file first, and sends the executing result to other processing cores which are not failed according to the routing file, such as the processing core with the absolute coordinate of (1,2), the processing core which receives the result and has the absolute coordinate of (1,2) executes the partial operation corresponding to the processing core in the executable file according to the result, and so on, until all the processing cores which are not failed execute the compiling result mapped to the processing core, the algorithm to be compiled is realized.
As shown in fig. 7, a chip (i.e., the largest block in fig. 7) has a plurality of processing cores (i.e., a plurality of small blocks included in the largest block in fig. 7), and the chip groups the algorithm compiling results according to the number of failed processing cores, obtains a grouping result to be mapped, and maps the grouping result to be mapped to each processing core of the chip that has not failed.
Specifically, referring to fig. 8, the ARM or APU of the chip obtains the algorithm compilation result, groups the algorithm compilation result according to the number of the fault processing cores, obtains the grouping result to be mapped, and maps the current compilation result to each processing core that has no fault, and the algorithm compilation result and the grouping result to be mapped may be stored in a memory space of the chip, such as a DDR (double data rate synchronous dynamic random access memory).
Referring to fig. 3, mapping the packet result to be mapped to the processing core having no chip failure (S203) includes:
and S301, mapping the grouping result to the processing core without the chip failure according to the computing capability of the processing core without the chip failure.
And the ARM or APU of the chip determines the absolute coordinates of the non-fault processing cores of the chip according to the absolute coordinates of the fault processing cores of the chip, acquires the computing capacity of the non-fault processing cores of the chip and maps the grouping result to the non-fault processing cores of the chip according to the computing capacity and the absolute coordinates of the non-fault processing cores.
Since a plurality of processing cores of a chip cooperate cooperatively, the reasonableness of the calculation amount of each processing core needs to be considered in the process of mapping the grouping result to the processing core without the failure of the chip, and the cooperative cooperation efficiency between the processing cores, such as data transmission and information transmission efficiency, also needs to be considered.
The reasonableness of the calculation amount of the non-fault processing core can be obtained according to the calculation capacity of the non-fault processing core, and the calculation amount divided into each non-fault processing core should be matched with the standard calculation amount which can be provided by the non-fault processing core (namely, the maximum calculation amount which can be provided by the non-fault processing core in one calculation).
For example, a standard calculation amount that an un-failed processing core can provide is a (mb), and according to actual usage experience, the calculation amount of actual operation of the un-failed processing core is preferably 70% -80% of the standard calculation amount, and too small calculation amount of actual operation may cause waste of chip performance, and too large calculation amount of actual operation may cause excessive calculation load of the chip. Therefore, the standard calculation amount of the non-fault processing core can be referred to, and the grouping result to be mapped can be reasonably mapped to the non-fault processing core of the chip.
The data transmission efficiency between the non-fault processing cores can be obtained according to the absolute coordinates of the non-fault processing cores, and the farther the distance between the two non-fault processing cores is, the longer the time required by the two non-fault processing cores to transmit data is, the lower the transmission efficiency is, so that in the process of reasonably mapping the packet result to be mapped to the non-fault processing cores of the chip, the packet result required to be transmitted to the non-fault processing cores with the shorter distance should be mapped as much as possible.
Fig. 4 is a flowchart of another compiling method for a chip according to an embodiment of the disclosure.
Referring to fig. 4, the compiling method for a chip according to the embodiment of the present disclosure specifically includes:
s401, obtaining fault processing core information of the chip.
The ARM or APU of the chip obtains the fault processing core information of the chip by reading the efuse of the chip, wherein the fault processing core information comprises the number of fault processing cores and the absolute coordinates of the fault processing cores.
S402, grouping the algorithm compiling results according to the pre-grouping results and the number of the chip fault processing cores, and obtaining grouping results to be mapped.
And the ARM or APU of the chip groups (or folds) the algorithm compiling results according to the pre-grouping result and the number of the fault processing cores of the chip, and divides the algorithm compiling results into compiling results (namely grouping results to be mapped) for a certain number of processing cores which are not in fault to execute.
The pre-grouping result is a grouping result obtained by grouping the algorithm compiling result under the condition that the number of the fault-free processing cores of the chip is a preset number.
The pre-grouping result may be obtained by grouping the algorithm compiling result according to the number of the non-fault processing cores of the chip being the preset number before the step S402 by the ARM or APU of the chip, or may be obtained by grouping the algorithm compiling result by other devices (such as a server) to obtain the pre-grouping result and then sending the pre-grouping result to the chip.
Referring to fig. 5, the step may specifically include:
s501, under the condition that the number of the non-fault processing cores of the chip is the same as the preset number, taking the pre-grouping result as a grouping result to be mapped.
S502, under the condition that the number of the non-fault processing cores of the chip is different from the preset number, grouping algorithm compiling results according to the number of the fault processing cores of the chip, and obtaining grouping results to be mapped.
If the number of the fault processing cores of the chip is consistent with the preset number of the fault processing cores, the algorithm compiling result can be directly used as the grouping result to be mapped of the chip without further processing.
And if the number of the fault processing cores of the chip is inconsistent with the preset number of the fault processing cores, grouping the algorithm compiling results according to the number of the fault processing cores of the chip, and acquiring a grouping result to be mapped.
The preset number of the fault processing cores is determined according to the characteristics of the chips, namely, the number of most of the fault processing cores of the chips in a plurality of chips manufactured in batch is possibly the preset number, and the pre-grouping result can be used as the grouping result to be mapped of most of the chips, so that the compiling workload of the chips is greatly reduced, and the computing resources of the chips are saved.
Referring to fig. 6, the step may further include:
s601, under the condition that the number of the fault-free processing cores of the chip is not less than the preset number, taking the pre-grouping result as a grouping result to be mapped.
S602, under the condition that the number of the non-fault processing cores of the chip is smaller than the preset number, grouping the algorithm compiling results according to the number of the fault processing cores of the chip, and obtaining grouping results to be mapped.
If the number of the fault processing cores of the chip is greater than or equal to the preset number of the fault processing cores, the algorithm compiling result can be directly used as the grouping result to be mapped of the chip without further processing.
And if the number of the fault processing cores of the chip is greater than the preset number of the fault processing cores, grouping the algorithm compiling results according to the number of the fault processing cores of the chip, and acquiring the grouping result to be mapped.
Compared with the method that when the number of the fault processing cores of the chip is different from the preset number, the algorithm compiling results are grouped, and when the number of the fault processing cores of the chip is larger than the preset number of the fault processing cores, the algorithm compiling results are grouped according to the number of the fault processing cores of the chip, so that the compiling workload of the chip can be further reduced, and the computing resources of the chip can be saved.
And S403, mapping the grouping result to be mapped to the processing core of which the chip has no fault.
And the ARM or APU of the chip maps the grouping result to be mapped to the processing core corresponding to the absolute coordinate determined by the chip according to the absolute coordinate of the fault processing core of the chip.
Because the algorithm compiling result is mapped to the processing core of the chip which is not in fault, the processing core of the chip which is in fault can not be mapped with the algorithm compiling result, namely the processing core of the chip which is in fault does not need to execute the algorithm compiling result, the algorithm compiling result can be executed by the chip, the condition that the chip can not be used is avoided, the utilization rate of chip resources is improved, and the manufacturing cost of the chip is reduced.
Fig. 9 is a block diagram of a chip according to an embodiment of the disclosure.
Referring to fig. 9, an embodiment of the present disclosure provides a chip 100, where the chip 100 includes:
a plurality of processing cores 101;
an information module 102, configured to obtain fault processing core information of a chip;
and the compiling module 103 is used for mapping an algorithm compiling result to a processing core of the chip without a fault according to the fault processing core information of the chip, and is also used for reading the one-time programmable memory of the chip to acquire the fault processing core information of the chip.
In addition, the embodiment of the disclosure also provides a computer readable medium, on which a computer program is stored, wherein the computer program realizes the compiling method when being executed by the processing core.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in connection with other embodiments, unless expressly stated otherwise, as would be apparent to one skilled in the art. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure as set forth in the appended claims.
Claims (10)
1. A compilation method for a chip, the chip including a plurality of processing cores, the method comprising:
acquiring fault processing core information of the chip;
and mapping an algorithm compiling result to the processing core without the fault of the chip according to the fault processing core information of the chip.
2. The compiling method of claim 1, wherein the obtaining fault handling core information of the chip comprises:
and reading the one-time programmable memory of the chip and acquiring the fault processing core information of the chip.
3. The compiling method of claim 1, wherein,
the fault processing core information comprises the number and absolute coordinates of fault processing cores;
the mapping an algorithm compiling result to the processing core without the fault of the chip according to the fault processing core information of the chip comprises the following steps:
grouping the algorithm compiling results according to the number of the chip fault processing cores to obtain grouping results to be mapped;
and mapping the grouping result to be mapped to the processing core of which the chip does not fail.
4. The compilation method of claim 3, wherein the mapping the grouped results to processing cores that have not failed the chip comprises:
and mapping the grouping result to the processing core without the chip failure according to the computing capability of the processing core without the chip failure.
5. The compiling method according to claim 3, wherein the grouping the algorithm compiling results according to the number of the chip fault processing cores, and the obtaining of the grouping result to be mapped comprises:
and grouping the algorithm compiling results according to a pre-grouping result and the number of the chip fault processing cores to obtain a grouping result to be mapped, wherein the pre-grouping result is the grouping result obtained by grouping the algorithm compiling results under the condition that the number of the chip fault processing cores is not a preset number.
6. The compiling method according to claim 5, wherein the grouping the algorithm compiling results according to the pre-grouping results and the number of the chip fault processing cores, and the obtaining of the grouping results to be mapped comprises:
under the condition that the number of the non-fault processing cores of the chip is the same as the preset number, taking the pre-grouping result as a grouping result to be mapped;
and under the condition that the number of the non-fault processing cores of the chip is different from the preset number, grouping the algorithm compiling results according to the number of the fault processing cores of the chip, and acquiring a grouping result to be mapped.
7. The compiling method according to claim 5, wherein the grouping the algorithm compiling results according to the pre-grouping results and the number of the chip fault processing cores, and the obtaining of the grouping results to be mapped comprises:
under the condition that the number of the non-fault processing cores of the chip is not less than the preset number, taking the pre-grouping result as a grouping result to be mapped;
and under the condition that the number of the non-fault processing cores of the chip is less than the preset number, grouping the algorithm compiling results according to the number of the fault processing cores of the chip, and acquiring grouping results to be mapped.
8. A chip, comprising:
a plurality of processing cores;
the information module is used for acquiring fault processing core information of the chip;
and the compiling module is used for mapping the algorithm compiling result to the processing core without the fault of the chip according to the fault processing core information of the chip.
9. The chip of claim 8,
the information module is also used for reading the one-time programmable memory of the chip and acquiring the fault processing core information of the chip.
10. A computer-readable medium, on which a computer program is stored, wherein the computer program, when being executed by a processing core, implements the compiling method according to any one of claims 1-7.
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| CN202110325748.9A CN112882722A (en) | 2021-03-26 | 2021-03-26 | Compiling method, chip, computer readable medium |
| PCT/CN2022/081695 WO2022199483A1 (en) | 2021-03-26 | 2022-03-18 | Compiling method and apparatus, electronic device, and computer-readable storage medium |
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