CN112882531B - Time sequence bias pulling method, system and equipment based on double counter - Google Patents
Time sequence bias pulling method, system and equipment based on double counter Download PDFInfo
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Abstract
The invention provides a time sequence bias pulling method, a system, equipment and a storage medium based on double counter implementation, wherein the method comprises the following steps: based on a level segment of the memory read signal, the level segment including n segments; counting n sections of the level sections in sequence according to a preset pull bias stepping time length through a first counter, and recording counting data of each section, wherein after the first counter finishes counting the level sections of the i section, the first counter assigns the counting data of the i section as 1, and the value of the second counter is i+1; and acquiring the minimum time reference of the level segment according to the count data of each segment recorded by the first counter. The method adopts two types of counters to rapidly realize the step generation of the pull bias time sequence of the signal according to the level, can calculate the reference time scale required by the system, avoids the unnecessary power consumption increase caused by the system running a too high-frequency clock, and is convenient for long-term running in a single particle irradiation environment to verify the interface performance of the memory.
Description
Technical Field
The invention belongs to the technical field of irradiation test, relates to a low-power-consumption time sequence bias method for a single-particle test of a dynamic memory, and particularly relates to a time sequence bias method, a system, equipment and a storage medium which are realized based on double counters.
Background
In the development and test process of the memory chip, a special test machine (AT) for the chip is mainly used for completing the limit bias test on the time sequence parameters of the chip interface to obtain all time parameters (namely AC characteristics including limit characteristics and normal operation characteristics) of the chip, while the AT machine is precisely and expensive, must be used in a clean room and is difficult to work in other environment test environments, especially in a single particle test environment. Therefore, in the single-particle environment application verification stage, the mode (the main control device and the memory) realized by the PCB board level is adopted to verify whether each function of the memory operates normally in various environment tests (such as high-low temperature, single-particle test and the like). The main control devices CPU, MCU, DSP are various and mainly application-oriented, so that only a few typical main control devices can be selected and the memory chip is accessed by using normal time parameter settings, and various limit situations are difficult to cover. The FPGA (programmable logic device) is used as a master control, and a hardware description language (HDL, such as Verilog language) can be used for carrying out variable counting on a reference clock period by using a counter to realize signal timing, so that the duration of a signal level is directly controlled, and the capability of controlling the time sequence bias of a memory signal is provided. The FPGA consumes more power when using a high frequency reference clock, resulting in a counter circuit that requires a larger bit width at the same time, and also resulting in increased power consumption. The high power consumption easily causes the FPGA device to trigger junction temperature protection in a high-temperature high-radiation environment to cause reset, so that the frequency of a reference clock needs to be reduced as much as possible on the basis of meeting the time bias verification requirement.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: aiming at the problems in the prior art, the invention provides a method for verifying the interface performance of a memory chip, which can reduce the power consumption of a main control device to develop a long-time sequence bias environment test in an irradiation test environment.
In order to solve the technical problems, the invention adopts the following technical scheme:
in a first aspect, the present invention provides a time sequence bias method implemented based on a dual counter, the method comprising:
a level segment based on a memory read signal, the level segment comprising n segments, wherein n is a positive integer greater than or equal to 2;
counting n sections of the level sections in sequence according to a preset pull bias stepping time length through a first counter, and recording counting data of each section, wherein after the first counter finishes counting the i-th section of the level sections, the first counter assigns the counting data of the i-th section to be 1, the value of a second counter is i+1, and i is a positive integer which is greater than or equal to 1 and less than or equal to n;
and acquiring the minimum time reference of the level segment according to the count data of each segment recorded by the first counter.
In a second aspect, the present invention further provides a timing offset system implemented based on a dual counter, where the system includes:
and a reading module: a level segment for reading a signal based on a memory, the level segment comprising n segments, wherein n is a positive integer greater than or equal to 2;
and a counting module: the method comprises the steps that n sections of level sections are counted in sequence according to preset pulling bias stepping time length through a first counter, and counting data of each section are recorded, wherein after the first counter finishes counting the i sections of the level sections, the first counter assigns the counting data of the i sections to be 1, the value of a second counter is i+1, and i is a positive integer which is greater than or equal to 1 and smaller than or equal to n;
the acquisition module is used for: and the minimum time reference of the level segment is acquired according to the count data of each segment recorded by the first counter.
In a third aspect, the present invention further provides a dual counter-based timing offset device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the steps in the dual counter-based timing offset method according to the first aspect when the processor executes the computer program.
In a fourth aspect, the present invention also provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the double counter based implementation of the time sequence bias method described in the first aspect.
The invention provides a time sequence bias pulling method based on double counter, which comprises the following steps: a level segment based on a memory read signal, the level segment comprising n segments, wherein n is a positive integer greater than or equal to 2; counting n sections of the level sections in sequence according to a preset pull bias stepping time length through a first counter, and recording counting data of each section, wherein after the first counter finishes counting the i-th section of the level sections, the first counter assigns the counting data of the i-th section to be 1, the value of a second counter is i+1, and i is a positive integer which is greater than or equal to 1 and less than or equal to n; and acquiring the minimum time reference of the level segment according to the count data of each segment recorded by the first counter. The method adopts two types of counters to rapidly realize the step generation of the pull bias time sequence of the signal according to the level, can calculate the reference time scale required by the system, avoids the unnecessary power consumption increase caused by the system running a too high-frequency clock, and is convenient for long-term running in a single particle irradiation environment to verify the interface performance of the memory.
Drawings
The following details the specific construction of the present invention with reference to the accompanying drawings
FIG. 1 is a flow chart of a timing offset method based on a dual counter implementation of the present invention;
FIG. 2 is a schematic diagram of a sub-flow of a time sequence bias method based on a dual counter implementation of the present invention;
FIG. 3 is a schematic diagram of a level segment of a time sequence bias method based on a dual counter implementation of the present invention;
FIG. 4 is a memory read timing chart of the dual counter based timing bias method of the present invention;
fig. 5 is a schematic diagram of a program module of a timing offset method implemented based on a dual counter of the present invention.
Detailed Description
In order to describe the technical content, the constructional features, the achieved objects and effects of the present invention in detail, the following description is made in connection with the embodiments and the accompanying drawings.
Referring to fig. 1, fig. 1 is a flow chart of a timing offset pulling method implemented based on a dual counter in an embodiment of the present application, where the method includes:
step 101, a level segment of a read signal based on a memory, wherein the level segment comprises n segments, and n is a positive integer greater than or equal to 2.
In the present embodiment, the timing of the signal is composed of a plurality of level segments (level segments) that are continuous in time. Different operations (such as erasing, writing, reading, resetting, etc.) on the memory are realized by injecting and reading the excitation and response of the timing signals with specific level to each pin combination of the chip. The controller of the master control end (such as a CPU, MCU, DSP, FPGA master control device or test machine) operates CE#, WE#, OE#, and Address pin signals of the memory chip according to the corresponding read timing chart, so that the corresponding address storage Data can be read back on Output pins (Data pins, 16 bits (Data [15:0 ])) in corresponding Trc time (the time for inputting the effective address into readable effective Data is minimum 110 ns). Similarly, other operations on the memory (e.g., erasing, writing, resetting, etc.) are performed in this manner, except that different operations are performed using respective corresponding timing variations and combinations of signal levels.
Step 102, counting n sections of the level sections in sequence according to a preset pull bias stepping time length through a first counter, and recording counting data of each section, wherein after the first counter finishes counting the i section of the level sections, the first counter assigns the counting data of the i section to be 1, the value of the second counter is i+1, and i is a positive integer which is greater than or equal to 1 and less than or equal to n.
In this embodiment, the first counter counts according to the duration of a certain level segment, and the second counter actually calculates how many level segments are. When the first counter finishes counting the duration of a certain level segment, the second counter is increased by 1.
And 103, acquiring the minimum time reference of the level segment according to the count data of each segment recorded by the first counter.
In this embodiment, the minimum time reference of the level segment is obtained according to the duration of each segment level segment calculated by the first counter and the pull-bias stepping duration.
The embodiment of the application provides a time sequence bias pulling method based on double-counter implementation, which comprises the following steps: a level segment based on a memory read signal, the level segment comprising n segments, wherein n is a positive integer greater than or equal to 2; counting n sections of the level sections in sequence according to a preset pull bias stepping time length through a first counter, and recording counting data of each section, wherein after the first counter finishes counting the i-th section of the level sections, the first counter assigns the counting data of the i-th section to be 1, the value of a second counter is i+1, and i is a positive integer which is greater than or equal to 1 and less than or equal to n; and acquiring the minimum time reference of the level segment according to the count data of each segment recorded by the first counter. The method adopts two types of counters to rapidly realize the step generation of the pull bias time sequence of the signal according to the level, can calculate the reference time scale required by the system, avoids the unnecessary power consumption increase caused by the system running a too high-frequency clock, and is convenient for long-term running in a single particle irradiation environment to verify the interface performance of the memory.
Further, in this embodiment, the acquiring the minimum time reference of the level segment includes:
and calculating the count full value of each level segment according to the minimum time reference.
In this embodiment, the count full value of the level segment may be obtained according to the minimum time reference and the duration of the level segment, where the duration of the level segment is fixed, and the count full value is the actual count data of the counter. The count full value of the first counter is also designed using a variable parameter. The level segments of each signal are not overlapped, so that only one first counter is needed, each segment redetermines the counting data of the current first counter through the counting data of the second counter and the pulling deviation step number, and circuit resources are saved.
Further, in this embodiment, the obtaining the minimum time reference of the level segment according to the count data of each segment recorded by the first counter includes:
and acquiring the greatest common divisor of each level segment based on the count data of each level segment and the pull bias stepping time length.
In this embodiment, please refer to fig. 3, fig. 3 is a schematic diagram of a level segment in the embodiment of the present application, and the minimum time reference scale T of the system step Period T of system clock for determining board operation sysclk General requirement T step ＝n*T sysclk Wherein n is a positive integer greater than 1. Because of the positive correlation of the frequency of the clock with the system power consumption, n=1 is typically given, using the system clock period as the minimum time reference scale: t (T) step ＝T sysclk . So that the level period time length (T a1 ，T a2 ，…，T a4 ，T b1 ，…，T e6 ) And the length of time of the pull-bias step (T) delta ) Are all T sysclk Therefore, T can be determined by taking the greatest common divisor (gcd) of each time length sysclk Is (typically generated using a voltage-controlled oscillator VCO, a phase-locked loop PLL, etc. circuit and converted to the desired T sysclk Periodic system clock signal):
T step ＝T sysclk ＝gcd(T a1 ，T a2 ，…，T a4 ，T b1 ，…，T e6 ，T delta )
in this embodiment, the condition T for directly skipping the counter of the first counter when the timing is biased a1/ T step Becomes (T) a1 /T step )±T delta The timing is regenerated. The signal with preset time sequence can be generated quickly and in real time no matter the parameter is acquired by using an internal table look-up or is input by an external interface.
Further, in this embodiment, the greatest common divisor of each of the level segments is a smallest time reference of the level segments.
Further, referring to fig. 2, fig. 2 is a schematic sub-flowchart of a time sequence bias pulling method implemented based on a dual counter in the embodiment of the present application, where sequentially counting n segments of the level segments by a first counter according to a preset bias pulling step duration includes:
step 201, the first counter counts the level segments of the ith segment based on a preset level segment duration;
step 202, if the counting duration of the first counter is the same as the preset level segment duration, the first counter counts the level segment of the i+1th segment.
In this embodiment, referring to fig. 4, fig. 4 is a memory read timing chart in the embodiment of the present application, and the level segment of a certain signal is changed in only two triggering manners: internal timing triggers and external related triggers. The internal timing trigger means that the corresponding level segment is a predefined fixed time length and is irrelevant to the change of other input and output signals, so that the end condition of the level segment is that the count value reaches a preset value; the external correlation trigger means that the count value of the level segment ending condition of the current signal has no fixed upper limit, and stops counting along with the level segment change of other correlation signals, and shifts to the next level segment. For example, a level segment jump in which A1 through A2 is an internal timing trigger in which the intra-segment count of A1 reaches a fixed value. The level segment jumps of E3 to E4 are externally related triggers where the count within the segment of C4 reaches a fixed value. The time length value and the bias pulling stepping time length of each level section can be determined according to the test specification of the memory chip interface, and the bias pulling stepping time length is used for completing time sequence bias pulling.
Further, in this embodiment, the first counter assigns the count data of the i-th segment to 1, and the second counter has a value i and includes:
counting the level segments of the (i+1) th segment based on the first counter.
In this embodiment, after the first counter counts the ith segment, the first counter assigns 1 to the count data of the ith segment, and then continues to count the level segments of the i+1 segment until the counting of all the level segments is completed.
Further, in this embodiment, the second counter returns to the initial value 1 after counting is completed.
In the present embodiment, when the second counter counts the number of segments of the level segment, the initial value 1 is returned.
Further, the embodiment of the present application further provides a timing offset system 300 implemented based on dual counters, referring to fig. 5, fig. 5 is a schematic program module diagram of the timing offset system implemented based on dual counters in the embodiment of the present application, where in the embodiment, the timing offset system implemented based on dual counters includes:
the reading module 301: a level segment for reading a signal based on a memory, the level segment comprising n segments, wherein n is a positive integer greater than or equal to 2;
counting module 302: the method comprises the steps that n sections of level sections are counted in sequence according to preset pulling bias stepping time length through a first counter, and counting data of each section are recorded, wherein after the first counter finishes counting the i sections of the level sections, the first counter assigns the counting data of the i sections to be 1, the value of a second counter is i+1, and i is a positive integer which is greater than or equal to 1 and smaller than or equal to n;
acquisition module 303: and the minimum time reference of the level segment is acquired according to the count data of each segment recorded by the first counter.
The time sequence bias pulling system based on the double counter implementation provided by the embodiment of the application can be realized: a level segment based on a memory read signal, the level segment comprising n segments, wherein n is a positive integer greater than or equal to 2; counting n sections of the level sections in sequence according to a preset pull bias stepping time length through a first counter, and recording counting data of each section, wherein after the first counter finishes counting the i-th section of the level sections, the first counter assigns the counting data of the i-th section to be 1, the value of a second counter is i+1, and i is a positive integer which is greater than or equal to 1 and less than or equal to n; and acquiring the minimum time reference of the level segment according to the count data of each segment recorded by the first counter. The method adopts two types of counters to rapidly realize the step generation of the pull bias time sequence of the signal according to the level, can calculate the reference time scale required by the system, avoids the unnecessary power consumption increase caused by the system running a too high-frequency clock, and is convenient for long-term running in a single particle irradiation environment to verify the interface performance of the memory.
Further, the present application also provides a time sequence bias device based on the dual counter implementation, which includes a memory, a processor, and a computer program stored in the memory and capable of running on the processor, wherein when the processor executes the computer program, each step in the time sequence bias method based on the dual counter implementation is implemented.
Further, the embodiment of the application further provides a computer readable storage medium, on which a computer program is stored, the computer program, when executed by a processor, implements each step in the time sequence bias method implemented based on the double counter.
The functional modules in the embodiments of the present invention may be integrated into one processing module, or each module may exist alone physically, or two or more modules may be integrated into one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
It should be noted that, for the sake of simplicity of description, the foregoing method embodiments are all expressed as a series of combinations of actions, but it should be understood by those skilled in the art that the present invention is not limited by the order of actions described, as some steps may be performed in other order or simultaneously in accordance with the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily all required for the present invention.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.
The foregoing describes a method, a system, a device and a storage medium for implementing a time sequence bias based on a dual counter, which are provided by the present invention, and the present disclosure should not be construed as limiting the present invention in view of the specific implementation and application scope of the present application according to the concepts of the embodiments of the present application.
Claims (10)
1. A timing sequence bias method implemented based on double counters, the method comprising:
a level segment based on a memory read signal, the level segment comprising n segments, wherein n is a positive integer greater than or equal to 2;
counting n sections of the level sections in sequence according to a preset pull bias stepping time length through a first counter, and recording counting data of each section, wherein after the first counter finishes counting the level sections of the i section, the first counter assigns the counting data of the i section to be 1, the value of a second counter is i+1, the second counter is used for calculating the number of the level sections, and i is a positive integer which is greater than or equal to 1 and less than or equal to n;
and acquiring the minimum time reference of the level segment according to the count data of each segment recorded by the first counter.
2. The method of claim 1, wherein the obtaining the minimum time reference for the level segment is followed by:
and calculating the count full value of each level segment according to the minimum time reference.
3. The method of claim 1, wherein said obtaining a minimum time reference for the level segment based on count data for each segment recorded by the first counter comprises:
and acquiring the greatest common divisor of each level segment based on the count data of each level segment and the pull bias stepping time length.
4. A method as claimed in claim 3, wherein the greatest common divisor of each of said level segments is the smallest time reference of said level segments.
5. The method of claim 1, wherein sequentially counting n segments of the level segments by the first counter according to a preset pull-off step duration comprises:
the first counter counts the level segments of the ith segment based on the preset level segment duration;
and if the counting time length of the first counter is the same as the preset level segment time length, the first counter counts the level segments of the (i+1) th segment.
6. The method of claim 1, wherein the first counter assigns the count data of the i-th segment to 1, and the second counter has a value of i, and further comprising:
counting the level segments of the (i+1) th segment based on the first counter.
7. The method of claim 1, wherein the second counter returns to an initial value of 1 after counting is completed.
8. A time sequential bias system implemented based on double counters, the system comprising:
and a reading module: a level segment for reading a signal based on a memory, the level segment comprising n segments, wherein n is a positive integer greater than or equal to 2;
and a counting module: the method comprises the steps that n sections of level sections are counted in sequence according to preset pulling bias stepping time length through a first counter, and counting data of each section are recorded, wherein after the first counter finishes counting the level sections of the i section, the first counter assigns the counting data of the i section to be 1, the value of a second counter is i+1, the second counter is used for calculating the number of the level sections, and i is a positive integer which is greater than or equal to 1 and less than or equal to n;
the acquisition module is used for: and the minimum time reference of the level segment is acquired according to the count data of each segment recorded by the first counter.
9. A dual counter based implemented time sequential bias device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, performs the steps of the dual counter based implemented time sequential bias method of any of claims 1 to 7.
10. A computer readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the steps of the double counter based implemented time sequential bias method according to any of claims 1 to 7.
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