CN112864229A - NMOS transistor, manufacturing method thereof and three-dimensional heterogeneous integrated chip - Google Patents
NMOS transistor, manufacturing method thereof and three-dimensional heterogeneous integrated chip Download PDFInfo
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract
The invention discloses an NMOS (N-channel metal oxide semiconductor) transistor, a manufacturing method thereof and a three-dimensional heterogeneous integrated chip, relates to the technical field of semiconductors, and is used for reducing the activation temperature of N-type impurities when a germanium-based NMOS transistor is manufactured, preventing the performance degradation of a bottom device included in the three-dimensional heterogeneous integrated chip under the condition that the germanium-based NMOS transistor is used as an upper device included in the three-dimensional heterogeneous integrated chip, and improving the working performance of the three-dimensional heterogeneous integrated chip. The manufacturing method of the NMOS transistor comprises the following steps: a fin structure is formed on a substrate. The fin structure is made of germanium. N-type impurities are doped into a source region forming region and a drain region forming region which are included in the fin-shaped structure. A metal layer is formed to cover at least the source region formation region and the drain region formation region. And carrying out low-temperature annealing treatment on the substrate on which the fin-shaped structure and the metal layer are formed so as to form a source region and a drain region in the source region forming region and the drain region forming region respectively, form a first metal contact layer on the source region and form a second metal contact layer on the drain region.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an NMOS (N-channel metal oxide semiconductor) transistor, a manufacturing method thereof and a three-dimensional heterogeneous integrated chip.
Background
In the semiconductor field, germanium materials have a high and symmetric carrier rate. Meanwhile, the forbidden bandwidth of germanium is smaller than that of silicon. Based on this, when a transistor is manufactured using a germanium-based substrate, it is possible to make the transistor have a larger drive current, a faster switching speed, and a lower drive voltage. Moreover, the germanium material has natural low-temperature process advantages, so that the germanium-based transistor becomes the first choice for manufacturing an upper-layer device included in a three-dimensional heterogeneous integrated chip.
However, in the case of using the existing manufacturing method and using the germanium-based NMOS transistor as an upper device included in the three-dimensional heterogeneous integrated chip, performance degradation of a lower device included in the three-dimensional heterogeneous integrated chip may be caused.
Disclosure of Invention
The invention aims to provide an NMOS transistor, a manufacturing method thereof and a three-dimensional heterogeneous integrated chip, which are used for reducing the activation temperature of N-type impurities when manufacturing a germanium-based NMOS transistor, preventing the performance degradation of a bottom device included in the three-dimensional heterogeneous integrated chip under the condition that the germanium-based NMOS transistor is used as an upper device included in the three-dimensional heterogeneous integrated chip, and improving the working performance of the three-dimensional heterogeneous integrated chip.
In order to achieve the above object, the present invention provides a method of manufacturing an NMOS transistor, including:
forming a fin structure on a substrate; the fin-shaped structure is made of germanium and comprises a source region forming region, a drain region forming region and a channel region positioned between the source region forming region and the drain region forming region;
doping N-type impurities into the source region forming region and the drain region forming region;
forming a metal layer at least covering the source region forming region and the drain region forming region;
and carrying out low-temperature annealing treatment on the substrate on which the fin-shaped structure and the metal layer are formed so as to form a source region and a drain region in the source region forming region and the drain region forming region respectively, form a first metal contact layer on the source region and form a second metal contact layer on the drain region.
Compared with the prior art, in the manufacturing method of the NMOS transistor, the fin-shaped structure made of germanium is formed on the substrate. And then doping N-type impurities in a source region forming region and a drain region forming region included in the fin-shaped structure. And a metal layer is formed to cover at least the source region formation region and the drain region formation region. Therefore, in the process of carrying out low-temperature annealing treatment on the substrate with the fin-shaped structure and the metal layer, the metal layer can carry out metal germanidation reaction with the source region forming region and the drain region forming region which are in contact with the metal layer, and a first metal contact layer and a second metal contact layer which are made of metal germanidation are formed. Meanwhile, in the process of the metal germanidation reaction, amorphous germanium in the source region forming region and the drain region forming region is crystallized along the crystalline phase of the metal germanidation, so that impurities can enter lattice point positions, and N-type impurity activation is realized. In other words, when the low-temperature annealing treatment is performed, the metal layer is subjected to a metal germanidation reaction with the source region formation region and the drain region formation region, respectively, so that N-type impurity activation can be induced. In addition, the N-type impurities are segregated to the interface of the metal germanide and the germanium due to the snow pear effect in the metal germanidation reaction process, so that a source region and a drain region can be obtained without higher activation temperature, and therefore when the manufacturing method of the NMOS transistor provided by the invention is adopted to manufacture an upper layer device included in the three-dimensional heterogeneous integrated chip, the performance degradation of a bottom layer device included in the three-dimensional heterogeneous integrated chip caused by the higher activation temperature can be prevented, and the working performance of the three-dimensional heterogeneous integrated chip is improved.
As can be seen from the above, in the method for manufacturing an NMOS transistor according to the present invention, by performing a low-temperature annealing process on a substrate on which a fin structure and a metal layer are formed, a first metal contact layer can be formed on a source region and a second metal contact layer can be formed on a drain region while forming a source region and a drain region in a source region formation region, respectively, without performing an annealing process for forming the source region and the drain region, and the first metal contact layer and the second metal contact layer, respectively, thereby simplifying a manufacturing process of the NMOS transistor and facilitating the manufacturing of the NMOS transistor.
The invention also provides an NMOS transistor which is manufactured by the manufacturing method of the NMOS transistor provided by the technical scheme.
Compared with the prior art, the beneficial effects of the NMOS transistor provided by the invention are the same as those of the manufacturing method of the NMOS transistor provided by the technical scheme, and the details are not repeated here.
The invention also provides a three-dimensional heterogeneous integrated chip which comprises the NMOS transistor provided by the technical scheme.
Compared with the prior art, the three-dimensional heterogeneous integrated chip provided by the invention has the same beneficial effects as the NMOS transistor manufacturing method provided by the technical scheme, and the details are not repeated here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart of a method for manufacturing an NMOS transistor according to an embodiment of the present invention;
FIG. 2 is a schematic view of a substrate according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a step structure formed on a substrate according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram illustrating a first layer of sidewall material formed over a substrate in accordance with an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a substrate after forming a first sidewall and a second sidewall on the substrate according to an embodiment of the present invention;
figure 6 is a cross-sectional view of a fin structure formed on a substrate along a width of the fin structure in an embodiment of the present invention;
figure 7 is a cross-sectional view of a fin structure formed on a substrate along a length of the fin structure in an embodiment of the present invention;
FIG. 8 is a schematic diagram illustrating a structure of an oxide layer formed on a substrate according to an embodiment of the present invention;
FIG. 9 is a schematic structural diagram illustrating the structure of the embodiment of the present invention after the oxide layer is removed;
FIG. 10 is a schematic structural diagram illustrating a first dielectric layer, a gate material layer and a protective material layer formed on a substrate according to an embodiment of the present invention;
figure 11 is a cross-sectional view of a fin structure taken along the width of the fin structure after forming a gate and a protective layer on a substrate in accordance with an embodiment of the present invention;
figure 12 is a cross-sectional view of the fin structure along the length after forming a gate and a protective layer on the substrate in an embodiment of the present invention;
figure 13 is a cross-sectional view of the fin structure along the length of the fin structure after forming a second layer of sidewall material over the substrate in accordance with an embodiment of the present invention;
fig. 14 is a cross-sectional view of the fin structure along the length direction after forming first and second gate spacers on the substrate according to an embodiment of the present invention;
fig. 15 is a schematic structural view of doping N-type impurities into the source region formation region and the drain region formation region in the embodiment of the present invention;
FIG. 16 is a schematic view of the structure of the first dielectric layer removed after the portions of the first dielectric layer over the source formation region, the drain formation region and the substrate are removed;
FIG. 17 is a schematic structural diagram illustrating a metal layer formed according to an embodiment of the present invention;
FIG. 18 is a schematic structural diagram of an embodiment of the present invention after a low temperature annealing process;
FIG. 19 is a schematic diagram illustrating a second dielectric layer formed according to an embodiment of the present invention;
FIG. 20 is a schematic structural diagram illustrating a first contact hole and a second contact hole formed in an embodiment of the present invention;
FIG. 21 is a schematic structural view after forming a first diffusion barrier layer and a second diffusion barrier layer in an embodiment of the present invention;
fig. 22 is a schematic structural diagram of the source and the drain in the embodiment of the invention.
Reference numerals: 11 is a substrate, 111 is a step structure, 12 is a first sidewall material layer, 121 is a first sidewall, 122 is a second sidewall, 13 is a fin structure, 131 is a source region forming region, 132 is a drain region forming region, 133 is a channel region, 14 is an oxide layer, 15 is a first dielectric layer, 16 is a gate material layer, 161 is a gate, 17 is a protective material layer, 171 is a protective layer, 18 is a second sidewall material layer, 181 is a first gate sidewall, 182 is a second gate sidewall, 19 is a metal layer, 20 is a source region, 21 is a drain region, 22 is a first metal contact layer, 23 is a second metal contact layer, 24 is a second dielectric layer, 25 is a first contact hole, 26 is a second contact hole, 27 is a first diffusion barrier layer, 28 is a second diffusion barrier layer, 29 is a source electrode, and 30 is a drain electrode.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Germanium materials have a high and symmetric carrier rate. Meanwhile, the forbidden bandwidth of germanium is smaller than that of silicon. Based on this, when a transistor is manufactured using a germanium-based substrate, the transistor can be made to have a larger drive current, a faster switching speed, and a lower drive voltage, which is advantageous for miniaturization of a semiconductor device. Moreover, the germanium material has natural low-temperature process advantages, so that the germanium-based transistor becomes the first choice for manufacturing an upper-layer device included in a three-dimensional heterogeneous integrated chip.
However, when an NMOS transistor is manufactured using a germanium-based substrate, there is a problem that the activation temperature of N-type impurities is high. For example: when the source and drain regions included in the germanium-based NMOS transistor are doped with phosphorus, a high temperature of about 600 ℃ is usually required to activate the impurity. However, the manufacturing temperature of the devices in the middle and upper layers included in the three-dimensional heterogeneous integrated chip needs to be less than or equal to 520 ℃. If the manufacturing temperature is higher than 520 ℃, the performance degradation of bottom layer devices included in the three-dimensional heterogeneous integrated chip is caused, and finally the yield of the three-dimensional heterogeneous integrated chip is reduced, so that the three-dimensional heterogeneous integrated chip cannot be ensured to have good working performance by adopting the conventional manufacturing method of the germanium-based NMOS transistor under the condition that upper layer devices included in the three-dimensional heterogeneous integrated chip are manufactured by using the germanium-based NMOS transistor.
In order to solve the above technical problems, embodiments of the present invention provide an NMOS transistor, a method for manufacturing the NMOS transistor, and a three-dimensional heterogeneous integrated chip. In the method for manufacturing an NMOS transistor according to the present invention, a fin structure made of germanium is formed on a substrate. And then doping N-type impurities in a source region forming region and a drain region forming region included in the fin-shaped structure. And a metal layer is formed to cover at least the source region formation region and the drain region formation region. Based on this, in the process of low-temperature annealing treatment, the metal layer respectively generates metal germanidation reaction with the source region forming region and the drain region forming region to induce the activation of the N-type impurities, so that the source region and the drain region can be obtained without higher activation temperature, and therefore when the manufacturing method of the NMOS transistor provided by the embodiment of the invention is adopted to manufacture an upper layer device included in the three-dimensional heterogeneous integrated chip, the performance degradation of a bottom layer device included in the three-dimensional heterogeneous integrated chip caused by the higher activation temperature can be prevented, and the working performance of the three-dimensional heterogeneous integrated chip is improved.
As shown in fig. 1, an embodiment of the invention provides a method for manufacturing an NMOS transistor. The manufacturing process will be described below based on the cross-sectional views of the operations shown in fig. 2 to 22. Specifically, the manufacturing method of the NMOS transistor includes:
as shown in fig. 2 to 7, a fin structure 13 is formed on a substrate 11. The fin structure 13 is made of germanium. The fin structure 13 includes a source region formation region 131, a drain region formation region 132, and a channel region 133 between the source region formation region 131 and the drain region formation region 132.
Specifically, the base may be a germanium substrate or a germanium-on-insulator substrate. Of course, the base may also be a semiconductor substrate having a layer of germanium material epitaxial thereon, and in addition to a germanium substrate and a germanium-on-insulator substrate. For example: the base may be a silicon substrate having a layer of germanium material epitaxial thereon. The thickness of the germanium material layer may be set according to actual requirements, and is not specifically limited herein. For example: the thickness of the layer of germanium material may be greater than the height of the fin structure. In addition, the specification and the number of the fin structures formed on the substrate can be set according to actual requirements. The length extending direction of the fin-shaped structure can be any direction parallel to the surface of the substrate.
In one example, a fin structure may be formed on a substrate using a self-aligned double patterning technique. The method specifically comprises the following steps:
as shown in fig. 2 and 3, the substrate 11 is subjected to a second patterning process to form an upper step structure 111 on the substrate 11.
Illustratively, a first lithographic pattern may be formed on the substrate using a lithographic process. The area of the substrate exposed outside the first photoetching pattern is an area where a step structure is not required to be formed subsequently. Then, under the mask action of the first photoetching pattern, a second patterning treatment is carried out on the substrate by adopting a dry etching process, so that a step structure is formed on the substrate. Specifically, the height of the step structure can be set according to actual requirements. The width of the step structure determines the distance between the adjacent fin structures, so the width of the step structure can be set according to the requirement on the distance between the adjacent fin structures in the practical application scene.
As shown in fig. 4 and 5, a first sidewall 121 and a second sidewall 122 are formed on the substrate 11. The first side wall 121 and the second side wall 122 are distributed on the substrate 11 along the width direction of the step structure 111, and extend along the length direction of the step structure 111. The step structure 111 is located between the first side wall 121 and the second side wall 122.
Illustratively, as shown in fig. 4, a first sidewall material layer 12 covering the substrate 11 and the step structure 111 may be formed by a plasma enhanced chemical vapor deposition process. As shown in fig. 5, the first sidewall material layer 12 may be etched by an anisotropic etching process to remove a portion of the first sidewall material layer 12 parallel to the surface of the substrate 11, so as to obtain a first sidewall 121 and a second sidewall 122. The first side wall 121 and the second side wall 122 may be made of materials such as silicon dioxide which are easy to remove. The widths of the first sidewall 121 and the second sidewall 122 determine the width of the fin structure 13, so the widths of the first sidewall 121 and the second sidewall 122 (i.e., the thickness of the first sidewall material layer 12) can be set according to the width of the fin structure 13.
The source and drain regions may then be defined by a photolithographic process. Specifically, after the first side wall and the second side wall are obtained, a region for subsequently forming a source region and a drain region may be defined on the fin structure through a photolithography process.
As shown in fig. 6, the substrate 11 and the step structure 111 are etched by using the first sidewall 121 and the second sidewall 122 as masks, so as to obtain the fin structure 13. Specifically, the substrate 11 and the step structure 111 may be etched by a dry etching process or the like under the mask effect of the first sidewall 121 and the second sidewall 122, so as to obtain the fin structure 13.
As shown in fig. 7, the first and second sidewalls 121 and 122 are removed.
For example, when the first side wall and the second side wall are made of silicon dioxide, the first side wall and the second side wall on the fin structure may be removed by buffered hydrofluoric acid etching solution, so as to facilitate subsequent operations.
In another example, in addition to forming the fin structure on the substrate using the self-aligned double patterning technique described above, the substrate may be etched using photolithography and etching processes to form the fin structure described above. Specifically, a spin-on process may be used to first form a photoresist layer on a substrate. The photoresist layer is then exposed and developed to form a second lithographic pattern. The area of the substrate exposed outside the second photolithographic pattern is the area where the fin structure is not required to be formed subsequently. And etching the substrate from top to bottom along the thickness direction of the substrate under the mask action of the second photoetching pattern to obtain the fin-shaped structure.
It should be noted that the fin structure can be formed on the substrate by using either a self-aligned double patterning technique or directly using a photolithography and etching process. When the self-aligned double pattern forming technology is adopted, the requirement on manufacturing equipment is low, and the manufacturing cost of the NMOS transistor is favorably reduced. Under the condition that the photoetching precision can meet the critical dimension of the fin-shaped structure, the manufacturing process of the NMOS transistor can be simplified by adopting a mode of etching the substrate to form the fin-shaped structure by photoetching and etching processes, and the manufacturing efficiency of the NMOS transistor is improved, so that the fin-shaped structure can be formed by selecting a proper mode according to actual conditions.
In one example, after forming the fin structure on the substrate, before performing subsequent operations, the method for manufacturing the NMOS transistor may further include: as shown in fig. 8, the fin structure 13 is oxidized to form an oxide layer 14 on the surface of the fin structure 13 and the substrate 11. The oxide layer 14 is removed as shown at 9.
It should be appreciated that whichever manner described above is used to form the fin structure on the substrate, the substrate needs to be etched. The etching process is adopted to etch the substrate, so that the surface of the formed fin-shaped structure is easily subjected to etching damage, after the fin-shaped structure is formed, the surface damage of the fin-shaped structure can be transferred to the formed oxide layer in an oxidation mode, and the etching damage on the surface of the fin-shaped structure is repaired in a mode of removing the oxide layer, so that the quality of the fin-shaped structure meets the requirement of a preset scheme, and the working performance of the NMOS transistor can be improved.
Specifically, the temperature can be 200-400 deg.CO2Or O3The fin structure is oxidized to form an oxide layer on the surface of the fin structure and the substrate. Of course, the fin structure may be oxidized under other suitable temperature conditions, which are not limited herein. In addition, since the fin-shaped structure is made of germanium and the oxide layer formed by oxidizing the fin-shaped structure is made of germanium dioxide, the oxide layer can be removed by hydrochloric acid (dilute hydrochloric acid) with a mass fraction of less than 20%. Of course, other suitable etching solutions may be used to remove the oxide layer, and are not limited herein.
In one example, a fin structure is formed on a substrate, and a gate-first process may be used to form a gate stack around a channel region included in the fin structure before subsequent operations are performed. The method specifically comprises the following steps:
as shown in fig. 10, a first dielectric layer 15 is formed overlying substrate 11 and fin structures 13.
Illustratively, the first dielectric layer may be formed by an atomic layer deposition process. The first dielectric layer is a film layer for forming a gate dielectric layer, so the first dielectric layer is made of an insulating material. The insulating material may be a high-k material (e.g., Al)2O3). The thickness of the first dielectric layer can be set according to actual requirements. For example: the first dielectric layer may have a thickness of
For example, in a case that the material of the first dielectric layer is a high-k material, after the first dielectric layer is formed, before performing subsequent operations, the method for manufacturing the NMOS transistor may further include: and passivating the interface of the first dielectric layer and the fin-shaped structure.
It should be understood that, in the case that the fin structure is made of germanium, when the first dielectric layer formed on the outer periphery of the fin structure is made of a high-k material, a severe interface state is generated between the high-k material and the germanium, and thus the electron mobility of the germanium is affected. And passivating the interface of the first dielectric layer and the fin-shaped structure after the first dielectric layer is formed, so that passivation can be formed between the first dielectric layer and the fin-shaped structureAnd (7) layering. The first dielectric layer and the fin-shaped structure can be isolated by the passivation layer, so that the interface state of the fin-shaped structure is improved, and the quality of an NMOS transistor is improved. Specifically, the interface between the first dielectric layer and the fin-shaped structure can be passivated by an ozone oxidation process, so that a lamination of germanium oxide and aluminum oxide can be formed. In particular, the thickness of the stack may be set according to actual requirements. For example: the germanium oxide may have a thickness of greater than 0 and less than or equal to
The thickness of the aluminum oxide is
As shown in fig. 10 to 12, a gate electrode 161 and a protective layer 171 are formed on a portion of the first dielectric layer 15 located at the outer periphery of the channel region 133. The protective layer 171 is on the gate electrode 161.
Illustratively, as shown in fig. 10, the gate material layer 16 covering the first dielectric layer 15 may be formed by an atomic layer deposition process or a sputtering process. The material and thickness of the gate material layer 16 can be set according to actual requirements. For example: the gate material layer 16 may be tantalum nitride or titanium nitride. At this time, the gate electrode 161 formed on the basis of the gate material layer 16 is a metal gate electrode. The thickness of the gate material layer 16 may be 50nm to 100 nm. A layer of protective material 17 may then be formed on the layer of gate material 16 using a plasma enhanced chemical vapor deposition process. The material and thickness of the protective material layer 17 can be set according to actual requirements. For example: the material of the protective material layer 17 may be silicon nitride. The thickness of the protective material layer 17 may be
As shown in fig. 11 and 12, the first dielectric layer 15 may be used as an etching stop layer, and the protective material layer 17 and the gate material layer 16 are sequentially etched through photolithography and etching processes, so as to leave the portions of the gate material layer 16 and the protective material layer 17 located at the periphery of the channel region 133, and obtain the gate 161 and the protective layer 171.
In another example, the gate stack structure may be formed by a gate-last process, in addition to the gate-first process. Specifically, in the case of the gate last process, a sacrificial gate may be formed in advance on the periphery of the channel region after the fin structure is formed on the substrate and before the subsequent operations are performed. The area where the sacrificial gate is located is an area where a gate stack structure is formed subsequently.
Illustratively, the gate material used to form the sacrificial gate may be first deposited on the substrate and fin structure by a physical vapor deposition or chemical vapor deposition process. And etching the gate material by dry etching and other processes, and only reserving the part of the gate material, which is positioned at the periphery of the channel region, to obtain the sacrificial gate.
In an example, as described above, in the case where the first dielectric layer, the gate electrode, and the protective layer are formed, after the gate electrode and the protective layer are formed on the portion of the first dielectric layer located at the periphery of the channel region, before performing the subsequent operation, the method for manufacturing the NMOS transistor may further include:
as shown in fig. 13 and 14, first gate sidewall spacers 181 and second gate sidewall spacers 182 are formed on the first dielectric layer 15. The first gate sidewall spacers 181 and the second gate sidewall spacers 182 are distributed on the first dielectric layer 15 along the width direction of the gate 161, and extend along the length direction of the gate 161. The gate 161 and the protective layer 171 are located between the first gate sidewall spacers 181 and the second gate sidewall spacers 182.
Illustratively, as shown in fig. 13, a plasma chemical vapor deposition process may be used to form the second sidewall material layer 18 overlying the first dielectric layer 15 and the protective layer 171. The material and thickness of the second sidewall material layer 18 can be set according to the actual application scenario. For example: the second sidewall material layer 18 may be made of silicon nitride. The thickness of the second layer of sidewall material 18 may be
As shown in fig. 14, the first dielectric layer 15 may be used as an etching stop layer, and the second sidewall material layer 18 is etched by dry etching or the like to remove the second sidewall material layerThe portions of the two sidewall material layers 18 parallel to the surface of the substrate 11, thereby obtaining first gate sidewall spacers 181 and second gate sidewall spacers 182.
It should be noted that, as described above, when a sacrificial gate is formed on the periphery of the channel region by using the gate-last process, the first gate sidewall and the second gate sidewall may also be formed by using the above method. At the moment, the second side wall material layer covers the first dielectric layer and the sacrificial gate. After the first grid side wall and the second grid side wall are formed, the sacrificial grid is located between the first grid side wall and the second grid side wall.
As shown in fig. 15, N-type impurities are doped into the source region formation region 131 and the drain region formation region 132.
Illustratively, as shown in fig. 15, N-type impurities may be doped into the source region formation region 131 and the drain region formation region 132 by ion implantation. Wherein, the N-type impurity can be phosphorus or arsenic, or the N-type impurity can also comprise phosphorus and antimony. Specifically, when the N-type impurity is doped by an ion implantation method, the implantation energy, the implantation dose, and the implantation direction of the ion implantation method of each impurity may be set according to actual requirements.
Illustratively, in the case where the N-type impurity includes phosphorus and antimony, the implantation energy of phosphorus in the ion implantation may be 30keV to 50 keV. The implant dose of phosphorus may be 6 x 1014cm-2～2×1015cm-2. The antimony implantation energy in the ion implantation method may be 40keV to 65 keV. The dose of antimony implant may be 6 x 1014cm-2～2×1015cm-2. It should be understood that, when the N-type impurity includes phosphorus and antimony, and phosphorus and antimony are doped into the source region formation region and the drain region formation region, on one hand, the impurity antimony can counteract tensile stress generated by the impurity phosphorus in the source region formation region and the drain region formation region, so that the solid concentration of the impurity phosphorus in the source region formation region and the drain region formation region can be increased, and the activation degree of the impurity phosphorus can be increased. On the other hand, antimony is easier to combine with a hole formed by adopting an ion injection mode compared with phosphorus, the diffusion of phosphorus is reduced, the activation of the phosphorus on the surfaces of a source region forming region and a drain region forming region is facilitated, and the working performance of the NMOS transistor can be improved.
Illustratively, as shown in fig. 15, the angle between the implantation direction of the ion implantation and the normal of the surface of the substrate 11 may be 30 ° to 45 °. At this time, the N-type impurity is injected into the source region forming region 131 and the drain region forming region 132 in an inclined injection manner, which is beneficial to forming an ultra-shallow and steep N +/P junction, and improves the working performance of the NMOS transistor.
As shown in fig. 16 and 17, a metal layer 19 is formed so as to cover at least the source region formation region 131 and the drain region formation region 132. Specifically, the material and thickness of the metal layer 19 may be set according to actual requirements. For example: the material of the metal layer 19 may be nickel. The thickness of the metal layer 19 may be 10nm to 30 nm.
In one example, as described above, in the case where the first dielectric layer, the gate electrode, and the protective layer are formed, the forming of the metal layer may include:
as shown in fig. 16, the portions of the first dielectric layer 15 on the substrate 11, the source region formation region 131, and the drain region formation region 132 are removed.
Illustratively, under the condition that the first dielectric layer is made of silicon nitride, the parts of the first dielectric layer, which are positioned on the substrate, the source region forming region and the drain region forming region, can be removed by buffered hydrofluoric acid etching solution, and only the part of the first dielectric layer, which is positioned on the periphery of the channel region, is reserved to obtain the gate dielectric layer.
As shown in fig. 17, a metal layer 19 is formed overlying the substrate 11, the fin structures 13, and the protective layer 171. Illustratively, the metal layer 19 may be formed by a physical vapor deposition process or the like.
In another example, as described above, in the case where a sacrificial gate is formed on the outer periphery of the channel region by using a gate-last process, after doping N-type impurities into the source region formation region and the drain region formation region, the metal layer may be formed directly by using a process such as physical vapor deposition. At this time, the metal layer covers the substrate, the fin structure and the sacrificial gate.
As shown in fig. 18, the substrate 11 formed with the fin structure 13 and the metal layer 19 is subjected to a low temperature annealing process to form a source region 20 and a drain region 21 in the source region formation region 131 and the drain region formation region 132, respectively, to form a first metal contact layer 22 on the source region 20, and to form a second metal contact layer 23 on the drain region 21.
For example, the processing conditions of the low-temperature annealing treatment may be: the annealing temperature is 360-400 ℃. The annealing time is 2 min-30 min. Of course, the specific values of the annealing temperature and the annealing time can be set according to actual requirements, and are not specifically limited herein. In addition, after the low-temperature annealing treatment is carried out, the unreacted metal layer can be removed through HCl so as to facilitate subsequent operation.
It is to be noted that, as described above, in the case where the N-type impurity includes phosphorus and antimony, the phosphorus and antimony form a segregated layer having a high concentration and a small thickness at the interface between the first metal contact layer and the source region and at the interface between the second metal contact layer and the drain region during the low-temperature annealing, and the on-resistance of the NMOS transistor can be reduced as compared with the case where the N-type impurity is phosphorus alone.
In an example, after performing a low temperature annealing process on the substrate on which the fin structure and the metal layer are formed, the method for manufacturing the NMOS transistor may further include:
as shown in fig. 19, in the case where the first dielectric layer 15, the gate electrode 161, and the protective layer 171 are formed as described above, the second dielectric layer 24 is formed to cover the first metal contact layer 22, the second metal contact layer 23, and the protective layer 171. And the second dielectric layer 24 is planarized.
Illustratively, the second dielectric layer may be formed by a physical vapor deposition or chemical vapor deposition process. The second dielectric layer may then be planarized by chemical mechanical polishing or the like to make the top of each region of the second dielectric layer flush. Based on the structure, the depths of the first contact hole and the second contact hole which are formed in the second medium layer with the flat top through the etching agent are the same, so that the etching uniformity can be improved, and the yield of the NMOS transistor is improved.
As described above, in the case where a sacrificial gate is formed on the periphery of the channel region by using the gate-last process, after the source region, the drain region, the first metal contact layer and the second metal contact layer are formed, the first dielectric material covering the first metal contact layer, the second metal contact layer and the sacrificial gate may be formed by a physical vapor deposition or a chemical vapor deposition, and the first dielectric material is etched back until the top of the sacrificial gate is exposed. And then removing the sacrificial gate, and sequentially forming a gate dielectric layer and a gate on the periphery of the channel region to obtain a gate stack structure. Finally, a second dielectric material covering the first dielectric material and the gate stack structure may be formed, and the second dielectric material is etched back, so that the remaining first dielectric material and the second dielectric material form a second dielectric layer.
As shown in fig. 20, the second dielectric layer 24 is subjected to a first patterning process to form a first contact hole 25 and a second contact hole 26 penetrating the second dielectric layer 24. Wherein the bottom of the first contact hole 25 is in contact with the first metal contact layer 22. The bottom of the second contact hole 26 is in contact with the second metal contact layer 23. Specifically, the first contact hole 25 and the second contact hole 26 may be formed in the second dielectric layer 24 by photolithography and etching processes.
In one example, as shown in fig. 21, a first diffusion barrier layer 27 is formed at the bottom of the first contact hole 25, and a second diffusion barrier layer 28 is formed at the bottom of the second contact hole 26. The thickness of the first diffusion barrier layer 27 is smaller than the depth of the first contact hole 25. The thickness of the second diffusion barrier layer 28 is smaller than the depth of the second contact hole 26. The first diffusion barrier layer 27 and the second diffusion barrier layer 28 may be film layers made of a single material, or may be stacked layers made of two or more materials. Specifically, the materials of the first diffusion barrier layer 27 and the second diffusion barrier layer 28 may be set according to practical application scenarios. For example: the first diffusion barrier layer 27 and the second diffusion barrier layer 28 are a stack of titanium and titanium nitride.
As shown in fig. 22, a source electrode 29 is formed in the first contact hole 25, and a drain electrode 30 is formed in the second contact hole 26. Specifically, the source electrode 29 and the drain electrode 30 may be formed by a physical vapor deposition process or the like. Source electrode 29 is electrically connected to source region 20 through first diffusion barrier 27 and first metal contact layer 22. The drain electrode 30 is electrically connected to the drain region 21 through the second diffusion barrier layer 28 and the second metal contact layer 23. The source electrode 29 and the drain electrode 30 may protrude from the first contact hole 25 and the second contact hole 26, respectively. The source electrode 29 and the drain electrode 30 are made of a conductive material. For example: aluminum.
It is noted that the source and drain electrodes are made of conductive materials having relatively reactive ions. During the manufacturing process or operation of the NMOS transistor, these active ions may diffuse into other regions in the NMOS transistor. And the existence of the first diffusion impervious layer and the second diffusion impervious layer can prevent the source electrode and the drain electrode from having ions and diffusing to other areas of the NMOS transistor from the bottoms of the source electrode and the drain electrode, so that the NMOS transistor is ensured to have good working performance.
As can be seen from the above, in the method for manufacturing an NMOS transistor according to the embodiment of the present invention, the fin structure made of germanium is formed on the substrate. And then doping N-type impurities in a source region forming region and a drain region forming region included in the fin-shaped structure. And a metal layer is formed to cover at least the source region formation region and the drain region formation region. Therefore, in the process of carrying out low-temperature annealing treatment on the substrate with the fin-shaped structure and the metal layer, the metal layer can carry out metal germanidation reaction with the source region forming region and the drain region forming region which are in contact with the metal layer, and a first metal contact layer and a second metal contact layer which are made of metal germanidation are formed. Meanwhile, in the process of the metal germanidation reaction, amorphous germanium in the source region forming region and the drain region forming region is crystallized along the crystalline phase of the metal germanidation, so that impurities can enter lattice point positions, and N-type impurity activation is realized. In other words, when the low-temperature annealing treatment is performed, the metal layer is subjected to a metal germanidation reaction with the source region formation region and the drain region formation region, respectively, so that N-type impurity activation can be induced. In addition, the N-type impurity is segregated to the interface of the metal germanide and the germanium due to the snow pear effect in the metal germanidation reaction process, so that a source region and a drain region can be obtained without higher activation temperature, and therefore when the manufacturing method of the NMOS transistor provided by the embodiment of the invention is adopted to manufacture an upper layer device included in the three-dimensional heterogeneous integrated chip, the performance degradation of a bottom layer device included in the three-dimensional heterogeneous integrated chip caused by the higher activation temperature can be prevented, and the working performance of the three-dimensional heterogeneous integrated chip is improved.
As can be seen from the above, in the method for manufacturing an NMOS transistor according to the embodiments of the present invention, by performing a low-temperature annealing process on the substrate on which the fin structure and the metal layer are formed, the first metal contact layer can be formed on the source region and the second metal contact layer can be formed on the drain region while the source region and the drain region are formed, respectively, without performing an annealing process for forming the source region and the drain region, and the first metal contact layer and the second metal contact layer, respectively, so that the manufacturing process of the NMOS transistor can be simplified, and the manufacturing of the NMOS transistor can be facilitated.
As shown in fig. 22, an embodiment of the present invention further provides an NMOS transistor, which is manufactured and formed by using the manufacturing method of the NMOS transistor provided in the foregoing embodiment.
Compared with the prior art, the NMOS transistor provided by the embodiment of the present invention has the same beneficial effects as the manufacturing method of the NMOS transistor provided by the above embodiment, and details are not described here.
The embodiment of the invention also provides a three-dimensional heterogeneous integrated chip which comprises the NMOS transistor provided by the embodiment.
Compared with the prior art, the three-dimensional heterogeneous integrated chip provided by the embodiment of the invention has the same beneficial effects as the NMOS transistor manufacturing method provided by the embodiment, and the details are not repeated herein.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (13)
1. A method for manufacturing an NMOS transistor, comprising:
forming a fin structure on a substrate; the fin-shaped structure is made of germanium and comprises a source region forming region, a drain region forming region and a channel region located between the source region forming region and the drain region forming region;
doping N-type impurities into the source region forming region and the drain region forming region;
forming a metal layer at least covering the source region formation region and the drain region formation region;
and carrying out low-temperature annealing treatment on the substrate on which the fin-shaped structure and the metal layer are formed so as to form a source region and a drain region in the source region forming region and the drain region forming region respectively, form a first metal contact layer on the source region and form a second metal contact layer on the drain region.
2. The method of claim 1, wherein the low temperature annealing process is performed under the following conditions: the annealing temperature is 360-400 ℃, and the annealing time is 2-30 min.
3. The method of manufacturing an NMOS transistor according to claim 1, wherein said doping the N-type impurity into the source region formation region and the drain region formation region comprises:
doping the N-type impurities into the source region forming region and the drain region forming region by adopting an ion implantation mode; wherein the N-type impurities comprise phosphorus and antimony.
4. The method of claim 3 wherein the ion implantation has an energy of 30keV to 50keV and a dose of 6 x 1014cm-2～2×1015cm-2(ii) a The implantation energy of antimony in the ion implantation mode is 40 keV-65 keV, and the implantation dosage of antimony is 6 x 1014cm-2～2×1015cm-2(ii) a And/or the presence of a gas in the gas,
the included angle between the implantation direction of the ion implantation mode and the normal of the surface of the substrate is 30-45 degrees.
5. The method of manufacturing an NMOS transistor according to claim 1, wherein after the fin structure is formed on the substrate and before the N-type impurity is doped into the source region formation region and the drain region formation region, the method of manufacturing an NMOS transistor further comprises:
forming a first dielectric layer overlying the substrate and the fin structure;
forming a grid electrode and a protective layer on the part of the first dielectric layer, which is positioned on the periphery of the channel region; the protective layer is positioned on the grid electrode;
the forming of the metal layer covering at least the source region formation region and the drain region formation region includes:
removing the parts of the first dielectric layer, which are positioned on the substrate, the source region forming region and the drain region forming region;
forming the metal layer overlying the substrate, the fin structure, and the protective layer.
6. The method of claim 5, wherein after the forming the fin structure on the substrate and before the forming the first dielectric layer covering the substrate and the fin structure, the method further comprises:
oxidizing the fin structure to form an oxide layer on the surface of the fin structure and the substrate;
and removing the oxide layer.
7. The method of manufacturing the NMOS transistor of claim 6, wherein the oxidizing the fin structure to form an oxide layer on the surface of the fin structure and the substrate comprises:
under the temperature condition of 200-400 ℃, O is adopted2Or O3Oxidizing the fin structure to form the oxide layer on the surface of the fin structure and the substrate; and/or the presence of a gas in the gas,
the removing the oxide layer comprises:
and removing the oxide layer by adopting hydrochloric acid with the mass fraction of less than 20%.
8. The method of claim 5, wherein the first dielectric layer is made of a high-k material; the gate is a metal gate;
after the forming of the first dielectric layer covering the substrate and the fin-shaped structure, and before the forming of the gate and the protective layer on the first dielectric layer at the outer periphery of the channel region, the method for manufacturing the NMOS transistor further includes:
and passivating the interface of the first dielectric layer and the fin-shaped structure.
9. The method of claim 5, wherein after the low temperature annealing process is performed on the substrate on which the fin structure and the metal layer are formed, the method further comprises:
forming a second dielectric layer covering the first metal contact layer, the second metal contact layer and the protective layer;
carrying out planarization treatment on the second dielectric layer;
performing first patterning treatment on the second dielectric layer to form a first contact hole and a second contact hole which penetrate through the second dielectric layer; wherein the bottom of the first contact hole is in contact with the first metal contact layer; the bottom of the second contact hole is in contact with the second metal contact layer;
and forming a source electrode in the first contact hole and forming a drain electrode in the second contact hole.
10. The method of manufacturing an NMOS transistor according to any one of claims 5 to 9, wherein after the gate electrode and the protective layer are formed on the portion of the first dielectric layer located on the outer periphery of the channel region, and before the N-type impurity is doped into the source region formation region and the drain region formation region, the method of manufacturing an NMOS transistor further comprises:
forming a first grid side wall and a second grid side wall on the first dielectric layer; the first grid side wall and the second grid side wall are distributed on the first dielectric layer along the width direction of the grid and extend along the length direction of the grid; the grid and the protective layer are located between the first grid side wall and the second grid side wall.
11. The method of claim 1, wherein the forming the fin structure on the substrate comprises:
performing second patterning treatment on the substrate to form a step structure on the substrate;
forming a first side wall and a second side wall on the substrate; the first side wall and the second side wall are distributed on the substrate along the width direction of the step structure and extend along the length direction of the step structure; the step structure is positioned between the first side wall and the second side wall;
defining the source region and the drain region through a photoetching process;
etching the substrate and the step structure by taking the first side wall and the second side wall as masks to obtain the fin-shaped structure;
and removing the first side wall and the second side wall.
12. An NMOS transistor, wherein the NMOS transistor is manufactured by the method of any one of claims 1 to 11.
13. A three-dimensional heterogeneous integrated chip comprising the NMOS transistor of claim 12.
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| CN102832126A (en) * | 2011-06-13 | 2012-12-19 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN103021854A (en) * | 2011-09-28 | 2013-04-03 | 中国科学院微电子研究所 | Method for manufacturing fin type field effect transistor and semiconductor structure formed by fin type field effect transistor |
| CN105742362A (en) * | 2016-02-05 | 2016-07-06 | 中国科学院微电子研究所 | Semiconductor device with multi-gate FinFETs and manufacturing method of semiconductor device and electronic equipment |
| CN109950316A (en) * | 2019-03-26 | 2019-06-28 | 湘潭大学 | A kind of hafnium oxide base ferroelectricity grid field effect transistor and preparation method thereof |
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