CN112864099B - Memory and forming method thereof - Google Patents
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- CN112864099B CN112864099B CN202110261692.5A CN202110261692A CN112864099B CN 112864099 B CN112864099 B CN 112864099B CN 202110261692 A CN202110261692 A CN 202110261692A CN 112864099 B CN112864099 B CN 112864099B
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 150000002500 ions Chemical class 0.000 claims description 97
- 239000000758 substrate Substances 0.000 claims description 76
- 238000002955 isolation Methods 0.000 claims description 67
- 230000002093 peripheral effect Effects 0.000 claims description 28
- 238000005468 ion implantation Methods 0.000 claims description 25
- 230000001413 cellular effect Effects 0.000 claims description 9
- 125000006850 spacer group Chemical group 0.000 claims description 7
- 239000002019 doping agent Substances 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 7
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
Abstract
The invention provides a memory and a forming method thereof. The active area in the active area array and the edge surrounding part positioned at the periphery of the active area array have different ion doping conditions, so that the edge surrounding part does not have the same conductive performance as the active area, the bit line can be prevented from being electrically conducted with the edge surrounding part when crossing the edge surrounding part, the problem that the bit line is short-circuited through the edge surrounding part to cause electric signals to be difficult to be conducted into the active area array is effectively solved, and the normal operation of the memory is ensured.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a memory and a method for forming the same.
Background
Memory (e.g., dynamic random access memory, DRAM) typically includes an array of memory cells for storing data, and peripheral circuitry located at the periphery of the array of memory cells. The memory cell array is formed by a plurality of memory cells arranged in an array, and the memory cells are generally connected to the peripheral circuit by using word lines and bit lines so as to control the operation of the corresponding memory cells through the word lines and the bit lines.
Specifically, the memory cell generally includes an active region, and the active region is further electrically connected to the bit line. When performing operations such as access, the operation of the corresponding memory cell is controlled by applying an electrical signal to the selected bit line and further utilizing the bit line to conduct the electrical signal to the active region to which it is connected. However, in the present memory, a problem often occurs that a portion of the memory cells are difficult to be selected and cannot perform the corresponding operation, thereby affecting the performance of the memory.
Disclosure of Invention
The present invention is directed to a memory, which solves the problem that some memory cells are difficult to be selected and cannot perform corresponding operations in the existing memory.
In order to solve the above technical problems, the present invention provides a memory, comprising:
a substrate having a cell region and a peripheral region;
an isolation structure at least arranged in a substrate of the cell region to isolate an active region array in the cell region and an edge surrounding part surrounding the periphery of the active region array, wherein the active region array comprises a plurality of active regions which are mutually separated by the isolation structure, the active regions contain preset ions, and the edge surrounding part does not contain the preset ions; the method comprises the steps of,
and a plurality of bit lines positioned on the substrate and extending along a first direction so as to intersect corresponding active regions in the active region array and further extend from the active region array into the peripheral region via the edge surrounding portion.
Optionally, the isolation structure includes a plurality of first isolation parts extending along a second direction to define a long boundary of the active region, and a plurality of second isolation parts formed between adjacent first isolation parts and connecting the adjacent first isolation parts to define a short boundary of the active region.
Optionally, the end portion of the first isolation portion extends and stops in the edge surrounding portion, so that a plurality of extended strip patterns are formed on the inner side, close to the active area array, of the edge surrounding portion, the strip patterns form inactive active areas, and the bit lines further intersect at least part of the inactive active areas.
Optionally, the predetermined ions are doped in an active region located in an ion active region in the active region array, a region range of the ion active region is located in a region range of the active region array, and at least an end portion of an edge active region located at an edge position in the active region array is located outside the ion implantation region and does not contain the predetermined ions.
Optionally, the entirety of at least part of the edge active regions in the active region array is located outside the ion active region without containing the predetermined ions.
Optionally, the predetermined ions in the active region include source/drain dopant ions to form a source/drain doped region, the source/drain doped region extending to the top surface of the substrate and electrically connected to the bit line.
Optionally, the substrate of the active region includes a base region and the source/drain doped region formed on a top surface of the base region, the substrate of the edge surrounding portion includes only the base region, the base region is of a first doping type, the source/drain doped region is of a second doping type, and an ion concentration of ions of the first doping type in the base region is lower than an ion concentration of ions of the second doping type in the source/drain doped region.
Optionally, the substrate of the active region includes the source/drain doped region, the well region and the base region sequentially arranged from the top surface of the substrate to the inside of the substrate; and only the base region is included in the edge enclosure.
Optionally, the memory further includes: and the contact plug is arranged on the end part of the bit line, which is positioned in the peripheral area, so as to be electrically connected with the bit line.
Still another object of the present invention is to provide a method for forming a memory, including:
providing a substrate, wherein the substrate is provided with a cellular region and a peripheral region;
forming an isolation structure in a substrate, wherein the isolation structure isolates an active region array in the cellular region and an edge surrounding part surrounding the periphery of the active region array, and the active region array comprises a plurality of active regions which are separated from each other by the isolation structure;
at least masking the edge surrounding portion, and performing an ion implantation process on the active region array to implant predetermined ions into the active region;
a plurality of bit lines are formed on the substrate, the bit lines extending along a first direction to intersect corresponding active regions in the active region array and further extending from the active region array into the peripheral region via the edge enclosures.
Optionally, the method for forming the isolation structure includes: forming an isolation trench in the substrate, the isolation trench including a plurality of first trenches extending along a second direction and a plurality of second trenches formed between and communicating adjacent first trenches; and filling an insulating material in the isolation trenches to form first isolation portions corresponding to the first trenches and second isolation portions corresponding to the second trenches.
Optionally, when the ion implantation process is performed, an edge of the active region array is further extended to cover, so that at least an end portion of an edge active region located at an edge position in the active region array is covered and not doped with the predetermined ions.
Optionally, performing the ion implantation process includes: performing a well region ion implantation process to form a well region in the substrate; and performing a source/drain ion implantation process to form a source/drain doped region in the well region, the source/drain doped region extending to the top surface of the substrate.
According to the memory and the forming method thereof, the ion implantation area in the cell area is redefined, so that the substrate of the edge surrounding part in the cell area does not contain preset ions, the conductivity of the edge surrounding part is different from that of the active area, the problem that the edge surrounding part is easy to electrically connect to the bit line is effectively solved, the problem that the bit line is easy to short-circuit through the edge surrounding part in the existing memory is effectively solved, and the electric signals in the bit line can be effectively conducted into the active area, so that the normal operation of the memory is ensured.
Drawings
FIG. 1 is a schematic diagram of a short circuit between an output bit line and an edge surrounding portion.
FIG. 2 is a schematic diagram of a memory according to an embodiment of the invention.
Fig. 3 is a schematic diagram mainly illustrating an isolation structure according to an embodiment of the invention.
FIG. 4 is a schematic diagram of a mask covering an edge enclosure to define an ion implantation region according to an embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of a substrate portion corresponding to an edge surrounding portion and an active region according to an embodiment of the invention.
Wherein, the reference numerals are as follows:
10/100-substrate;
10A/100A-cell region;
10B/100B-peripheral region;
101-a substrate region;
102-a well region;
103-source/drain doped regions;
11/110-active region;
111-an inner active region;
120-edge active region;
12/120-edge containment zone;
121/122/123/124-striped pattern;
120Y-first boundary;
120X-second boundary;
200-isolation structures;
210-a first separator;
220-a second separator;
30/31/32/300-bit lines;
400-contact plugs;
500-mask layer.
Detailed Description
As described in the background art, when the conventional memory performs operations such as access, the problem that a part of memory cells are difficult to be selected and cannot perform corresponding operations is easily generated, thereby affecting the normal operation of the memory.
For the technical problem that a part of the memory cells are difficult to be selected as described above, the reasons for the occurrence may include poor contact between the bit lines and the active regions, and various solutions for improving the contact performance between the bit lines and the active regions are currently available. Therefore, the inventors of the present application have further studied, without considering the contact performance between the bit line and the active region, to find that another important cause of the technical problems as described above is: the bit lines are liable to short with the peripheral edge of the active region array.
For ease of understanding, the problem of the bit line shorting based on the edge enclosures will be explained below with reference to fig. 1. Fig. 1 is a schematic structural diagram schematically illustrating that a short circuit occurs between a bit line and an edge surrounding portion, so that an electrical signal in the bit line is difficult to reach an active region.
Referring to fig. 1 with emphasis, in the prior art, in order to simplify the process, an ion implantation process is generally performed on the entire cell region 10A when the active region array in the cell region 10A is prepared, and at this time, the same ions (including source/drain doped ions) are doped in the active region array and the edge surrounding portion 12, so that the edge surrounding portion 12 and the active region 11 have the same conductivity. Based on this, the bit line 30 crossing the edge surrounding portion 12 is not only electrically connected to the active region 11, but also easily electrically connected to the edge surrounding portion 12, and at this time, a problem of short-circuiting of the bit line 30 via the edge surrounding portion 12 is caused. For example, referring to FIG. 1, bit lines 31 and 32 loop through the edge enclosures 12, making it difficult for electrical signals in the bit lines 31/32 to reach into the active area array.
Therefore, the invention provides a memory, which can prevent the bit line from being electrically connected with the edge surrounding part by making the edge surrounding part not contain preset doping ions so that the edge surrounding part does not have the same conductive performance as the active region. Therefore, the problem that electrical signals in the bit line are difficult to conduct to a corresponding active area due to short circuit of the bit line and the edge surrounding part can be effectively solved, and normal operation of the memory is guaranteed.
The memory and the method of forming the same according to the present invention are described in further detail below with reference to the accompanying drawings and detailed description. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. And relative terms such as "above," "below," "top," "bottom," "over" and "under" as illustrated in the accompanying drawings may be used to describe various elements' relationship to one another. These relative terms are intended to encompass different orientations of the element in addition to the orientation depicted in the figures. For example, if the device is inverted relative to the view in the drawings, an element described as "above" another element, for example, will now be below the element.
FIG. 2 is a schematic diagram of a memory according to an embodiment of the invention. As shown in fig. 2, the memory includes a substrate 100, an isolation structure 200 formed in the substrate 100, and a bit line 300 formed on the substrate 100.
Specifically, the substrate 100 has a cell region 100A and a peripheral region 100B. The isolation structure 200 is used to define a memory cell array in the cell area 100A, and a peripheral circuit (not shown) may be generally formed in the peripheral area 100B, where the memory cell array is connected to the peripheral circuit, for example, through a word line (not shown) and a bit line 300, so as to control the operation of each memory cell in the memory cell array through the peripheral circuit. In this embodiment, the cell region 100A may be a rectangular cell region, and the peripheral region 100B is located outside the rectangular cell region.
With continued reference to fig. 2, the isolation structure 200 is disposed in the substrate 100 of the cellular region 100A to isolate an active region array (including a plurality of active regions 110) and an edge enclosure 120 surrounding the periphery of the active region array in the cellular region 100A. That is, the edge surrounding portion 120 is located at the edge of the cellular region 100A, and the active region array (including the plurality of active regions 110) is surrounded by the edge surrounding portion 120. In this embodiment, the edge enclosing parts 120 are correspondingly located on four boundaries of the rectangular cellular region 100A, and are connected to each other on the four boundaries to surround the active region array.
Further, the active region array includes a plurality of active regions 110 arranged in an array, and adjacent active regions 110 are separated from each other by the isolation structure 200. Wherein each active region 110 in the active region array has a complete active region pattern around the isolation structure 200, and the active region patterns of each active region 110 are identical (for example, in this embodiment, each active region 110 is a stripe pattern and extends parallel to the same direction, and the length dimension and the width dimension of each active region 110 are also identical). In a specific embodiment, the active region 110 is used to form a memory cell, and specifically, an active/drain doped region may be formed in a substrate of the active region 110 to form a memory transistor.
The isolation structure 200 may be considered to separate the active area array from the edge enclosures 120 and also to separate adjacent active areas 110 in the active area array. The isolation structure 200 may directly or indirectly determine the shape of the edge surrounding portion 120 and the shape of the active region 110. The isolation structure 200 in this embodiment is described in detail below with reference to fig. 3. Fig. 3 is a schematic diagram mainly illustrating an isolation structure according to an embodiment of the invention.
Referring to fig. 3 with emphasis, the isolation structure 200 may include a plurality of first isolation portions 210 extending along the second direction (in this embodiment, the first isolation portions 210 extend along the Z direction) and a plurality of second isolation portions 220. Wherein a plurality of the first spacers 210 are parallel to each other to define a long boundary of the active region 110, and the second spacers 220 are formed between adjacent first spacers 210 and connect the adjacent first spacers 210 to define a short boundary of the active region 110. That is, the second isolation part 220 and the first isolation part 210 are connected to each other to surround the active region pattern of the active region 110.
The ends of the first isolation portions 210 extend and stop in the edge surrounding portion 120, but do not cross the edge surrounding portion 120, so that the edge surrounding portion 120 is still an integral structure connected to each other. At this time, a plurality of extended stripe patterns (such as stripe patterns 121/122/123/124 shown in fig. 3) may be formed on the inner side of the edge surrounding portion 120 near the active area array, where the stripe patterns correspondingly extend along the second direction, and the stripe patterns are aligned with the active areas 110 in the second direction. It is considered that the stripe pattern inside the edge surrounding portion 120 and the active region 110 closest to and arranged on the same line are separated from each other by the second isolation portion 220.
Further, the strip-shaped patterns inside the edge surrounding portion 120 may have the same or different extended length dimensions. For example, referring to fig. 3, in the present embodiment, the stripe patterns 121/122/123 corresponding to the first boundary 120Y of the rectangular cell region 100A may have different extension lengths, however, the stripe patterns 124 corresponding to the second boundary 120X of the rectangular cell region 100A may have the same extension length.
Note that, although the stripe pattern inside the edge surrounding portion 120 and the active region 110 have similar shapes, the stripe pattern does not have the function of the active region, so the stripe pattern 121/122/123/124 inside the edge surrounding portion 120 can be defined as an inactive active region so as to be distinguished from an active region having an electrical function.
Specifically, the active regions 110 in the active region array contain predetermined ions to form predetermined doped regions, and the predetermined doped regions can be electrically connected to the bit lines 300. However, the predetermined ions are not contained in the edge surrounding portion 120. For example, the predetermined ions in the active region 110 include N-type conductive ions, and the substrate of the edge surrounding portion 120 does not include the N-type conductive ions. That is, the edge surrounding portion 120 does not have the same conductive property as a predetermined doped region in the active region 110.
In an alternative solution, when an ion implantation process is performed on the active area array to form a predetermined doped region, the edge surrounding portion 120 may be covered by a mask, so as to avoid that the predetermined ions are doped in the edge surrounding portion 120.
Referring specifically to fig. 4, when an ion implantation process is performed on the active area array, the edge surrounding portion 120 is blocked by using a mask layer 500, and an opening area exposing the active area array is formed in the mask layer 500, where the opening area corresponds to an ion active area implanted with ions in the active area array. In this embodiment, the mask layer 500 extends a small amount to cover the edge of the active area array, so as to ensure that the edge surrounding portion 120 can be completely covered, that is, the area of the ion active area is within the area of the active area array. At this time, the edge active region at the edge position in the active region array is at least partially covered and is not fully doped with the predetermined ions, specifically, at least the end of the edge active region at the edge position is located outside the ion active region and does not contain the predetermined ions. For example, referring to fig. 4, the edge active region 112 of the active region array located at the edge position has an end portion near the edge surrounding portion 120 which is not doped with predetermined ions, and the inner active region 111 of the active region array located entirely in the ion active region is entirely implanted with predetermined ions.
Of course, in other embodiments, the entirety of at least a portion of the edge active regions 112 in the active region array may be located outside of the ion active region without containing the predetermined ions. For example, the plurality of active regions 110 in the active region array may be arranged in a plurality of rows along the first direction (X direction), and the plurality of rows of active regions may be arranged in sequence in the third direction (Y direction), in which case the active regions in the first row and the active regions in the last row of the plurality of rows of active regions may be located entirely outside the ion active region without the predetermined ion, and the edge active regions arranged at both side edges of each row of active regions may be located only at the end outside the ion active region without the predetermined ion.
It is believed that the edge active region 112 that is not fully doped at the edge location may not form a functional memory cell, at which point the edge active region 112 that does not form a functional memory cell may be considered an inactive active region, while the inner active region 111 that is fully within the ion active region is able to form a functional memory cell and thus may be positioned as an active region.
In a specific embodiment, the predetermined ions in the active region 110 include source/drain doped ions, and the predetermined doped region forms the source/drain doped region. Wherein the source/drain doped regions may be formed on the substrate surface of the active region 110 to be electrically connected to the bit line 300. Correspondingly, the edge surrounding portion 120 does not include the source/drain doping ions.
For example, referring to fig. 5, fig. 5 is a schematic cross-sectional view of a substrate portion corresponding to the edge surrounding portion 120 and the active region 110. As shown in fig. 5, the substrate of the active region 110 includes a base region 101 and source/drain doped regions 103 formed on the top surface of the base region, whereas the substrate of the edge enclosure 120 includes only the original base region 101. In a specific embodiment, when the original substrate region 101 is the first doping type, the predetermined ion (source/drain doping ion in this embodiment) is the second doping type ion, and the ion concentration of the first doping type ion in the substrate region 101 is far lower than the ion concentration of the second doping type ion in the source/drain doping region 103.
Further, the substrate of the active region 110 further includes a well region 102 formed in the base region 101, and the source/drain doped region 103 is formed in the well region 102 and diffused to the top surface of the substrate. Wherein the well region 102 may be further of a first doping type ion, and the ion concentration of the first doping type ion in the well region 102 is higher than the ion concentration of the first doping type ion in the substrate region 101, and the ion concentration of the second doping type ion in the source/drain doping region 103 is higher than the ion concentration in the well region 102. The first doping type is P-type, and the second doping type is N-type; alternatively, the first doping type is, for example, N-type, and the second doping type is, for example, P-type.
It is considered that, in this embodiment, the ion implantation process performed for the ion active region of the active region array in the cell region 100A is not applied to the edge surrounding portion 120, and the substrate of the active region 110 may include the source/drain doped region 103, the well region 102 and the base region 101 sequentially arranged from the top surface of the substrate to the inside of the substrate, and substantially the well region 102 and the source/drain doped region 103 are formed in the base region 101. While the substrate of the edge enclosure 120 may contain only the original base region 101.
With continued reference to fig. 2, a plurality of bit lines 300 are formed on the substrate 100, the bit lines 300 extending along a first direction (in this embodiment, the bit lines 300 extend along an X direction) to intersect the corresponding active regions 110 in the active region array and further extend from the active region array into the peripheral region 100B via the edge enclosures 120. Wherein, the bit line 300 extending into the peripheral region 100B may be further electrically connected to a peripheral circuit.
Specifically, the predetermined doped region (i.e., the source/drain doped region in the present embodiment) is formed in the substrate intersecting the bit line 300 in the active region 110, and the bit line 300 is electrically connected to the source/drain doped region.
As described above, in this embodiment, the predetermined doping ions are not included in the edge surrounding portion 120, so that the edge surrounding portion 120 does not have the same conductive performance as the active region 110, and thus, the electrical signal of the bit line 300 crossing the edge surrounding portion 120 cannot flow through the edge surrounding portion 120, which avoids the electrical signal in the bit line 300 being difficult to be conducted into the active region array due to the current loop formed by the bit line 300 and the edge surrounding portion 120, and ensures the normal operation of the memory.
Specifically, when the bit line 300 on the substrate 100 passes through the edge surrounding portion 120, it also intersects at least a portion of the stripe pattern (i.e., the inactive active region) extending from the inner side of the edge surrounding portion 120, where the stripe pattern does not have the same conductive property as the active region 110, and therefore, the bit line 300 is not electrically connected to the inactive active region formed by the stripe pattern.
Further, the bit line 300 includes a bit line contact portion embedded in the substrate of the active region 110 (specifically, a bit line contact window is formed in the substrate of the active region 110, the bit line contact portion fills the bit line contact window) so as to be electrically connected to the predetermined doped region, and a bit line conductive portion extending along the first direction and contacting a top surface of the corresponding bit line contact portion.
Alternatively, the bit line contact portion is also formed in the edge surrounding portion 120, and the bit line contact portion is also connected to the corresponding bit line conduction portion. Specifically, the bit line contact may be formed on a stripe pattern (i.e., an inactive active region) inside the edge surrounding portion 120, and the bit line conductive portion may intersect the inactive active region to contact and cover the corresponding bit line contact.
It should be noted that, since the inactive active region of the edge surrounding portion 120 does not contain predetermined ions (source/drain ions in the present embodiment), the substrate portion thereof includes only the base region 101 having an extremely low ion concentration, and the base region 101 has a relatively large resistance and does not electrically conduct with the bit line 300, and therefore, even if the inactive active region of the edge surrounding portion 120 is embedded with a bit line contact portion, and is physically connected to the bit line 300, the problem that the bit line 300 is shorted by the edge surrounding portion 120 can be avoided.
With continued reference to fig. 2, the memory further includes a contact plug 400, where the contact plug 400 is disposed on an end of the bit line 300 located in the peripheral region 100B, so as to electrically connect the bit line 300. In this embodiment, two sets of contact plugs 400 connected to adjacent bit lines 300 are disposed on opposite sides of the cell region 100A.
The method of forming the memory is described in detail below based on the memory described above. Specifically, the method for forming the memory may include the following steps.
In step S100, a substrate 100 is provided, wherein the substrate 100 has a cell region 100A and a peripheral region 100B. The base region of the substrate 100 may be, for example, a first doping type, and may be a P-type substrate.
In step S200, an isolation structure 200 is formed in the substrate 100. The isolation structure 200 may isolate an active area array and an edge surrounding portion 120 surrounding the periphery of the active area array in the cellular area 100A, and the active area array includes a plurality of active areas 110 separated from each other by the isolation structure 200.
Specifically, the method for forming the isolation structure 120 may be shown in fig. 3, for example, including: firstly, forming an isolation trench in the substrate, wherein the isolation trench specifically comprises a plurality of first trenches extending along a second direction and a plurality of second trenches located between adjacent first trenches, the second trenches are formed between the adjacent first trenches and communicated with the adjacent first trenches, and a plurality of active region patterns are surrounded by the first trenches and the second trenches; next, an insulating material is filled in the isolation trenches to form the isolation structures 200. The isolation structure 200 includes a first isolation portion 210 extending along the second direction and a second isolation portion 220 located between adjacent first isolation portions.
It is considered that the first spacers 210 achieve the mutual spacing of the adjacent rows of the active regions 110, and the second spacers 220 achieve the mutual spacing of the adjacent active regions 110 aligned in the same row. In addition, the isolation structure 200 further separates the active area array and the edge surrounding portion 120 from each other.
Further, the first isolation portion 210 further extends into the edge surrounding portion 120, and the second isolation portion 220 separates the edge surrounding portion 120 and the adjacent active region 110, and forms a plurality of extended stripe patterns (stripe patterns 121/122/123/124 shown in fig. 3) on the inner side of the edge surrounding portion 120 near the active region array.
In step S300, at least the edge surrounding portion 120 is covered by a mask, and an ion implantation process is performed on the active region array to implant predetermined ions into the active region 110.
Referring to fig. 4, when the ion implantation process is performed on the active area array, the mask layer 500 may be used to block the edge surrounding portion 120, and an opening area exposing the active area array is formed in the mask layer 500, where the opening area corresponds to an ion active area in the active area array that needs to be subjected to ion implantation.
In this embodiment, the mask layer 500 extends a small amount to cover the edges of the active area array, so as to ensure that the edge surrounding portion 120 can be completely covered. That is, the area range of the opening region of the mask layer 500 (i.e., the ion active region of the active region array) is smaller than the area range of the active region array. At this time, at least the end portion of the edge active region 112 located at the edge position in the active region array is covered and not doped with the predetermined ions, and the inner active region 111 located entirely within the ion active region is completely implanted with the predetermined ions.
In one version, as shown in fig. 4, all edge active regions 112 at the edge locations are capped at the ends and are not doped with the predetermined ions. However, in other embodiments, a part of the edge active regions 112 located at the edge positions may be covered at the ends, and the other part of the edge active regions 112 may be covered in their entirety without being doped with the predetermined ions (e.g., the active regions located in the first row and the active regions located in the last row may be covered in their entirety by the mask layer 500, and the active regions located at both side edges in each row may be covered at only the ends).
In a specific embodiment, referring to fig. 5, the process of performing an ion implantation process on the ion active region may include: performing a well region ion implantation process to form a well region 102 in the substrate region 101; and performing a source/drain ion implantation process to form a source/drain doped region 103 in the well region 102, the source/drain doped region 103 being expandable to a substrate surface of the active region 110 for electrical connection to the bit line 300. In this embodiment, the predetermined ions in the active region 110 may include the source/drain dopant ions.
It should be appreciated that during ion implantation of the ion active regions of the active region array, the edge enclosures 120 are always under the mask coverage of the mask layer 500 without ion implantation, and thus, the edge enclosures 120 may contain only the original substrate region 101.
In step S400, a plurality of bit lines 300 are formed on the substrate 100. The bit lines 300 extend along a first direction (X-direction) to intersect the respective active regions 110 in the active region array, and further extend from the active region array into the peripheral region 100B via the edge enclosures 120. Specifically, the bit line 300 is electrically connected to a predetermined ion doped region in the active region 110. In this embodiment, the bit line 300 is electrically connected to the source/drain doped region in the active region 110.
The method for forming the bit line 300 includes the following steps, for example. In a first step, the substrate is etched to form a plurality of bit line contacts (not shown), and the bit line contacts are formed in the substrate of the active region to expose predetermined doped regions (source/drain doped regions in this embodiment) in the active region. In an alternative solution, the bit line contact window is also formed in the edge surrounding portion 120, that is, an additional bit line contact window is further disposed at the periphery of the active area array. In this way, the bit line contact windows positioned at the edge positions in the active area array can be prevented from being exposed to the open areas, so that the pattern precision of the bit line contact windows positioned at the edge positions in the active area array is similar or identical to the pattern precision of the bit line contact windows positioned inside. Specifically, the bit line contact window in the edge surrounding portion 120 may be formed on the stripe pattern inside the edge surrounding portion 120, that is, the bit line contact window in the edge surrounding portion 120 may be formed in the inactive active region of the edge surrounding portion 120. In the second step, the bit lines 300 are formed, and the bit lines 300 correspondingly fill the bit line contact windows and extend along the first direction.
Although the bit line contact is also formed in the inactive active region of the edge surrounding portion 120, the bit line 300 is physically connected by being further filled with a bit line material. However, as described above, the substrate of the edge surrounding portion 120 includes only the base region 101, and the base region 101 has a sufficiently large resistance so as not to be electrically connected to the bit line 300, so that the problem of short-circuiting of the bit line 300 through the edge surrounding portion 120 can be avoided.
With continued reference to fig. 2, the bit line 300 further extends into the peripheral region 100B to connect to peripheral circuitry to control the on or off of the memory transistor formed by the active region 110.
In a further aspect, the method for forming a memory further includes: a contact plug 400 is formed on the end of the bit line 300 at the peripheral region 100B. In this embodiment, two sets of contact plugs 400 connected to adjacent bit lines 300 are disposed on opposite sides of the cell region 100A. In this way, it is advantageous to increase the size of each contact plug 400 and also to increase the photolithography process window of the contact plug 400.
In summary, in the memory and the forming method thereof provided by the invention, by redefining the ion active area in the cell area, which needs to be subjected to ion implantation, the edge surrounding part in the cell area does not contain predetermined ions, and correspondingly, the active area in the active area array and the edge surrounding part positioned at the periphery of the active area array have different ion doping conditions, so that the conductivity of the edge surrounding part is different from that of the active area, the problem that the electrical signals in the bit line are difficult to be conducted to the corresponding active area due to short circuit between the bit line and the edge surrounding part is avoided, and the normal operation of the memory is ensured.
It should be noted that, in the present description, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. While the invention has been described in terms of preferred embodiments, the above embodiments are not intended to limit the invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
It should also be noted that references in the specification to "one embodiment," "an embodiment," "a particular embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
And it should be understood that the terms "first," "second," "third," and the like in this specification are used merely as a distinction between various components, elements, steps, etc. in the specification, and are not intended to denote a logical or sequential relationship between various components, elements, steps, etc., unless specifically indicated or indicated.
It should also be understood that the terminology described herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses, and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense.
And, the word "or" should be understood as having the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates the contrary. Furthermore, implementation of the methods and/or apparatus in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.
Claims (11)
1. A memory, comprising:
a substrate having a cell region and a peripheral region;
an isolation structure at least arranged in a substrate of the cell area so as to isolate an active area array and an edge surrounding part surrounding the periphery of the active area array in the cell area, wherein the active area array comprises a plurality of active areas which are mutually isolated by the isolation structure, a predetermined ion is doped in an active area which is positioned in an ion active area in the active area array, the area range of the ion active area is positioned in the area range of the active area array, at least the end part of an edge active area which is positioned at an edge position in the active area array is positioned outside the ion active area and does not contain the predetermined ion, and the substrate of the edge surrounding part does not contain the predetermined ion; the method comprises the steps of,
and a plurality of bit lines positioned on the substrate and extending along a first direction so as to intersect corresponding active regions in the active region array and further extend from the active region array into the peripheral region via the edge surrounding portion.
2. The memory of claim 1, wherein the isolation structure includes a plurality of first isolation portions extending along a second direction to define long boundaries of the active region and a plurality of second isolation portions formed between adjacent first isolation portions and connecting adjacent first isolation portions to define short boundaries of the active region.
3. The memory of claim 2, wherein an end extension of the first spacer stops in the edge enclosure such that the edge enclosure forms a plurality of extended stripe patterns proximate an inner side of the active area array, the stripe patterns constituting inactive active areas, the bit lines further intersecting at least a portion of the inactive active areas.
4. The memory of claim 1 wherein the entirety of at least a portion of the edge active regions of the array of active regions are outside the ion active region and do not contain the predetermined ions.
5. The memory of claim 1 wherein the predetermined ions in the active region comprise source/drain dopant ions to form a source/drain doped region, the source/drain doped region extending to a top surface of the substrate and being electrically connected to the bit line.
6. The memory of claim 5 wherein the substrate of the active region comprises a base region and the source/drain doping region is formed on a top surface of the base region, the substrate of the edge enclosure comprises only the base region, the base region is of a first doping type, the source/drain doping region is of a second doping type, and an ion concentration of ions of the first doping type in the base region is lower than an ion concentration of ions of the second doping type in the source/drain doping region.
7. The memory of claim 5 wherein the substrate of the active region comprises the source/drain doped region, well region and base region arranged in that order from a top surface of the substrate to an interior of the substrate; and only the base region is included in the edge enclosure.
8. The memory of claim 1, further comprising:
and the contact plug is arranged on the end part of the bit line, which is positioned in the peripheral area, so as to be electrically connected with the bit line.
9. A method of forming a memory, comprising:
providing a substrate, wherein the substrate is provided with a cellular region and a peripheral region;
forming an isolation structure in a substrate, wherein the isolation structure isolates an active region array in the cellular region and an edge surrounding part surrounding the periphery of the active region array, and the active region array comprises a plurality of active regions which are separated from each other by the isolation structure;
at least masking the edge surrounding part and the edge of the active area array, and performing an ion implantation process on the active area array to implant predetermined ions into the active area, wherein at least the end part of the edge active area located at the edge position in the active area array is masked and not doped with the predetermined ions;
a plurality of bit lines are formed on the substrate, the bit lines extending along a first direction to intersect corresponding active regions in the active region array and further extending from the active region array into the peripheral region via the edge enclosures.
10. The method of forming a memory of claim 9, wherein the method of forming an isolation structure comprises:
forming an isolation trench in the substrate, the isolation trench including a plurality of first trenches extending along a second direction and a plurality of second trenches formed between and communicating adjacent first trenches; the method comprises the steps of,
an insulating material is filled in the isolation trenches to form first isolation portions corresponding to the first trenches and second isolation portions corresponding to the second trenches.
11. The method of forming a memory of claim 9, wherein performing the ion implantation process comprises: performing a well region ion implantation process to form a well region in the substrate; and performing a source/drain ion implantation process to form a source/drain doped region in the well region, the source/drain doped region extending to the top surface of the substrate.
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| CN109991806A (en) * | 2017-12-29 | 2019-07-09 | 长鑫存储技术有限公司 | The manufacturing method of mask plate, memory and memory |
| CN111354728A (en) * | 2018-12-24 | 2020-06-30 | 三星电子株式会社 | Semiconductor device with a plurality of transistors |
| CN212182325U (en) * | 2020-06-19 | 2020-12-18 | 福建省晋华集成电路有限公司 | Semiconductor memory device with a plurality of memory cells |
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| KR102104058B1 (en) * | 2013-09-27 | 2020-04-23 | 삼성전자 주식회사 | Semiconductor device and method of manufacturing the same |
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| CN111354728A (en) * | 2018-12-24 | 2020-06-30 | 三星电子株式会社 | Semiconductor device with a plurality of transistors |
| CN212182325U (en) * | 2020-06-19 | 2020-12-18 | 福建省晋华集成电路有限公司 | Semiconductor memory device with a plurality of memory cells |
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