CN112864027A - Fan-out type board level packaging method and structure thereof - Google Patents
Fan-out type board level packaging method and structure thereof Download PDFInfo
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- CN112864027A CN112864027A CN202110035869.XA CN202110035869A CN112864027A CN 112864027 A CN112864027 A CN 112864027A CN 202110035869 A CN202110035869 A CN 202110035869A CN 112864027 A CN112864027 A CN 112864027A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 70
- 238000000034 method Methods 0.000 title claims abstract description 62
- 239000010408 film Substances 0.000 claims description 167
- 239000000758 substrate Substances 0.000 claims description 32
- 239000000853 adhesive Substances 0.000 claims description 20
- 230000001070 adhesive effect Effects 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 19
- 239000003292 glue Substances 0.000 claims description 11
- 239000010409 thin film Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000004642 Polyimide Substances 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 238000012858 packaging process Methods 0.000 abstract description 13
- 238000010586 diagram Methods 0.000 description 8
- 238000005520 cutting process Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000004033 plastic Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 239000002390 adhesive tape Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a fan-out board-level packaging method, which comprises the following steps: providing a film having a plurality of windows arranged in an array; attaching the film to a first carrier plate; attaching a chip to the corresponding window; covering the film and the chip with a dry film and filling a gap between the film and the chip; curing the dry film; and removing the first carrier plate to obtain a film-chip-dry film structure. A fan-out type board level package structure is also disclosed. The invention can solve the problems of easy warpage, easy fracture, complex process and the like of the whole board in the existing fan-out board level packaging process, effectively reduces the packaging cost and has high reliability.
Description
Technical Field
The invention belongs to the technical field of fan-out type board level packaging, and particularly relates to a fan-out type board level packaging method and a fan-out type board level packaging structure.
Background
With the development of microelectronic packaging technology, the chip size is smaller and smaller, the number of transistors is higher and higher, and the traditional BGA packaging is difficult to satisfy the trend of miniaturization, and fan-out packaging technology is derived. Fan-out packages are further classified into fan-out wafer packages (FOWLP) and fan-out board level packages (FOPLP); the fan-out type wafer packaging is characterized in that a wafer is integrally packaged and then cut into single chips, and the fan-out type wafer packaging is small and thin; the fan-out board level packaging adopts a large-area carrier plate, a large number of selected chips are placed on the carrier plate to be packaged integrally, and then the chips are cut into single chips, so that the fan-out board level packaging has the characteristic of low cost.
In the prior art, a large-scale board-level packaging process adopts hard materials such as epoxy resin and the like to construct a packaging body structure on a hard substrate, but due to the influence of Coefficient of Thermal Expansion (CTE) matching, the warping problem of a whole board cannot be well controlled by the process method, and after the whole board is released, the whole board is easy to break, so that part of the packaging body is easy to lose effectiveness or damage. Meanwhile, the process scheme also needs multiple processes of coating, curing, leveling and the like on the epoxy, and has complex process and higher requirements on process level and equipment capacity.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a fan-out board level packaging method and a fan-out board level packaging structure which can solve the problems that the whole board is easy to warp, break and have complex process in the existing fan-out board level packaging process.
In a first aspect, a fan-out board level packaging method includes:
providing a film having a plurality of windows arranged in an array;
providing a first carrier plate, and attaching the film to the first carrier plate through a first bonding adhesive;
providing a plurality of chips, respectively attaching each chip to the corresponding window, and attaching the front surface of each chip to the first bonding glue;
providing a dry film, covering the film and the chip with the dry film, and filling a gap between the film and the chip;
curing the dry film;
and removing the first carrier plate to obtain a film-chip-dry film structure.
In an embodiment, after removing the first carrier to obtain the film-chip-dry film structure, the method further includes:
providing a second carrier plate, and attaching one side of the dry film of the film-chip-dry film structure to the second carrier plate through a second bonding adhesive;
and manufacturing a wiring medium layer and a rewiring layer on the surfaces of the film and the chip.
The second aspect, a fan-out type board level packaging structure, is located including packaging substrate and front the chip of packaging substrate upper surface, packaging substrate includes the dry film of lower floor and the film of upper strata, seted up on the film and held the window of chip, the window size is greater than the chip, the window edge with part between the chip edge by the dry film is filled.
In one embodiment, the chip package further comprises a wiring medium layer and a rewiring layer which are arranged on one side of the upper surface of the package substrate, and the rewiring layer is electrically connected with the chip.
In one embodiment, the distance between the window edge of the thin film and the corresponding chip edge is greater than twice the dry film thickness.
In one embodiment, the CTE and elastic modulus of the dry film are matched to the film.
In one embodiment, the film is an FPC film substrate, and the dry film is made of a polyimide dry film material; or
The film adopts the PET substrate, the dry film adopts RCC dry film curing piece.
In one embodiment, the thickness of the thin film is greater than the thickness of the chip.
In one embodiment, the thickness of the dry film is not less than the thickness of the thin film.
In one embodiment, the thickness of the chip is below 50 μm.
Compared with the prior art, the invention has the following beneficial effects:
1. the packaging body is formed by adopting a dry film packaging process, and the traditional liquid, solid encapsulation and plastic packaging processes are replaced, so that the stress influence is reduced, the warping is effectively prevented, the process steps are reduced, the process complexity is reduced, and the packaging cost is effectively reduced;
2. the filling is finished by a dry film back-pasting mode, so that a dry film with photosensitive property is not needed, the material selection is more flexible, a surface with high flatness can be constructed on the front surface of the chip, and the subsequent processes such as photoetching are facilitated;
3. the overall packaging thickness is effectively reduced through dry film packaging, the problem that the packaging body is too large in thickness and is not easy to peel off from the carrier plate is solved, and high-density integration is facilitated;
4. by adopting the ultra-thin packaging and temporary bonding modes, the influence of warping in the large-area board-level packaging process on reliability is reduced as much as possible.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow diagram of a fan-out type board level packaging method of the present invention;
FIG. 2 and FIG. 3 are schematic diagrams of a first step of a fan-out board level packaging method of the present invention;
FIG. 4 is a schematic diagram of step two of a fan-out type board level packaging method of the present invention;
FIG. 5 is a schematic diagram of step three of a fan-out type board level packaging method of the present invention;
FIG. 6 is a schematic diagram of step four of a fan-out type board level packaging method of the present invention;
FIG. 7 is a schematic diagram of step six of a fan-out board level packaging method of the present invention;
FIGS. 8 and 9 are diagrams of a seventh step of a fan-out board level packaging method of the present invention;
fig. 10 is a schematic structural diagram of a fan-out type board-level package structure according to the present invention.
Wherein, 1, a film; 11. a window; 12. a gap; 2. a first carrier plate; 3. a first bonding glue; 4. a chip; 5. drying the film; 6. a wiring dielectric layer; 7. a rewiring layer; 8. and packaging the substrate.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In a first aspect, as shown in fig. 1, a fan-out board level packaging method may include the steps of:
the method comprises the following steps: a membrane 1 having a plurality of windows 11 distributed in an array is provided.
As shown in fig. 2, a film 1 is provided, and the film 1 is used as a structure of a fan-out board level package, and a PI substrate or a PET substrate can be used. The thickness of the film 1 can be selected according to the thickness of the chip and the actual requirements.
As shown in fig. 3, the film 1 may be windowed by a cutting method to obtain the array windows 11, the cutting method may be laser cutting or blade cutting, and each of the windows 11 is corresponding to a chip attached subsequently.
The size of the window 11 is related to the size of the chip, and the size of the window 11 is larger than that of the chip in consideration of the subsequent attachment of the chip.
Step two: providing a first carrier plate 2, and attaching the film 1 to the first carrier plate 2 through a first bonding adhesive 3.
As shown in fig. 4, a first carrier 2 is provided, and the windowed film 1 can be attached to the first carrier 2 by a first bonding adhesive 3. Specifically, a first bonding adhesive 3 may be disposed on the first carrier 2, and then the film 1 is attached to the first bonding adhesive 3. The bottom surface of the first bonding glue 3 is attached to the first carrier plate 2, and the top surface of the first bonding glue is attached to the film 1; the window 11 on the film 1 exposes a part of the top surface of the first bonding glue 3 for subsequent attachment to a chip.
Wherein the first carrier plate 2 may be a glass plate. In order to reduce the generation of air bubbles, the film 1 is preferably attached by vacuum film attaching, and the attaching can be performed in a vacuum film attaching device. The material of the first bonding glue 3 can be selected from a pyrolytic adhesive tape, an ultraviolet release adhesive tape and the like. The first carrier plate 2 should have good thermal stability and load-bearing capacity. The window 11 may be used for positioning when attaching the chip.
Step three: providing a plurality of chips 4, and attaching each chip 4 to the middle position of the corresponding window 11 on the first carrier plate 2.
As shown in fig. 5, the front surfaces of the chips 4 are attached to the top surface of the first bonding adhesive 3 exposed by the windows 11 toward the first carrier 2, one chip 4 corresponds to one window 11, and the attaching position of the chip 4 is located at the center of the window 11.
Considering that the chip 4 is too thick to facilitate the subsequent dry film attachment, which may result in the subsequent dry film attachment not being completely wrapped or having air bubbles, the chip may be a relatively thin bare chip; considering that the silicon-based material will exhibit flexible and bendable properties after the wafer thickness is less than 50 μm, in order to further improve the problem of chip cracking due to warpage in board level packaging, it is preferable to use a chip with a thickness of 50 μm or less.
Step four: and providing a dry film 5, and attaching the dry film 5 to one side of the film 1 of the first carrier plate 2 in a vacuum manner to coat the film 1 and the chip 4.
As shown in fig. 6, a dry film 5 is applied to cover the surfaces of the film 1 and the chip 4, and the gap 12 between the film 1 and the chip 4 is sufficiently filled.
Wherein the dry film 5 is used as a packaging material for fan-out type board level packaging. The dry film 5 can adopt a permanent dry film, and the attaching of the dry film 5 is preferably carried out by adopting a vacuum film attaching process. The applicant has found in practice that a certain distance should be left between the edge of the window 11 and the edge of the chip 4 before the dry film 5 is attached, and if the distance is too narrow, the distance may cause the dry film 5 not to completely cover the film 1 and the chip 4 and not to be sufficiently attached to the first bonding adhesive 3. Generally, the distance should be more than twice the thickness of the dry film 5, so that the dry film 5 can completely fill the gap, achieving void-free filling, and preventing bubbles.
As an optimization, the thickness of the film 1 may be made larger than the thickness of the chip 4; this ensures that the dry film 5 can better cover the back side of the chip 4. In order to make the subsequent planarization process of the dry film 5 easier to perform, the thickness of the dry film 5 can be not less than the thickness of the film 1; this means that the lowest part of the dry film 5 filled in the gap between the film 1 and the chip 4 is not lower than the thickness of the film 1, and subsequent planarization only needs to be leveled to ensure that no bubbles are introduced, so that subsequent testing links are not affected.
Step five: the dry film 5 is cured and planarized.
After the dry film 5 is attached, curing the dry film 5 by heating; the surface of the dry film 5 can be flattened by adopting a flattening process of a vacuum film pasting device.
Wherein the curing temperature of the dry film 5 should not exceed the limit temperature of the film material and the first bonding paste material, and the CTE and elastic modulus of the dry film 5 after curing are also preferably matched (i.e., substantially the same) as those of the film 1; in addition, a good bonding force is required between the dry film 5 and the film 1. The film 1 and the dry film 5 can be respectively made of FPC film substrate and polyimide dry film material, and can also be respectively made of PET substrate and RCC dry film curing sheet by comprehensively considering the above factors.
Step six: and removing the first carrier plate 2.
As shown in fig. 7, the thin film-chip-dry film structure is peeled off from the first carrier 2 by a bonding-breaking process, and particularly, the first carrier 2 can be peeled off by UV irradiation or laser peeling.
It should be noted that, if the film 1 is not provided, and the dry film 5 is directly attached to the first bonding adhesive 3 on the first carrier plate 2, the bonding area between the dry film 5 and the first bonding adhesive 3 is large, so that the peeling is difficult and the operation is inconvenient; in the application, the film 1 with the window 11 is used as a structural body, and the dry film 5 and the first bonding adhesive 3 are only attached to the gap part between the window 11 and the chip 4, so that the attaching surface of the dry film 5 and the first bonding adhesive 3 is small, and the peeling is more convenient.
Step seven: and continuing to complete subsequent process flows, such as forming the wiring dielectric layer 6 and forming the rewiring layer 7.
As shown in fig. 8, after the film-chip-dry film structure is entirely peeled off from the first carrier 2, the film-chip-dry film structure can be turned over to make the front surface of the chip 4 face upward, and at this time, due to the sufficient filling of the dry film 5, the front surface of the chip 4 is a flat surface, and the subsequent process flow can be performed on this basis.
As shown in fig. 9, one side of the dry film 5 of the film-chip-dry film structure may be attached to a second carrier (not shown), and a suitable second bonding adhesive (not shown) is selected according to a subsequent required process; and then, subsequent processes such as dielectric layer coating (forming a wiring dielectric layer 6) and photoetching rewiring (forming a rewiring layer 7) can be carried out on the surfaces of the film 1 and the chip 4. And the second carrier plate can be peeled off by a bonding and detaching process after the manufacture is finished.
The packaging material adopted in the fan-out type board level packaging method provided by the invention has certain flexibility or higher elastic modulus except for the chip. On one hand, the packaging body is formed by adopting a dry film packaging process, and the traditional liquid, solid encapsulation and plastic packaging processes are replaced, so that the stress influence is reduced, the process steps are reduced, the process complexity is reduced, and the packaging cost is effectively reduced. Particularly, the packaging substrate is made of flexible materials such as dry films and thin films to replace hard materials such as epoxy resin in the traditional board level packaging process, the problem that the whole board cannot be well controlled in the prior art is solved, the whole board can be prevented from being broken after being released, and the failure or damage of part of packaging bodies is avoided. On the other hand, the filling is completed by a dry film back pasting mode, a dry film with photosensitive property is not needed, the material selection is more flexible, the surface with high flatness can be constructed on the front surface of the chip, and the subsequent processes of photoetching and the like are facilitated. On the other hand, the whole packaging thickness is effectively reduced through dry film packaging, the problem that the packaging body is too large in thickness and not easy to peel off from the support plate is solved, and high-density integration is facilitated. In another aspect, the influence of warpage on reliability in a large-area board level packaging process is reduced as much as possible by adopting an ultrathin packaging and temporary bonding mode. The temporary bonding can comprise two times, wherein the first time is to manufacture a film-chip-dry film structure on the first carrier plate, and the second time is to bond the film-chip-dry film structure on the second carrier plate after overturning to continuously manufacture a wiring dielectric layer and a rewiring layer. In addition, by adopting the vacuum attaching process, controlling the distance between the window and the chip, reducing the thickness of the chip and the like, the problem that bubbles, particles and the like are easily introduced in the epoxy plastic packaging process in the prior art is solved, and the adverse effect on the subsequent process and the reliability test is reduced.
In general, the invention can solve the problems of serious warpage, complicated epoxy encapsulation process and the like in the board-level packaging process, the finally formed package body has the advantages of lightness, thinness and high reliability, and the whole set of process does not relate to non-standard processes or equipment, and can adopt the existing mature process system.
Specific examples are now listed for further illustration:
s1: a PI substrate having a thickness of 30 μm and a size of 200 mm. times.250 mm was used as a board level package structure (i.e., a film). The PI substrate is windowed by laser cutting or blade cutting. The window size is selected according to the dry film thickness used and the chip size, where 2mm x 2.2mm is selected; and opening the array windows according to actual production needs.
S2: the PI base material is connected with a glass plate (namely a first carrier plate) with the same size into a whole through a temporary first bonding adhesive. The first bonding adhesive can be UV ultraviolet film or laser bonding adhesive, such as UV double-sided tape or laser tape, and can also be used for bonding glass-PI substrate by using a bonding machine, and a glass plate with proper wavelength transmittance is selected according to the debonding wavelength of the first bonding adhesive.
S3: and (3) finishing the processes of picking up, inverting and attaching the chip by using a chip mounter, and attaching the chip to the center of the window with the front surface facing downwards, namely attaching the chip to the first bonding adhesive. The chip size selected here was 1.8mm × 1.6mm, and the thickness was 25 μm.
S4: and (3) sticking a film on the front surface of the PI base material by using a permanent dry film and a vacuum film sticking process, and filling a gap between the window and the chip. The thickness of the dry film selected here should be larger than the thickness of the chip, and the curing temperature should not exceed the limit temperature of the first bonding glue used. The thickness of the dry film used in this example was 30 μm, and the curing temperature was 150 ℃. The dry film needs to fully wrap the chip and the gap.
S5: the dry film is cured and planarized. And flattening the surface of the dry film by adopting a leveling process of vacuum film pasting equipment.
S6: the glass plate is uncovered through a UV irradiation or laser stripping mode, UV irradiation equipment can be used for carrying out UV irradiation glue dissolution, equipment with a laser bonding removal function can also be used for carrying out a bonding removal process on the laser bonding glue, and a proper process scheme is selected according to the selected first bonding glue.
S7: and after the film-chip-dry film structure is integrally stripped, the film-chip-dry film structure is turned over, so that the surface of the chip faces upwards, and the front surface of the chip is a flat surface, so that the subsequent RDL dielectric layer or photoetching process can be realized.
In a second aspect, a fan-out type board level package structure is shown in fig. 10, and includes a package substrate 8 and a chip 4 whose front surface is located on the upper surface of the package substrate 8, where the package substrate 8 includes a lower dry film 5 and an upper film 1, a window 11 is formed on the film 1 and used for accommodating the chip 4, the size of the window 11 is larger than that of the chip 4, and the portion between the edge of the window 11 and the edge of the chip 4 is filled with the dry film 5.
Wherein the dry film 5 is a cured dry film. The film 1 may be a PI substrate as a structure for positioning the chip 4. The window 11 being larger in size than the chip 4 means that both the length and width of the window are larger than the chip. In the scheme, the packaging substrate is made of flexible materials such as dry films and thin films to replace hard materials such as epoxy resin in the traditional board-level packaging process; compared with the traditional hard material, the elastic modulus and CTE of the flexible material are closer to those of the subsequent RDL dielectric layer material, the problem that the whole board cannot be well controlled in the prior art can be solved, the whole board can be prevented from being broken after being released, and the failure or damage of part of the packaging body can be avoided.
As an optimization, the CTE and the elastic modulus of the dry film 5 are matched to the film 1. Particularly, the film 1 adopts an FPC film substrate, and the dry film 5 adopts a polyimide dry film material; or the film 1 adopts a PET substrate, and the dry film 5 adopts an RCC dry film curing sheet. This further reduces the effects of warpage and thermal stress.
In one embodiment, as shown in fig. 10, the package substrate further includes a wiring dielectric layer 6 and a redistribution layer 7 disposed on a side of the upper surface of the package substrate 8, where the redistribution layer 7 is electrically connected to the chip 4.
In one embodiment, the thickness of the chip 4 is below 50 μm. Considering that the silicon-based material will exhibit flexible and bendable properties after the wafer thickness is less than 50 μm, in order to further improve the problem of chip cracking due to warpage in board level packaging, it is preferable to use a chip with a thickness of 50 μm or less.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (10)
1. A fan-out board level packaging method, comprising:
providing a film having a plurality of windows arranged in an array;
providing a first carrier plate, and attaching the film to the first carrier plate through a first bonding adhesive;
providing a plurality of chips, respectively attaching each chip to the corresponding window, and attaching the front surface of each chip to the first bonding glue;
providing a dry film, covering the film and the chip with the dry film, and filling a gap between the film and the chip;
curing the dry film;
and removing the first carrier plate to obtain a film-chip-dry film structure.
2. The fan-out board level packaging method of claim 1, wherein after removing the first carrier board to obtain the thin film-chip-dry film structure, further comprising:
providing a second carrier plate, and attaching one side of the dry film of the film-chip-dry film structure to the second carrier plate through a second bonding adhesive;
and manufacturing a wiring medium layer and a rewiring layer on the surfaces of the film and the chip.
3. The utility model provides a fan-out type board level packaging structure, its characterized in that includes packaging substrate and openly is located the chip of packaging substrate upper surface, packaging substrate includes the dry film of lower floor and the film of upper strata, seted up on the film and held the window of chip, the window size is greater than the chip, the window edge with part between the chip edge by the dry film is filled.
4. The fan-out board-level package structure of claim 3, wherein:
the packaging substrate further comprises a wiring medium layer and a rewiring layer, wherein the wiring medium layer and the rewiring layer are arranged on one side of the upper surface of the packaging substrate, and the rewiring layer is electrically connected with the chip.
5. A fan-out board level packaging method as claimed in claim 1 or 2 or a fan-out board level packaging structure as claimed in claim 3 or 4, wherein:
the distance between the window edge of the thin film and the corresponding chip edge is more than twice the thickness of the dry film.
6. A fan-out board level packaging method as claimed in claim 1 or 2 or a fan-out board level packaging structure as claimed in claim 3 or 4, wherein:
the CTE and elastic modulus of the dry film are matched to the film.
7. The fan-out board-level packaging method or the fan-out board-level packaging structure of claim 6, wherein:
the film adopts an FPC film substrate, and the dry film adopts a polyimide dry film material; or
The film adopts the PET substrate, the dry film adopts RCC dry film curing piece.
8. A fan-out board level packaging method as claimed in claim 1 or 2 or a fan-out board level packaging structure as claimed in claim 3 or 4, wherein:
the thickness of the thin film is greater than that of the chip.
9. The fan-out board-level packaging method or the fan-out board-level packaging structure of claim 8, wherein:
the thickness of the dry film is not less than the thickness of the film.
10. A fan-out board level packaging method as claimed in claim 1 or 2 or a fan-out board level packaging structure as claimed in claim 3 or 4, wherein:
the thickness of the chip is below 50 μm.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110035869.XA CN112864027A (en) | 2021-01-12 | 2021-01-12 | Fan-out type board level packaging method and structure thereof |
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| CN202110035869.XA CN112864027A (en) | 2021-01-12 | 2021-01-12 | Fan-out type board level packaging method and structure thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116844969A (en) * | 2023-07-04 | 2023-10-03 | 江苏中科智芯集成科技有限公司 | Chip mounting positioning method and fan-out type packaging process |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20180061788A1 (en) * | 2016-08-29 | 2018-03-01 | Via Alliance Semiconductor Co., Ltd. | Chip package array, and chip package |
| CN110998799A (en) * | 2017-08-09 | 2020-04-10 | 琳得科株式会社 | Method for heating and peeling object to be processed and inspected |
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2021
- 2021-01-12 CN CN202110035869.XA patent/CN112864027A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20180061788A1 (en) * | 2016-08-29 | 2018-03-01 | Via Alliance Semiconductor Co., Ltd. | Chip package array, and chip package |
| CN110998799A (en) * | 2017-08-09 | 2020-04-10 | 琳得科株式会社 | Method for heating and peeling object to be processed and inspected |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116844969A (en) * | 2023-07-04 | 2023-10-03 | 江苏中科智芯集成科技有限公司 | Chip mounting positioning method and fan-out type packaging process |
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Application publication date: 20210528 |