CN112861454A - Method for realizing top-level automatic instantiation of chip system based on python - Google Patents
Method for realizing top-level automatic instantiation of chip system based on python Download PDFInfo
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- CN112861454A CN112861454A CN202110131740.9A CN202110131740A CN112861454A CN 112861454 A CN112861454 A CN 112861454A CN 202110131740 A CN202110131740 A CN 202110131740A CN 112861454 A CN112861454 A CN 112861454A
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Abstract
The invention discloses a method for realizing top-level automatic instantiation of a chip system based on python, which comprises the following steps: collecting interface information of the RTL sub-module, filling an interface information table, and distinguishing the modules by sheet; processing the interface information table by using a script written by a python language; inputting a desired module top-level name in an input line in a pop-up window to generate a top-level file; and checking the generated checking result, namely the log file, to check whether a problem exists. The script written by the python language can process the interface information table and generate a correct connected top-level file. The invention uses the understandable python language to compile the top-level code automatic instantiation script, processes the filled interface information table to generate the top-level code, greatly reduces the workload of top-level code integration, is easy to modify, carries out check on bit width and interface type of some signal interfaces, and is not easy to make mistakes.
Description
Technical Field
The invention relates to the technical field of integrated circuit design verification, in particular to a method for realizing top-level automatic instantiation of a chip system based on python.
Background
Due to the promotion of chip manufacturing processes, from 40nm to 28nm, 16nm and 7nm, a large number of modules which can be integrated in a chip are more and more, namely, the circuit complexity is higher and higher, and more difficulties are brought to the integration of the top layer of the chip.
At present, the top layer of the chip is connected in a manual mode, namely a manual connection mode. The more instantiated modules at the top of the chip, the more workload and error rate are brought. In an actual design, for a large-scale chip, when a designer instantiates a top layer, hundreds of modules are possible, each module has at least tens of signals, and often tens of thousands of signals need to be connected, so that the error rate of manual connection is high.
In addition, from the viewpoint of workload, in order to reduce errors, a designer needs to carefully and repeatedly check after completing connection, and once a large amount of signal changes between modules occur, the manual and time costs are high. It is also a large impact on project progress. These are all disadvantages of the prior art because the project cycle has to be allowed a certain amount of time when the top level is instantiated.
Disclosure of Invention
The invention aims to provide a method for realizing top-level automatic instantiation of a chip based on python language, which aims to solve the problems of complex work, more time consumption and easy error when manual connection is carried out on top-level instantiation.
In order to achieve the purpose, the invention provides the following technical scheme:
a method for realizing top-level automatic instantiation of a chip system based on python comprises the following steps:
s1, collecting interface information of the RTL sub-module to fill in an interface information table, and distinguishing the modules by sheet;
s2, processing the interface information table by using a script (converted into an exe file) written by a python language;
s3, inputting the top-level name of the desired module in the input line of the pop-up window to generate a top-level file;
s4, the generated log file is checked to see if there is a problem.
As a further scheme of the invention: the sheet of each module in the interface information table needs to be filled with an interface name, a signal bit width, an interface attribute, a signal source module, a signal destination module and a top-level signal name.
As a further scheme of the invention: the script written by the python language can process the interface information table and generate a correct connected top-level file.
As a further scheme of the invention: the script written in the python language is divided into three functions:
(1) the first function is used for inputting signals in each sub-module in an excel table into a dictionary, wherein indexes (keys) are module names, values are signal information (signal names, sources, purposes, bit widths and the like), namely, an input-oriented object is defined and the input-oriented object is realized by using a class statement which is most commonly used by python.
(2) The second function is used for checking the signals recorded into the dictionary once, and for a signal recorded into the signal effective dictionary which accords with the specification, the index (key) is the module name, and the value is the signal information; signals that do not meet the specification are marked, and the marked signals are printed in logs of the module in which the signals are located, and errors that do not meet the specification are printed.
(3) The third function is used for generating corresponding integrated codes through the checked signals (the signal effective dictionary), and the function defines the module name, generates an instantiation module and generates a connection signal on the basis of the passing of the function (2) according to the standard verilog grammar; further, it is also possible to print a syntax, set a format of printing, a space, a bit width syntax, an end symbol, and related contents.
As a further scheme of the invention: function (2) is checked as follows: (a) whether the name signal in the table module is repeated; (b) whether the dest/src name corresponding to the source end input/output is different from the name of the module or not is judged; (c) the signal has no opposite terminal module; (d) whether the opposite end module signal names are matched; (e) whether the opposite end is matched with the source end in/out or not; (f) whether the bit width of the opposite end is matched with that of the source end or not; (g) interface information is inaccurate (three cases of non-input/output/input); (h) whether the signal bit width filling meets the specification or not; (i) whether the signal has multi-drive exists or not is reported; (j) whether there is a signal is not considered, there is no connection; if a problem is detected, an error number is printed.
Compared with the prior art, the invention has the beneficial effects that: the top-level code automatic instantiation script is compiled by using an easily understood python language, the filled interface information table is processed to generate the top-level code, the workload of top-level code integration is greatly reduced, the modification is easy, and errors are not easy to occur due to the check of bit width and interface types of some signal interfaces.
Drawings
FIG. 1 is a flow diagram for implementing top-level automation of a system-on-a-chip based on python.
FIG. 2 is a table of interface information for block A modules.
FIG. 3 is a table of interface information for the block B module.
Detailed Description
The technical solution of the present patent will be described in further detail with reference to the following embodiments.
Referring to fig. 1, a method for implementing automatic instantiation at the top level of a chip system based on python includes the following steps:
s1, collecting interface information of the RTL sub-module to fill in an interface information table, and distinguishing the modules by sheet; filling in the sheet of each module in the form, wherein the sheet comprises an interface name, a signal bit width, an interface attribute, a signal source module, a signal destination module and a top-layer signal name;
s2, processing the interface information table by using a script (converted into an exe file) written by a python language;
s3, inputting the top-level name of the desired module in the input line of the pop-up window to generate a top-level file;
s4, the generated log file is checked to see if there is a problem.
The operation instance on script completion basis:
the requirement is that block a and block B are instantiated and connected to form top layer top.
Interface information tables (two sheets of one form) of the two modules of block A and block B, which are respectively shown in FIG. 2 and FIG. 3, are filled, and common projects of the forms are maintained, so that the interface information of the modules can be conveniently checked together in the later period of the projects, and no extra work is needed.
The filling contents mainly include SIG _ NMAE (signal name), WIDTH (signal bit WIDTH), I/O (interface type), SOURCE (signal SOURCE module), DESTINATION (signal DESTINATION module), TOP _ PIN (name of the specified signal at the TOP layer).
After completion of filling, drag the form with the left mouse button onto the written python script (. exe), then pop up the window, enter the desired top-level name, output the top-level file, and check the report.
Although the preferred embodiments of the present patent have been described in detail, the present patent is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present patent within the knowledge of those skilled in the art.
Claims (9)
1. A method for realizing top-level automatic instantiation of a chip system based on python is characterized by comprising the following steps:
s1, collecting interface information of the RTL sub-module to fill in an interface information table, and distinguishing the modules by sheet;
s2, processing the interface information table by using a script written by a python language;
s3, inputting the top-level name of the required module in the input line of the pop-up window to generate a top-level file;
s4, the generated log file is checked to see if there is a problem.
2. The method for implementing top-level automatic instantiation of a chip system based on python as claimed in claim 1, wherein an interface name, a signal bit width, an interface attribute, a signal source module, a signal destination module and a top-level signal name are filled in a sheet of each module of said interface information table.
3. The method for implementing the top-level automatic instantiation of a system-on-a-chip based on python as claimed in claim 1, wherein the script written in the python language is converted into an exe file.
4. The method for implementing the top-level automatic instantiation of a chip system based on python as claimed in claim 1, wherein the script written in python language can process the interface information table and generate the correct linked top-level file.
5. The method for implementing the top-level automatic instantiation of a system-on-a-chip based on python as claimed in claim 1, wherein the script written in python language is divided into three functions:
(1) the first function is used for recording signals in each sub-module in the excel table into a dictionary, wherein indexes are module names, and values are signal information;
(2) the second function is used for checking the signals recorded into the dictionary in sequence;
(3) the third function has the effect of generating a corresponding integrated code from the examined signal.
6. The method of claim 5, wherein the first function defines the object-oriented input implemented using the most common class statements of python.
7. The method of claim 5, wherein the second function checks as follows:
(a) whether the name signal in the table module is repeated;
(b) whether the dest/src name corresponding to the source end input/output is different from the name of the module or not is judged;
(c) the signal has no opposite terminal module;
(d) whether the opposite end module signal names are matched;
(e) whether the opposite end is matched with the source end in/out or not;
(f) whether the bit width of the opposite end is matched with that of the source end or not;
(g) the interface information is inaccurate;
(h) whether the signal bit width filling meets the specification or not;
(i) whether the signal has multi-drive exists or not is reported;
(j) whether there is a signal is not considered, there is no connection;
if the function detects a problem, an error number is printed.
8. The method for implementing automatic top-level instantiation of a chip system based on python as claimed in claim 5, wherein said second function is a signal entry valid dictionary with module names as indices and signal information as values for signals meeting specifications; signals that do not meet the specification are marked, and the marked signals are printed in logs of the module in which the signals are located, and errors that do not meet the specification are printed.
9. The method for implementing automatic instantiation at the top level of a chip system based on python as claimed in claim 5, wherein said third function defines module name, generates instantiation module, generates connection signal based on the passing of the second function according to standard verilog syntax; the third function is also capable of printing grammars, setting the format of the print, spaces, bit width grammars, end symbols, and related content.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113778395A (en) * | 2021-08-30 | 2021-12-10 | 东风汽车集团股份有限公司 | Software automatic integration control method based on software development platform |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102012954A (en) * | 2010-11-29 | 2011-04-13 | 杭州中天微系统有限公司 | Subsystem integration method and subsystem integration system for integration design of system-on-chip |
| CN110442929A (en) * | 2019-07-18 | 2019-11-12 | 上海磐启微电子有限公司 | A method of the automatic example of chip system top layer is realized based on perl |
| CN111045948A (en) * | 2019-12-13 | 2020-04-21 | 盛科网络（苏州）有限公司 | Method, apparatus and storage medium for checking interface signal between modules |
| CN111859827A (en) * | 2020-06-29 | 2020-10-30 | 山东云海国创云计算装备产业创新中心有限公司 | Chip IP integration method and device, electronic equipment and storage medium |
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- 2021-01-30 CN CN202110131740.9A patent/CN112861454B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102012954A (en) * | 2010-11-29 | 2011-04-13 | 杭州中天微系统有限公司 | Subsystem integration method and subsystem integration system for integration design of system-on-chip |
| CN110442929A (en) * | 2019-07-18 | 2019-11-12 | 上海磐启微电子有限公司 | A method of the automatic example of chip system top layer is realized based on perl |
| CN111045948A (en) * | 2019-12-13 | 2020-04-21 | 盛科网络（苏州）有限公司 | Method, apparatus and storage medium for checking interface signal between modules |
| CN111859827A (en) * | 2020-06-29 | 2020-10-30 | 山东云海国创云计算装备产业创新中心有限公司 | Chip IP integration method and device, electronic equipment and storage medium |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113778395A (en) * | 2021-08-30 | 2021-12-10 | 东风汽车集团股份有限公司 | Software automatic integration control method based on software development platform |
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