CN112860266A - Intelligent binary compilation information inference method based on assembly representation - Google Patents
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Abstract
The invention discloses an intelligent binary compilation information inference method based on assembly representation, which belongs to the technical field of assembly, and comprises the following steps of S1, establishing an inference model; s2, compiling, characterizing and optimizing; s3, learning and optimizing an inference model; s4, basic compiling; s5, converting an intermediate instruction; s6, optimizing middle-end analysis; and S7, binary compilation information generation. According to the invention, the characteristics of the assembly language are rapidly extracted, the complicacy of the assembly language material is effectively reduced, the performance of a translated local program is effectively improved after redundant instruction deduplication is carried out in the intermediate process, the maintenance cost of a global register is reduced by carrying out cyclic weighted distribution on the priority value of the register, the overflow of an unnecessary register is reduced by means of the distribution of a control register, the expansion rate of a body code is reduced, the efficiency of translating a target program is improved, and the fast binary compiling capability of assembly data is realized by representing the learning optimization of an input value after the learning optimization to an inference model.
Description
Technical Field
The invention belongs to the technical field of assembly, and particularly relates to an intelligent binary compilation information inference method based on assembly representation.
Background
Assembly is the basic computer language, and in different machine frameworks, a single assembly language cannot well meet the software calling requirement, so binary compiling and translating are required to be carried out to realize software transplantation between different architectures and processor platforms.
The traditional binary translation is mostly processed by a static method, but the efficiency of a large amount of data is low, the translation is difficult to process indirect branches, the existing optimization method mostly optimizes data for an intermediate code layer, the processing optimization capability of redundant instructions and front-end data in the translation process is lacked, the inference efficiency of information is influenced by the redundant instructions of a large amount of data, and the requirement for quick compilation of assembly language cannot be well met.
Disclosure of Invention
The invention aims to: in order to solve the problems that the efficiency of mass data is low, translation is difficult to process indirect branches, the existing optimization method mostly realizes data optimization on an intermediate code layer, redundant instructions in the translation process and the processing optimization capability of front-end data are lacked, and the redundant instructions of mass data influence the inference efficiency of information, the intelligent binary compiling information inference method based on the assembly representation is provided.
In order to achieve the purpose, the invention adopts the following technical scheme:
an intelligent binary compilation information inference method based on assembly representation comprises the following steps:
s1, establishing an inference model, collecting a large amount of language material information based on assembly language, and establishing an intelligent structure inference model based on assembly information, wherein the model comprises a front-end source code parser and a decoder, a middle-end distribution optimization register and a rear-end target code generation translator;
s2, compiling representation optimization, performing input value optimization of representation learning on the model through the representation sharing of multitask or transfer learning of compiled information, improving interpretability of the inferred model through the representation learning, performing exploration optimization on the structure of the model, solving a partial derivative through a minimized loss function, and optimizing each module of the inferred model through the structure of input data and given label output of the derivative;
s3, learning and optimizing an inference model, namely preprocessing data, and performing reverse inference model learning on the inference model through an optimized input vector to optimize the binary translation capability of the model;
s4, basic compilation, namely, optimizing the input of source code compilation information through a model, removing duplication of redundant memory access instructions in a compilation core, screening out important compilation information, preprocessing data, arranging a binary assembly language program, and performing static pre-translation on the optimization model through a decoder;
s5, converting intermediate instructions, decoding the original platform instructions one by encoding through a source file analyzer and a front-end decoder, generating intermediate instructions with the same voice according to the front-end source instructions analyzed by the decoder, and translating the binary codes of the original platform into intermediate codes;
s6, analyzing and optimizing the middle end, and optimizing the reacted middle code and the irrelevant information of the platform end;
and S7, binary compilation information is generated, a back-end target code translates a terminal code into a binary code of a target platform through a back-end translator, the translated terminal code is analyzed through a decoder to generate an instruction, after the binary information instruction is input, all entry instructions are found, the entry instructions are marked, address variable conversion is carried out when an entry instruction pointer is met, unknown threshold values are set among the marks, common threshold values among different modules are observed, model backstepping is carried out through the values of the common threshold values, residual blank information is dynamically translated through the models, and the binary compilation information after the compilation is concluded is obtained after the translation result.
As a further description of the above technical solution:
and the corpus information in the S1 realizes data interaction through sharing, and the sharing mode comprises a hard sharing mode, a soft sharing mode, a hierarchical sharing mode and a sharing private mode.
As a further description of the above technical solution:
the S6 intermediate code layer optimization includes liveness analysis by regular basic block partitioning of program entry points, next to branch instructions, target addresses of branch instructions, and liveness analysis of the basic block for temporary variables active in the compiler.
As a further description of the above technical solution:
the temporary variables of the S6 intermediate codes are optimized to be virtual register allocation, the number of the virtual registers is prioritized, register allocation is performed through an optimization algorithm, write-back processing is performed, a redundant access instruction is introduced, the registers are set to be a loop block and located in a loop body, the execution frequency P is 1000, when the loop block allocates the instruction registers, the access instruction is added at the head and the tail of the loop block, and accumulation requirements in the loop body are preferably met.
As a further description of the above technical solution:
the redundant memory access instruction in S4 is a read or write instruction for the same memory address, and the value of the address is still retained in the same register, and the current memory access instruction can be defined as a redundant memory access instruction.
As a further description of the above technical solution:
the multi-task characterization sharing optimization in the S2 includes that S related tasks are assumed, a training set of the S-th task is Ds and includes Ns samples, models corresponding to the S tasks are assumed to be fs (x; theta), S is larger than or equal to 1 and smaller than or equal to S, a joint objective function of multi-task learning is linear weighting of loss functions of all tasks, and the weighting can be assigned according to importance degrees of different tasks or difficulty degrees of the tasks.
As a further description of the above technical solution:
the tasks set the same weight, namely eta S is 1, and S is not less than 1 and not more than S.
As a further description of the above technical solution:
and optimizing the inference model in the step S3, wherein the step S comprises the step of gradually adjusting a front-end source code parser and a decoder, a middle-end allocation optimization register and a translator to perform threshold optimization after data of an output end and an input end are input through a BP algorithm.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
according to the invention, through learning of the assembly representation, the input value of the judgment model is effectively optimized, the interpretability of the inference model is improved, the original data is effectively developed through special evidence extraction and running learning, the characteristics of the assembly language are quickly extracted, the complexity of the assembly language material is effectively reduced, the performance of a translated local program is effectively improved after redundant instruction deduplication is carried out in the middle process, the maintenance expense of a global register is reduced through cyclic weighted distribution of the priority value of the register, the overflow of an unnecessary register is reduced by means of the distribution of a control register, the expansion rate of a body code is reduced, the efficiency of a translation target program is improved, and the quick binary compiling capability of the assembly data is realized through the learning optimization of the inference model by characterizing the input value after learning optimization.
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Fig. 1 is a flowchart of an intelligent binary compilation information inference method based on assembly characterization according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the present invention provides a technical solution: an intelligent binary compilation information inference method based on assembly representation comprises the following steps:
s1, establishing an inference model, collecting a large amount of language material information based on assembly language, and establishing an intelligent structure inference model based on assembly information, wherein the model comprises a front-end source code parser and a decoder, a middle-end distribution optimization register and a rear-end target code generation translator;
s2, compiling characterization optimization, performing input value optimization of characterization learning on the model through characterization sharing of multitask or transfer learning of compiled information, improving interpretability of the inference model through the characterization learning, performing exploration optimization on the structure of the model, solving a partial derivative through a minimized loss function, and optimizing each module of the inference model through the structure of input data and given label output of the derivative, wherein the multitask characterization sharing optimization comprises S related tasks, and a training set of an S-th task is Ns and comprises a plurality of samples, and the formula (1):
assuming that the models corresponding to the S tasks are fs (x; theta), S is more than or equal to 1 and less than or equal to S, the joint objective function of the multi-task learning is the linear weighting of all task loss functions, and the weighting function is as the following formula (2):
the weights can be assigned according to the importance degrees of different tasks, and also can be assigned according to the difficulty degrees of the tasks, the tasks are provided with the same weights, namely eta S is 1, S is more than or equal to 1 and is less than or equal to S, one task is randomly selected during each iteration, then training samples are randomly selected from the task, the gradient is calculated, the parameters are updated, the representation learning aims at representing the nodes in the network into a low-dimensional, real-valued and dense vector form, so that the obtained vector form can have the representing and reasoning capabilities in a vector space, and can be more flexibly applied to different data mining tasks;
s3, learning and optimizing an inference model, namely performing reverse inference model learning on the inference model through an optimized input vector after preprocessing data, optimizing the binary translation capability of the model, and realizing optimization processing on the inference model through comparison and adjustment of the input vector and the output vector;
s4, basic compilation, namely, optimizing the input of source code compilation information through a model, removing duplication of redundant memory access instructions in a compilation core, screening out important compilation information, preprocessing data, arranging a binary assembly language program, and performing static pre-translation on the optimization model through a decoder;
s5, converting intermediate instructions, decoding the original platform instructions one by encoding through a source file analyzer and a front-end decoder, generating intermediate instructions with the same voice according to the front-end source instructions analyzed by the decoder, and translating the binary codes of the original platform into intermediate codes;
s6, middle-end analysis and optimization, wherein the reacted intermediate code and the irrelevant information of the platform end are optimized, the optimization of the intermediate code layer comprises activity analysis, the division of a regular basic block is carried out by a program entry point, a next instruction of a branch instruction and a target address of the branch instruction, and the activity analysis is carried out on the activity of a temporary variable of the basic block in a compiler;
and S7, binary compilation information is generated, a back-end target code translates a terminal code into a binary code of a target platform through a back-end translator, the translated terminal code is analyzed through a decoder to generate an instruction, after the binary information instruction is input, all entry instructions are found, the entry instructions are marked, address variable conversion is carried out when an entry instruction pointer is met, unknown threshold values are set among the marks, common threshold values among different modules are observed, model backstepping is carried out through the values of the common threshold values, residual blank information is dynamically translated through the models, and the binary compilation information after the compilation is concluded is obtained after the translation result.
And the corpus information in the S1 realizes data interaction through sharing, and the sharing mode comprises a hard sharing mode, a soft sharing mode, a hierarchical sharing mode and a sharing private mode.
The temporary variables of the S6 intermediate codes are optimized to be virtual register allocation, the number of the virtual registers is prioritized, register allocation is carried out through an optimization algorithm, write-back processing is carried out, a redundant access instruction is introduced, the registers are set to be a loop block and located in the loop body, the execution frequency P is 1000, when the loop block allocates the instruction registers, the access instruction is added to the head and the tail of the loop block, the accumulation requirement in the loop body is preferably met, and after optimization, the speed-up ratio is obtained through judgment of execution time.
The redundant memory access instruction in S4 is a read or write instruction for the same memory address, and the value of the address is still retained in the same register, and the current memory access instruction can be defined as a redundant memory access instruction.
And optimizing the inference model in the step S3, wherein the step S comprises the step of gradually adjusting a front-end source code parser and a decoder, a middle-end allocation optimization register and a translator to perform threshold optimization after data of an output end and an input end are input through a BP algorithm.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.
Claims (8)
1. An intelligent binary compilation information inference method based on assembly characterization is characterized by comprising the following steps of:
s1, establishing an inference model, collecting a large amount of language material information based on assembly language, and establishing an intelligent structure inference model based on assembly information, wherein the model comprises a front-end source code parser and a decoder, a middle-end distribution optimization register and a rear-end target code generation translator;
s2, compiling representation optimization, performing input value optimization of representation learning on the model through the representation sharing of multitask or transfer learning of compiled information, improving interpretability of the inferred model through the representation learning, performing exploration optimization on the structure of the model, solving a partial derivative through a minimized loss function, and optimizing each module of the inferred model through the structure of input data and given label output of the derivative;
s3, learning and optimizing an inference model, namely preprocessing data, and performing reverse inference model learning on the inference model through an optimized input vector to optimize the binary translation capability of the model;
s4, basic compilation, namely, optimizing the input of source code compilation information through a model, removing duplication of redundant memory access instructions in a compilation core, screening out important compilation information, preprocessing data, arranging a binary assembly language program, and performing static pre-translation on the optimization model through a decoder;
s5, converting intermediate instructions, decoding the original platform instructions one by encoding through a source file analyzer and a front-end decoder, generating intermediate instructions with the same voice according to the front-end source instructions analyzed by the decoder, and translating the binary codes of the original platform into intermediate codes;
s6, analyzing and optimizing the middle end, and optimizing the reacted middle code and the irrelevant information of the platform end;
and S7, binary compilation information is generated, a back-end target code translates a terminal code into a binary code of a target platform through a back-end translator, the translated terminal code is analyzed through a decoder to generate an instruction, after the binary information instruction is input, all entry instructions are found, the entry instructions are marked, address variable conversion is carried out when an entry instruction pointer is met, unknown threshold values are set among the marks, common threshold values among different modules are observed, model backstepping is carried out through the values of the common threshold values, residual blank information is dynamically translated through the models, and the binary compilation information after the compilation is concluded is obtained after the translation result.
2. The method according to claim 1, wherein the corpus information in S1 is shared to realize data interaction, and the sharing modes include hard sharing, soft sharing, hierarchical sharing and private sharing.
3. The method of claim 1, wherein the optimizing of the S6 intermediate code layer comprises activity analysis by partitioning regular basic blocks of program entry points, next instructions of branch instructions, target addresses of branch instructions, and activity analysis of the basic blocks for activity of temporary variables in the compiler.
4. The intelligent binary compilation information inference method based on assembly characterization according to claim 1, wherein temporary variables of the S6 intermediate code are optimized to virtual register allocation, the number of virtual registers is prioritized, register allocation is performed through an optimization algorithm, write-back processing is performed, a redundant access instruction is introduced, the registers are set as loop blocks and located in a loop body, the execution frequency P is 1000, when the loop blocks allocate instruction registers, access instructions are added at the head and the tail of the loop blocks, and accumulation requirements inside the loop body are preferably met.
5. The method as claimed in claim 1, wherein the redundant access instruction in S4 is a read or write instruction for the same memory address, and the value of the address remains in the same register, and the current access instruction can be defined as a redundant access instruction.
6. The method as claimed in claim 1, wherein the sharing optimization of the multitask representation in S2 includes assuming that there are S related tasks and the training set of the S-th task is Ds and includes Ns samples, assuming that the models corresponding to the S tasks are fs (x; θ) respectively, S is greater than or equal to 1 and less than or equal to S, and the joint objective function of the multitask learning is a linear weighting of the loss functions of all tasks, and the weights may be assigned according to the importance of different tasks or according to the difficulty of tasks.
7. The method as claimed in claim 6, wherein the task sets the same weight, i.e. η S ═ 1, and S ≦ 1.
8. The method of claim 1, wherein the optimizing of the inference model in S3 comprises successively adjusting a front-end source code parser and decoder, a middle-end allocation optimization register, and a translator to perform threshold optimization after inputting data at the output end and the input end through a BP algorithm.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7111290B1 (en) * | 1999-01-28 | 2006-09-19 | Ati International Srl | Profiling program execution to identify frequently-executed portions and to assist binary translation |
| CN102932328A (en) * | 2012-09-26 | 2013-02-13 | 上海交通大学 | Access control policy synthesis method based on BSset (binary string set) |
| US20130227693A1 (en) * | 2012-02-24 | 2013-08-29 | David Bryan Dewey | Software module object analysis |
| CN103942082A (en) * | 2014-04-02 | 2014-07-23 | 南阳理工学院 | Complier optimization method for eliminating redundant storage access operations |
| CN108694056A (en) * | 2017-03-30 | 2018-10-23 | 英特尔公司 | Mixing atomicity for the microprocessor based on binary translation is supported |
| US20200174765A1 (en) * | 2018-11-30 | 2020-06-04 | Grammatech, Inc. | Systems and/or methods for generating reassemblable disassemblies of binaries using declarative logic |
-
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- 2021-04-07 CN CN202110372215.6A patent/CN112860266B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7111290B1 (en) * | 1999-01-28 | 2006-09-19 | Ati International Srl | Profiling program execution to identify frequently-executed portions and to assist binary translation |
| US20130227693A1 (en) * | 2012-02-24 | 2013-08-29 | David Bryan Dewey | Software module object analysis |
| CN102932328A (en) * | 2012-09-26 | 2013-02-13 | 上海交通大学 | Access control policy synthesis method based on BSset (binary string set) |
| CN103942082A (en) * | 2014-04-02 | 2014-07-23 | 南阳理工学院 | Complier optimization method for eliminating redundant storage access operations |
| CN108694056A (en) * | 2017-03-30 | 2018-10-23 | 英特尔公司 | Mixing atomicity for the microprocessor based on binary translation is supported |
| US20200174765A1 (en) * | 2018-11-30 | 2020-06-04 | Grammatech, Inc. | Systems and/or methods for generating reassemblable disassemblies of binaries using declarative logic |
Non-Patent Citations (1)
| Title |
|---|
| 张柏年: "基于动态二进制翻译技术的反编译研究", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
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