CN112840309B - Command scheduling method, device and storage medium - Google Patents
Command scheduling method, device and storage medium Download PDFInfo
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- CN112840309B CN112840309B CN201880098676.5A CN201880098676A CN112840309B CN 112840309 B CN112840309 B CN 112840309B CN 201880098676 A CN201880098676 A CN 201880098676A CN 112840309 B CN112840309 B CN 112840309B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
A command scheduling method for use in a UFS chip is provided for scheduling commands located in a command queue. The command scheduling method comprises the following steps: starting a timer when the read command in the command queue is from scratch, wherein the timer counts until the timer is cleared; after each write command is executed, when the read command exists in the command queue and the value of the timer exceeds the preset value, all the read commands in the command queue are scheduled to be executed preferentially, so that the read commands in the command queue are scheduled faster, and the normal operation of the host is ensured.
Description
Technical Field
The embodiment of the application relates to a communication technology, in particular to a command scheduling method, a device and a storage medium.
Background
In general, to ensure that power is not lost, a terminal device typically has a built-in power-down nonvolatile storage medium. Currently, the mainstream power-down nonvolatile storage medium is a universal flash storage (Universal Flash Storage, UFS) chip. In application, the host performs read-write operation on the UFS chip through a small computer system interface (Small Computer System Interface, SCSI) command defined by the UFS protocol. Specifically, the UFS protocol provides a command queue of depth 32, i.e., the host can send up to 32 SCSI commands simultaneously to the UFS chip. Wherein the SCSI commands include read commands and write commands.
For SCSI commands in the command queue, the UFS chip processes according to a first-in first-out (First Input First Output, FIFO) policy, prioritizing the SCSI commands received first. In addition, in UFS chip applications, the execution speed of read commands is much faster than the execution speed of write commands; moreover, it is generally desirable for the host to respond more quickly to read commands. Thus, if a read command is placed in the back portion of the command queue according to the FIFO policy, the read command is placed, for example, in the 29 th bit of the command queue, and its latency is affected by the superposition of the latencies of the first 28 SCSI commands, resulting in a larger latency, which affects the operation of the host.
Disclosure of Invention
The embodiment of the application provides a command scheduling method, a device and a storage medium, which are used for enabling a read command in a command queue to be scheduled faster and ensuring the normal operation of a host.
In a first aspect, an embodiment of the present application provides a command scheduling method, configured to schedule a command located in a command queue, including: starting a timer when the read command in the command queue is from scratch, wherein the timer counts until the timer is cleared; after each write command is executed, when the read command exists in the command queue and the value of the timer exceeds the preset value, all the read commands in the command queue are scheduled to be executed preferentially.
Each time a SCSI command is received, the UFS controller generates an interrupt signal, and during the validity of the interrupt signal, the counter determines the type of SCSI command currently received: a read command or a write command, and when the currently received SCSI command is a read command, the counter is incremented by 1. The initial value of the counter is 0.
When the counter changes from 0 to 1, it indicates that a read command is present in the command queue, and at this time, the UFS controller starts a timer to time the first read command present in the command queue.
Optionally, a read command is preferentially executed per dispatch command queue, with the counter decremented by 1.
The preset value can be set according to historical experience values or actual requirements.
When the read command in the command queue is not received, starting a timer, and after each write command is executed, when the read command exists in the command queue and the value of the timer exceeds a preset value, dispatching all the read commands in the command queue to be executed preferentially, thereby improving the response efficiency of the read command in the UFS chip, reducing the time delay of the read command in the command queue and ensuring the normal operation of a host.
In one possible implementation, the command scheduling method may further include: after each write command is executed, when the read command is judged to be not in the command queue, or when the read command is judged to be in the command queue but the value of the timer does not exceed the preset value, executing the command in the command queue by using the FIFO strategy. The scheme considers the characteristic that the time length of the UFS controller for executing the write command is longer than the time length of the read command, when a large number of write commands exist in a command queue, the time delay of the read command positioned behind the write command is reduced, and the read command can be ensured to be responded quickly. In addition, since the execution speed of the read command is fast, even if all the read commands in the command queue are preferentially scheduled, too much delay is not caused to the write commands in the command queue.
Optionally, the duration of executing the write command is longer than the duration of executing the read command, so that the response efficiency of the write command in the command queue is ensured while the time delay of the read command is reduced while all the read commands in the command queue are preferentially scheduled.
In some embodiments, after all the read commands in the command queue are preferentially executed, the command scheduling method may further include: and executing other commands to be processed in the command queue according to the FIFO strategy.
After all the read commands in the dispatching command queue are preferentially executed, other commands to be processed in the command queue are executed according to the FIFO strategy, so that only the read commands which are currently put in the command queue are processed, and the newly-entered read commands are not preferentially dispatched in the processing process, so that the write commands which are originally entered into the command queue are not blocked by the continuously-entered read commands. When all the read commands in the command queue are executed, the FIFO strategy is switched back again, so that the write commands which enter the command queue can be executed faster, the total delay of the write commands is controlled not to be particularly long, the delay of the read commands can be reduced, and the scheduled blocking of the write commands caused by the simple adoption of the read priority strategy can be avoided, namely, the execution of the read commands and the write commands in the command queue is ensured at the same time.
Further, since the host may always issue a SCSI command, or a new SCSI command always enters in the process of executing a SCSI command in the command queue, the command scheduling method may further include: the UFS controller obtains a command to be processed sent by a host; and placing the commands to be processed into a command queue according to the sequence, and executing according to the FIFO strategy.
Optionally, after each write command is executed, when it is determined that a read command exists in the command queue and the value of the timer exceeds the preset value, before all the read commands in the command queue are scheduled to be executed preferentially, the command scheduling method may further include: zero clearing or closing the timer. Through this scheme, guarantee the validity of time-keeping function of time-keeping device. Further, the timer is restarted from time to time in the command queue for the read command, and so on.
In a second aspect, an embodiment of the present application provides a command scheduling apparatus, configured to schedule a command located in a command queue, including: and a processing module. Wherein, the liquid crystal display device comprises a liquid crystal display device,
the processing module is used for starting a timer when the read command in the command queue is from scratch, wherein the timer counts time until being cleared; and after each write command is executed, when the read command exists in the command queue and the value of the timer exceeds the preset value, all the read commands in the command queue are scheduled to be executed preferentially.
The command scheduling means may be a UFS chip or a UFS controller within a UFS chip.
In one possible implementation, the processing module may be further configured to: after each write command is executed, when the read command is judged to be not in the command queue, or when the read command is judged to be in the command queue but the value of the timer does not exceed the preset value, executing the command in the command queue by using the FIFO strategy.
In one possible implementation, the write command is executed for a longer period of time than the read command.
In one possible implementation, the processing module may be further configured to: after all read commands in the dispatch command queue are preferentially executed, other pending commands in the command queue are executed according to the FIFO policy.
In one possible implementation, the processing module may be further configured to: acquiring a command to be processed sent by a host; and placing the commands to be processed into a command queue according to the sequence, and executing according to the FIFO strategy.
In one possible implementation, the processing module may be further configured to: after each write command is executed, when the read command exists in the command queue and the value of the timer exceeds the preset value, the timer is cleared or closed before all the read commands in the dispatch command queue are executed preferentially.
In a third aspect, an embodiment of the present application provides a command scheduling apparatus configured to schedule a command located in a command queue. The command scheduling apparatus includes: memory and a processor, and a computer program stored on the memory for execution by the processor. The computer program, when read and executed by a processor, causes the processor to perform the operations of:
starting a timer when the read command in the command queue is from scratch, wherein the timer counts until the timer is cleared; and after each write command is executed, when the read command exists in the command queue and the value of the timer exceeds the preset value, all the read commands in the command queue are scheduled to be executed preferentially.
The command scheduling means may be a UFS chip or a UFS controller within a UFS chip. The processor here may be embodied as a CPU in a UFS controller.
Based on the same inventive concept, since the principle of the command scheduling device for solving the problem corresponds to the solution in the method design of the first aspect, the implementation of the command scheduling device can refer to the implementation of the method, and the repetition is not repeated.
In a fourth aspect, embodiments of the present application provide a computer readable storage medium storing a computer program comprising at least one piece of code executable by a processor to implement a method as described in any of the first aspects.
In a fifth aspect, an embodiment of the present application provides a UFS chip, including: UFS controller and Nand Flash grain. The UFS controller includes a processor and a memory. The memory has stored thereon a computer program executable by the processor; the computer program, when read and executed by a processor, causes the processor to perform the method of any of the first aspects above.
Alternatively, the memory may comprise at least one of ROM and RAM.
Optionally, the UFS chip may further include: UFS interfaces, nand interfaces, and other related hardware modules.
In a sixth aspect, an embodiment of the present application provides an electronic device, including: the UFS chip of the fifth aspect.
In a seventh aspect, an embodiment of the present application provides a program for performing the method of any one of the above first aspects when being executed by a UFS controller of a UFS chip.
In an eighth aspect, an embodiment of the present application provides a computer program product comprising the program of the seventh aspect.
These and other aspects of the application will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.
Drawings
Fig. 1 is a schematic structural diagram of a UFS chip according to an embodiment of the present application;
FIG. 2 is a schematic diagram illustrating a command queue according to an embodiment of the present application;
FIG. 3 is a flow chart of a command scheduling method according to an embodiment of the present application;
FIG. 4 is another flow chart of a command scheduling method according to an embodiment of the present application;
FIG. 5 is a diagram illustrating an example of an application of a command scheduling method according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a command dispatcher according to an embodiment of the present application;
fig. 7 is another schematic structural diagram of a command scheduling device according to an embodiment of the present application.
Detailed Description
Fig. 1 is a schematic structural diagram of a UFS chip according to an embodiment of the present application. Referring to fig. 1, the UFS chip includes a UFS controller and Nand Flash particles, and a central processing unit (Central Processing Unit, CPU), a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a UFS interface, a Nand interface, and other related hardware modules are integrated within the UFS controller.
The UFS controller performs SCSI command interaction based on the UFS protocol through the UFS interface and the host, and puts the received SCSI command into a command queue. In addition, the UFS controller finishes analysis and processing of SCSI commands and cooperates with a Nand interface to realize operations such as reading and writing of Nand Flash particles.
The Firmware (Firmware) of the UFS chip mainly solves the problems of bad blocks, data Retention, read interference and the like inherent to Nand Flash particles, improves the reliability of the Nand Flash particles, and shields the Host (Host) from the differences of the Nand Flash particles brought by various manufacturers and processes.
As described above, in application, the host performs read/write operation on the UFS chip through SCSI commands defined by the UFS protocol. A command queue with a depth of 32 may be composed of 32 SCSI commands, where the command queue is schematically configured as shown in fig. 2. When the SCSI command in the command queue includes a read command and a write command, in order to enable the read command to be scheduled faster, the normal operation of the host is ensured. An example of this command scheduling method is described below.
Fig. 3 is a flow chart illustrating a command scheduling method according to an embodiment of the present application. The embodiment of the application provides a command scheduling method, which is used for scheduling commands in a command queue, and can be executed by a command scheduling device, and the command scheduling device can be realized in a hardware and/or software mode. The command scheduler may be firmware of the UFS chip, or the command scheduler may be a UFS controller, for example. The following description will be made with the UFS controller as an execution subject.
Referring to fig. 3, the command scheduling method in the embodiment of the present application includes the steps of:
s301, starting a timer when a read command in a command queue is never reached.
Wherein the timer counts until cleared.
In practical application, the host computer issues SCSI commands to the UFS chip, and the UFS chip counts the number of read commands in the SCSI commands issued by the host computer through the counter. Each time a SCSI command is received, the UFS controller generates an interrupt signal, and during the validity of the interrupt signal, the counter determines the type of SCSI command currently received: a read command or a write command, and when the currently received SCSI command is a read command, the counter is incremented by 1. The initial value of the counter is 0.
When the counter changes from 0 to 1, it indicates that a read command is present in the command queue, and at this time, the UFS controller starts a timer to time the first read command present in the command queue.
S302, after each write command is executed, when the read command exists in the command queue and the value of the timer exceeds the preset value, all the read commands in the command queue are scheduled to be executed preferentially.
The preset value can be set according to historical experience values or actual requirements.
In the initial stage, the UFS controller processes according to the FIFO strategy. Because the order of the read command and the write command is random in the SCSI command issued by the host, the timer records the retention time of the first read command in the command queue, and the first read command in the command queue may be scheduled for execution first or the last read command in the command queue may be scheduled for execution, which greatly increases the delay of the read command if there are more write commands ordered before the read command in the command queue.
Therefore, after each write command is executed, the UFS controller first determines whether a read command exists in the command queue, for example, determines whether the value of the counter is 0, and if the value of the counter is not 0, it indicates that a read command exists in the command queue; further, the UFS controller determines whether the value of the timer exceeds a preset value, and when the value of the timer exceeds the preset value, it indicates that the duration of the first read command in the command queue is longer since the first read command appears, and priority processing needs to be performed on the read command in the command queue, at this time, a read priority policy is forcedly adopted, so that the read command is prevented from having a longer delay, and normal operation of the host is ensured.
Optionally, a read command is preferentially executed per dispatch command queue, with the counter decremented by 1.
In the embodiment, when the read command in the command queue is from time to time, a timer is started, and after each write command is executed, when the read command exists in the command queue and the value of the timer exceeds a preset value, all the read commands in the command queue are scheduled to be executed preferentially, so that the response efficiency of the read command in the UFS chip is improved, the time delay of the read command in the command queue is reduced, and the normal operation of a host is ensured.
On the basis of the above embodiment, optionally, the command scheduling method may further include: after each write command is executed, when it is judged that a read command does not exist in the command queue, or when it is judged that a read command exists in the command queue but the value of the timer does not exceed a preset value, executing the command in the command queue by using the FIFO strategy.
Specifically, in one implementation, after the execution of the write command is completed, when it is determined that there is no read command in the command queue, that is, all the write commands in the command queue, the FIFO policy is used to execute the commands in the command queue.
In another implementation, after the execution of the write command is completed, when it is determined that the read command exists in the command queue but the value of the timer does not exceed the preset value, it is indicated that the time for waiting for the read command in the command queue to be executed is shorter, and the FIFO policy is not needed to be used for executing the command in the command queue.
It is noted that, in the embodiment of the present application, considering the feature that the duration (for example, 30 ms) of executing the write command by the UFS controller is longer than the duration (for example, 2 ms) of executing the read command, when there are a large number of write commands in the command queue, the delay of the read command located after the write command is reduced, so as to ensure that the read command can be responded quickly. In addition, since the execution speed of the read command is fast, even if all the read commands in the command queue are preferentially scheduled, too much delay is not caused to the write commands in the command queue.
Fig. 4 is another flow chart of a command scheduling method according to an embodiment of the present application. As shown in fig. 4, on the basis of the flow shown in fig. 3, after S302, after each write command is executed, when it is determined that a read command exists in the command queue and the value of the timer exceeds the preset value, the command scheduling method in this embodiment further includes:
s401, executing other commands to be processed in the command queue according to the FIFO strategy.
If the issuing of a new SCSI command in the process of preferentially executing all the read commands is not considered, after the preferentially executing of all the read commands in the dispatching command queue, the rest of the commands to be processed in the command queue are write commands, so that the rest of the commands to be processed in the command queue are executed according to the FIFO strategy.
If the issuing of a new SCSI command is considered in the process that all the read commands are executed preferentially, after all the read commands in the command queue are executed preferentially, the other pending commands in the command queue include the remaining write commands and the new SCSI commands, and the new SCSI commands include the read commands and/or the write commands, at this time, the other pending commands in the command queue are executed first according to the FIFO policy, and when the read commands appear in the command queue, S301-S302 are repeated.
In this embodiment, after all the read commands in the command queue are scheduled to be executed preferentially, other commands to be processed in the command queue are executed according to the FIFO policy, so that only the read command currently put in the command queue will be processed, and during this processing, the newly entered read command will not be scheduled preferentially, and therefore, the write command originally entered in the command queue will not be blocked by the read command that is continuously entered. When all the read commands in the command queue are executed, the FIFO strategy is switched back again, so that the write commands which enter the command queue can be executed faster, the total delay of the write commands is controlled not to be particularly long, the delay of the read commands can be reduced, and the scheduled blocking of the write commands caused by the simple adoption of the read priority strategy can be avoided, namely, the execution of the read commands and the write commands in the command queue is ensured at the same time.
Further, since the host may always issue a SCSI command, or a new SCSI command always enters in the process of executing a SCSI command in the command queue, the command scheduling method may further include: the UFS controller obtains a command to be processed sent by a host; and placing the commands to be processed into a command queue according to the sequence, and executing according to the FIFO strategy. It should be clear that, because of randomness of issuing the SCSI command, the embodiment of the present application does not limit the execution sequence of the step of the UFS controller obtaining the command to be processed sent by the host and other steps.
In some embodiments, all read commands in the dispatch command queue are preferentially executed, which may include: scheduling all read commands in the command queue to the read command queue; and sequentially executing the read commands in the read command queue according to the FIFO strategy. For each execution of a read command, the counter is decremented by 1 until the value of the counter is 0.
Optionally, after each write command is executed, when it is determined that a read command exists in the command queue and the value of the timer exceeds the preset value, before all the read commands in the command queue are scheduled to be executed preferentially, the command scheduling method may further include: and resetting or closing the timer to ensure the effectiveness of the timing function of the timer. Further, the timer is restarted from time to time in the command queue for the read command, and so on.
Next, the above-described command scheduling method is described in connection with specific examples.
Example one
The preset value is set to 40 milliseconds (ms).
Referring to fig. 5, the command scheduling method may include:
the host issues 6 write commands to the UFS chip.
Correspondingly, the UFS chip receives these 6 write commands, i.e., write command W0, write command W1, write command W2, write command W3, write command W4, and write command W5, and places them in the command queue.
And then, the UFS chip sequentially fetches the write command to execute by using the FIFO strategy.
In this process, before the UFS chip executes the write command W1 (has been fetched, and has not yet started to execute), the host issues the read command R0, the read command R1, and the write command W6 again.
The UFS chip determines that the read command in the command queue is from scratch, starts a timer, and starts timing.
The UFS chip takes 30ms to execute the write command W1. After the execution of the write command W1 is completed, the UFS chip determines that the read command R1 is present in the command queue but the timer has a value of 30ms and does not exceed a preset value (40 ms), and continues to execute the commands in the command queue using the FIFO policy.
The UFS chip takes 20ms to execute the write command W2. After the execution of the write command W2 is completed, the UFS chip determines that the read command R1 exists in the command queue, but the timer has a value of 50ms and exceeds a preset value (40 ms), and then all the read commands in the command queue are scheduled to be executed preferentially, that is, the read command R0 and the read command R1 are sequentially taken out from the command queue and executed, and the timer is cleared or closed.
After all the read commands are executed, the UFS chip switches back to the FIFO strategy, and sequentially fetches and executes the write command W3, the write command W4, the write command W5 and the write command W6 in the command queue.
Example two
The preset value is set to 40ms.
The host issues 31 write commands to the UFS chip.
Correspondingly, the UFS chip receives these 31 write commands, i.e., write command W0, write command W1, write command W2, write command W3, write commands W4, … …, write command W30, and places them in the command queue.
And then, the UFS chip sequentially fetches the write command to execute by using the FIFO strategy.
In this process, before the UFS chip executes the write command W0 (it has been fetched and has not yet started to execute), the host issues the read command R0 again. At this time, the UFS chip determines that the read command in the command queue is from scratch, starts a timer, and starts timing.
The UFS chip takes 25ms to execute the write command W0. After the execution of the write command W0 is completed, the UFS chip determines that the read command R0 exists in the command queue but the timer has a value of 25ms and does not exceed a preset value (40 ms), and continues to execute the commands in the command queue by using the FIFO policy.
Before the UFS chip executes the write command W1 (it has been fetched and has not yet started to execute), the host issues a read command R1 again.
The UFS chip takes 20ms to execute the write command W1. After the execution of the write command W1 is completed, the UFS chip determines that the read command R0 and the read command R1 exist in the command queue, but the timer has a value of 45ms and exceeds a preset value (40 ms), and then all the read commands in the command queue are scheduled to be executed preferentially, that is, the read command R0 and the read command R1 are sequentially taken out from the command queue and executed, and the timer is cleared or closed.
In the process of executing the read command R0 and the read command R1, the host issues the read command R2 again, and the UFS chip places the read command R2 in the command queue. At this time, the UFS chip determines that the read command in the command queue is from scratch, starts a timer, and restarts the timer.
After the read command R1 is executed, the UFS chip switches back to FIFO policy, fetches and executes the write command W2 in the command queue. At this point, the host issues a read command R3 again.
The UFS chip takes 10ms to execute the write command W2. After the execution of the write command W2 is completed, the UFS chip determines that the read command R2 and the read command R3 exist in the command queue, but the value of the timer is 10ms, and does not exceed the preset value (40 ms), and then continues to execute the commands in the command queue by using the FIFO strategy.
The UFS chip takes 20ms to execute the write command W3. After the execution of the write command W3 is completed, the UFS chip determines that the read command R2 and the read command R3 exist in the command queue, but the timer has a value of 30ms and does not exceed a preset value (40 ms), and then continues to execute the commands in the command queue by using the FIFO strategy.
The UFS chip takes 10ms to execute the write command W4. After the execution of the write command W4 is completed, the UFS chip determines that the read command R2 and the read command R3 exist in the command queue, but the timer has a value of 40ms and is equal to a preset value (40 ms), and then all the read commands in the command queue are scheduled to be executed preferentially, that is, the read command R2 and the read command R3 are sequentially taken out from the command queue and executed, and the timer is cleared or closed.
After the read command R0 and the read command R1 are executed, the UFS chip switches back to the FIFO policy, and sequentially fetches and executes the write command W5 through the write command W30 in the command queue.
This embodiment shows that when all read commands are scheduled to be executed preferentially, the newly received read command is not included in all read commands currently scheduled preferentially, so as to ensure that the phenomenon that the write command is blocked too long and the write command times out due to continuous read command priority scheduling does not occur.
The command scheduling method provided by the embodiment of the application is described in detail above, and the command scheduling device provided by the embodiment of the application is described below.
Fig. 6 is a schematic structural diagram of a command scheduling device according to an embodiment of the present application. The embodiment of the application provides a command scheduling device which is used for scheduling commands in a command queue. The command scheduling means may be implemented in hardware and/or software. The command scheduler may be firmware of the UFS chip, or the command scheduler may be a UFS controller, for example.
Referring to fig. 6, a command scheduling apparatus 60 in an embodiment of the present application includes: a processing module 61 and a storage module 62. The processing module 61, when executing the computer program stored in the storage module 62, causes the processing module 61 to implement the steps of:
starting a timer when the read command in the command queue is from scratch, wherein the timer counts until the timer is cleared;
after each write command is executed, when the read command exists in the command queue and the value of the timer exceeds the preset value, all the read commands in the command queue are scheduled to be executed preferentially.
The command scheduling device of the present embodiment may be used to execute the steps of the command scheduling method provided in the foregoing embodiments, and the specific implementation principle and technical effects are similar, and are not repeated herein.
Optionally, when the processing module 61 executes the above-mentioned computer program, the processing module 61 is further caused to implement the steps of:
after each write command is executed, when the read command is judged to be not in the command queue, or when the read command is judged to be in the command queue but the value of the timer does not exceed the preset value, executing the command in the command queue by using the FIFO strategy.
Wherein the duration of executing the write command is greater than the duration of executing the read command.
In some embodiments, the processing module 61 is further caused to implement the following steps when the processing module 61 executes the above-mentioned computer program: after all read commands in the dispatch command queue are preferentially executed, other pending commands in the command queue are executed according to the FIFO policy.
Further, the processing module 61 may also be configured to: acquiring a command to be processed sent by a host; and placing the commands to be processed into a command queue according to the sequence, and executing according to the FIFO strategy.
Still further, the processing module 61 may be further configured to: after each write command is executed, when the read command exists in the command queue and the value of the timer exceeds the preset value, the timer is cleared or closed before all the read commands in the dispatch command queue are executed preferentially.
Fig. 7 is another schematic structural diagram of a command scheduling device according to an embodiment of the present application. The command scheduling means is for scheduling commands located in the command queue. Referring to fig. 7, the command scheduler 70 includes: memory 71 and processor 72, and a computer program (not shown) stored on memory 71 for execution by the processor. The computer program, when read and executed by the processor 72, causes the processor 72 to perform the steps of any of the method embodiments described above.
The command scheduling means may be a UFS chip or a UFS controller within a UFS chip. The processor 72 here may be embodied as a CPU in a UFS controller.
The detailed description of each module or unit in the command scheduling device and the technical effects brought by each module or unit after executing the method steps of any method embodiment of the present application may refer to the related description in the method embodiment of the present application, and are not repeated herein.
The embodiment of the application provides a UFS chip, which comprises: UFS controller and Nand Flash grain, for example, as shown in fig. 1. The UFS controller includes a processor and a memory. The memory has stored thereon a computer program executable by the processor; the computer program, when read and executed by a processor, causes the processor to perform any of the methods described above.
Alternatively, the memory may comprise at least one of ROM and RAM.
Optionally, the UFS chip may further include: UFS interfaces, nand interfaces, and other related hardware modules.
An embodiment of the present application provides an electronic device, including: UFS chips as described above. By way of example, the electronic device may be a smart phone, tablet, personal digital assistant (Personal Digital Assistant, PDA), wearable device, or the like.
Embodiments of the present application provide a computer readable storage medium storing a computer program comprising at least one piece of code executable by a processor to implement a method as described in any of the above.
The present application provides a program or a computer program product comprising the program for performing any of the above methods when executed by a UFS controller of a UFS chip.
It should be appreciated that the processors referred to in embodiments of the present application may be central processing units (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
It should also be understood that the memory referred to in embodiments of the present application may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be a ROM, a Programmable ROM (PROM), an Erasable Programmable EPROM (EPROM), an Electrically Erasable EPROM (EEPROM), or a flash memory. The volatile memory may be RAM, which acts as external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (Double Data Rate SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and Direct RAM (DR RAM).
It should be noted that the memory described herein is intended to comprise, without being limited to, these and any other suitable types of memory.
In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device or a terminal device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk, etc.
The relevant parts among the method embodiments of the application can be mutually referred to; the apparatus provided by each apparatus embodiment is configured to perform the method provided by the corresponding method embodiment, so each apparatus embodiment may be understood with reference to the relevant part of the relevant method embodiment.
The device configuration diagrams presented in the device embodiments of the present application only show a simplified design of the corresponding device. In practical applications, the apparatus may include any number of transmitters, receivers, processors, memories, etc. to implement the functions or operations performed by the apparatus in the embodiments of the present application, and all apparatuses that may implement the present application are within the scope of the present application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
The word "if" or "if" as used herein may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to detection", depending on the context. Similarly, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determination" or "when detected (stated condition or event)" or "in response to detection (stated condition or event), depending on the context.
Those of ordinary skill in the art will appreciate that all or some of the steps in implementing the methods of the above embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a readable storage medium of a device, where the program includes all or some of the steps when executed, where the storage medium includes, for example: FLASH, EEPROM, etc.
While the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be appreciated that various embodiments of the application may be practiced otherwise than as specifically described, and that no limitations are intended to the scope of the application except as may be modified or practiced in any way within the spirit and principles of the application.
Claims (8)
1. A method for scheduling commands located in a command queue, comprising:
starting a timer when the read command in the command queue is from scratch, wherein the timer counts up until the timer is cleared;
after each write command is executed, when the read command exists in the command queue and the value of the timer exceeds a preset value, clearing or closing the timer, and dispatching all the read commands in the command queue to be executed preferentially; wherein, the duration of executing the write command is longer than the duration of executing the read command;
after said scheduling all of said read commands in said command queue to be executed preferentially, said method further comprises:
executing other commands to be processed in the command queue according to a first-in first-out FIFO strategy; the commands to be processed comprise remaining write commands and/or newly received commands, wherein the newly received commands comprise read commands and/or write commands; the newly received command is a newly received command in the process that all read commands are preferentially executed;
if the newly received command includes a read command, starting a timer from the absence of the read command in the command queue, and restarting the timing.
2. The method according to claim 1, wherein the method further comprises:
after each write command is executed, when the read command is judged to be absent from the command queue, or when the read command is judged to be present from the command queue but the value of the timer does not exceed the preset value, executing the command in the command queue by using a first-in first-out FIFO strategy.
3. The method according to claim 1 or 2, characterized in that the method further comprises:
acquiring a command to be processed sent by a host;
and placing the commands to be processed into the command queue according to the sequence, and executing according to a first-in first-out FIFO strategy.
4. A command scheduling apparatus for scheduling commands located in a command queue, comprising: a memory and a processor, a computer program stored on the memory for execution by the processor;
the computer program, when read and executed by the processor, causes the processor to:
starting a timer when the read command in the command queue is from scratch, wherein the timer counts up until the timer is cleared;
after each write command is executed, when the read command exists in the command queue and the value of the timer exceeds a preset value, clearing or closing the timer, and dispatching all the read commands in the command queue to be executed preferentially; wherein, the duration of executing the write command is longer than the duration of executing the read command;
the computer program, when read and executed by the processor, causes the processor to further perform the operations of:
after all the read commands in the command queue are scheduled to be executed preferentially, executing other commands to be processed in the command queue according to a first-in first-out FIFO strategy; the commands to be processed comprise remaining write commands and/or newly received commands, wherein the newly received commands comprise read commands and/or write commands; the newly received command is a newly received command in the process that all read commands are preferentially executed;
if the newly received command includes a read command, starting a timer from the absence of the read command in the command queue, and restarting the timing.
5. The apparatus of claim 4, wherein the computer program, when read and executed by the processor, causes the processor to further perform the operations of:
after each write command is executed, when the read command is judged to be absent from the command queue, or when the read command is judged to be present from the command queue but the value of the timer does not exceed the preset value, executing the command in the command queue by using a first-in first-out FIFO strategy.
6. A universal flash memory storage UFS chip, comprising: UFS controller and Nand Flash particles; wherein the UFS controller includes a processor and a memory;
the memory has stored thereon a computer program executable by the processor;
the computer program, when read and executed by the processor, causes the processor to perform the method of any one of claims 1 to 3.
7. An electronic device, comprising: the UFS chip of claim 6.
8. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program comprising at least one piece of code executable by a processor for implementing the method according to any one of claims 1 to 3.
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| PCT/CN2018/110263 WO2020077495A1 (en) | 2018-10-15 | 2018-10-15 | Command scheduling method and device and storage medium |
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| CN113778317A (en) * | 2020-06-10 | 2021-12-10 | 慧荣科技股份有限公司 | Computer readable storage medium, method and device for scheduling host commands |
| CN115469816B (en) * | 2022-11-02 | 2024-01-30 | 摩尔线程智能科技(北京)有限责任公司 | Method, device, equipment and storage medium for switching reading and writing of memory |
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| CN106484315A (en) * | 2015-09-01 | 2017-03-08 | 慧荣科技股份有限公司 | Method for scheduling read and write commands and apparatus using the same |
| CN107273045A (en) * | 2017-05-24 | 2017-10-20 | 记忆科技(深圳)有限公司 | A kind of method for improving solid state hard disc mixing readwrite performance |
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| US8082396B2 (en) * | 2005-04-28 | 2011-12-20 | International Business Machines Corporation | Selecting a command to send to memory |
| US9679658B2 (en) * | 2015-06-26 | 2017-06-13 | Intel Corporation | Method and apparatus for reducing read latency for a block erasable non-volatile memory |
| US10025531B2 (en) * | 2015-09-10 | 2018-07-17 | HoneycombData Inc. | Reducing read command latency in storage devices |
| CN106708441B (en) * | 2016-12-29 | 2019-06-21 | 至誉科技（武汉）有限公司 | A kind of operating method for reducing solid-state storage read latency |
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| CN106484315A (en) * | 2015-09-01 | 2017-03-08 | 慧荣科技股份有限公司 | Method for scheduling read and write commands and apparatus using the same |
| CN107273045A (en) * | 2017-05-24 | 2017-10-20 | 记忆科技(深圳)有限公司 | A kind of method for improving solid state hard disc mixing readwrite performance |
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