CN112838760A

CN112838760A - Power converter

Info

Publication number: CN112838760A
Application number: CN202110224392.XA
Authority: CN
Inventors: D·朱利亚诺
Original assignee: PASSION
Current assignee: Murata Manufacturing Co Ltd
Priority date: 2016-05-09
Filing date: 2017-05-09
Publication date: 2021-05-25
Also published as: DE112017002374T5; WO2017196826A1; CN109478845A; CN109478845B

Abstract

An apparatus for power conversion includes a conversion stage for converting a first voltage to a second voltage. The conversion stage includes a switching network, a filter, and a controller. The filter is configured to connect the transform stage to a regulator. The controller controls the switching network.

Description

Power converter

The application is a divisional application of Chinese patent application (Chinese application number 201780042383.0 entering China national phase) with international application date of 2017, 5, 9 and 2017, international application number of PCT/US2017/031726 and invention name of 'power converter'.

Technical Field

The present invention relates to power supplies, and in particular to power converters.

Background

Many power converters include a switch and one or more capacitors, for example, for powering portable electronic devices and consumer electronics. Switched mode power converters regulate the output voltage or current by switching the energy storage element (i.e., inductor and capacitor) into different electrical configurations using a switching network.

Switched capacitor converters are switch mode power converters that primarily use capacitors to transfer energy. These converters transfer energy from the input to the output by using switches to cycle the capacitor network through different topological states. Common converters of this type (known as "charge pumps") are commonly used to generate high voltages in flash memory and other reprogrammable memory. Charge pumps are also used in connection with overcoming the brute force of atomic nuclei to transform one element into another.

In a switched capacitor converter, the number of capacitors and switches increases with increasing conversion ratio. The switches in the switching network are typically active devices implemented with transistors. The switching network may be integrated on a single or multiple monolithic semiconductor substrates or formed using discrete devices. Furthermore, since each switch in a power converter typically carries high currents, each switch may consist of many smaller switches connected in parallel.

Disclosure of Invention

A typical DC-DC converter performs voltage conversion and output regulation. This is typically done in a single stage converter such as a buck converter. However, these two functions can be split into two specific levels, namely: a conversion stage such as a switching network, and a separate regulation stage such as a regulation circuit. The converter stage converts one voltage to another, while the regulation stage ensures that the voltage and/or current output of the converter stage maintains the desired characteristics.

In case the transformation stage and the adjustment stage are close together, a direct connection is possible. In other cases, however, the conditioning stage may be remote from the transform stage. In these cases, it is useful to filter the output of the transform stage to reduce losses.

In one aspect, the invention features a conversion stage for converting a first voltage to a second voltage. Such a conversion stage comprises a switching network, a filter and a controller. The filter is configured to connect the conversion stage to the regulator, and the controller controls the switching network.

In some embodiments, the filter comprises an LC filter.

In other embodiments, the filter includes an inductance that maintains a peak-to-peak voltage ripple when operating at a particular switching frequency and supports an inductor current delivered into the load, which defines an average inductor current. In these embodiments, also included are embodiments where the inductance is selected by multiplying 13/24 by the quotient of the peak-to-peak voltage ripple divided by the product of the average inductor current and the switching frequency.

Some embodiments include a conditioning circuit.

In an embodiment, further comprising an embodiment wherein the filter is configured to connect the conversion stage to more than one regulator.

Still other embodiments include a plurality of conditioning circuits, wherein a filter connects the converter to all of the regulators.

In embodiments, embodiments are also included in which the conversion stage comprises a plurality of switching networks. In these embodiments, the filter connects all of the switching networks in the switching network to the conditioning circuit.

Other embodiments include embodiments in which the conversion stage comprises a plurality of cells connected in series. Each cell includes a switching network in series with a filter.

In case the transformation stage and the adjustment stage are close together, a direct connection is possible. However, in other cases, the conditioning stage may be remote from the transform stage. In these cases, it is useful to filter the output of the transform stage to reduce losses.

In one aspect, the invention includes an apparatus having a phase switch and a stacked switch for operating a switched capacitor converter. The phase switch and the stacked switch are on the respective first die and second die.

Some embodiments include a first controller for controlling the switches on the first die, and a second controller for controlling the switches on the second die. The inter-controller engagement provides a link between the first controller and the second controller to allow operation of the first switch to be at least partially dependent on operation of the second switch and to allow operation of the second switch to be at least partially dependent on operation of the first switch. In these embodiments, embodiments are also included in which the first controller extends between the first die and the second die, the second controller extends between the first die and the second die, and the inter-controller junction. In embodiments, embodiments are also included that include a third die and a fourth die. In these embodiments, the first controller is on the third die, the second controller is on the fourth die, and the inter-controller junction extends between the third die and the fourth die.

In some embodiments, the switched capacitor converter is a two-phase converter. Some of these embodiments have a third die and a fourth die. The stacked switch includes a first set and a second set, each associated with one of the two phases. The first stacked switch group is on the second die and the second stacked switch group is on the fourth die. Meanwhile, the phase switches include a first phase switch set and a second phase switch set, each associated with one of the two phases. The first phase switch bank is on a first die and the second phase switch bank is on a third die.

In embodiments, embodiments are also included that include a charge transfer capacitor connected to the stacked switch and the phase switch. In these embodiments, embodiments are also included having a third die with integrated charge transfer capacitors. In these embodiments, also included are embodiments in which the charge transfer capacitor is a discrete capacitor connected to the first die and the second die. In some of these embodiments, the first die and the second die are connected via an inter-die joint having a length corresponding to a distance between positive and negative terminals of the charge transfer capacitor. In embodiments, also included are embodiments having an inter-die joint for connecting a first die and a second die, wherein the first die and the second die have a first terminal for connecting to a positive terminal of a charge transfer capacitor, and a second terminal for connecting to a negative terminal of the charge transfer capacitor, wherein the first terminal and the second terminal are configured on opposite ends of the inter-die joint, and wherein the charge transfer capacitor is oriented such that: the positive terminal of the charge transfer capacitor is closer to the first terminal than the distance of the positive terminal of the charge transfer capacitor from the second terminal, and the negative terminal of the charge transfer capacitor is closer to the second terminal than the distance of the negative terminal of the charge transfer capacitor from the first terminal. In embodiments, embodiments are also included in which the inter-die joint has a first region and a second region such that the first region carries more current than the second region during operation. In these embodiments, the first region is wider than the second region.

In some embodiments, the charge transfer capacitor has a capacitance that is a function of the voltage applied across the charge transfer capacitor. In operation, the charge transfer capacitors maintain different maximum voltages. The charge transfer capacitors are selected such that they all have the same capacitance at their respective maximum voltages.

Some embodiments include an inter-die joint connecting a first die and a second die. The first die and the second die are located on different planes as a result of the fold in the inter-die joint. Features of other embodiments include coplanar first and second dies.

Embodiments include those in which the switched capacitor converter is a multi-phase converter, and the apparatus has a third die. In these embodiments, the phase switches include a first set of phase switches associated with the first phase and a second set of phase switches associated with the second phase, where the first set is on the first die and the second set is on the second die. In these embodiments, embodiments are included having a first charge transfer capacitor bank and a second charge transfer capacitor bank, where the first charge transfer capacitor bank is connected between the first die and the second die, and the second charge transfer capacitor bank is connected between the third die and the second die.

Other embodiments include a substrate and a charge transfer capacitor. In these embodiments, a substrate supports a charge transfer capacitor, a first die, and a second die. In these embodiments, embodiments are also included in which the device sides of the first and second dies face the substrate, and conductive bumps between the device sides and the substrate provide electrical communication between the dies and the charge transfer capacitors. In these embodiments, embodiments are also included having a package, wherein the first die and the second die are in the package and are oriented such that they are coplanar or non-coplanar.

Other embodiments include a substrate, a package, a third die, and a charge transfer capacitor. In these embodiments, the charge transfer capacitor is integrated into a third die, the substrate supports a package, the package includes a first die, a second die, and a third die, and the first die, the second die, and the third die are distributed in different layers of the package. Among these embodiments are embodiments in which the package includes a first layer and a second layer. In these embodiments, the first die and the second die are in a first tier, and the third die is in a second tier. In these embodiments, embodiments are also included in which the package includes a first layer and a second layer. In these embodiments, the first die and the third die are in a first tier, and the second die is in a second tier. In these embodiments, embodiments are also included in which the package includes a first layer, a second layer, and a third layer. In these embodiments, each layer includes at most one die. In some of these embodiments, the second tier is between the first tier and the third tier, and the third die is in the second tier.

Some embodiments include a substrate supporting the package. The package has an upper layer and a lower layer, wherein the lower layer is closer to the substrate than the upper layer. The lower layer includes a die and the upper layer includes a charge transfer capacitor. The inductor is on the substrate outside the package. In these embodiments, the device side including the die faces the substrate. The apparatus also includes a first interconnect layer, a second interconnect layer, and a conductive bump. A first interconnect layer connects the charge transfer capacitors to the die, and a second interconnect layer connects the die to the charge transfer capacitors and the conductive bumps. The conductive bumps connect the package with the inductor.

In these embodiments, embodiments are also included in which the device side of the die faces away from the substrate. These embodiments include a heat spreader, thermally conductive bumps, a first interconnect layer, a second interconnect layer, and electrically conductive bumps. A first interconnect layer connects the charge transfer capacitor to the die. A second interconnect layer connects the die to the charge transfer capacitors and the conductive bumps. The conductive bumps connect the package with the inductor. In these embodiments, the heat spreader faces the substrate, and the thermally conductive bumps connect the heat spreader to the substrate. These thermally conductive bumps carry heat only. They are electrically disconnected from the circuit.

In these embodiments, embodiments are also included in which the device side of the die faces away from the substrate. In these embodiments, a first interconnect layer connects the charge transfer capacitor to the die, and a second interconnect layer connects the die to the charge transfer capacitor and the conductive pad. The conductive pads connect the package with the inductor. The conductive pads connect the heat spreader facing the substrate to the substrate. The thermal pad carries heat only. The thermal pad is electrically isolated from the inductor, the charge transfer capacitor, and the die.

Other embodiments also include a substrate for supporting a package having an upper layer and a lower layer, wherein the lower layer is closer to the substrate than the upper layer. The inductor is in a package. The lower layer includes a die and the upper layer includes a charge transfer capacitor. In these embodiments, embodiments in which the inductor is configured in an upper layer are included. In these embodiments, also included are embodiments in which the conductive traces surrounding the inductor core in the layer form an inductor.

In the foregoing embodiments, the device including the chip faces away from the substrate. In these embodiments, the thermally conductive bumps connect the heat spreader to the substrate. These thermally conductive bumps carry heat only. The thermally conductive bumps are electrically isolated from the die, the charge transfer capacitor, and the inductor.

Still other embodiments include a regulator switch in the first die.

These and other features of the present invention will be apparent from the following detailed description and the accompanying drawings.

Drawings

Fig. 1 shows a power converter with separable conversion and regulation stages;

FIG. 2 shows the same power converter as shown in FIG. 1, but with an isolated converter stage;

FIGS. 3-10 illustrate different ways of connecting the conversion stage and the conditioning stage;

FIG. 11 shows a DC-DC converter with separate regulating circuit and switching network;

fig. 12 shows a power converter with a filter between the switching network and the regulation stage;

FIG. 13 illustrates the power converter of FIG. 12, but without a regulation stage;

FIG. 14 explicitly shows the control circuitry associated with the converter shown in FIG. 11;

FIG. 15 shows details of the control circuit shown in FIG. 14;

FIG. 16 shows signals present during operation of the control circuit of FIG. 15;

FIG. 17 is a close-up of the four signals from FIG. 12 showing dead time intervals;

fig. 18 shows details of the switch layout in a converter similar to that shown in fig. 1;

figures 19 and 20 show the dependence of the switching period and the peak-to-peak ripple as a function of the output load current in two embodiments of the control circuit as shown in figure 14;

fig. 21 shows a multiphase converter similar to that shown in fig. 14;

FIGS. 22 and 23 show signals present during operation of the control circuit of FIG. 21;

FIG. 24 shows another power converter similar to that shown in FIG. 14, but having one regulator and multiple switching networks;

FIG. 25 shows another power converter similar to that shown in FIG. 14, but having one switching network and multiple regulators;

FIG. 26 shows a power converter similar to that shown in FIG. 25, but with a filter between the switching network and the regulator;

FIG. 27 shows a power converter similar to that shown in FIG. 24, but with a filter between the switching network and the regulator;

FIG. 28 shows a bi-directional version of FIG. 11;

FIGS. 29-30 illustrate an alternately configured DC-DC converter having a regulating circuit and a switching network;

FIG. 31 shows a DC-DC converter like the DC-DC converter shown in FIG. 30 with a controller;

fig. 32 shows another configuration of the DC-DC converter;

FIG. 33 illustrates a particular implementation of the power converter shown in FIG. 32;

FIG. 34 shows an embodiment with multiple adjustment circuits;

FIG. 35 shows an RC circuit;

fig. 36 shows a model of a switched capacitor DC-DC converter;

FIG. 37 shows the isolation variation of FIG. 36;

FIG. 38 shows the output resistance of a switched capacitor network as a function of switching frequency;

FIGS. 39-40 show series-parallel SC converters operating in a charge phase and a discharge phase, respectively;

FIG. 41 shows a pump series symmetric cascade multiplier with diodes;

FIG. 42 shows a pump parallel symmetric cascade multiplier with diodes;

FIG. 43 shows charge pump signals;

FIG. 44 shows a two-phase symmetric pump series cascade multiplier with switches;

FIG. 45 shows a two-phase symmetric pump parallel cascade multiplier with switches;

FIG. 46 shows four cascade multipliers and corresponding half-wave versions;

FIG. 47 shows the circuit of FIG. 35 with an auxiliary converter for reducing losses associated with charging the capacitor;

FIG. 48 illustrates an implementation of the circuit of FIG. 47;

FIG. 49 shows a cascade multiplier with clocked current sources;

fig. 50 shows the output impedance of a switched capacitor converter as a function of frequency;

FIGS. 51, 52 and 53 illustrate clocked current sources;

FIG. 54 shows a cascade multiplier with the clocked current sources of FIG. 52;

FIG. 55 shows an embodiment of the circuit shown in FIG. 54;

FIG. 56 shows current and voltage at selected locations in the circuit of FIG. 55;

FIG. 57 illustrates a particular implementation of the DC-DC converter shown in FIG. 28 with a full-wave adiabatic charge switching network;

fig. 58 shows the DC-DC converter shown in fig. 54 during phase a;

fig. 59 shows the DC-DC converter shown in fig. 54 during phase B;

FIG. 60 illustrates various waveforms associated with a 4:1 adiabatic charge converter;

FIG. 61 illustrates adiabatic charging of series connected stages;

FIG. 62 illustrates a particular implementation of the power converter shown in FIG. 61;

FIG. 63 illustrates adiabatic charging of series connected stages with filters between stages;

FIG. 64 illustrates a particular implementation of the power converter shown in FIG. 63;

FIG. 65 illustrates an AC-DC power converter architecture;

FIG. 66 shows an AC voltage rectified using a reconfigured switched capacitor stage;

fig. 67 shows an embodiment of the AC-DC power converter architecture of fig. 65 including an AC switching network;

fig. 68 illustrates a particular implementation of the AC-DC converter shown in fig. 67;

FIGS. 69-70 show the AC-DC converter of FIG. 68 during the positive and negative portions of the AC cycle, respectively;

FIG. 71 shows an AC-DC power converter architecture with power factor correction;

FIG. 72 shows a converter with an isolation controller;

FIG. 73 shows an alternative architecture of the converter in which the switching network of FIG. 72 is loaded by an LC filter;

FIG. 74 shows a converter with control signals for the regulating circuit isolated from control signals for the switching network;

FIG. 75 shows the configuration of FIG. 29 with the isolation controller shown in FIG. 74;

FIG. 76 shows the configuration of FIG. 32 with the isolation controller shown in FIG. 74;

FIG. 77 illustrates an implementation of the rectifier shown in FIG. 65;

FIG. 78 illustrates an alternative implementation of the rectifier shown in FIG. 65;

FIG. 79 illustrates an EMI filter in the rectifier shown in FIGS. 77 and 78;

fig. 80 illustrates an alternative EMI filter in the rectifier shown in fig. 77 and 78;

FIG. 81 illustrates an AC bridge for the embodiment shown in FIGS. 77 and 78;

figure 82 shows one conversion stage driving two parallel regulation stages;

figure 83 shows a conversion stage providing a filtered output to a parallel regulation stage;

FIGS. 84 and 85 illustrate an implementation of the DC-DC converter shown in FIG. 28;

fig. 86 and 87 illustrate an implementation of the DC-DC converter shown in fig. 30;

FIGS. 88 and 89 illustrate an implementation of the DC-DC converter shown in FIG. 29;

fig. 90 and 91 illustrate an implementation of the DC-DC converter shown in fig. 32;

FIG. 92 illustrates a switching network implemented as a stack of layers;

FIGS. 93-96 are cross-sections of the stack of FIG. 92 with a different order of passive and active layers;

97-100 illustrate active and passive device facets for different positions of the two layer stack shown in FIG. 93;

101-104 illustrate active and passive device facets in different positions for the two layer stack shown in FIG. 94;

FIG. 105 illustrates the implementation of FIG. 93 with a passive device layer having planar capacitors;

fig. 106 illustrates the implementation of fig. 93 with a passive device layer having trench capacitors;

FIG. 107 shows the implementation of FIG. 105 with wafer-to-wafer bonding instead of die-to-die bonding;

FIG. 108 shows the implementation of FIG. 107, but with the device side of the active layer being above the active layer rather than below it;

fig. 109 shows three partitioned current paths of a switching network;

fig. 110 shows an active layer with 8 switches superimposed on a passive layer with 8 capacitors underneath it;

FIG. 111 shows one of the switches in FIG. 110 that has been partitioned into 9 partitions;

FIG. 112 shows switches and capacitors switched in segments but not partitioned;

FIG. 113 shows partitioned switches and capacitors;

FIG. 114 shows a capacitor partitioned into two dimensions;

FIG. 115 is a functional block diagram of one embodiment of the switching network shown in FIGS. 13 and 12;

FIG. 116 shows a representative diagram of the switching network shown in FIG. 115;

FIG. 117 shows a specific terminal layout for implementation of the switching network shown in FIG. 115;

FIG. 118 is a functional block diagram of another embodiment of the switching network shown in FIGS. 13 and 12;

FIG. 119 illustrates an exemplary circuit of the switching network shown in FIG. 118;

FIG. 120 illustrates a particular terminal layout used in the implementation of the switching network shown in FIG. 118;

fig. 121 shows a terminal layout for the phase die (phase-die) in fig. 120, with the position of the phase switch in fig. 119 being explicitly shown in fig. 121;

FIG. 122 is a functional block diagram of another embodiment of the switching network shown in FIGS. 13 and 12, but including switches for the regulators to which the switching network is to be connected;

FIG. 123 illustrates a substrate for supporting components implementing a switching network;

fig. 124 shows the phase die and stacked die of fig. 123 within the same package;

fig. 125 shows stacked phase and stacked dies;

FIG. 126 shows the circuit of FIG. 124, but with the charge transfer capacitor now on its own capacitor die and included on a layer of the charge transfer capacitor itself within the package;

fig. 127 shows the circuit of fig. 124, but with the charge transfer capacitor now on its own capacitor die, included in the package, and occupying the same layer as the phase die;

figure 128 shows a package with a charge transfer capacitor die sandwiched between a phase die and a stacked die; and

129-133 illustrate embodiments of circuits that also include inductors.

Detailed Description

Some power converters perform these functions by mixing both regulation and conversion with a limited number of circuit components into a single stage. As a result, certain components are used for both adjustment and transformation. Sometimes, the regulation stage is referred to as a regulation circuit and the transformation stage is referred to as a switching network. As used herein, these terms mean the same thing.

Fig. 1 shows a modular multilevel power converter that separates the conversion and regulation functions of the converter. These functions are no longer implemented together as they would in a single-stage converter design. As a result, in a multi-stage power converter, as shown in fig. 1, the transformation stage and the regulation stage can be optimized for a specific function. The transformation stage and the conditioning stage may be considered as separate entities or as coupled entities.

In the power converter of fig. 1, the converter stage receives an input voltage V across its two input terminals_INAnd outputs an intermediate voltage V across its two output terminals at a fixed voltage conversion ratio_X. Thus, the intermediate voltage V_XResponsive to input voltage V_INMay vary. Thus, a conversion stage is considered "variable" if the voltage conversion ratio can be changed. However, the transform stages are not required to be "variable".

In the particular embodiment shown in fig. 1, there is an electrical connection between the negative input terminal of the converter stage and its negative output terminal. In this configuration, the transform stage is said to be "non-isolated". In contrast, in the embodiment shown in fig. 2, there is no such connection between the negative input of the converter stage and its negative output. An example of such a conversion stage is shown in fig. 37, where the voltage conversion ratio is N₁:N₂。

Generally, two functional components of a circuit or system are said to be isolated in a galvanic sense if there is no direct conductive path between the two components, but energy and information can still be communicated between the two components. This communication of energy and information can be performed in various ways without the need for actual current. Examples include communication via waves, whether the waves are electromagnetic, mechanical, or acoustic waves. In this context, electromagnetic waves include waves in the visible range, as well as waves just outside the visible range. Such communication may also be achieved by static or quasi-static electric or magnetic fields, capacitively, inductively, or by mechanical means.

Galvanic isolation is particularly useful for the case where the two functional components have grounds of different potentials. The occurrence of ground loops can be substantially precluded by galvanic isolation of the components. It also reduces the likelihood that the current will reach ground through unintended paths such as the human body.

Conversion stage for efficiently providing an intermediate voltage V_XThe intermediate voltage V_XAnd an input voltage V_INIs different and at a specific input voltage V_INMuch less. In practice, the intermediate voltage V is changed if the input or output of the converter stage changes_XChanges occur during operation. These variations need to be corrected to achieve the desired output voltage V_O. For this purpose, a regulating stage is necessary. As shown in fig. 1 and 28, the regulating stage receives an intermediate voltage V across its input terminals_XAnd provides a regulated voltage V across its output terminals_O。

The architecture shown in fig. 1 is flexible enough to allow designs with different requirements. For example, if magnetic isolation is desired, a magnetically isolated flyback converter may be used. Designs requiring multiple regulated output voltages can be implemented by using two separate regulation stages and a single conversion stage.

The architecture shown in fig. 1 actually creates a modular architecture of the power converter, where the basic building blocks can be mixed and matched in various ways to achieve specific goals.

FIGS. 3-10 are block diagrams illustrating different ways of arranging the conversion stage and the conditioning stage relative to the source or load. The fact that these approaches can even be fully represented as block diagrams stems from the modularity of the architecture. Such modularity is not present in conventional single-stage converters. In such converters, the functions of regulation and transformation are intimately mixed together, so that two separate circuits cannot be extracted and one circuit is said to perform regulation while the other circuit performs transformation. Instead, in a conventional converter, if an attempt is made to extract two circuits (one of which is a regulator and the other of which is a transformer), the usual result is that both circuits do not operate.

Fig. 3 shows a general architecture of a pair of conversion stages sandwiching a regulation stage. Each conversion stage comprises one or more switched capacitor networks. Likewise, each regulation stage comprises one or more regulation circuits. There may also be more than one source and more than one load. The double-headed arrows in fig. 3 and other figures represent bi-directional power flow.

Fig. 4 shows a source regulation configuration for power flow from a source to a conversion stage. The conversion stage then provides power to the regulation stage, which then delivers the power to the load. Thus, in this configuration, the load ultimately receives power from the regulation stage.

In contrast, fig. 5 shows a load regulation configuration. In a load regulation configuration, power flows from a source to a regulation stage, which then regulates and delivers the power to a conversion stage. In this embodiment, the load receives power directly from the conversion stage, rather than directly from the regulation stage.

FIG. 6 shows the same reverse source regulation configuration as shown in FIG. 4, but with power flowing in the opposite direction.

Fig. 7 shows the same reverse load regulation configuration as shown in fig. 5, but with power flowing in the other direction.

In the embodiment shown in fig. 8 and 9, two transform stages encase the conditioning stage. Fig. 8 and 9 are distinguished by the direction of the current flow. Fig. 8 shows a source/load regulation configuration in which power flows from a source to a load via a first conversion stage, a regulation stage and a second conversion stage, and fig. 9 shows a reverse source/load regulation configuration in which power flows from a load to a source via a first conversion stage, a regulation stage and a second conversion stage.

In another embodiment shown in fig. 10, multiple regulating circuits rely on the same switched capacitor converter. Note that of the three power supply paths, the first and second power supply paths are in a load regulation configuration, while the third power supply path is in a source/load regulation configuration. The embodiment with multiple regulating circuits is particularly useful because it enables different output voltages to be supplied to different loads.

Fig. 11 shows a power converter 10 assembled by combining two modules using the principles shown in fig. 1. The illustrated power converter 10 includes a switching network 12A, a voltage source 14, a conditioning circuit 16A, and an inter-module link 11A for connecting an output of the switching network 12A to an input of the conditioning circuit 16A. A load 18A is connected to the output of the regulating circuit 16A. Power flows between voltage source 14 and load 18A in the direction indicated by the arrows. The separation of the connections to the positive and negative lines is omitted for simplicity of illustration.

In the embodiment shown in fig. 11, the regulating circuit 16A may be located at a distance from the switching circuit 12A. In this case, it is useful to include a filter at the output of the switching network 12A.

FIG. 12 shows the embodiment as in FIG. 11 with a circuit for providing a first voltage V to the switching network 12A₁Of a voltage source 14. However, in this embodiment, the switching network 12A leads to an inductance L₁Providing a second voltage V₂. In the embodiment shown, there is also a capacitance C across the load 18A₁. Inductor L₁And a capacitor C₁Together define an LC filter that outputs a third voltage V that eventually reaches a regulating circuit 16A shown in fig. 11₃. The regulating circuit 16A regulates the unregulated third voltage V₃To generate a regulated fourth voltage V₄The regulated fourth voltage V₄And then provided to the load 18A.

The alternative embodiment shown in fig. 13 connects the third voltage V3 directly to the load 18A. In this embodiment, the third voltage V3 is regulated by the filter formed by combining the capacitor C1 and the inductor L1 without the need for the regulating circuit 16A. The various configurations shown above have switches that need to be opened and closed at specific times. Thus, both of these configurations implicitly require one or more controllers to provide the control signals for opening and closing the switches. The structure and operation of such a controller 20A is described in connection with FIGS. 14-23.

Fig. 14 illustrates the power converter 10 of fig. 11, but with the controller 20A explicitly shown. The features of the controller 20A include three sensor inputs: for an intermediate voltage V_XFor the output voltage V_OAnd for the input voltage V_INThe selectable input voltage input. The controller 20A has two other inputs: a clock input for receiving a clock signal CLK and a reference voltage V_REFIs input to the computer. Examples of the various signals above, as well as other signals described below, can be seen in fig. 16.

Based on the inputs, the controller 20A provides a first control signal to control the switches in the switched capacitor element 12A

And a second control signal PWM to control the switching of the regulating circuit 16A. The first control signals have complementary first phases

And a second phase

Is measured. In some embodiments, the first control signal is a vector having a higher dimension. In the embodiment shown, the second control signal PWM is a scalar. However, in the later-described multiphase embodiment, the second control signal PWM is also a vector.

The controller 20A depends on the clock signal CLK and the intermediate voltage V_XThe period of the second control signal PWM for controlling the regulating circuit 16A is set. Reference voltage V_REFAnd an output voltage V_OThe comparison therebetween provides for controlling the output voltage V_OThe basis of (1).

Controller 20A synchronizes the operation of switching network 12A and regulating circuit 16A. The controller 20A controls the voltage V by adjusting the voltage V to an intermediate voltage_XThe relevant ripple is synchronized with the second control signal PWM to do this. This synchronization relaxes the requirement to run the conditioning circuit 16A at a significantly higher frequency than the switching network 12A in an attempt to achieve effective feed forward control.

The control method described herein also avoids glitches (glitches) inherent in changing the switching frequency of the switching network 12A. The control method does this by using a regulating circuit 16A for drawing a discontinuous input current. An example of such a regulating circuit 16A is a regulating circuit using a buck converter.

Referring now to fig. 15, the controller 20A has a switched capacitor portion 301 and a regulator portion 302. These portions may be on the same die or on different dies.

The switched capacitor part 301 outputs a first control signal

Complementary first phases forming a first control signal

And a second phase

Shown as the last two traces in fig. 16.

Switched capacitor section 301 has a receiving input voltage V_INAnd an intermediate voltage V_XUndershoot limiter 36. Based on these voltages, undershoot limiter 36 determines trigger level V_{X_L}. The trigger level VX L is shown as a dashed horizontal line superimposed on the sixth trace in fig. 16. The switched capacitor part 301 finally uses the trigger level V_{X_L}To determine when to generate the first control signal

Details of how this is done are described below.

Has been based on the input voltage V_INAnd an intermediate voltage V_XGenerating a trigger level V_{X_L}Undershoot limiter 36 then sets the trigger level V_{X_L}Is supplied to the first comparator 35. The first comparator 35 will then trigger the level V_{X_L}And intermediate signal V_XA comparison is made. Based on the comparison, the first comparator 35 provides a first trigger signal to the first control signal generator 34, wherein the first control signal generator 34 finally outputs a first control signal

Thus, the switched capacitor part 301 forms a first feedback loop, wherein the first feedback loop is based on the intermediate voltage V_XAnd an input voltage V_INTo manipulate the first control signal

To control the intermediate voltage V_X。

The first control signal generator 34 does not immediately generate the first control signal

Instead, the first control signal generator 34 waits for an appropriate timing to generate the first control signal

The occurrence of this suitable timing depends on what the regulator portion 302 is doing.

During the time that the switched capacitor part 301 is busy providing the first trigger signal to the first control signal generator 34, the regulator part 302 is also busy generating the second control signal PWM. Regulator portion 302 utilizes for receiving voltage output V_OAnd a reference voltage V_REFThe voltage compensator 31 to start the process. Thus, the voltage compensator 31 generates an error voltage V_ERR。

Some implementations of voltage compensator 31 include linear voltage mode control and peak current mode control. However, other modes are possible. Assuming linear voltage mode control for the regulation circuit 16A, the voltage compensator 31 will adjust the output voltage V of the power converter 10_OAnd a reference voltage V_REFComparing and comparing the error signal V_ERRIs provided to a second comparator 32. The error signal V_ERRShown in FIG. 16 as a sawtooth waveform V superimposed on the second trace shown in FIG. 16_SAWThe above.

Thus, the regulator portion 302 forms a second feedback loop, wherein the second feedback loop is based on the reference signal V_REFAnd an output voltage V_OTo manipulate the second control signal PWM to control the output voltage V_O. However, for reasons discussed in more detail below, the switched capacitor portion 301 and the regulator portion 302 do not operate independently. Instead, the controller 20A synchronizes their operation.

To provide a basis for such synchronization, the regulator portion 302 includes the sawtooth generator 30. The sawtooth generator 30 is based on the clock signal CLK and the intermediate voltage V_XTo generate saw teethWave form V_SAW. The sawtooth waveform V_SAWFinally providing a control signal for controlling the first control signal

In synchronization with the second control signal PWM.

The second comparator 32 compares the error voltage V_ERRAnd a sawtooth waveform V_SAWA comparison is made and a second trigger signal is output based on the comparison. As shown in FIG. 16, the second control signal PWM is responsive to the error voltage V_ERRAnd a sawtooth waveform V_SAWThe change in sign of the difference between changes state. Due to sawtooth waveform V_SAWFinally based on the intermediate voltage V_XThis therefore provides the basis for synchronizing the operation of the switched capacitor section 301 and the regulator section 302.

The second control signal generator 33 receives the second trigger signal from the second comparator 32 and uses the second trigger signal as a basis for generating the second control signal PWM.

This second control signal PWM is ultimately used as a gate drive to actually drive the gates of the transistors used to implement the main switch 152 in the conditioning circuit 16A, the details of which can be seen in fig. 18. The main switch 152 ultimately controls the inductor voltage V across the inductor 154 within the regulating circuit 16A as shown in the fourth and fifth traces of FIG. 16_LAnd an inductor current I through an inductor 154 within the regulation circuit 16A_L。

The particular configuration shown illustrates the feed forward control of the conditioning circuit 16A implemented in the sawtooth generator 30. However, such control may also be implemented in the voltage compensator 31.

The switched capacitor part 301 implements a hysteretic control system in which the control variable, i.e. the intermediate voltage V_XSwitching abruptly between the two states based on hysteresis. Intermediate voltage V_XIs a piecewise linear approximation of a sawtooth waveform.

Synchronization between regulator portion 302 and switched capacitor portion 301 is important to enable dead time intervals of switching network 12A to occur without regulating circuit 16A drawing current.

In the actual switching network 12A, the first control signal

In effect cycling through three states, not just two. In the first state, the first control signal

The first switch set is opened and the second switch set is closed. In the second state, the first control signal

The first switch set is closed and the second switch set is opened.

A practical difficulty arises in that the switch cannot be opened and closed immediately. Nor can it be guaranteed that these switches operate simultaneously. Thus, the first control signal

Cycling through a third state lasting a dead time interval DT. During this third state, all switches are open. This minimizes the undesirable possibility that the switches in the second set will not open until the switches in the first set have closed.

On the other hand, some regulating circuits 16A, such as buck converters, do not continuously draw input current. In particular, these regulating circuits 16A have short intervals, wherein during these short intervals the regulating circuits 16A draw zero current.

Controller 20A avoids glitches by synchronizing the operation of switching network 12A and regulation circuit 16A so that regulation circuit 16A draws zero current during dead time interval DT.

Another benefit of such synchronization is the ability to cause the switches in the switching network 12A to change state without current flowing therebetween. This reduces commutation losses. As shown in fig. 17, dead time interval DT is made to occur when regulating circuit 16A is not drawing current positively, and the switches in switching network 12A are made to change state only at the beginning and end of dead time interval DT, thus ensuring zero current switching.

In operation, the regulator portion 302 and the switched capacitor portion 301 cooperate to ensure the first control signal

Will be equal to an integer number of periods of the second control signal PWM. In FIG. 16, due to the first control signal

Is equal to an integer number of periods of the second control signal PWM, so that this constraint is satisfied.

The first control signal generator 34 receives the indication of the intermediate voltage V from the first comparator 35_XHas fallen to a trigger level V_{X_L}The following first trigger signal. However, as mentioned above, the first control signal generator 34 does not act immediately. Instead, it waits for an appropriate time to make a state change. Meanwhile, as shown in fig. 16, as the first control signal generator 34 waits, the intermediate voltage V_XAnd continues to descend.

As shown in fig. 16, the intermediate voltage will have dropped below the trigger level V before the first control signal generator 34 acts_{X_L}Undershoot Δ V of_d. In most cases, the undershoot Δ V_dIs smaller and is 1/2 Δ V_XWherein the undershoot upper limit occurs only if the switching frequencies of the regulator portion 302 and the switched capacitor portion 301 are equal. The undershoot upper limit depends on the load current and the input voltage V_IN。

Due to undershoot Δ V_dExerts a pressure on the regulating circuit 18A, so that the undershoot Δ V_dLarge variations in (a) are undesirable. Undershoot limiter 36 indirectly controls undershoot upper limit 1/2 Δ V_XTo select the appropriate trigger level V_{X_L}To limit the undershoot Δ V_d. Undershoot limiter 36 uses an intermediate voltage V_XAnd an input voltage V_INTo select the trigger level V_{X_L}Is a suitable value of.

FIG. 17 shows a close-up of the waveform selected in FIG. 16 to a scale where the scale is actually large enough to show that the first control signal is being composed

Two phases of

And

the dead time interval DT in between. To aid in the discussion, it is useful to consider the circuit shown in fig. 18 introduced earlier when discussing the function of the second control signal PWM.

FIG. 18 shows a first switch set 141, 143, 146, 148 controlled by a first phase φ and a second phase

A second set of controlled

switches

142, 144, 145, 147. Fig. 18 also shows a main switch 152 for connecting the regulating circuit 16A to the switching network 12A. The main switch 152 has been discussed above.

During this dead time interval DT, the phase

All

switches

141, 143, 146, 148, 142, 144, 145, 147 are opened. This dead time interval DT must occur with the main switch 152 open. This requirement sets the first control signal for the regulating circuit 16A

Maximum possible duty cycle D during the switching transition of_max：

As is apparent from the above relationship, the dead time DT versus the maximum possible duty cycle D_maxIs provided with a limit. Therefore, it is desirable to reduce the dead time DT as much as possible to increase the range of possible conversion ratios of the adjusting circuit 16A.

For many practical power converters, the desire for electromagnetic compatibility dictates that the regulating circuit 16A should operate at a constant switching frequency. In these cases, the maximum possible duty cycle D is considered_maxThe above limitations of (a) are not overly burdensome, particularly if the feedback controller used by the regulation circuit 16A would otherwise have maximum duty cycle requirements.

The control strategy described above and implemented by controller 20A in fig. 15 is one of many possible implementations. Generally, as the load current of power converter 10 varies, the switching frequency of

switches

141, 143, 146, 148, 142, 144, 145, 147 in switching network 12A will change in discrete steps.

FIG. 19 illustrates how the output current affects the period over which the

switches

141, 143, 146, 148, 142, 144, 145, 147 in the switching network 12A change state and the corresponding Δ V_XBoth of which ripple.

For this particular control strategy, the ripple amplitude Δ V_XDepending on the load current. In particular, the ripple amplitude Δ V_XA sawtooth waveform is defined having a peak-to-peak amplitude that decreases with load current. As the load current approaches zero, the peak-to-peak amplitude approaches half of the maximum peak-to-peak amplitude. With some modifications to the controller, as shown in FIG. 20, Δ V may also be made when the load current is near zero_XThe ripple is close to the maximum peak-to-peak amplitude.

As is apparent from both fig. 19 and 20, as the load current increases, the switching period of the

switches

141, 143, 146, 148, 142, 144, 145, 147 remains the same for the range of output currents. In this range of output currents, the converter relies on the regulating circuit 16A to make up for the difference between the voltage provided by the switching network 12A and the desired voltage. At some point in time, the adjustment circuit 16A is no longer able to make the necessary corrections. At this point, the period may drop by one step.

The controller 20A shown in fig. 14 is a single-phase converter. Thus, the first control signal

Is a two-dimensional vector and the second control signal PWM is a scalar. In the case of an N-phase converter, the first control signal

Are 2N-dimensional vectors and the second control signal PWM is a component PWM phase-shifted with respect to each other₁、PWM₂、...PWM_nIs a vector of dimension N. Typically, the phase shift between these components is 360/N degrees.

Fig. 21 shows an example of an N-phase converter having a plurality of adjusting

circuits

16A, 16B. Each regulating

circuit

16A, 16B has a

respective switching network

12A, 12B. Each regulating

circuit

16A, 16B is also driven by its own control signal and therefore requires a second control signal PWM of dimension N. Each

switching network

12A, 12B is driven by a pair of phases, and therefore requires a 2N-dimensional first control signal.

The N-phase controller 20A controls the N-phase converter. The N-phase controller 20A is the same as the single-phase controller in fig. 14, but has a control for N intermediate voltages V_X1、V_X2、...V_XNAdditional inputs of (2).

Fig. 22 shows waveforms similar to those shown in fig. 16, but for a three-phase version of the controller shown in fig. 14.

As shown in fig. 22, the second control signal PWM includes second control signal elements PWM separated from each other by delay times corresponding to 120 ° phase shifts therebetween₁、PWM₂、PWM₃. Three intermediate voltages V_X1、V_X2、V_X3Are offset from each other by integer multiples of the delay time. In fig. 22, the integer is 1. However, as shown in fig. 23, other integers are possible.

Due to the intermediate voltage V_X1、V_X2、V_X3Is shorter than the second control signal element PWM₁、PWM₂、PWM₃Are long, so shifting the intermediate voltages by the delay time will not cause them to be 120 degrees out of phase with each other. In practice, the period of the intermediate voltage is too long, so that the voltage is shiftedThe delay time only causes the intermediate voltage V_X1、V_X2、V_X3Of very small phase shifts.

FIG. 23 shows an alternative method of operation similar to that shown in FIG. 22, but with an intermediate voltage V that has been offset by a greater multiple of the delay time_X1、V_X2、V_X3. This results in an intermediate voltage V_X1、V_X2、V_X3With a more pronounced phase shift between them, as a result of which the output voltage V is output_OThe ripple in (2) is reduced.

The multiphase controller 20A for controlling the N-phase converter shown in fig. 21 can be regarded as N single-phase controllers 20A shown in fig. 15 operating in parallel but having a specific phase relationship. Thus, the multi-phase controller 20A looks very similar to the multi-phase controller in fig. 15, but with additional input and output signals. Usually, the intermediate voltage (V)_X1、V_X2...V_XN) And an output voltage V_OIs required for proper operation of the controller 20A.

Fig. 24 shows a converter similar to that shown in fig. 21, but with only one regulating circuit 16A connected to a plurality of switching

networks

12A, 12B. Since there is only one regulating circuit 16A, only the second control signal PWM of 1 dimension is required. Each

switching network

Fig. 25 shows a converter that is substantially the reverse of fig. 24. In fig. 25, the converter has a plurality of regulating

circuits

16A, 16B, all connected to the same switching network 12A. Each regulating

circuit

16A, 16B is driven by its own control signal and therefore requires a second control signal PWM of dimension N. The unique switching network 12A is driven by a pair of phases and therefore requires a first control signal in 2 dimensions.

Fig. 26 shows an inductance L similar to the converter shown in fig. 25, but with both the output of the switching network 12A and the input of the regulating

circuits

16A, 16B connected₁The converter of (1). The grounded capacitor C1 provides a location to store excess charge during operation. N-phase controller 20A observes output voltage V of switching network_YAnd the input voltage V of the regulating circuit_XBoth of them。

Fig. 27 shows an inductor L similar to the converter shown in fig. 24, but with the inductor L connected to the output of each of the

switching networks

12A, 12B and the input of the regulating circuit 16A₁...L_NThe converter of (1). The grounded capacitor C1 provides a location to store excess charge during operation. N-phase controller 20A uses the output voltage V of the switching network_Y1…V_YNAnd the input voltage V of the regulating circuit_XTo generate the appropriate control signals.

In fig. 14, the non-capacitive regulation circuit 16A offloads the switching network 12A. The adjusting circuit 16A switches at a high frequency. As shown in the sixth trace in fig. 16, the component of the high-frequency switching from the regulator circuit 16A is finally superimposed on the intermediate voltage V_XOn a lower frequency sawtooth waveform. The duty cycle of the sawtooth approximation waveform depends on the topology of the switching network 12A. In general, the frequency of the complementary switch network control signals varies with changes in response to changes in the slope of the intermediate signal. These changes in turn occur as a result of changes in the operating point of the power converter.

Switching network 12A and regulating circuit 16A are substantially modular and may be mixed and matched in a variety of different ways. As such, the configuration shown in fig. 11 represents just one of a variety of ways to configure one or more switching networks 12A to form multi-level converter 10 with one or more regulating circuits 16A.

For example, fig. 28 shows a bidirectional version of fig. 11, where power may flow from voltage source 14 to load 18A or from load 18A to voltage source 14, as indicated by the arrows.

Two basic elements are described in connection with the following examples: a switching network 12A and a regulating circuit 16A. Assuming that series connection elements of the same type are combined, there are a total of four basic building blocks. These basic building blocks are shown in fig. 28, 29, 30 and 32. The power converter disclosed herein includes at least one of four basic building blocks. More complex converters can be realized by combining basic building blocks.

The feature of the first building block shown in fig. 28 includes a switching network 12A, wherein the output of the switching network 12A is connected to the input of the regulating circuit 16A. The features of the second building block shown in fig. 29 include a first switching network 12A, wherein the output of the first switching network 12A is connected to the regulating circuit 16A via a first inter-module link 11A, and the output of the regulating circuit 16A is connected to the input of a second switching network 12B via a second inter-module link 11B. In the third building block shown in fig. 30, the output of the regulating circuit 16A is connected to the input of the switching network 12A via the inter-module link 11B. The feature of the fourth building block shown in fig. 33 comprises a first regulating circuit 300A, wherein the first regulating circuit 300A has an output connected to an input of the first switching network 200, and an output of the first switching network 200 is connected to an input of the second regulating circuit 300B.

Additional embodiments further contemplate applying the object-oriented programming concept to the design of a power converter by enabling switching network 12A and regulation circuit 16A to be "instantiated" in a variety of different ways, so long as their inputs and outputs continue to match in a manner that facilitates modular assembly of power converters having various properties.

In many embodiments, the switching network 12A is instantiated as a switched capacitor network. A more useful switched capacitor topology is as follows: ladder, Dickson, series-parallel, Fibonacci, and voltage doubler, all of which topologies may be adiabatically charged and configured as a multiphase network. A particularly useful switched capacitor network is an adiabatically charged version of the full wave cascade multiplier. However, a non-adiabatic charging version may also be used.

As used herein, "adiabatically" changing the charge on a capacitor means passing the charge stored in the capacitor through a non-capacitive element to change the amount of the charge. A positive adiabatic change in charge on a capacitor is considered an adiabatic charging, while a negative adiabatic change in charge on a capacitor is considered an adiabatic discharge. Examples of non-capacitive elements include inductors, magnetic elements, resistors, and combinations thereof.

In some cases, the capacitor may be adiabatically charged for a portion of the time and non-adiabatically charged for the remainder of the time. Such capacitors are considered to be adiabatically charged. Also, in some cases, the capacitor may discharge adiabatically for a portion of the time and non-adiabatically for the remainder of the time. Such capacitors are considered to discharge adiabatically.

Non-adiabatic charging includes all charging that is not adiabatic, and non-adiabatic discharging includes all discharging that is not adiabatic.

As used herein, an "adiabatic charge switching network" is a switching network having at least one capacitor that performs both adiabatic charging and adiabatic discharging. A "non-adiabatic charge switch network" is a switch network that is not an adiabatic charge switch network.

The regulation circuit 16A may be embodied as any converter having the capability of regulating the output voltage. For example, buck converters are attractive candidates due to their high efficiency and speed. Other suitable regulation circuits 16A include boost converters, buck/boost converters, flyback converters, forward converters, half-bridge converters, full-bridge converters, Cuk converters, resonant converters, and linear regulators. The flyback converter may more specifically be a quasi-resonant flyback converter, or an active-clamp flyback converter, or an interleaved flyback converter, or a two-switch flyback converter. Also, the forward converter may more specifically be a multi-resonant forward converter, or an active-clamp forward converter, or an interleaved forward converter, or a two-switch forward converter. Also, the half-bridge converter may more specifically be an asymmetric half-bridge converter, or a multi-resonant half-bridge converter, or an LLC resonant half-bridge.

In the embodiment shown in fig. 28, the source voltage 14 provides an input to a first switching network 12A, which is instantiated as a switched capacitor network. The output of the first switching network 12A is a voltage that is lower than the input voltage provided to the regulating circuit 16A (e.g., a buck converter, a boost converter, or a buck/boost converter). The regulating circuit 16A provides a regulated input voltage to a second switching network 12B, such as another switched capacitor network. The high voltage output of the second switching network 12B is then applied to the load 18A.

Embodiments such as that shown in fig. 28 may be configured to adjust the load 18A or adjust the voltage source 14 depending on the direction of energy flow.

In another embodiment shown in fig. 30, low voltage source 14 is connected to an input of regulation circuit 16A, wherein an output of regulation circuit 16A is provided to an input of switching network 12A to boost switching network 12A to a higher DC value. The output of the switching network is then provided to the load 18A.

An embodiment such as that shown in fig. 30 may be used to adjust voltage source 14 or load 18A depending on the direction of energy flow.

Fig. 31 shows the modular DC-DC converter 10C of fig. 30, but with the controller 20A explicitly shown. The controller 20A is the same as the controller described in connection with fig. 15.

As discussed in connection with fig. 15, the features of controller 20A include three sensor inputs: for an intermediate voltage V_XFor the output voltage V_OAnd optionally for the input voltage V_INThe sensor input of (1). The controller 20A also has two inputs that are not sensor inputs. One non-sensor input receives the clock signal CLK and the other non-sensor input receives the reference voltage V_REF. The clock signal CLK is used to set the period of the second control signal PWM and the reference voltage V_REFFor setting the desired output voltage. Based on these inputs, the controller 20A outputs a first control signal having two phases for the switched capacitor element 12A, and a second control signal PWM to control switching of the regulating circuit 16A. The second control signal PWM is a pulse width modulated signal.

Referring now to fig. 32, another embodiment of the converter 100 includes a first regulation circuit 300A connected to the converter input 102, and a second regulation circuit 300B connected to the converter output 104. Between the first conditioning circuit 300A and the second conditioning circuit 300B is a switching network 200 having a switching network input 202 and a switching network output 204. The switching network 200 includes charge storage elements 210 interconnected by switches 212. These charge storage elements 210 are partitioned into a first group 206 and a second group 208.

In some embodiments, the switching network 200 is a bidirectional switched capacitor network such as that shown in fig. 33.

The feature of the switched capacitor network in fig. 33 includes the first capacitor 20 in parallel with the second capacitor 22. First switch 24 selectively connects one of first capacitor 20 and second capacitor 22 to first conditioning circuit 300A, and second switch 26 selectively connects one of first capacitor 20 and second capacitor 22 to second conditioning circuit 300B. Both the first switch 24 and the second switch 26 are capable of operating at high frequencies, thereby facilitating adiabatic charging and discharging of the first capacitor 20 and the second capacitor 22.

The particular embodiment shown in fig. 33 has a two-phase switching network 200. However, other types of switching networks may be used instead.

In yet another embodiment shown in fig. 34, a plurality of regulating

circuits

16A, 16B, 16C are provided at the output of the first switching network 12A to drive a plurality of loads 18A-18C. For one of the loads 18C, a second switching network 12B is provided between the load 18C and the corresponding regulating circuit 16C, thereby creating the same path as shown in fig. 30. Thus, fig. 34 provides an example of the ability of how the modular structure of the conditioning circuits and switching networks facilitates mixing and matching of components to provide flexibility in the DC-DC converter architecture.

Switched capacitor power converters include a network of switches and capacitors. Energy can be transferred from the input to the output of a switched capacitor network by cycling the network through different topological states using the switches. Some converter known as a "charge pump" may be used to generate high voltages in flash memory and other reprogrammable memory.

To help understand the loss mechanism in a switched capacitor converter, it is beneficial to first analyze the classical capacitor charging problem, as depicted in fig. 35.

FIG. 35 shows initial charging to a certain value V_C(0) The capacitor C of (a). When t is 0, the switch S is closed. At this moment, when the capacitor C is charged to its final value V_INA brief surge of current flows. The charge rate may be described by a time constant τ — RC, where the time isThe constant τ represents the time required to raise or lower the voltage to within 1/e of its final value. Across capacitor v_c(t) voltage and through a capacitor i_cThe instantaneous value of the current of (t) is given by:

v_c(t)＝v_c(0)+[V_in-v_c(0)](1-e^-t/RC)，

and

the energy loss generated during the charging of the capacitor can be determined by calculating the energy dissipated by the resistor R, i.e. the energy loss

Can be obtained by mixing i_cSubstituting the expression of (t) into the above equation further simplifies the equation. Evaluating the integral and then generating

It is therefore evident that the only term relating to resistance is in the exponential of decay. Therefore, if the transient is made statically determinate (i.e., t → ∞), the total energy loss produced when charging the capacitor is independent of its resistance R. In this case, the amount of energy lost is equal to

As shown in fig. 36, the switched capacitor converter can be modeled as an ideal transformer having a limited output resistance R as shown in fig. 36 that takes into account power loss generated upon charging or discharging of the energy transfer capacitor_o. The embodiment shown in fig. 36 is non-isolated because the negative terminals on both sides of the transformer are connected.However, this is by no means necessary. As an example, fig. 37 shows an embodiment where the same terminals are not connected, wherein in this case the converter is isolated.

It should be noted that the transformer shown is used for modeling purposes only. This type of converter will typically not have windings wound around the core. The power losses associated with charging and discharging are typically dissipated in the on-resistance of the MOSFET and the equivalent series resistance of the capacitor.

The output voltage of a switched capacitor converter is given by

There is a possibility of simplifying the operation of the switched capacitor converter and easily finding R_oTwo limiting cases of (2). These limiting conditions are referred to as "slow handover limits" and "fast handover limits".

At fast switching limits (tau)>>T_sw) The charging current and the discharging current are approximately constant, resulting in a triangular AC ripple on the capacitor. Thus, R_oIs sensitive to the series resistance of the MOSFET and capacitor, but is not a function of the operating frequency. In this case, R of the converter operating under fast switching limits_oIs a function of parasitic resistance, and R_oGiven by:

although tending to underestimate R_oBut R, which serves as a good starting point in the design process_oA useful approximation of (d) is given by:

in the slow switching limit, the switching period T_swMuch longer than the RC time constant τ of the energy transfer capacitor. At the stripUnder conditions, a voltage of 1/2C × Δ V occurs regardless of the resistance of the capacitor and the switch_c ²Given the system energy losses. This system energy loss occurs in part because the Root Mean Square (RMS) of the charge and discharge currents is a function of the RC time constant. In these cases, R_oIs given by

The behavior of the output resistance as a function of frequency can be understood by examining FIG. 38, where FIG. 32 shows that as the frequency increases, the output resistance is matched by 1/f_swThe term falls in a consistent manner and at higher frequencies the output resistance statically settles to a stable value.

R given above_SSLAnd R_FSLIs based on the charge multiplier vector concept. The vector a can be obtained by examining the appropriate n-phase converter for any criteria¹～aⁿ. The charge multiplier vectors are calculated using the constraints imposed by kirchhoff's current law in various topological states and the steady state constraint that the n charge multiplier quantities on each capacitor must sum to zero.

Once R is known_oThe conduction loss P can be calculated by the following formula_cond：

In addition, other losses such as switching losses, driver losses, and control losses may be calculated. Preferably, the switching losses are comparable to the conduction losses. The losses resulting from charging and discharging the transistor node are given by

P_sw＝W_swf_sw＝(W_ds+W_on+W_g)f_sw

Wherein W_gIs gate capacitance loss, W_onIs an overlap or commutation loss, and W_dsIs the output capacitance loss. Thus, it is possible to provideThe total converter loss can be calculated using the following equation

Once R is determined_oAnd additional loss mechanisms, the overall efficiency of the converter is given by

In order to optimize the efficiency of a switched capacitor converter, the optimum switching frequency, capacitance and device size must be selected. If the switching frequency is too low, the conduction loss P_condPredominate. On the other hand, if the switching frequency is too high, P_swPredominate. While doing so tends to reduce output ripple, switched capacitor converters rarely operate well above the transition region between the slow switching limit and the fast switching limit. After all, operating above this region tends to increase switching losses without lowering the output resistance to compensate for those increased switching losses. Thus, there is little benefit to working above this region.

If the effective resistance R of the charging path is reduced, for example by reducing the RC time constant_effRMS current increases and this occurs so that the total charge energy is lost (E)_loss＝I_RMS ²R_eff＝1/2C×ΔV_C2) And R_effIs irrelevant. One solution to minimize this energy loss is to increase the size of the pump capacitors in the switched capacitor network.

Although many switched capacitor networks can provide a particular voltage transformation, most of these switched capacitor networks are impractical for a variety of reasons. Practical switched capacitor networks typically have large conversion ratios, low switching stress, low DC capacitor voltages, and low output resistance. Topologies suitable for the converter described herein include ladder, Dickson, series-parallel, Fibonacci, and voltage doubler topologies.

One useful converter is a series-parallel switched capacitor converter. FIGS. 39-40 show a 2:1 series-parallel switched capacitor converter operating in a charge phase and a discharge phase, respectively. During the charging phase, the capacitors are connected in series. During the discharge phase, the capacitors are connected in parallel. In its charging phase, the capacitor voltage v_C1And v_C2In total being V₁In its discharge phase, v_C1And v_C2Is equal to V₂. This means that V₂＝V₁/2。

Another useful topology is the topology shown in fig. 41 and 42. In both charge pumps, the source is at V₁And the load is located at V₂. In these types of charge pumps, packets of charge are pumped along the diode chain as the coupling capacitors are continuously charged and discharged. As shown in fig. 43, has an amplitude v_pumpOf the clock signal v_clkAnd

180 degrees out of phase. The coupling capacitors may be pumped in series or in parallel.

It takes n clock cycles for the initial charge to reach the output. The charge on the final pump capacitor is n times larger than the charge on the initial pump capacitor. Thus, in both pumping configurations, V of the converter in FIG. 42₂Is V₁+(n-1)×v_pump。

Although the above topologies are suitable for stepping up the voltage, they can also be used to step down the voltage by switching the position of the source and load. In this case, the diode may be replaced with a controlled switch such as a MOSFET and a BJT.

Fig. 41 and 42 show topologies where charge is transferred only during one phase of the clock signal. This topology is referred to as a "half-wave" topology because charge transfer occurs only within one half of a clock cycle. The disadvantage of the half-wave topology is the discontinuous input current.

The topologies shown in fig. 41 and 42 may be converted so that they transfer charge during both phases of the clock signal. This can be performed by connecting two such topologies in parallel and driving them 180 degrees out of phase. This topology is referred to herein as a "full wave" topology because charge transfer occurs in both halves of the clock cycle.

Fig. 44 shows a topology derived from the topology shown in fig. 41, but modified such that charge transfer occurs in both phases of the clock signal. Fig. 45 shows a topology derived from the topology shown in fig. 42, but modified such that charge transfer occurs in both phases of the clock signal. Instead of diodes as shown in the topologies of fig. 41 and 42, the topologies shown in fig. 44 and 45 use switches. Unlike diodes which are inherently unidirectional, the switches shown in fig. 44 and 45 are bidirectional. As a result, in the topologies shown in fig. 44 and 45, the power may be from V₁Terminal flows to V₂Terminals, or vice versa. As such, these topologies can be used to step up or step down the voltage.

In the topology shown so far, there are two switching chains, wherein each switching chain is pumped. However, it is also possible to pump only one of the two switching chains. This topology is referred to as "asymmetric".

In an asymmetric topology, half of the capacitors are used to support the DC voltage rather than to transfer energy. However, these embodiments do not require that the switches withstand such high peak voltages. In particular, the peak voltage in the case where only one switching chain is being pumped is only half of the peak voltage in the case where two switching chains are actually being pumped. In these asymmetric topologies, the principle set forth in connection with fig. 44 may be used to modify the unique switch chain being used to transfer energy to transfer charge during both phases of the clock signal.

FIG. 46 shows eight exemplary topologies using the principles set forth in connection with FIGS. 41-45. The first and second columns show half-wave topologies for both the asymmetric and symmetric configurations, while the third and fourth columns show full-wave topologies for both the asymmetric and symmetric configurations. The topology shown in fig. 46 can be further modified to combine the N phases in parallel and operate them 180 degrees/N out of phase. Doing so reduces output voltage ripple and improves output power handling capability.

The basic building blocks in the modular architectures shown in fig. 28, 29, 30 and 32 may be connected as independent entities or coupled entities. In the case of a tightly coupled switching network and regulating circuit, the system energy loss mechanism of the switching network can be prevented and/or reduced by adiabatic charging. This typically involves the use of a regulating circuit to control the charging and discharging of capacitors in the switching network. Furthermore, the output voltage of the regulating circuit and thus of the overall converter may be regulated in response to an external stimulus. One way to regulate the output voltage is by controlling the average DC current in the magnetic storage element.

In general, it is desirable for the regulating circuit to operate in a manner that limits the Root Mean Square (RMS) current through the capacitors in the switching network. The conditioning circuit may do this using resistive elements or magnetic memory elements. Since the resistance element consumes power, a magnetic memory element is generally preferable for this purpose. Thus, the embodiments described herein rely on a combination of switches and magnetic storage elements in the conditioning circuit to limit the RMS current in the switching network.

To limit the RMS current, the regulating circuit forces a capacitor current through a magnetic storage element in the regulating circuit with an average DC current. Then, a switch in the regulating circuit is operated to maintain an average DC current through the magnetic storage element.

The regulating circuit may limit both the RMS charging current and the RMS discharging current of at least one capacitor in the switching network. A single regulating circuit may limit the current flowing into or out of the switching network by sinking and/or sourcing current. Thus, there are four basic configurations shown in fig. 28, 29, 30 and 32.

Assuming that power flows from the source to the load, in fig. 28, the regulating circuit 16A may sink both the charging and discharging currents of the switching network 12A.

In fig. 29, regulation circuit 16A may provide both the charging and discharging currents of switching network 12B while also sinking both the charging and discharging currents of switching network 12A. Furthermore, if both the switching network and the regulating circuit allow power to flow in both directions, bidirectional power flow is possible.

In fig. 30, regulation circuit 16A may provide both the charging current and the discharging current of switching network 12A.

In fig. 32, regulation circuit 300A may provide the charging current of the switching network 200, while regulation circuit 300B may sink the discharging current of the same switching network 200, and vice versa.

The fundamental difficulty that plagues switched capacitor networks is that the act of merely charging the capacitor causes energy loss. This energy loss depends largely on the extent to which the voltage across the capacitor varies due to the charging event. Energy loss E associated with charging capacitor C from zero to V using a fixed voltage source of voltage V_LIs 1/2CV². The loss does not depend on the parasitic series resistance R. Since such losses occur whenever the voltage changes, every charging interval during operation results in a voltage equal to 1/2C Δ V²Where Δ V corresponds to the difference between the initial and final values of the capacitor voltage.

Fixed charging losses cannot be reduced by using switches with lower on-state resistance. Known ways of reducing the fixed charging losses only avoid having the voltage vary greatly during operation. This is why such converters work most efficiently only at a certain conversion ratio.

Since the amount of charge transferred into or out of the charging cycle is the product of the voltage difference and the capacitance, one way to transfer a large amount of charge with only a small voltage difference is to make the capacitance very large. However, large capacitors are not without disadvantages. On the one hand, large capacitors consume a large amount of physical area. In addition, switched capacitor networks with large capacitances are not well suited for efficient operation.

The converter as described herein overcomes the above disadvantages by providing a more efficient use of the capacitor. This means that the capacitor can be smaller and/or the system efficiency will be improved overall. Although the converter as described herein does not require a reconfigurable switched capacitor circuit, it may utilize a switched capacitor circuit as described above.

Fig. 47 illustrates a method for improving the charging efficiency of the capacitor C illustrated in fig. 35 after the switch S is closed. The regulating circuit 16A adiabatically charges the capacitor C. In some embodiments, the conditioning circuit 16A is a switch mode converter that provides an output. A suitable regulating circuit is a low voltage magnetic based converter.

In the system shown in FIG. 47, the input voltage V is during the charging of the capacitor C_INAnd capacitor stack voltage V_CMost of the difference between appears across the input terminals of the regulating circuit 16A. Instead of dissipating as heat in the parasitic resistor R, the energy associated with the charging of the capacitor stack is instead delivered to the output of the regulating circuit 16A. Thus, by making the apparent input resistance of the regulating circuit 16A higher than the parasitic resistor R, a large portion of the capacitor charging energy can be recovered (i.e., redirected to the load).

Thus, the embodiment shown in fig. 47 allows for more efficient use of the capacitor than that shown in fig. 35. This may reduce the required capacitor size and/or improve system efficiency with extension to switched capacitor converters.

FIG. 48 illustrates one implementation of the above-described embodiment in which switching network 12A is connected to regulation circuit 16A, where regulation circuit 16A functions to adiabatically charge/discharge a capacitor in switching network 12A and regulate output voltage V_OThe component (2). Note that the conditioning circuit 16A need not be at a higher frequency than the switching network to promote adiabatic operation; the conditioning circuit 16A may be at even lower frequencies. In the particular embodiment shown, the regulating circuit 16A is a synchronous buck converter, while the switching network 12A is a single-phase series-parallel converter. The characteristics of the switching network 12A include a first switch 1 that opens and closes simultaneously, a second switch 2 that also opens and closes simultaneously, a first pump capacitor C₁And a second pump capacitor C₂。

The regulating circuit 16A includes a filter capacitor C_XWherein the filter capacitor C_XFor filtering only by the adjusting circuit 16AA bypass and a bypass. Thus, the filter capacitor C_XShould be much smaller than the first pump capacitor C of the switching network 12A₁And a second pump capacitor C₂The capacitance of (c).

The switching network 12A alternates between being in a charging state and a discharging state. During the charging state, the switching network 12A couples the first pump capacitor C₁And a second pump capacitor C₂And charging is carried out. Then, during the discharge state, the switching network 12A discharges the first pump capacitor C1 and the second pump capacitor C2 in parallel.

In the charging state, the first switch 1 is closed and the second switch 2 is open. Input voltage V_INThe difference from the sum of the voltage across the first pump capacitor C1 and the voltage across the second pump capacitor C2 appears at the input of the regulating circuit 16A. As a result, the first pump capacitor C1 and the second pump capacitor C2 charge with low loss and at a rate determined by the power drawn from the conditioning circuit 16A to control the system output.

Also in the discharge state, the second switch 2 is closed and the first switch 1 is open. The switching network 12A then discharges in parallel at a rate based on the power required to regulate the output.

Another embodiment relies on charging the full wave cascade multiplier at least partially adiabatically. The cascade multiplier is a preferred switching network due to its superior fast switching limiting impedance, easy amplification of the voltage, two-phase operation, and low switching stress.

In cascade multipliers, the coupling capacitor is usually a time-controlled voltage source v_clkAnd

pumping is performed. However, alternatively, if the coupling capacitor is used as a time-controlled current source i as shown in FIG. 49_clkAnd

pumping, the RMS charging current and RMS discharging current in the coupling capacitor may be limited. In this case, the capacitor is at least partially insulatedThe charging is performed thermally, thereby reducing, if not eliminating, 1/2C Δ V associated with the switched capacitor converter when operating under slow switching limits_c ²And (4) loss. This has the effect of dropping the output impedance to the fast switching limiting impedance. As shown by the black dashed line in fig. 50, which depicts adiabatic operation under fully adiabatic charging, the output impedance will no longer be a function of the switching frequency.

All else being equal, an adiabatic charge switched capacitor converter can operate at a much lower switching frequency than a conventional charge switched capacitor converter, but with greater efficiency. In contrast, an adiabatic charge switched capacitor converter can operate at the same frequency and with the same efficiency as a conventional charge switched capacitor converter, but with much smaller (e.g., 4 to 10 times smaller) coupling capacitors.

The embodiments described herein may utilize two clocked current sources i operating 180 degrees out of phase as shown in FIG. 51_clk、

To operate. One implementation shown in fig. 52 uses one current source 72, a first switch pair 1 and a second switch pair 2. The first switch pair 1 and the second switch pair 2 are optimally synchronized with the switch chain. A suitable implementation of the current source in fig. 52 is an inductance (represented by inductor L in fig. 53).

Fig. 54 shows the cascade multiplier of fig. 49 with the clocked current sources of fig. 52. Fig. 55 shows the cascade multiplier of fig. 49 with the clocked current sources of fig. 53. There are a number of ways to implement the current source 72. These approaches include buck converters, boost converters, flyback converters, resonant converters, and linear regulators. In some embodiments, a power converter with a constant input current implements a constant current source. In other embodiments, the constant current source is implemented for a power converter having a constant input current for a portion of the interval defined by the inverse of the switching frequency of the power converter. In still other embodiments, the linear regulator implements a constant current source.

At the position of FIG. 55In the illustrated embodiment, the inductor L should limit the RMS current through the coupling capacitor (to provide adiabatic operation) while also providing a relatively constant output voltage V_O. This may be achieved by having a large inductance and/or capacitance (not shown) in parallel with the load 18A. However, large inductors consume a considerable area. Also worse, the windings required for large inductances will result in considerable resistive losses.

By proper selection of the inductors and capacitors (not shown) in fig. 55, a relatively static output voltage V can be generated_OWhile confining the current I_X. In particular, a proper selection of the inductance will result in a rectified sinusoidal current I as shown in FIG. 56_XHowever, the rectified sinusoidal current I_XWill still result in a limited RMS current through the coupling capacitor and a relatively constant output voltage V_O。

In fig. 56, the boundary between each half-cycle of the sinusoid corresponds to a switching event of the switches of the clocked current source. Ideally, the current I is measured every time a switching event occurs_XShould be zero. This will minimize switching losses. However, it is difficult to achieve such accuracy in practice. Furthermore, in any attempt to achieve such accuracy, there is a risk that the inductance is less than expected. This will result in a current I_XBecomes negative and may destabilize the circuit.

Therefore, in selecting the inductance L in fig. 55, it is desirable to select a small enough to avoid consuming too much area and generating losses, but large enough to provide the current I_XWill only wipe across the zero line and will not actually have an inductance that becomes negative. Can be controlled by applying a voltage V_XIs divided by the current I_XThe average value of the inductance and the product of the switching frequency. The result is then multiplied by a constant. A suitable constant is 13/24.

Fig. 57 shows a step-down converter in accordance with the architecture shown in fig. 28. However, in this embodiment, the conditioning circuit 16A is used to adiabatically charge the switching network 12A. Time-controlled current source i_clkAnd

simulation was performed by four switching and regulation circuits 16A. Output capacitor C_OHas also been removed so that V_XCan swing. In this example, the regulating circuit 16A is a boost converter that appears as a constant source with small AC ripple. Any power converter with a non-capacitive input impedance at the operating frequency will allow adiabatic operation. Although switch mode power converters are attractive candidates due to their high efficiency, linear regulators are also practical.

In operation, closing the switch labeled "1" causes the capacitor C to be charged₄、C₅And C₆Is charged to the capacitor C₁、C₂And C₃And discharging is performed. Also, closing switch "2" has a complementary effect. The first topological state (phase a) is shown in fig. 57, where all switches labeled "1" are closed and all switches labeled "2" are open. Likewise, a second topological state (phase B) is shown in fig. 58, where all switches labeled "2" are closed and all switches labeled "1" are open.

In this embodiment, regulation circuit 16A limits the RMS charging and discharging currents of each capacitor. For example, a capacitor C₃Discharged through the filter inductor in the conditioning circuit 16A during phase a, while the capacitor C₃Charging through the filter inductor in the conditioning circuit 16A during phase B clearly demonstrates the adiabatic concept. Furthermore, all active components are implemented with switches so that the converter can handle power in both directions.

Some representative node voltages and currents are shown in fig. 60. Two currents (I) shown_P1And I_P2) There is slight distortion of the rising and falling edges of (a) but for the most part the current is similar to two clocks that are 180 degrees out of phase. In general, as is the case in this embodiment, adiabatic charging occurs in a cascade multiplier if at least one end of the switch stack is not loaded with a large capacitance, where V_XThe node is offloaded through the conditioning circuit 16A.

In operation, different amountsWill flow through the different switches. It is therefore useful to dimension these switches in a manner suitable for the current that will flow through the switches. E.g. to V_P1And V_P2The switch of (a) carries more current than the other switches in fig. 57. By making these switches larger than the others, this avoids the need for unnecessarily large switches and thus makes the circuit footprint smaller. This also avoids unnecessary additional capacitance losses proportional to the size of the switch.

The switch shown in fig. 57 will transition between states at a certain switching frequency. To reduce losses, it is desirable for the switching network 12A to operate such that the RMS current through the switch is constrained at the switching frequency. One way to ensure that this is the case is to select the resistance of the switch so that it is so large that the RC time constant for charge transfer between the capacitors is the same no longer than the switching frequency. As can be seen in fig. 50, by controlling the width "W" of the switch, and thus its resistance and size, the switching network 12A can be forced into a fast switching confinement region.

Unfortunately, by using the resistance of the switch to constrain the RMS current, conduction power losses increase and overall efficiency decreases. However, the adjusting circuit 16A enables the resistance of the switch to be reduced and the operation to be performed adiabatically. Thus, the switches can be optimally sized for maximum efficiency without fear of constraining the RMS current, as it is processed by the conditioning circuit 16A (or optional magnetic filter). The optimal size of the switches is selected by balancing the resistive and capacitive losses in the switches at a given switching frequency and a given current.

The modular architecture with the basic building blocks shown in fig. 11, 29, 30 and 32 can be extended to cover a wider range of applications (such as high voltage DC, AC-AC, buck-boost, and multiple output voltages, etc.). Each of these applications includes separating the transformation function and the adjustment function. An extension of the architecture may also incorporate an adiabatically charged switched capacitor converter.

In many switched capacitor converters, the number of capacitors and switches increases linearly with the conversion ratio. Therefore, the temperature of the molten metal is controlled,if the conversion ratio is large, the number of capacitors and switches required is large. Alternatively, a large conversion ratio can be achieved by connecting multiple low-gain stages in series without an intervening filter as depicted in fig. 61, or with an intervening filter between stages as shown in fig. 63. Conversion ratio (V) of total switched capacitor stack_IN/V_X) The following were used:

the main disadvantage of the series stacked configuration is that the voltage stress of the front stage is much higher than the voltage stress of the rear stage. This typically requires stages with different voltage ratings and sizes. However, by bypassing one or both stages, the transform ratio can be easily changed.

The aforementioned adiabatic charging of the series-connected switching network only takes place if the following switching network controls the charging current and the discharging current of the preceding stage. Therefore, it is preferable to use a full-wave switched capacitor converter in the preceding stage, or to use a switched capacitor stage such as a single-phase series-parallel switched capacitor converter with a magnetically based filter.

Fig. 62 shows a converter with two series-connected switching networks in accordance with the architecture shown in fig. 61. Fig. 64 shows the same architecture but with filters between the series connected switching networks in a manner consistent with the architecture shown in fig. 63. Both switching

networks

12A, 12D are two-phase cascaded multipliers. In operation, the switches labeled "1" and "2" are always in complementary states, and the switches labeled "7" and "8" are always in complementary states. Thus, in the first switch state, all switches labeled "1" are open and all switches labeled "2" are closed. In the second switching state, all switches labeled "1" are closed and all switches labeled "2" are open. In this embodiment, closing switch 1 causes a pair of capacitors C to be paired₁、C₂、C₃Is charged to the capacitor C₄、C₅、C₆Discharging takes place and closing the switch 2 has a complementary effect. In addition, closing the switch 7 causes the capacitor C to be charged₇、C₈、C₉Is charged to the capacitor C₁₀、C₁₁、C₁₂Discharging takes place and closing the switch 8 has a complementary effect.

Assuming that the regulation circuit 16A is a buck converter with a nominal step-down ratio of 2:1, the power converter provides a total step-down of 32: 1. Further, if the input voltage is 32V and the output voltage is 1V, the switches in the first switching network 12A will need to block 8 volts, while the switches in the second switching network 12D will need to block 2 volts.

A modular architecture having the basic building blocks shown in fig. 11, 29, 30 and 32 may be configured to handle AC input voltages as shown in fig. 65. AC rectification stage 19A receives an AC waveform from AC source 14B and provides an average DC voltage to converter 10, where the output of converter 10 is connected to load 18A. In this embodiment, the converter 10 may be isolated or take other forms.

One of the main properties of a switched capacitor converter is its ability to operate efficiently for a large input range by reconfiguring the switched capacitor network. If the AC wall voltage is (i.e. 60Hz and 120V)_RMS) Which may be considered a slowly moving DC voltage, the front-end AC switching network 13A should be able to spread out the time-varying input voltage into a relatively stable DC voltage.

FIG. 66 shows 120V over a single 60Hz cycle overlaid with an unwrapped DC voltage_RMSGraph of AC waveform. Fig. 67 illustrates an AC switching network 13A of the type that may be incorporated into AC rectification stage 19A of fig. 65. The AC switching network 13A is a front-end switched capacitor stage (i.e., switching network) combined with a selective inverter stage (i.e., rectification stage). The front-end switched capacitor stages have different configurations (1/3, 1/2, 1/1) for their use. In the particular embodiment shown, the AC switching network 13A maintains the DC voltage below 60V. In some embodiments, the AC switching network 13A is a dedicated adiabatic switched capacitor network.

Once the AC voltage is developed by the AC switching network 13A, the regulating circuit shown in FIG. 6716A produces the final output voltage. In some embodiments, another switching network 16A between the AC switching network 13A and the regulating circuit 16A further regulates the voltage. If this is the case, the warning for the series connected stages applies, since the AC switching network 13A is a dedicated switching network 12A. For safety reasons, some form of magnetic or electrical isolation is also common in AC-DC converters. Therefore, in FIG. 67, the voltage V_AC、V_DCAnd V_OIntentionally defined as being unknown to the common ground.

Fig. 68 shows an AC-DC converter corresponding to the architecture shown in fig. 67. In this embodiment, the AC switching network 13A is a synchronous AC bridge rectifier followed by a reconfigurable two-phase step-down cascade multiplier with three different conversion ratios (1/3, 1/2, 1/1), and the regulating circuit 16A is a synchronous buck converter. In operation, the switches labeled 7 and 8 are always in complementary states. As shown in FIG. 69, during the positive portion (0- π radians) of the AC cycle, all switches labeled "7" are closed, while all switches labeled "8" are open. Also, as shown in FIG. 70, during the negative portion of the AC cycle (π -2 π radians), all switches labeled "8" are closed, while all switches labeled "7" are open.

In addition to the inverting function provided by

switches

7 and 8, switches 1A-1E and switches 2A-2E can be selectively opened and closed as shown in Table 1 to provide three different conversion ratios: 1/3, 1/2, and 1.

TABLE 1

The AC switching network 13A is provided with a digital clock signal CLK. A second signal CLKB is also generated, where the second signal CLKB may be the complement of CLK only (i.e., high if CLK is low and low if CLK is high), or may be generated as a non-overlapping complement. With the switching pattern set according to the first row of table 1, AC switching network 13A provides a step-down ratio of one-third (1/3). With the switching pattern set according to the second row of table 1, AC switching network 13A provides a step-down ratio of one-half (1/2). With the switching pattern set according to the third row of table 1, AC switching network 13A provides a step down ratio of 1.

Most power supplies mounted to a wall meet certain power factor specifications. The power factor is a dimensionless number between 0 and 1, which defines the ratio of the flowing active power to the apparent power. A common method to control harmonic currents and thus improve power factor is to use an active power factor corrector. Fig. 71 shows an AC-DC converter 8 for controlling harmonic currents and improving the power factor to 1. The illustrated features of the AC-DC converter 8 include an AC switching network 13A, wherein the AC switching network 13A receives and rectifies an AC voltage from an AC source 14B. The output of the AC switching network 13A is connected to the input of the active power factor correction circuit 17A. The AC switching network 13A may also provide voltage conversion via a switched capacitor circuit. The power factor correction circuit 21A controls its input current so that it remains as in phase as possible with the voltage waveform provided by the AC source 14B. This drives the reactive power towards zero. The output of the power factor correction circuit 17A is then supplied to the adjustment circuit 16A which operates in the same manner as shown in fig. 67.

Fig. 72 shows a particular embodiment of the modular power converter 10 of fig. 65 connected between a first circuit 251 and a second circuit 252. The first circuit 251 and the second circuit 252 may be a source, a load, or other circuits such as a power converter, a PFC circuit, or an EMI filter.

The illustrated power converter 10 includes a conditioning circuit 16A, a switching network 12A, and an isolation controller 60. As used herein, a circuit having an input and an output is considered isolated if the input voltage and the output voltage do not share a common ground. Such isolation may be performed by corresponding the input voltage to the input voltage of the transformer and the output voltage to the output voltage of the transformer. In some embodiments, conditioning circuit 16A is isolated. In other embodiments, the switching network 12A is isolated. Although only one of the foregoing embodiments is needed to view the modular DC-DC converter 10 as being entirely isolated, embodiments exist in which both the switching network 12A and the regulating circuit 16A are isolated.

In some embodiments, the switching network 12A is an unregulated switched capacitor converter with a fixed voltage conversion ratio. These embodiments generally include a conditioning circuit 16A to condition the output of the switching network 12A. Examples of suitable regulation circuits 16A include boost converters, buck converters, flyback converters, and linear regulators.

Fig. 73 shows a variation of the converter shown in fig. 72, in which an LC filter 21A is added between the switching network 12A and the second circuit 252. The purpose of the LC filter is to facilitate adiabatic charging of the switching network 12A via the method shown in fig. 53.

Fig. 74 illustrates a particular embodiment of the modular DC-DC converter 10 shown in fig. 73. The regulating circuit 16A is implemented with a switch S₁Diode D₁Capacitor C₁And a transformer T₁The flyback transformer of (1). When operating in the continuous conduction mode, conditioning circuit 16A transitions between a first state and a second state. In the first state, the switch S₁Closed and diode D₁No conduction is performed. During this first state, the capacitor C₁Which acts as a charge reservoir to power the output of regulator 16A. In the second state, the switch S₁Off, diode D₁Conduction is performed.

As shown in fig. 74, the isolation controller 60 includes a first control signal CTR1 for controlling the switching network 12A, a second control signal CTR2 for controlling the regulating circuit 16A, and an isolation barrier 61 between the first control signal CTR1 and the second control signal CTR 2. As a result, the first control signal CTR1 and the second control signal CTR2 have different grounds and are connected to the transformer T₁On different sides of the plate. The isolation barrier 61 may include any one or more of acoustic isolation, optical isolation, capacitive isolation, inductive isolation, and mechanical isolation.

As shown in fig. 75, the embodiment shown in fig. 29 may be modified to operate with an AC source 14B, where fig. 75 shows the modular DC-DC converter 10 connected between the first circuit 251 and the second circuit 252. The modular DC-DC converter 10 includes first and

second switching networks

12A and 12B and a regulating circuit 16A. The first switching network 12A receives at its input the voltage from the first circuit 251. The second switching network 12B provides its output to the second circuit 252. The regulating circuit 16A receives an output from the first switching network 12A and provides its own output to an input of the second switching network 12B. Isolation controller 60 provides a first control signal to first switching network 12A, a second control signal to second switching network 12B, and a third control signal to regulation circuit 16A.

Also, as shown in fig. 76, the embodiment shown in fig. 32 may be modified to operate with an AC source 14B, where fig. 76 shows first and

second conditioning circuits

16A and 16B and a switching network 12A. The first regulating circuit 16A receives at its input the voltage from the first circuit 251. The second regulating circuit 16B supplies its output to the second circuit 252. Switching network 12A receives the output from first conditioning circuit 16A and provides its own output to the input of second conditioning circuit 126. Isolation controller 60 provides a first control signal to first conditioning circuit 16A, a second control signal to conditioning circuit 16B, and a third control signal to switching network 12A. In some embodiments, as shown in fig. 73, the second adjusting circuit 16B may be implemented as an LC filter 21A. The AC rectification stage 19A shown in fig. 65 may be implemented in various ways. In one embodiment shown in FIG. 77, the features of rectifier 19A include fuse 71, capacitor C₁ An AC bridge 80, and a first electromagnetic interference filter 70A between the AC bridge 80 and the AC source 14B. In another embodiment shown in FIG. 78, a second EMI filter 70B and a power factor correction circuit 90 replace capacitor C₁。

The first electromagnetic interference filter 70A (which is realized as can be seen in fig. 79 and 80) reduces the common mode noise and the differential mode noise generated by the AC-DC converter 8 by a desired amount. The degree of such noise reduction is typically set by a governmental agency such as the FCC.

The AC bridge 80 accepts the AC voltage and outputs an average DC voltage. A specific implementation of the AC bridge 80 is shown in fig. 81. The bridge comprising a first diode D₁Second, secondDiode D₂A third diode D₃And a fourth diode D₄. In operation, the AC bridge 80 transitions between a first state and a second state. In the first state, the first diode D₁And a third diode D₃Reverse biased, and the second diode and the fourth diode forward biased. In the second state, the second diode D₂And a fourth diode D₄Is forward biased and the first diode D₁And a third diode D₃Is reverse biased.

Many modern devices require different voltages to operate different components such as a Power Management Integrated Circuit (PMIC) in a cell phone. For example, one voltage may be required to operate the processor, while another voltage may be required to operate the display. In principle, it is possible to have separate transformation and regulation stages corresponding to the respective output voltages required. However, this solution wastes both physical space and pin count. This difficult solution is illustrated in fig. 82, where one conversion stage drives two or more regulation stages in parallel. Thus, each regulation stage provides a separate output voltage. The regulator stage may be any regulator already described (including a linear regulator). As shown in fig. 83, some embodiments include a filter between the transform stage and the conditioning stage.

To ensure adiabatic charging of the switching capacitor network in the converter stage, the majority of the power drawn by the individual regulation stages is preferably derived from a constant current (or a constrained current). This can be achieved, for example, by: the regulation stages are synchronized such that they draw as constant a current as possible, thereby avoiding large resistive losses of the conversion stages in the switched capacitor network (i.e. due to high RMS currents).

FIGS. 84-91 illustrate specific implementations of modular power converters conforming to the architecture diagrams shown in FIGS. 28, 29, 30, and 32. In implementations, the regulating circuit or circuits may limit the RMS charging current and RMS discharging current of at least one capacitor in each switching network, so all of these switching networks are adiabatic charging switching networks. However, if

decoupling capacitors

9A or 9B are present9B, the ability of the regulation circuit to limit the RMS charging current and the RMS discharging current may be diminished. The

capacitors

9A and 9B are optional and in order to keep the output voltage suitably constant, a capacitor C is used_O. All stages share a common ground, but this need not be the case. For example, if the regulating circuit is implemented as a flyback converter, the ground can be easily separated, even the switching network can have a separate ground by capacitive isolation. Furthermore, for simplicity, the switching networks in each implementation have a single switching ratio. However, reconfigurable switching networks that provide power conversion at a plurality of different conversion ratios may be used instead.

In operation, the switches labeled "1" and "2" are always in complementary states. Thus, in the first switch state, all switches labeled "1" are open and all switches labeled "2" are closed. In the second switch state, all switches labeled "1" are closed and all switches labeled "2" are open. Likewise, the switches labeled "3" and "4" are in complementary states, the switches labeled "5" and "6" are in complementary states, and the switches labeled "7" and "8" are in complementary states. Generally, the regulating circuit operates at a higher switching frequency than the switching network. However, there is no requirement for the switching frequency between the switching network and the regulating circuit.

Fig. 84 shows a step-up converter corresponding to the architecture shown in fig. 11. In this embodiment, the switching network 12A is a two-phase step-up cascade multiplier with a conversion ratio of 1:3, and the regulating circuit 16A is a two-phase step-up converter. In operation, closing switch labeled 1 and opening switch 2 causes capacitor C to be charged₃And C₄Is charged to C₁And C₂And discharging is performed. Conversely, opening switch 1 and closing switch 2 causes capacitor C to be charged₁And C₂Is charged to the capacitor C₃And C₄And discharging is performed.

Fig. 85 shows a bidirectional step-down converter corresponding to the architecture shown in fig. 28. In this embodiment, the switching network 12A is a two-phase step-down cascade multiplication with a 4:1 conversion ratioAnd the regulating circuit 16A is a synchronous buck converter. In operation, closing switch 1 and opening switch 2 causes capacitor C to be charged₁、C₂And C₃Is charged to the capacitor C₄、C₅And C₆And discharging is performed. Conversely, opening switch 1 and closing switch 2 causes capacitor C to be charged₄、C₅And C₆Is charged to the capacitor C₁、C₂And C₃And discharging is performed. All active components are implemented with switches so that the converter can handle power in both directions.

Fig. 86 shows a step-up converter consistent with the architecture shown in fig. 30. In this embodiment, the regulating circuit 16A is a boost converter and the switching network 12A is a two-phase step-up series-parallel switched capacitor converter with a conversion ratio of 1: 2. In operation, closing switch 1 causes a pair of capacitors C₂Is charged to the capacitor C₁And discharging is performed. Closing the switch 2 has a complementary effect.

Fig. 87 shows a bi-directional buck-boost converter consistent with the architecture shown in fig. 30. In this embodiment, the regulating circuit 16A is a synchronous four-switch buck-boost converter, while the switching network 12A is a two-phase step-up cascade multiplier with a conversion ratio of 1: 4. In operation, closing switch 1 causes a pair of capacitors C₄、C₅And C₆Is charged to the capacitor C₁、C₂And C₃And discharging is performed. Closing the switch 2 has a complementary effect. All active components are implemented with switches so that the converter can handle power in both directions.

Fig. 88 shows an inverting buck-boost converter consistent with the architecture shown in fig. 2. In this embodiment, the first switching network 12A is a step-down series-parallel switched capacitor converter with a slew ratio of 2:1, the first regulating circuit 16A is a buck/boost converter, and the second switching network 12B is a step-up series-parallel switched capacitor converter with a slew ratio of 1: 2. In operation, closing switch 1 causes a pair of capacitors C₁Charging is carried out, and the switch 2 is closed to make the capacitor C₁And discharging is performed. Also, make the switch7 closing so as to make the pair of capacitors C₂Is discharged and the switch 8 is closed to charge the capacitor C₂And charging is carried out.

Fig. 89 shows a bidirectional inverting buck-boost converter consistent with the architecture shown in fig. 29. In this embodiment, the first switching network 12A is a two-phase step-down series-parallel switched capacitor converter with a conversion ratio of 2:1, the regulating circuit 16A is a synchronous buck/boost converter, and the second switching network 12B is a two-phase step-up series-parallel switched capacitor converter with a conversion ratio of 1: 2. In operation, closing switch 1 causes a pair of capacitors C₁Is charged to the capacitor C₂And discharging is performed. Closing the switch 2 has a complementary effect. Likewise, closing switch 7 causes a pair of capacitors C₄Is charged to the capacitor C₃And discharging is performed. Closing the switch 2 has a complementary effect. All active components are implemented with switches so that the converter can handle power in both directions.

Fig. 90 shows a step-down converter consistent with the block diagram shown in fig. 32. In this embodiment, the first regulating circuit 300A is a boost converter, the switching network 200 is a two-phase step-up series-parallel switched capacitor converter with a conversion ratio of 1:2, and the second regulating circuit 300B is a boost converter. In operation, closing switch 1 causes a pair of capacitors C₁And C₂Is charged to the capacitor C₃And C₄And simultaneously discharging. Closing the switch 2 has a complementary effect.

Fig. 91 shows a bidirectional buck-boost converter consistent with the block diagram shown in fig. 32. In this embodiment, the first regulation circuit 300A is a synchronous boost converter, the switching network 200 is a two-phase step-down series-parallel switched capacitor converter with a conversion ratio of 3:2, and the second regulation circuit 300B is a synchronous buck converter. In operation, closing switch 1 causes a pair of capacitors C₃And C₄Is charged to the capacitor C₁And C₂And discharging is performed at the same time. Closing the switch 2 has a complementary effect. All active components are implemented with switches so that the converter can handle power in both directions.

It should be understood that the topology of the regulation circuit may be any type of power converter with output voltage regulation capability, including but not limited to a synchronous buck converter, a three-level synchronous buck converter, a sepic converter, a soft switching converter, or a resonant converter. Also, various switched capacitor topologies may be utilized to implement the switching network depending on the desired voltage transformation and the allowed switching voltage.

The physical implementation of the aforementioned switching network 12A includes four main components: a passive device layer, an active device layer, an interconnect structure, and a via. The passive device layer has passive devices such as capacitors. The active device layer has active devices such as switches.

Since the active devices are manufactured by CMOS processes, separation of active and passive devices in different layers occurs. Thus, if passive devices are on the same layer, these passive devices must be fabricated by CMOS compatible process steps to avoid destruction of the active devices. This constraint makes it difficult to manufacture capacitors that provide high capacitance in a small area of the chip. This also makes it difficult to manufacture high Q inductors. To avoid these difficulties, it is preferable to produce integrated passive devices on the wafer of the passive devices themselves using a process flow optimized for manufacturing such passive devices.

In some embodiments, the devices are integrated into a single monolithic substrate. In other embodiments, the devices are integrated into a plurality of monolithic substrates. Monolithic substrates are typically made of a semiconductor material such as silicon.

In preferred practice, the passive devices are fabricated on the passive device layer using an integrated passive device process, and the active devices are fabricated on the active device layer using a CMOS process. These device layers are electrically connected together by a fine interconnect structure including vias to allow electrical connection across the device layers.

Fig. 92 shows a circuit block diagram of a modular converter that uses capacitors in a switched capacitor circuit to transfer energy. The block diagram shows a layer stack comprising layers for both the switch and the capacitor. The switches within the layer stack comprise a first switch S₁And a firstTwo switches S₂. The capacitor in the layer stack comprises a first capacitor C₁And a second capacitor C₂. Discrete inductor L₁Mounted outside the layer stack.

The layers within the layer stack in fig. 92 may be stacked in different ways. FIGS. 93-95 show side views of different ways of stacking layers, and the placement of interconnect structures and vias corresponding to each such layer configuration. The active device layer (also referred to as a switching device layer) includes switches, while the passive device layer includes capacitors.

In fig. 93, the active device layer is connected to the printed circuit board by a set of C4 bumps, and the passive device layer is stacked over the active device layer. The via TV provides a connection between the printed circuit board and the interconnect structure between the two layers.

In fig. 94, the orientation is reversed, with the passive layer connected to the printed circuit board by C4 bumps and the active layer over the passive layer. Again, the via TV provides a connection between the printed circuit board and the interconnect structure between the two layers.

Fig. 95 shows the possibility of stacking multiple passive or active layers. In the particular embodiment shown, there are n passive device layers and one active device layer. The via TV provides a path for connecting the printed circuit board to an interconnection structure between adjacent layers.

Fig. 96 illustrates an embodiment having at least two device layers, one having a switch and the other having a capacitor.

The C4 bumps are arranged at a first pitch along the printed circuit board. The interconnect structure includes C5 bumps arranged at a second pitch that is less than the first pitch. An example of such a C5 bump is visible in fig. 106.

Each passive layer has a capacitor that occupies a certain footprint (Footprint) on the chip. The capacitors are positioned such that each capacitor is located within the footprint of a switch on the active layer above or below the passive layer. This arrangement helps to reduce energy losses and other parasitic losses in the interconnect structure.

Additional alignment occurs because only one side of the wafer is typically processed as a result of the nature of known semiconductor manufacturing processes. This side of the wafer has devices integrated therein. For this reason, this face is referred to as a "device face".

For each stacked configuration, there are now additional arrangements relating to whether the device face is above or below. For a given layer, with reference to the z-axis shown in FIGS. 93-95, the "upper" of the layer faces in the + z direction and the "lower" faces in the-z direction.

As used herein, a layer is said to "face" in the + z direction if a vector perpendicular to the plane defined by the layer and pointing away from the layer points in the + z direction. If a layer does not face in the + z direction, the layer is said to face in the-z direction.

For the case where there are only two device layers, fig. 97-99 show four possible configurations of the device face in the case where the upper layer is a passive layer as shown in fig. 93. FIGS. 101-104 show four possible configurations of the device face in the case where the upper layer is the active layer as shown in FIG. 94.

In fig. 97, the device face of the active layer is the upper face thereof, and the device face of the passive layer is the lower face thereof. In view of the presence of only two layers, this means that they face each other. Fig. 99 shows the opposite case, in which the device face of the passive layer is above it and the device face of the active layer is below it. In fig. 98, the device faces of both the active and passive layers are above, while in fig. 100, the device faces are below.

FIGS. 101-104 show the reverse of FIGS. 97-100, where the active layer is now the upper layer. In fig. 101, active devices are located below and passive devices are located above. Since there are only two layers, the active and passive devices face each other as in fig. 97. In fig. 102, the active and passive devices are located above their respective layers, while in fig. 104, the active and passive devices are located below their respective layers. In fig. 103, active devices are located above and passive devices are located below.

Naturally, some configurations are preferred over others. The choice will depend on many factors, most of which involve the via technology and the number of pins available to connect the layer to external circuitry.

The passive device layer and the active device layer may take any form when mounted. Two common options are die or wafer form.

105-106 show cross-sections of two die-to-die arrangements of interconnect structures connecting switches in an active die to capacitors on a passive die. In fig. 105, the switch is connected to a planar capacitor, while in fig. 106, the switch is connected to a trench capacitor. The first bump C4 for providing an electrical connection from the die stack to the printed circuit board, and the via TV are omitted in FIGS. 105-106, but are visible in FIGS. 107-108.

Although any type of capacitor may be used, trench capacitors are preferred over planar capacitors because trench capacitors provide a greater capacitance, sometimes one or two orders of magnitude greater, per unit die area than planar capacitors. In addition, trench capacitors provide lower equivalent series resistance compared to planar capacitors. Both of these capacitor properties are applicable to power converters using capacitive energy transfer, as they affect the efficiency of the power converter.

As shown in FIGS. 105-106, interconnect structures connect switches on an active die to capacitors on a passive die. The interconnect structure may be implemented in a variety of ways. In the case of fig. 105-106, the interconnect structure is a combination of a multi-layer interconnect structure on a passive die, a single layer of second bumps C5, and a multi-layer interconnect structure on an active die. The only requirements are: the interconnection structure connects the switch on one device layer to the capacitor on the other device layer, the two device layers are stacked one on top of the other, and the second bump C5 has a much finer pitch than the first bump C4. In some embodiments, the pitch of the second bumps C5 is four times greater than the pitch of the first bumps. As used herein, "pitch" means the number of lugs per unit length.

FIGS. 107-108 illustrate another embodiment implemented by wafer-to-wafer stacking. In this embodiment, the second bump C5 is not required. Instead, the active wafer and the passive wafer are electrically connected to each other using a bonding process. In fig. 107, the device side of the active layer is the lower side thereof, and in fig. 108, the device side of the active layer is the upper side thereof. Examples of suitable bonding processes are copper-copper bonding and oxide-oxide bonding. In addition, FIGS. 107-108 show the omitted vias and some of the first bumps C4 of FIGS. 105-106.

Switched capacitor power converters of the type discussed herein have many switches and capacitors in the switched capacitor power converter. These switches and capacitors must all be properly interconnected for the power converter to operate. There are many ways to physically arrange the conductive paths used to interconnect these components. However, not all of these approaches are equally effective. Depending on the geometry of these conductive paths, some of them may introduce significant parasitic resistance and/or inductance. Since there are so many interconnects, selecting a set of interconnects that will provide both acceptable parasitic resistance and inductance for the power converter as a whole can be a formidable challenge.

One method that can be used to control these parasitic quantities is to partition the switches and capacitors.

One way to reduce this amount of parasitic is to select the shape and location of the switches on the active layer so that they fit under the capacitors on the passive layer. This avoids forcing the current to travel long distances along the face of the layer as it travels between the switch and the capacitor. An example of this technique is shown in fig. 110, where eight switches S₁～S₈And the controller 20A is configured on an active layer located below a passive layer having two capacitors. Although the switches are not fully visible through the passive layer, their positions are marked by dashed lines in the diagram 110. The figure shows a switch S₁、S₂、S₅、S₆First capacitor C of₁And a switch S₃、S₄、S₇、S₈Second capacitor C of₂。

Another way to reduce this amount of parasitics comes from the recognition that the switches in switching network 12A are typically active devices implemented with transistors. The switching network 12A may be integrated on a single monolithic semiconductor substrate or multiple monolithic semiconductor substrates, or formed using discrete devices. Furthermore, since the device is a power converter, each switch can be expected to carry a large amount of current. Switches carrying a large amount of current are typically implemented by a plurality of current paths connected in parallel with a common terminal.

In the switch as described above, the current paths constituting the switch are physically placed side by side, and therefore occupy a space having a non-zero width. These current paths are all connected to a terminal which is itself connected to a conducting path. Examples of this configuration are shown in fig. 109 and 112. In particular, fig. 112 shows a transistor on the first layer and a capacitor on the lower layer. The transistor has a first current path, a second current path, and a third current path, wherein the second current path is between the first current path and the third current path. Three current paths extend between one source terminal and one drain terminal of the transistor.

Some of the current entering the source terminal shown in fig. 112 enters the second current path directly. But some of the current turns left or right before turning back again to continue along the first and third current paths. At the other end of the transistor channel, the current through the first current path and the third current path must be diverted again to reach the drain terminal. These currents are referred to as "lateral" currents.

Likewise, the lower layer of fig. 112 shows a capacitor having three separate current paths connected to a first capacitor terminal and a second capacitor terminal. During charging and discharging, some lateral current is inevitable due to the reasons associated with the transistors in the upper layers.

One way to reduce this lateral current is to divide the switches and capacitors into multiple partitions as shown in fig. 109 and 113. Such partitioning basically involves converting an n-terminal device into an (n + m) -terminal device, where m depends on the number of partitions. Thus, after the partitioning, the two-terminal capacitor in fig. 112 is converted to the six-terminal capacitor in fig. 113. Similarly, the source terminal and the drain terminal of the transistor in fig. 112 are converted to three source terminals and three drain terminals of the transistor in fig. 113.

The difference between fig. 112 and 113 is that each current path in fig. 113 has its own terminal. In contrast, in fig. 112, all current paths share the same terminal. Thus, fig. 112 shows three current paths connected in parallel, while fig. 113 shows three current paths partitioned and thus isolated from each other.

The three current paths shown collectively represent a switch on the active layer formed by various doping profiles along the silicon wafer to provide charge carriers, and then connecting these three lines to a pair of external terminals as shown in fig. 112, or connecting each line to its own pair of external terminals as shown in fig. 113.

The capacitor represented by the lower layer in fig. 112 is a two-terminal capacitor like any conventional capacitor. The prior art converters use this type of capacitor. However, unlike prior art converters that use two terminal capacitors, converters as disclosed herein use six terminal capacitors as shown in fig. 113. Although this capacitor is more complex as it has more terminals that need to be manufactured and aligned correctly, it reduces the parasitic effects caused by lateral currents.

Also, the transistor switch represented by the upper layer in fig. 112 has one source terminal and one drain terminal. The transistor switch is a type of transistor used in conventional power converters. In contrast, the transistor shown by the upper layer in fig. 113 has three source terminals and three drain terminals. Although this transistor is more complex because it has more terminals that need to be fabricated and properly aligned, it reduces the parasitic effects caused by lateral currents.

It should be apparent that the partitioning action is independent of geometry. The essence is to convert the n-terminal device to an (n + m) -terminal device in an attempt to reduce parasitic effects. The device is not required to be oriented in any particular manner. In particular, it is not required that partitioning be performed in only one dimension as shown in fig. 113. For example, it is highly possible to partition the components along the x and y directions as shown in the nine-partition switch of fig. 111 and the six-partition capacitor shown in fig. 114.

Both techniques shown in fig. 113 and 114 reduce the longitudinal and lateral distances between the active and passive devices while also providing uniform current distribution to each individual switch and/or switched capacitor cell. This tends to reduce the parasitic resistance and inductance of the connection between the switch and the capacitor. This provides considerable advantages. Parasitic inductance limits the switching speed, while parasitic resistance limits the efficiency of the power conversion process.

Fig. 115 shows a functional block diagram of the switching network 12A of fig. 13 and 12. The illustrated switching network 12A is for applying a first voltage V₁Converted to a second voltage V₂Two-phase cascade multipliers of (1). The switching network 12A does this by designing the flow of charge in and out with respect to the charge transfer capacitors (also referred to as coupling capacitors) in the first charge transfer capacitor bank 50A.

Depending on the type of capacitor, each charge transfer capacitor may have a capacitance that is a function of the voltage across the charge transfer capacitor. The charge transfer capacitors are selected such that they all have the same capacitance at their respective operating voltages. However, at the same voltage, it is likely that different charge transfer capacitors will have different capacitances (e.g., MLCCs have a strong capacitance dependence on dc voltage bias).

Switching network 12A includes a first phase switch bank 54A and a second phase switch bank 54B, with each phase switch bank for one phase. The switches within each

phase switch group

54A, 54B will be referred to as "phase switches". Likewise, the switch network 12A includes a first stacked switch group 52A and a second stacked switch group 52B, where again, each stacked switch group is for one phase. The switches within each

stacked switch group

52A, 52B will be referred to as "stacked switches".

Each switch occupies a certain amount of area on a semiconductor substrate (e.g., silicon, GaA, GaN, and SiC). However, the area occupied by each switch need not be the same. In general, it is useful to make switches that are expected to carry a relatively large amount of current larger than switches that carry less current. This allows the overall circuit to be small while avoiding excessive conduction losses.

One or more of the switches may be partitioned to prevent lateral flow of current within the area defined by the switches. This may be performed by having multiple terminals at each end of the switch. With such a plurality of terminals, the current entering through any one terminal will be more likely to flow to the directly opposite terminal, thereby reducing the extent of lateral current flow within the switch.

To control the operation of the phase switches and the stack switches, the switching network 12A features two separate and distinct controllers: a phase controller 59A to control the phase switches, and a stack controller 51 to control the stack switches.

Phase controller 59A is based at least in part on phase controller input signal I_O1To control the phase switch. The phase controller 59A does this by connecting the phase controller 59A to the phase control path 55B of the phase switch. On the other hand, the stack controller 51 is based at least in part on the stack controller input signal I_O2To control the stack switch. The stack controller 51 does this by connecting the stack controller 51 to the phase control path 55A of the stack switch. The inter-controller junction 57 provides communication between the phase controller 59A and the stack controller 51. This allows the phase controller 59A and the stack controller 51 to control the phase switch and the stack switch in a coordinated manner, rather than independently.

An advantage of the manufacturing process used in integrated circuits is the ability to integrate many components on a single die. This makes it easier to manufacture many parts at once, thereby reducing the manufacturing cost for each component.

One way to fabricate the switching network 12A shown in fig. 115 is to place the first and second stacked switch sets 52A and 52B and the first and second phase switch sets 54A and 54B on the same die. Since only one die needs to be manufactured, the manufacturing cost for each switch is expected to be reduced.

Stacked switches and phase switches have different requirements due to their role in the circuit. In particular, the phase switch does not experience such high voltages or currents. As a result, the phase switch is relatively simple and inexpensive to manufacture. On the other hand, stacked switches are often exposed to a rather high voltage difference across these stacked switches. Due to these special requirements, the stacked switch requires different manufacturing steps.

More complex processes for manufacturing stacked switches may also be used to manufacture phase switches. Thus, the first and second stacked switch sets 52A, 52B and the first and second phase switch sets 54A, 54B may be fabricated on the same integrated circuit. This provides the advantage that only one manufacturing process has to be performed.

The switch network 12A shown in fig. 115 avoids this advantage by having the first and second

stacked switch groups

52A, 52B and the first and second

phase switch groups

54A, 54B on different die rather than on the same die. As a result, it is necessary to use two manufacturing steps instead of a single manufacturing step.

Specifically, fig. 115 shows a first phase die 58A and a stacked die 56. First phase die 58A includes first and second sets of

phase switches

54A and 54B and phase controller 59A. The stacked die 56 includes first and second

stacked switch groups

52A and 52B and a stacked controller 51.

In some embodiments, one or both of the phase controller 59A and the stack controller 51 are also on separate controller dies, thus further increasing the number of separate manufacturing operations that must be performed to build the switching network 12A.

In the embodiment shown in fig. 115, first phase switch set 54A and second phase switch set 54B are both on first phase die 58A, and first stacked switch set 52A and second stacked switch set 52B are on separate stacked dies 56. Thus, each die is associated with both phases. However, it is also possible to place each phase on its own die.

For example, fig. 116 shows a circuit that transforms the first voltage V1 to the second voltage V2, where the second voltage V2 is provided to the load 18A. The circuit has four separate dies: a first phase die for the first phase switch group 54A, a second phase die for the second phase switch group 54B, a first stacked die for the first stacked switch group 52A, and a fourth stacked die for the second stacked switch group 52B. In this embodiment, the first phase switch set 54A and the first stacked die are associated with a first phase and the second phase switch set 54B and the second stacked switch set 52B are associated with a second phase.

In fig. 116, the phase controller 59A and the stack controller 51 are omitted for the sake of clarity. The switches are also shown schematically rather than as transistors. If the switches are shown as transistors, the phase controller 59A and the stack controller 51 will be connected to the gate terminals of these transistors.

The first phase switch set 54A in fig. 115 and the first phase switch S in fig. 116_P1And a second phase switch S_P2And correspondingly. Second phase switch set 54B of FIG. 115 and third phase switch S of FIG. 116_P3Corresponding to the fourth phase switch SP 4. These phase switches are placed together on the same first phase die 58A in fig. 115.

The first stacked switch group 52A in fig. 115 and the switch S in fig. 116_1A、S_2A、S_3A、S_4AAnd correspondingly. The second stacked switch set 52B of FIG. 115 and the switch S of FIG. 116_1B、S_2B、S_3B、S_4BAnd correspondingly. These stacked switches are placed together on the same stacked die 56 in fig. 115.

Connecting each switch to a respective charge transfer capacitor C in the first charge transfer capacitor bank 50A_1A、C_2A、C_3A、C_4A、C_1B、C_2B、C_3B、C_4BWhile avoiding the charge transfer capacitor C_1A、C_2A、C_3A、C_4A、C_1B、C_2B、C_3B、C_4BAnd a stack switch S_1A、S_2A、S_3A、S_4A、S_1B、S_2B、S_3B、S_4B、S_P1、S_P2、S_P3、S_P4Too long a path length in between is useful. Excessively long path lengths are undesirable because they can increase the resistance between components. These path lengths can be reduced by appropriately arranging the die and the position of the terminals on each die.

Fig. 117 illustrates a particular implementation of the terminals on the stacked die 56 and the terminals on the first phase die 58A for the embodiment illustrated in fig. 115. The charge transfer capacitors in the first charge transfer capacitor bank 50A extend between the stacked die 56 and the first phase die 58A. The terminals shown in fig. 116 have been configured such that: the terminals connected to the positive terminals of the charge transfer capacitors are all located on one side, and the terminals connected to the negative terminals of the charge transfer capacitors are all located on the other side. This results in a reduced path length between the stacked switch, the phase switch and the charge transfer capacitor.

As shown in fig. 115, both stacked die 56 and first phase die 58A are connected to the output of switching network 12A. In FIG. 117, the length is Y₁The inter-die conductive joint 63 connects the output terminal of the switch network 12A to both the stacked die 56 and the first phase die 58A. The length Y₁Is adjusted to the length of the capacitors in the first charge transfer capacitor bank 50A.

The embodiment shown in fig. 117 results in the stacked die 56 being coplanar with the first phase die 58A. However, the conductive path length may be further reduced by having the stacked die 56 and the first phase die 58A located in different planes. This can be achieved by folding the layout shown in fig. 117 about a vertical line extending along the middle of the inter-die joint 63. Alternatively, by folding along a horizontal symmetry axis, it is possible to have different phases on different levels.

In the embodiment of FIG. 116, each charge transfer capacitor C_1A、C_2A、C_3A、C_4A、C_1B、C_2B、C_3B、C_4BWill be connected at some point to the first phase switch bank 54A and the second phase switch bank 54B. However, the assembly may be arranged to form a device with a first charge transferA switching network 12A of capacitor banks 50A and a second charge transfer capacitor bank 50B, wherein each charge transfer capacitor bank is connected to only one of the first phase switch bank 54A and the second phase switch bank 54B. An example of such a topology can be seen in fig. 118.

FIG. 118 shows a schematic diagram for applying a first voltage V₁Converted to a second voltage V₂A two-phase switching network 12A. The two-phase switching network 12A does this by designing the charge flow in and out with respect to the charge transfer capacitors.

The switch network 12A of fig. 118 has first and second

phase switch groups

53A and 53B (one for each phase), and first and second

stacked switch groups

52A and 52B (one for each phase). To control the operation of these switches, the switching network 12A features three separate and distinct controllers: a first phase controller 59A to control the phase switches in the first phase switch group 53A, a stack controller 51 to control the stack switches in the first stack switch group 52A and the second stack switch group 52B, and a second phase controller 59B to control the phase switches in the second phase switch group 53B.

The first phase controller 59A is based in part on the first phase controller input signal I_O1To control the operation of the phase switches in the first phase switch group 53A. The first phase controller 59A does this by connecting the phase controller 59A to the first phase control path 55B of the phase switch. The second phase controller 59B is based at least in part on the second phase controller input signal I_O3To control the operation of the phase switches in the second phase switch bank 53B. The second phase controller 59B does this by connecting the second phase controller 59B to the second phase control path 55C of the second phase switch bank 53B.

The stack controller 51 receives a stack control input signal I_O2And using the stack control input signal I_O2To control the operation of the stack switches in the first and second

stack switch groups

52A and 52B. Stack controller 51 does so via stack control path 55AThis is done. The first phase controller 59A, the second phase controller 59B, and the stack controller 51 all communicate via the inter-controller junction 57.

Fig. 119 shows a circuit with four separate dies as follows: a first phase die for first phase switch group 53A, a second phase die for second phase switch group 53B, a first stacked die for first stacked switch group 52A, and a fourth stacked die for second stacked switch group 52B.

In this embodiment, the first phase switch set 54A and the first stacked die are associated with a first phase and the second phase switch set 54B and the second stacked switch set 52B are associated with a second phase. The first and

second phase controllers

59A and 59B and the stack controller 51 are omitted to facilitate clarity. The switches are also shown schematically rather than as transistors.

The circuit shown in fig. 119 includes voltage source 14 and load 18A. The voltage source 14 provides a first voltage V in graph 118₁. The load 18A is connected to the second voltage V in fig. 118₂。

First phase switch set 53A in FIG. 118 and first phase switch S in FIG. 119_P1Second phase switch S_P2And a third phase switch S_P3And a fourth phase switch S_P4And correspondingly. Second phase switch group 53B and fifth phase switch S in FIG. 119_P5Sixth phase switch S_P6The seventh phase switch S_P7And an eighth phase switch S_P8And correspondingly. These phase switches are placed on the first phase die 58A and the second phase die 58B in fig. 118.

The first stack switch 52A in fig. 118 and the first switch S in fig. 119_1AA second switch S_2AAnd a third switch S_3AAnd a fourth switch S_4AAnd a fifth switch S_5AAnd correspondingly. The second stacked switch set 52B of FIG. 118 and the sixth switch S of FIG. 119_1BSeventh switch S_2BThe eighth switch S_3BAnd a ninth switch S_4BAnd a tenth switch S_5BAnd correspondingly. These stacked switches are illustrated in FIG. 118Together on the same stacked die 56.

Diagram 120 illustrates terminals on stacked die 56, terminals on second phase die 58B, and charge transfer capacitors C for the switching network 12A shown in fig. 118_1B、C_2B、C_3B、C_4BTo a specific implementation of (a). Phase switch S in second phase switch group 53B_P5、S_P6、S_P7、S_P8The location of the terminals connected to the second phase die 58B can be seen in fig. 121.

The terminals on the second phase die 58B are laid out in the same manner as shown for the first phase die 58A and are therefore omitted for clarity. Also, a charge transfer capacitor C_1A、C_2A、C_3A、C_4AThe interconnections between both the stacked die 56 and the first phase die 58A are the same as those shown in fig. 120 and are therefore omitted for clarity.

Referring back to fig. 120, the inter-die joints 63, in turn, connect the second phase switch die 58B to the stacked die 56. The inter-die joints 63 have a length Y₂Wherein the length is dependent on the charge transfer capacitor C in the second charge transfer capacitor bank 50B_1B、C_2B、C_3B、C_4BThe physical size of (2). The size of the inter-die joints 63 is enlarged at selected locations to avoid excessive accumulation of current density. As a result, the inter-die joints 63 are wider at locations where a relatively large current is expected to flow, but are narrower at locations where a smaller current is expected to flow. This avoids having an excessively large footprint, while also avoiding resistive losses.

In many cases, the switching network 12A is to be connected to a regulator (also referred to as a regulating circuit). In these cases, it is useful to include the bank of regulator switches 62 within the phase die 58C as shown in fig. 122. Since the regulator switches and phase switches have the same performance requirements, it is advantageous to integrate the first and second

phase switch banks

54A, 54B and the regulator switch bank 62 in the phase die 58C. Both the phase switch and the regulator switch are intended to maintain substantially the same voltage. As such, the same manufacturing process may be used for both switches.

The regulator to be connected to the regulator switch bank 62 introduces an inductive load that in turn introduces considerable noise in the substrate including any die of the regulator switch bank 62. Since the noise of the substrate of phase die 58C is inherently greater than the noise of the substrate of stacked die 56 during operation, the bank of regulator switches 62 is included in phase die 58C to enable operation of stacked die 56 with minimal disturbance due to electrical noise.

In the embodiment shown in fig. 122, the phase controller is replaced by a hybrid controller 59C, which hybrid controller 59C is configured to control both the set of regulator switches 62 and the sets of

phase switches

54A, 54B via a phase control path 55B and a regulator control path 55D, where the phase control path 55B extends from the hybrid controller 89C to the sets of

phase switches

54A, 54B, and the regulator control path 55D extends from the hybrid controller 59C to the set of regulator switches 62.

An advantage of placing the phase switch and the stacked switch on separate dies rather than integrating them in the same die is that this reduces the area of the die used to hold the stacked switch. Reducing the die area is advantageous because the die must undergo a more expensive manufacturing process and because the manufacturing cost is a function of the die area. Since stacking only the switches actually requires a more expensive manufacturing process, it is advantageous to omit the phase switches and place them on separate dies which can then be manufactured at lower cost.

Another advantage that results is that having the stacked switches and phase switches on different dies provides more flexibility in routing between components. This is because the components and interconnects are limited to two-dimensional space with all components on the same die. In contrast, where the third dimension becomes available, there are additional degrees of freedom that can be used to optimize the placement of the dies relative to each other to minimize path length.

Figures 123-128 collectively illustrate the flexibility associated with having separate phase die 58 and stacked die 56.

FIG. 123 shows a circuit for supporting a charge transfer capacitor C_1A、C_2AA first bare chip U₁And a second die U₂Substrate 28 of (a). In the embodiment shown, the first die U₁Corresponding to the stacked die 56, and a second die U₂Corresponding to phase die 58. First bare chip U₁And a second die U₂Side-by-side with their respective device faces facing substrate 28. Conductive bumps 45 on the first die U₁And a second die U₂And a charge transfer capacitor C_1A、C_2AProviding electrical communication therebetween.

FIG. 124 shows a circuit for supporting a charge transfer capacitor C_1A、C_2AA first bare chip U₁And a second die U₂Substrate 28 of (a). First bare chip U₁And a second die U₂Side-by-side within the package 82 with their respective device faces facing the substrate 28. Within the package 82, the first electrical interconnect layer 43A provides a first die U₁And a second die U₂To be interconnected. Conductive bump 45 in package 82 and charge transfer capacitor C_1A、C_2AProviding electrical communication therebetween.

FIG. 125 illustrates a substrate 28 for supporting a package 82, wherein in the package 82, a second die U₂Stacked on the first die U₁And (4) upward. The first interconnect layer 43A interconnects the first die U₁Interconnect with the rest of the switching network 12A, and a second interconnect layer 43B interconnects the second die U₂Interconnected with the rest of the switching network 12A. Conductive bump 45 in package 82 and charge transfer capacitor C_1A、C_2AProviding electrical communication therebetween.

Fig. 126 shows a substrate 28 for supporting a package 82 having a passive device layer 41A and an active device layer 42A. Charge transfer capacitor C_1A～C_4BIs integrated into its own capacitor die 81, wherein the capacitor die 81 is located in the passive device layer 41A. First bare chip U₁And a second die U₂In the active device layer 42A. In this embodiment, the passive device layer 41A may be regarded as a charge transport layer, and the active device layer 42A may be viewedIs a switching layer. The conductive bumps 45 provide electrical communication between the package 82 and any external components.

Fig. 127 shows a substrate 28 for supporting a package 82 having a hybrid device layer 40A and an active device layer 42A, where the hybrid device layer 40A is a hybrid layer that functions as both a switching layer and a charge transport layer, and the active device layer 42A is only a switching layer. Charge transfer capacitor C_1A～C_4BIs integrated into its own capacitor die 81, this capacitor die 81 being in contact with the second die U₂Together in the passive device layer 40A. First bare chip U₁In the active device layer 42A, but opposite the second die U₂Laterally offset. This is the first die U₁And a second die U₂The connection between provides a shorter path length. The conductive bumps 45 provide electrical communication between the package 82 and any external components.

Yet another advantage of having the various components of the switched capacitor circuit on separate dies is that this can facilitate heat dissipation. Since there will be more surface area available for radiating heat. The ability to efficiently dissipate heat is particularly important for power converters because of their tendency to become progressively hotter. An example of how the die may be arranged to facilitate cooling is shown in fig. 128.

Fig. 128 shows a substrate 28 for supporting a package 82 having a first active device layer 42A, a second active device layer 42B, and a passive device layer 41A between the first active device layer 42A and the second active device layer 42B. Charge transfer capacitor C_1A～C_4BIs integrated into its own capacitor die 81, wherein the capacitor die 81 is located in the passive device layer 41A. Second bare chip U₂In the second active device layer 42B, and the first die U₁In the first active device layer 42A. In this embodiment, the passive device layer 41A is a charge transport layer, and the first active device layer 42A and the second active device layer 42B are both switching layers. The conductive bumps 45 provide electrical communication between the package 82 and any external components.

An advantage of the embodiment shown in fig. 128 is that the hottest components of the circuit, i.e., the active device layers 42A, 42B, are external, while the cooler passive device layer 41A remains internal. Thus, this configuration promotes cooling.

FIG. 129 shows a support for inductor L₁And a substrate 28 of a package 82 having a passive device layer 41A and an active device layer 42A. Charge transfer capacitor C_1A、C_2AIs arranged in the passive device layer 41A. Charge transfer capacitor C_1A、C_2AAre discrete elements that are surrounded by a matrix 74 to mechanically support them in some embodiments. First bare chip U₁In the active device layer 42A, wherein the first die U₁For mounting on the package 82 and external components (including the inductor L)₁) Conductive bumps 45 that provide electrical communication therebetween. In this embodiment, the passive device layer 41A is a charge transport layer, and the active device layer 42A is a switching layer. The first interconnect layer 43A and the second interconnect layer 43B are on the charge transfer capacitor C_1A、C_2AAnd a first die U₁Providing electrical communication therebetween.

FIG. 130 shows a support for inductor L₁And substrate 28 of package 82. The package 82 has a passive device layer 41A and an active device layer 42A. The first interconnect layer 43A disposed on the conductive bumps 45 encapsulates 82 and external components (including the inductor L)₁) Providing electrical communication therebetween. Charge transfer capacitor C_1A、C_2AIs arranged in the passive device layer 41A. These charge transfer capacitors C_1A、C_2AAre discrete elements that are surrounded by a matrix 74 to mechanically support them in some embodiments. First bare chip U₁In the active device layer 42A, wherein the first die U₁Faces the second interconnect layer 43B at the passive-device layer 41A. Thus, the switching layer corresponds to the active device layer 42A, and the charge transport layer is the passive device layer 41A. The second interconnect layer 43B is on the first die U₁And a charge transfer capacitor C_1A、C_2AProviding electrical communication therebetween. The heat spreader 76, opposite the device face, contacts the thermally conductive bumps 46. Unlike the thermally and electrically conductive bumps 45, the thermally conductive bumps 46 are dedicated to heat transfer only.

FIG. 131 shows a support for inductor L₁And substrate 28 of package 82. The package 82 has a passive device layer 41A serving as a charge transport layer, and an active device layer 42A serving as a switching layer. The first interconnect layer 43A is disposed on the conductive pad 45B. The first interconnect layer 43A is between the package 82 and the external component (including the inductor L)₁) Providing electrical communication therebetween. Charge transfer capacitor C_1A、C_2AIs arranged in the passive device layer 41A. These charge transfer capacitors C_1A、C_2AAre discrete elements that are surrounded by a matrix 74 to mechanically support them in some embodiments. First bare chip U₁In the active device layer 42A, wherein the first die U₁Faces the second interconnect layer 43B at the passive-device layer 41A. The second interconnect layer 43B is on the first die U₁And a charge transfer capacitor C_1A、C_2AProviding electrical communication therebetween. The heat sink 76, which is opposite the device face, contacts the thermal pad 46B. Unlike the conductive pad 45B, which is thermally and electrically conductive, the thermal pad 46B is dedicated only to heat transfer.

Fig. 132 shows a substrate 28 for supporting a package 82 having a passive device layer 41A and an active device layer 42A. The passive device layer 41A functions as a charge transport layer, and the active device layer 42A functions as a switching layer. The first interconnect layer 43A disposed on the conductive bumps 45 provides electrical communication between the package 82 and external components. Inductor L₁And a charge transfer capacitor C_1A、C_2AIs arranged in the passive device layer 41A. These are discrete elements, which in some embodiments are surrounded by a matrix 74 to mechanically support them. First bare chip U₁In the active device layer 42A, wherein the first die U₁Faces the second interconnect layer 43B at the passive-device layer 41A. The second interconnect layer 43B is on the first die U₁And a charge transfer capacitor C_1A、C_2AAnd an inductor L₁Providing electrical communication therebetween. The heat spreader 76, opposite the device face, contacts the thermally conductive bumps 46. Unlike the thermally and electrically conductive bumps 45, the thermally conductive bumps 46 are dedicated to heat transfer only.

FIG. 133 shows a support with a bracketThe source device layer 41A and the substrate 28 of the package 82 of the hybrid device layer 40A. The passive device layer 41A functions as a charge transport layer, and the hybrid device layer 40A functions as a switching layer. The first interconnect layer 43A disposed on the conductive bumps 45 provides electrical communication between the package 82 and external components. Charge transfer capacitor C_1A、C_2AIs arranged in the passive device layer 41A. These are discrete elements, which in some embodiments are surrounded by a matrix 74 to mechanically support them. Inductor L₁And a first die U₁Side-by-side in hybrid device layer 40A. Inductor L1 is formed from a metal trace that is wrapped around the core in hybrid device layer 40A. The device side of the first die U1 faces the second interconnect layer 43B at the passive-device layer 41A. The second interconnect layer 43B is on the first die U₁And a charge transfer capacitor C_1A、C_2AAnd an inductor L₁Providing electrical communication therebetween. The heat spreader 76, opposite the device face, contacts the thermally conductive bumps 46. Unlike the thermally and electrically conductive bumps 45, the thermally conductive bumps 46 are dedicated to heat transfer only.

An additional advantage of using different dies to establish the switching network 12A is that some components do not co-exist well on the same die ("are co-located").

Since all components on the die share a common substrate, all components are inherently connected. This means that activity at one end of the die may significantly affect activity at the other end of the die.

Stacked switches handle a significant amount of power. As a result, stacked switches do not always co-exist well on the same die ("are" adjacent "). In particular, where the stacked switch and the phase switch are located on the same die, the phase switch operation may be adversely affected by the stacked switch operation.

In some embodiments, the stack controller 51 is integrated into the stacked die. This reduces the total pin count and also avoids the need to manufacture separate dies. However, due to EMI and due to electrical coupling, very high currents associated with the operation of the stack switch may interfere with the operation of the stack controller 51. Thus, in some embodiments, the stack controller 51 is located on a separate die.

Among other advantages, the above arrangement avoids loss of components and pin count, reduces energy loss in parasitic interconnect structures, and reduces the total footprint of the power converter that uses capacitors to transfer energy.

In some implementations, the computer accessible storage medium includes a database representing one or more components of the converter. For example, the database may include data representative of a switching network that has been optimized to facilitate low loss operation of the charge pump.

Generally speaking, a computer-accessible storage medium may include any non-transitory storage medium that a computer may access during use to provide instructions and/or data to the computer. For example, the computer-accessible storage medium may include storage media such as magnetic or optical disks and semiconductor memories.

In general, a database representing a system may be a database or other data structure readable by a program and used directly or indirectly in the manufacture of hardware comprising the system. For example, the database may be a behavioral level description or a Register Transfer Level (RTL) description of hardware functionality in a high level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool, where the synthesis tool may synthesize the description to produce a netlist comprising a list of gates from a synthesis library. The netlist comprises a collection of gates that also represent the functionality of the hardware comprising the system. The netlist can then be configured and routed to produce a data set describing the geometry to be applied to the mask. The mask may then be used in various semiconductor fabrication steps to produce a semiconductor circuit corresponding to the system. In other examples, the database itself may alternatively be a netlist (with or without a synthesis library) or a data set.

The present disclosure may also have the following configuration:

1. an apparatus comprising switches for operating a switched capacitor converter, the switches configured to transition between a first state and a second state to transition a switched capacitor network between a first switch arrangement and a second switch arrangement, the apparatus further comprising a first die and a second die, wherein the switches comprise phase switches and stacked switches, wherein the first die and the second die are configured according to a configuration selected from the group consisting of a first configuration and a second configuration, wherein in the first configuration, the phase switches are on the first die and the stacked switches are on the second die, and wherein in the second configuration, a controller is on the first die and the switches are on the second die.

2. The apparatus of scheme 1, further comprising a first controller, a second controller, and an inter-controller junction, wherein the first controller controls a switch on the first die, wherein the second controller controls a switch on the second die, wherein the inter-controller junction provides a link between the first controller and the second controller to allow operation of the first switch to be at least partially dependent on operation of the second switch and to allow operation of the second switch to be at least partially dependent on operation of the first switch.

3. The apparatus of scheme 2, wherein the first controller is on the first die and wherein the second controller is on the second die, and wherein the inter-controller junction extends between the first die and the second die.

4. The apparatus of scheme 2, further comprising a third die and a fourth die, wherein the first controller is on the third die and wherein the second controller is on the fourth die, and wherein the inter-controller junction extends between the third die and the fourth die.

5. The apparatus of any of schemes 1-4, wherein the switched capacitor converter is a two-phase converter, wherein the apparatus further comprises a third die and a fourth die, wherein the stacked switch comprises a first stacked switch set and a second stacked switch set, the first stacked switch set and the second stacked switch set are each associated with one of two phases, the first stacked switch set on the second die and the second stacked switch set on the fourth die, wherein the phase switches comprise a first set of phase switches and a second set of phase switches, each associated with one of the two phases, and the first set of phase switches is on the first die and the second set of phase switches is on the third die.

6. The apparatus of any of schemes 1-4, further comprising a charge transfer capacitor connected to the stacked switch and to the phase switch.

7. The apparatus of any of schemes 1-4, wherein the charge transfer capacitors have capacitances that are a function of voltages applied across the charge transfer capacitors, wherein in operation the charge transfer capacitors maintain different maximum voltages, and wherein the charge transfer capacitors are selected such that at the respective maximum voltages, the charge transfer capacitors all have the same capacitance.

8. The apparatus of scheme 6, further comprising a third die, wherein the charge transfer capacitor is integrated into the third die.

9. The apparatus of scheme 6, wherein the charge transfer capacitor is a discrete capacitor connected to the first die and the second die.

10. The apparatus of scheme 6, wherein the first die and the second die are connected via an inter-die joint having a length corresponding to a distance between positive and negative terminals of the charge transfer capacitor.

11. The apparatus of scheme 6, further comprising an inter-die joint for connecting the first die and the second die, wherein the first die and the second die include a first terminal for connecting to a positive terminal of the charge transfer capacitor, and a second terminal for connecting to a negative terminal of the charge transfer capacitor, wherein the first terminal and the second terminal are configured on opposite ends of the inter-die joint, wherein the charge transfer capacitor is oriented such that: the positive terminal of the charge transfer capacitor is closer to the first terminal than the distance of the positive terminal to the second terminal, and the negative terminal of the charge transfer capacitor is closer to the second terminal than the distance of the negative terminal of the charge transfer capacitor to the first terminal.

12. The apparatus of any of schemes 1-4, further comprising an inter-die joint for connecting the first die and the second die, wherein the inter-die joint is folded such that the first die and the second die are located on different planes.

13. The apparatus of any of schemes 1-4, wherein the first die and the second die are located on different planes.

14. The apparatus of any of schemes 1-4, wherein the switched capacitor converter is a multi-phase converter, the apparatus further comprising a third die, wherein the phase switches comprise a first set of phase switches associated with a first phase and a second set of phase switches associated with a second phase, wherein the first set of phase switches is on the first die and the second set of phase switches is on the second die.

15. The apparatus of scheme 14, further comprising a first charge transfer capacitor bank and a second charge transfer capacitor bank, wherein the first charge transfer capacitor bank is connected between the first die and the second die, and wherein the second charge transfer capacitor bank is connected between the third die and the second die.

16. The apparatus of scheme 10, wherein the inter-die joint has a first region and a second region, wherein during operation the first region carries more current than the second region, and wherein the first region is wider than the second region.

17. The apparatus of any of schemes 1-4, further comprising a substrate and a charge transfer capacitor, wherein the substrate supports the charge transfer capacitor, the first die, and the second die.

18. The apparatus of scheme 17, further comprising a package, wherein the first die and the second die are in the package.

19. The apparatus of scheme 18, wherein the first die and the second die are coplanar.

20. The apparatus of scheme 17, wherein device sides of the first and second dies face the substrate, and wherein conductive bumps between the device sides and the substrate provide electrical communication between the dies and the charge transfer capacitors.

21. The apparatus of scheme 18, wherein the first die and the second die are on different planes within the package.

22. The apparatus of any of schemes 1-4, further comprising a substrate, a package, a third die, and a charge transfer capacitor, wherein the charge transfer capacitor is integrated into the third die, wherein the substrate supports the package, wherein the package comprises the first die, the second die, and the third die, wherein the first die, the second die, and the third die are distributed in different layers of the package.

23. The apparatus of scheme 22, wherein the package comprises a first tier and a second tier, wherein the first die and the second die are in the first tier and the third die is in the second tier.

24. The apparatus of scheme 22, wherein the package comprises a first tier and a second tier, wherein the first die and the third die are in the first tier and the second die is in the second tier.

25. The apparatus of scheme 22, wherein the package comprises a first layer, a second layer, and a third layer, wherein each layer contains at most one die.

26. The apparatus of scheme 25, wherein the second tier is between the first tier and the third tier, and wherein the third die is in the second tier.

27. The apparatus of any of schemes 1-4, further comprising a substrate, a package, an inductor, and a charge transfer capacitor, wherein the substrate supports the package, wherein the package comprises a lower layer and an upper layer, wherein the lower layer is closer to the substrate than the upper layer, wherein a die is in the lower layer, wherein the charge transfer capacitor is in the upper layer, and wherein the inductor is on the substrate outside of the package, wherein the die is selected from the first die and the second die.

28. The apparatus of scheme 27, wherein a device side of the die faces the substrate, the apparatus further comprising a first interconnect layer, a second interconnect layer, and conductive bumps, wherein the first interconnect layer connects the charge transfer capacitors to the die, wherein the second interconnect layer connects the die to the charge transfer capacitors and the conductive bumps, and the conductive bumps connect the package with the inductor.

29. The apparatus of scheme 27, wherein a device face of the die faces away from the substrate, the apparatus further comprising a heat spreader, thermally conductive bumps, a first interconnect layer, a second interconnect layer, and electrically conductive bumps, wherein the first interconnect layer connects the charge transfer capacitors to the die, wherein the second interconnect layer connects the die to the charge transfer capacitors and the electrically conductive bumps, wherein the electrically conductive bumps connect the package with the inductor, wherein the heat spreader faces the substrate, wherein the thermally conductive bumps connect the heat spreader to the substrate, and wherein the thermally conductive bumps carry heat only and are electrically disconnected from the circuit.

30. The apparatus of scheme 27, wherein the device face of the die faces away from the substrate, wherein the apparatus further comprises a heat spreader, a thermal pad, a first interconnect layer, a second interconnect layer, and an electrically conductive pad, wherein the first interconnect layer connects the charge transfer capacitor to the die, wherein the second interconnect layer connects the die to the charge transfer capacitor and the electrically conductive pad, wherein the electrically conductive pad connects the package with the inductor, wherein the heat spreader faces the substrate, wherein the thermal pad connects the heat spreader to the substrate, and wherein the thermal pad carries heat only and is electrically isolated from the inductor, the charge transfer capacitor, and the die.

31. The apparatus of any of schemes 1-4, further comprising a substrate, a package, an inductor, and a charge transfer capacitor, wherein the substrate supports the package, wherein the package comprises a lower layer and an upper layer, wherein the inductor is in the package, wherein the lower layer is closer to the substrate than the upper layer, wherein a die is in the lower layer, wherein the charge transfer capacitor is in the upper layer, and wherein the die is selected from the first die and the second die.

32. The apparatus of aspect 31, wherein the inductor is configured in the upper layer.

33. The apparatus of scheme 31, wherein the inductor comprises an inductor core in the lower layer and conductive traces forming windings of the inductor.

34. The apparatus of scheme 31, further comprising a heat spreader and thermally conductive bumps, wherein a device face of a chip faces away from the substrate, wherein the heat spreader faces the substrate, wherein the thermally conductive bumps connect the heat spreader to the substrate, and wherein the thermally conductive bumps carry heat only and are isolated from the die, the charge transfer capacitor, and the inductor.

35. The apparatus of scheme 1, further comprising a regulator switch, wherein the regulator switch is in the first die.

36. An apparatus for power conversion, the apparatus comprising a conversion stage for converting a first voltage to a second voltage, wherein the conversion stage comprises a switch network having a plurality of switches that each transition between a first state and a second state, the switches being independently controlled to transition the switch network between at least a first switch arrangement and a second switch arrangement, wherein the apparatus further comprises a filter and a controller, wherein the filter is configured to connect the conversion stage to a regulator, and wherein the controller controls the switch network by transitioning the switch network between the first switch arrangement and the second switch arrangement.

37. The apparatus of scheme 36, wherein the filter comprises an LC filter.

38. The apparatus of claim 36 or 37, wherein the filter comprises an inductance that maintains a peak-to-peak voltage ripple and supports an inductor current delivered into the load when operating at a particular switching frequency, the inductor current defining an average inductor current.

39. The apparatus of scheme 38, wherein the inductance is proportional to a value selected by dividing the peak-to-peak voltage ripple by a product of the average inductor current and the switching frequency.

40. The apparatus of scheme 39, wherein the inductance is obtained by multiplying the value by a proportionality constant, the proportionality constant being 13/24.

41. The apparatus of claim 36 or 37, further comprising the conditioning circuit.

42. The apparatus of scheme 37, wherein the filter is configured to connect the transform stage to more than one regulator.

43. The apparatus of claim 36 or 37, further comprising a plurality of conditioning circuits, wherein the filter connects the conversion stage to all of the conditioners.

44. The apparatus of claim 36 or 37, wherein the conversion stage comprises a plurality of switching networks, and wherein the filter is configured to connect all of the switching networks to a regulation circuit.

45. The apparatus of claim 36 or 37, wherein the conversion stage comprises a plurality of cells in series, each cell comprising a switching network in series with a filter.

46. The apparatus of scheme 1, wherein the first die and the second die are configured according to the first configuration.

47. The apparatus of scheme 1, wherein the first die and the second die are configured according to the second configuration.

48. The apparatus of claim 36 or 37, wherein the filter comprises an inductance that constrains a rate at which an amount of charge stored in a capacitor in the conversion stage changes in response to transitions between the first and second switch arrangements.

49. The apparatus of claim 36 or 37, wherein the conversion stage is adiabatically charged.

50. The apparatus of scheme 1, wherein a rate at which a charge present on a capacitor in the switched capacitor network changes is constrained by inductance in response to a transition between the first and second switching arrangements.

Having described one or more preferred embodiments, it will be apparent to those of ordinary skill in the art that other embodiments incorporating such circuits, techniques, and concepts may be used. Accordingly, the scope of patented should not be limited to the described embodiments, but should be limited only by the spirit and scope of the appended claims.