CN1128382A - Single-color delta display device - Google Patents
Single-color delta display device Download PDFInfo
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- CN1128382A CN1128382A CN 95101409 CN95101409A CN1128382A CN 1128382 A CN1128382 A CN 1128382A CN 95101409 CN95101409 CN 95101409 CN 95101409 A CN95101409 A CN 95101409A CN 1128382 A CN1128382 A CN 1128382A
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Abstract
The display device includes at least one single-color delta treatment unit, one shared controller and one time-sequence generator. Delta parameter is stored in memory, read out by positioning shared controller, and after being compared with the horizontal and vertical scanning signal from the time-sequence generator, program signal produced by the shared controller determines one single-color delta treatment unit for delta treatment. Single-color delta treatment unit controls the color code signal output based on delta parameter and controls its depth through detection.
Description
The present invention relates to a display device, and more particularly to a monochrome delta display device.
The display device is used to process the image signal to some extent, for example, to perform address coding and other procedures, and then to convert the image signal by the digital-to-analog converter and send it to the screen for output.
In view of the fact that the conventional display device only processes the image signal slightly, and outputs the image signal on the screen almost directly, it has almost nothing to do with the complexity of the display content. Therefore, all the processing for displaying the stereoscopic graphics completely depends on the computer system to be executed by matching with the software program. Therefore, the workload of the computing unit of the system is heavy, the output efficiency of the image signal is reduced, the image display efficiency is not good, and the bottleneck of improving the image processing capability of the computer system is formed.
In fact, the image content outputted on the screen is mainly composed of polygons of various colors, and vivid pictures can be generated by the combination of geometric figure changes of different colors. The most basic shape of the various polygons is a triangle, i.e., the desired polygon will be assembled by a number of appropriately selected triangles.
Therefore, the present invention is directed to a triangle display device for generating triangles on a screen, so as to reduce the workload of a computing unit of a computer system and improve the efficiency of graphic display.
To achieve the above objective, the present invention provides a monochrome triangle display device, which comprises at least one monochrome triangle processing unit, a common controller and a timing generator. The triangle parameters are stored in a memory device, the values are read by addressing of a common controller, and after being compared with horizontal and vertical scanning signals sent by a time sequence generator, a single-color triangle processing unit is determined to carry out triangle processing work by program signals generated by the common controller. The monochrome triangle processing unit controls the color code signal output according to the triangle parameters, and the output has a depth relation in a depth detection mode. The processing of the monochrome triangular display device can greatly improve the display efficiency of the three-dimensional graph and can avoid the performance requirement on a central processing unit of a system.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail as follows:
brief description of the drawings:
FIG. 1 defines the triangle elements of a preferred embodiment of the present invention.
FIG. 2 is a diagram of a triangle parameter address relationship in accordance with a preferred embodiment of the present invention.
FIG. 3 is a circuit block diagram of a preferred embodiment of the present invention.
FIG. 4 is a circuit diagram of a common controller of the preferred embodiment of FIG. 3.
FIG. 5 is a schematic diagram of a preferred embodiment of the monochrome triangle processing unit of FIG. 3.
FIG. 6 is a circuit diagram of the depth detector of FIG. 5 in accordance with a preferred embodiment.
Referring first to FIG. 1, the definitions of each triangle ABC element shown according to the present invention are illustrated. Wherein,
xa is the horizontal coordinate of the vertex A of the triangle;
ya, Yb and Yc are vertical coordinates of three vertexes A, B and C of the triangle;
X1is the horizontal coordinate of the left boundary of the triangle;
X2is a horizontal coordinate of the right boundary of the triangle; and
mab, Mbc, and Mac are the inverse of the triangle trilateral slope, respectively.
Thus, each horizontal line down from the triangle vertex (Xa, Ya) falls within the triangle's area, i.e., X1And X2A defined area satisfying the following relationship:
Ya＋0：X1＝Xa，X2＝Xa
first horizontal line Ya + 1: x1＝Xa＋Mab＝X′1＋Mab；
X2＝Xa＋Mac＝X′2＋Mac；
Second horizontal line Ya + 2: x1＝(Xa＋Mab)＋Mab＝X′1＋Mab；
X2＝(Xa＋Mac)＋Mac＝X′2＋Mac；
Third horizontal line Ya + 3: x1＝[(Xa＋Mab)＋Mab]＋Mab＝X′1＋Mab；
X2＝[(Xa＋Mac)＋Mac]＋Mac＝X′2＋Mac；
I.e. the area of each horizontal line falling within the triangle, its two end points X1And X2Respectively, the horizontal coordinate values of the two end points of the upper horizontal line are added with the reciprocal value of the slope of the side line.
And when the horizontal line falls below the vertex B, the left endpoint X1The accumulation is performed with Mbc until the vertex C.
The invention outputs triangles on the screen according to the principle. The triangle itself uses two data of the hierarchy code Z and the color code CC as the display parameters. Please refer to fig. 2, which shows the address relationship of the parameter data structure in the memory.
The overall structure of a triangular display device according to a preferred embodiment of the present invention is shown in FIG. 3. The plural monochrome triangle processing units 11, 13 and 15, etc. are controlled by the common controller 21 for data transmission and the hierarchy code Z, and the graphics data is converted into color signals by the digital-to-analog converter 27 for output. There is also a timing generator 25 that provides two sets of signals HPC and VPC for each monochrome triangle processing unit, which are the horizontal and vertical reference positions of the scan lines, i.e., the horizontal scan signal and the vertical scan signal, respectively. The parameters for the triangle are stored in a memory device, such as a memory (ROM or SRAM)23, and provided to the individual monochrome triangle processing units via a common controller 21. The storage mode is shown as a parameter data structure in fig. 2.
The structure of the common controller 21 is shown in fig. 4. The state controller 31 controls the processing procedure of the entire circuit. The state controller 31 is connected to the timing generator 25, receives the horizontal scanning signal HPC, and sequentially sends out the program signals to the individual monochrome triangle processing units. The address generator 35 is connected to the state controller 31, the memory 23 and the monochrome triangle processing unit. The address generator 35 is controlled by the state controller 31 and is addressed to the memory 23 to read the triangle parameters stored in the memory 23, i.e. the parameters of the triangle shown in fig. 2. The vertical detector 33 is connected to the memory 23, the timing generator 25 and the state controller, the vertical detector 33 is used to detect the position represented by the vertical scanning signal VPC, which is compared with the vertical position of the vertex in the triangle parameter, i.e. the above-mentioned Ya, and if the relationship between Ya and VPC + 1 indicates that the next horizontal scanning line is to start displaying the triangle, the state controller 31 is required to send out the program signal, and according to the instruction of the signal, a triangle processing unit can be selected to take charge of various processing tasks of the triangle to be displayed. The triangle boundary generator 37 is connected to the memory device 23, the state controller 31 and each monochrome triangle processing unit for generating the parameters required by the monochrome triangle processing unit selected according to the program signals, including the left and right boundary values of the triangle.
The vertical detector 33 is a comparator, which takes the vertical scanning signal VPC and the output parameter of the memory device 23 as its two input signals, and sends the result generated by the comparator, that is, when Ya equals VPC + 1, to the state controller 31. As for the parameter generator 37, the triangle boundary generator is an accumulator comprising a register 38 and an adder 39. The register 38 is connected to each monochrome triangle processing unit for storing the parameters of the triangle. Adder 39 couples register 38 and memory 23 and takes the values of both to add them to correct the left and right boundary values to form a triangle. The tri-state buffers 36a and 36b connect the memory device 23 and the triangle boundary generator 37 and are controlled by the state controller 31 to select appropriate parameters to the particular monochrome triangle processing unit as appropriate.
A preferred embodiment of the monochrome triangle processing unit of the present invention, which is responsible for triangle processing, is shown in FIG. 5. The program controller 41 is connected to the state controller 31 in the common controller 21, and receives a program signal as an identification mark of the current working state of the monochrome triangle processing unit. The pointer register 42 is connected to the address generator 35 in the controller 21 for storing the triangle parameter used in the current processing procedure, and the address value in the memory 23. The registers 43, 45, and 47 respectively obtain and register the left and right boundary values and the color code value of the triangle from the parameter generator 37 in the common controller. Comparator 44 and comparator 46 then take the parameter values of registers 43 and 45, respectively, and compare them with horizontal scanning signal HPC from timing generator 25. Thus, when the horizontal position represented by the horizontal scanning signal HPC falls between the left and right boundaries of the triangle, i.e., for the left boundary parameter X1And the right boundary parameter X2In terms of having HPC ≧ X1And HPC is less than or equal to X2In the relation of (1), the outputs of the two comparators 44 and 46 control the depth detector 50 and then the tri-state buffer 48 to output the color code signal stored in the register 47 to the digital-to-analog converter 27 for conversion into three colors of red, green and blueA signal.
In order to make the displayed triangle have the depth hierarchy, a depth detector 50 can be configured in the monochrome triangle processing unit. Register 49 retrieves the level parameter storage from memory 23 and provides a reference for level comparison by depth detector 50. The depth detector 50 is connected between the single color triangle processing units, and compares the level codes at the same horizontal and vertical positions, and outputs the color code to the digital-to-analog converter 27 by the processing unit where the lightest level code is located, thereby achieving the effect of depth.
Referring to FIG. 6, a preferred embodiment of the depth detector 50 is shown. After the depth comparison between the level code Zb obtained from the register 49 and the level code Zi from another depth comparator is performed in the comparator 52, the enable signal EN formed by the result of the comparators 44 and 46 is passed through the and gate 56 to control the multiplexer 54 to select one of the level codes Zb and Zi to output to the next depth detector, and the signal is denoted by ZO. Thus, when Zb is shallower than Zi and EN is the enable information, ZO is Zb; otherwise, ZO ═ Zi. And, through the control of the logical combination formed by OR gate 58 and AND gate 59, the output signal out is enabled only if this Zb is the lightest of all depth detectors with EN enabled, so that the color code is output through tri-state buffer 48.
The processing procedure of the monochrome triangle processing unit, i.e. the state of the program signal SC, can be generally divided into several stages, so that the state controller 31 can make the best judgment to select the applicable processing unit for triangle processing. For example, in the preferred embodiment of the present invention, there are four program states in total, including
SC is 0: indicating that the monochrome triangle processing unit is in a standby state;
SC 1: indicating that the monochrome triangle processing unit has just been set with a parameter index address and that the triangle parameter will be written to each register during the upcoming horizontal blanking period, e.g., registers 43 and 45 are written to X1And X2Register 47 with CC (color code) and register 49 with CCZb (hierarchical code);
SC 2: indicating that the triangle processed by the monochrome triangle processing unit is between Ya and Yb, and its X in the horizontal blanking period1And X2Adding Mab and Mac respectively; and
SC-3: indicating that the triangle processed by the monochrome triangle processing unit is between Yb and Yc, and its X in the horizontal blanking period1And X2Mbc and Mac must be added separately.
By the operation of the above-mentioned monochrome triangle display device, the horizontal scanning signal sent by the timing generator 25 is sent to each monochrome triangle processing unit and the common controller, so that the triangle parameter stored in the memory (ROM or RAM) is processed by a proper program and outputted to the digital-to-analog converter.
Therefore, the monochrome triangle display device of the present invention can directly generate the picture signals which originally need to consume a large amount of processing time of the central processing unit by the simple hardware structure and the simple triangle parameters, which not only improves the efficiency, but also can effectively improve the quality of the graphic display without depending on a computer system with stronger processing capability.
Although the present invention has been described with respect to one or more embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A monochrome delta display device is suitable for a display system having a memory device and a digital-to-analog converter; the display system stores the triangle parameters in the memory device, and the monochrome triangle display device reads the triangle parameters for processing and then sends the color codes to the digital-to-analog converter for output; it is characterized by comprising:
a time sequence generator for generating horizontal scanning signals and vertical scanning signals;
a common controller, coupled to the timing generator and the memory device, for generating address signals according to the horizontal scanning signals and the vertical scanning signals to address the memory device and read the triangle parameters; the common controller generates a program signal to define a triangle processing program; and
at least one monochrome triangle processing unit coupled to the common controller, the timing generator, and the digital-to-analog converter; the monochrome triangle processing unit is controlled by a program signal of the common controller, and provides the color code to the digital-to-analog converter for output according to a comparison result of a horizontal scanning signal of the time sequence generator and the triangle parameter so as to display a triangle.
2. The apparatus of claim 1, wherein the monochrome triangle processing unit comprises:
a program controller coupled to the common controller for receiving the program signal;
an index register coupled to the common controller for registering an address of the triangle parameter;
a first register coupled to the common controller for storing a first one of the triangular parameters;
a second register coupled to the common controller for storing a second one of the triangular parameters;
a first comparator, coupled to the first register and the timing generator, for comparing the horizontal scanning signal with the first parameter;
a second comparator coupled to the second register and the timing generator for comparing the horizontal scanning signal with the second parameter;
a third register coupled to the common controller for storing the color code in the triangular parameter; and
and the tri-state buffer is controlled by the first comparator and the second comparator, selects the color code stored in the third register and outputs the color code to the digital-to-analog converter.
3. The apparatus of claim 2, wherein the first parameter and the second parameter are a left boundary and a right boundary of a triangle to be displayed on a same horizontal line as the horizontal scan signal, respectively; the first comparator and the second comparator are used for determining whether the horizontal scanning signal falls in the triangle to be displayed or not so as to control the tri-state buffer to send out an appropriate color code signal.
4. The apparatus of claim 2, wherein the monochrome triangle processing unit further comprises a depth detector coupled between the comparator and the tri-state buffer, and a fourth register coupled between the common controller and the depth detector for storing the level code in the triangle parameter; the depth detectors of the monochrome triangle processing units are connected in series, and the respective hierarchy codes are compared in depth at the same horizontal scanning position and vertical scanning position to control the tri-state buffer to generate the appropriate color code output.
5. The apparatus of claim 4, wherein the depth detector comprises:
a comparator for comparing the depth of the layer code of the fourth register with an input layer code;
a multiplexer controlled by the comparator to select a shallower one of the hierarchical codes for output; and
and the logic gate combination is controlled by the comparator, and controls the three-state buffer to output the color code of the third register when the hierarchy code of the fourth register is the lightest of the hierarchy codes.
6. The apparatus of claim 3, wherein the common controller comprises:
a state controller, coupled to the timing generator and the monochrome triangle processing unit, for receiving the horizontal scanning signal and generating a program signal;
an address generator, coupled to the state controller, the memory device and the monochrome triangle processing unit, controlled by the state controller to generate successive addresses, read the triangle parameters in the memory device, and store the addresses in the index register of the monochrome triangle processing unit;
a vertical detector coupled to the memory device, the timing generator and the state controller for requesting the state controller to send a program signal when the vertical scanning signal is detected to be about to display a triangle in a next horizontal scanning line; and
a parameter generator coupled to the address generator, the memory device, and the monochrome triangle processing unit to send the triangle parameter values to the registers of the monochrome triangle processing unit.
7. The apparatus of claim 6, wherein the vertical detector is a comparator for comparing the vertical scanning signal with a vertical position parameter of a vertex of a triangle among the triangle parameters, and the output signal requests the state controller to generate the program signal when the vertical scanning signal represents a position higher by one horizontal line than the vertical position of the vertex.
8. The apparatus of claim 6, wherein the parameter generator comprises:
at least one register coupled to the registers of the monochrome triangle processing unit to store the parameters; and
an adder, coupled to the register and the memory device, for modifying the parameter values to provide the appropriate parameters to the monochrome triangle processing unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN95101409A CN1076496C (en) | 1995-01-20 | 1995-01-20 | Single-color delta display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN95101409A CN1076496C (en) | 1995-01-20 | 1995-01-20 | Single-color delta display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1128382A true CN1128382A (en) | 1996-08-07 |
| CN1076496C CN1076496C (en) | 2001-12-19 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN95101409A Expired - Lifetime CN1076496C (en) | 1995-01-20 | 1995-01-20 | Single-color delta display device |
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Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0350686A (en) * | 1989-07-18 | 1991-03-05 | Nec Corp | Graphic processing system |
| AU7313491A (en) * | 1990-02-16 | 1991-09-03 | Silicon Graphics, Inc. | Method and apparatus for providing a visually improved image by converting a three-dimensional quadrilateral to a pair of triangles in a computer system |
| JP3050686B2 (en) * | 1992-03-26 | 2000-06-12 | 松下電工株式会社 | Wiring equipment |
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Expiration termination date: 20150120 Granted publication date: 20011219 |