CN112836462B - Standard cell preparation method, standard cell, integrated circuit and system chip - Google Patents
Standard cell preparation method, standard cell, integrated circuit and system chip Download PDFInfo
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Abstract
The application relates to a standard cell preparation method, a standard cell, an integrated circuit and a system chip, wherein the method comprises the steps of providing a first standard cell, wherein the first standard cell comprises at least one standard threshold voltage device, and the standard threshold voltage device is manufactured by adopting a fully-depleted silicon-on-insulator process; forming a back pressure through hole which extends downwards along the thickness direction of the first standard unit and penetrates through the buried oxide layer; forming a conductive plug in the back pressure through hole; and applying a forward bias to the other end of the conductive plug so that the switching speed of the first standard cell reaches the switching speed of a second standard cell, wherein the height of the first standard cell is smaller than that of the second standard cell. The method and the device realize that a user brings larger driving current under the condition of the same silicon process unit library area when using a new standard unit library design, and effectively meet the requirement of the fully-depleted silicon-on-insulator process design.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a standard cell manufacturing method, a standard cell, an integrated circuit, and a system chip.
Background
The development and design of the current standard cell library (Standard Cell Library) is focused mainly on the planar Bulk Silicon (Bulk Silicon) process and the fin field effect transistor (FinFET) process afterwards. For the fully depleted silicon on insulator process, the standard cell library on the planar body silicon process is often simply used directly on the fully depleted silicon on insulator process. The standard cell library is not optimized and modified by utilizing the unique process characteristics of fully depleted silicon on insulator.
The selection of standard cell libraries is important, and the selection of a suitable set of libraries is important for chip timing closure, physical closure, and ultimately the performance power area (Performance Power Area, PPA) of the chip. A typical process will have cell libraries of different heights available for selection. The cell library height is differentiated by track. In general, the greater the height, the greater the area occupied and the faster the speed provided. The higher the power consumption that follows. Conversely, the lower the height, the smaller the footprint, the slower the speed provided, but the lower the power consumption.
However, fully depleted silicon on insulator borrows the standard cell library of the conventional bulk silicon process, and the standard cell library of fully depleted silicon on insulator along with the conventional bulk silicon process does not take advantage of the technology itself. Instead, some designs optimized for bulk silicon processes become negative on fully depleted silicon on insulator. How to bring larger driving current under the condition of the same-volume silicon process unit library area, and meet the requirements of fully-depleted silicon-on-insulator process design becomes one of the technical problems to be solved.
Disclosure of Invention
Based on this, it is necessary to provide a standard cell manufacturing method, a standard cell, an integrated circuit and a system chip for solving the technical problems in the background art, so that a larger driving current is brought under the condition of equivalent silicon process cell library area, and the requirements of fully-depleted silicon-on-insulator process design are effectively met.
To achieve the above and other objects, a first aspect of the present application provides a standard cell preparation method, including:
providing a first standard cell, wherein the first standard cell comprises at least one standard threshold voltage device, and the standard threshold voltage device is manufactured by adopting a fully-depleted silicon-on-insulator process;
forming a back pressure through hole which extends downwards along the thickness direction of the first standard unit through the back pressure applying position of the front surface of the first standard unit and penetrates through the buried oxide layer;
forming a conductive plug in the back pressure through hole, wherein one end of the conductive plug is electrically connected with one side of the bottom silicon layer, which is close to the buried oxide layer;
and applying a forward bias to the other end of the conductive plug so that the switching speed of the first standard cell reaches the switching speed of a second standard cell, wherein the height of the first standard cell is smaller than that of the second standard cell.
In the method for manufacturing a standard cell in the above embodiment, by providing a first standard cell including at least one standard threshold voltage device manufactured by using a fully depleted silicon-on-insulator process, a Back-pressure through hole is formed in the front side of the first standard cell by using the Back Bias process (Back Bias) characteristic of the fully depleted silicon-on-insulator, the Back-pressure through hole extends downwards along the thickness direction of the first standard cell through the Back-pressure applying portion of the front side of the first standard cell and penetrates through the buried oxide layer, and then a conductive plug is formed in the Back-pressure through hole, and one end of the conductive plug is electrically connected with one side of the underlying silicon layer close to the buried oxide layer; to apply a forward bias to the other end of the conductive plug such that the switching speed of the first standard cell reaches the switching speed of a second standard cell, wherein the height of the first standard cell is smaller than the height of the second standard cell. The method and the device utilize the back pressure characteristic specific to the silicon-on-insulator process, realize that a user brings larger driving current under the condition of the area of the unit library of the equivalent silicon process when utilizing the new standard unit library design, and effectively meet the requirement of the fully-depleted silicon-on-insulator process design.
In one embodiment, the back pressure via is formed using a through silicon via technique.
In one embodiment, the first standard cell comprises at least one of a standard cell, or standard cell, a non-standard cell, a flip-flop standard cell, and a latch standard cell.
In one embodiment, an increase in forward bias voltage is applied to the other end of the conductive plug, which is positively correlated to an increase in gate current of the first standard cell.
In one embodiment, after the conductive plug is formed in the back pressure through hole, the method further includes a step of forming a bonding pad;
the bonding pad is electrically connected with the conductive plug, and the orthographic projection area of the bonding pad on the front surface of the first standard unit is larger than zero. In one embodiment, the height of the first standard cell is any one of 6.5T, 7T or 9T;
the height of the second standard cell is any one of 7T, 9T or 12T.
In one embodiment, if the height of the first standard cell is 6.5T and the height of the second standard cell is 9T, the voltage value of the forward bias voltage applied to the first standard cell is greater than 0 and less than or equal to 2Vdd, where Vdd is the nominal voltage value in the determination process.
A second aspect of the present application provides a standard cell made using any of the standard cell preparation methods described in the examples herein.
In the standard cell in the above embodiment, the driving current of the standard cell is improved under the area of the equivalent silicon process cell library by utilizing the back pressure characteristic specific to the silicon on insulator process, so that the requirement of fully depleted silicon on insulator process design is effectively met under the area of the equivalent silicon process cell library when a user designs the standard cell.
A third aspect of the present application provides an integrated circuit comprising a first macroblock, a second macroblock, and at least one standard cell as described in any of the embodiments of the present application, the standard cell being located between the first macroblock and the second macroblock. Due to the fact that the back pressure characteristic specific to the silicon-on-insulator process is utilized, the driving current of the standard unit is improved under the condition of the equivalent silicon process unit library area, when a user designs by utilizing the standard unit, the requirement of fully-depleted silicon-on-insulator process design is effectively met under the condition of the equivalent silicon process unit library area, and therefore the performance and stability of an integrated circuit manufactured by utilizing the standard unit are effectively improved.
A fourth aspect of the present application provides a system-on-chip comprising a memory and a processor comprising an integrated circuit as described in any of the embodiments of the present application. Due to the fact that the back pressure characteristic specific to the silicon-on-insulator process is utilized, the driving current of the standard unit is improved under the condition of the equivalent silicon process unit library area, when a user designs by utilizing the standard unit, the requirement of fully-depleted silicon-on-insulator process design is effectively met under the condition of the equivalent silicon process unit library area, and therefore the performance and stability of a system chip manufactured by utilizing the standard unit are effectively improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other embodiments of the drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a standard cell manufacturing method according to a first embodiment of the present application;
FIG. 2 is a schematic flow chart of a standard cell manufacturing method according to a second embodiment of the present application;
FIG. 3 is a schematic flow chart of a standard cell manufacturing method according to a third embodiment of the present application;
FIG. 4 is a schematic flow chart of a standard cell manufacturing method according to a fourth embodiment of the present disclosure;
FIG. 5 is a schematic cross-sectional view of a standard cell according to a fifth embodiment of the present application;
FIG. 6 is a schematic cross-sectional view of a standard cell according to a sixth embodiment of the present application;
fig. 7 is an application scenario schematic diagram of a standard cell provided in a seventh embodiment of the present application;
fig. 8 is a schematic architecture diagram of an integrated circuit according to an eighth embodiment of the present application.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
The multilayer structure can be formed layer by layer or integrally; wherein, the two adjacent layers of structures can be contacted or isolated from each other.
Please refer to fig. 1 to 8. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concepts of the application by way of illustration, and only the components related to the application are shown in the illustration, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Referring to fig. 1, in one embodiment of the present application, a standard cell preparation method is provided, including:
step 22: providing a first standard cell, wherein the first standard cell comprises at least one standard threshold voltage device, and the standard threshold voltage device is manufactured by adopting a fully-depleted silicon-on-insulator process;
step 24: forming a back pressure through hole which extends downwards along the thickness direction of the first standard unit through the back pressure applying position of the front surface of the first standard unit and penetrates through the buried oxide layer;
step 26: forming a conductive plug in the back pressure through hole, wherein one end of the conductive plug is electrically connected with one side of the bottom silicon layer, which is close to the buried oxide layer;
step 28: and applying a forward bias to the other end of the conductive plug so that the switching speed of the first standard cell reaches the switching speed of a second standard cell, wherein the height of the first standard cell is smaller than that of the second standard cell.
Specifically, please continue to refer to fig. 1, by setting a first standard cell including at least one standard threshold voltage device manufactured by using a fully depleted silicon-on-insulator process, forming a Back pressure through hole on the front side of the first standard cell by using the Back Bias process (Back Bias) characteristic of the fully depleted silicon-on-insulator, wherein the Back pressure through hole extends downwards along the thickness direction of the first standard cell through the Back pressure applying position of the front side of the first standard cell and penetrates through the buried oxide layer, and then forming a conductive plug in the Back pressure through hole, wherein one end of the conductive plug is electrically connected with one side of the bottom silicon layer close to the buried oxide layer; to apply a forward bias to the other end of the conductive plug such that the switching speed of the first standard cell reaches the switching speed of a second standard cell, wherein the height of the first standard cell is smaller than the height of the second standard cell. The method and the device utilize the back pressure characteristic specific to the silicon-on-insulator process, realize that a user brings larger driving current under the condition of the area of the unit library of the equivalent silicon process when utilizing the new standard unit library design, and effectively meet the requirement of the fully-depleted silicon-on-insulator process design.
As an example, referring to step S22 in fig. 1 and fig. 5, a first standard cell is provided that includes at least one standard threshold voltage device, and the standard threshold voltage device is fabricated using a fully depleted silicon-on-insulator process.
As an example, referring to fig. 5, a first standard cell is provided, which includes an SOI substrate and a gate 60 formed on one side of the SOI substrate, wherein the source 40 and the drain 50 are formed on two sides of the gate 60, respectively, the SOI substrate includes a bottom silicon layer 10, a middle oxygen-buried layer 20 and a top silicon layer (not shown) stacked in sequence from bottom to top, a trench structure 30 is formed in the SOI substrate, the trench structure 30 extends downwards from an upper surface of the top silicon layer, sequentially penetrates through the top silicon layer and the middle oxygen-buried layer 20 and extends into the bottom silicon layer 10, the trench structure 30 is used for defining a plurality of active regions, the trench structure 30 may include a liner layer 31 and an oxide layer 32 stacked in sequence from outside to inside, the source 40 and the drain 50 are both formed in the active regions, and the gate 60 is formed directly above the trench structure 30. Forming a Back pressure through hole 70 on the front surface of the first standard cell by utilizing the Back Bias process (Back Bias) characteristic of the fully depleted silicon on insulator, wherein the Back pressure through hole 70 extends downwards along the thickness direction OX of the first standard cell and penetrates through the buried oxide layer 20 through the Back pressure applying position of the front surface of the first standard cell, then forming a conductive plug 71 in the Back pressure through hole 70, and one end of the conductive plug 71 is electrically connected with one side of the bottom silicon layer 10 close to the buried oxide layer 20; to apply a forward bias to the other end of the conductive plug 71 so that the switching speed of the first standard cell reaches the switching speed of the second standard cell, wherein the height of the first standard cell is smaller than the height of the second standard cell. The method and the device utilize the back pressure characteristic specific to the silicon-on-insulator process, realize that a user brings larger driving current under the condition of the area of the unit library of the equivalent silicon process when utilizing the new standard unit library design, and effectively meet the requirement of the fully-depleted silicon-on-insulator process design.
As an example, referring to fig. 2, in one embodiment of the present application, a through-silicon via technology is used to form a back pressure via 70, so as to form a conductive plug 71 in the back pressure via 70, where one end of the conductive plug 71 is electrically connected to a side of the underlying silicon layer 10 close to the buried oxide layer 20; to apply a forward bias to the other end of the conductive plug 71 so that the switching speed of the first standard cell reaches the switching speed of the second standard cell. As an example, referring to fig. 3, in one embodiment of the present application, an increase in forward bias is applied to the other end of the conductive plug, which is positively correlated with an increase in gate current of the first standard cell.
Specifically, in one embodiment of the present application, the greater the forward back pressure (Forward Back Bias, FBB) of an FDSOI transistor, the greater the gate current, the faster the speed. Such as: in the absence of forward back pressure FBB, the gate current of the transistor within a standard threshold voltage device is 1.0, noting that the switching speed is 1.0. If the increase of the forward back pressure FBB is 60%, the increase of the transistor current in the standard threshold voltage device may be 20%, and the gate current of the transistor in the standard threshold voltage device reaches 1.2, so that the switching speed thereof also reaches 1.2; if the increase in forward backpressure FBB is 120%, the transistor current increase in a standard threshold voltage device can be 40%, so its switching speed also reaches 1.4. Thus, the back pressure can be appropriately adjusted in accordance with the required switching speed of the second standard cell so that the switching speed of the first standard cell reaches the switching speed of the second standard cell, wherein the height of the first standard cell is smaller than the height of the second standard cell.
As an example, referring to fig. 4, in one embodiment of the present application, after the conductive plug is formed in the back pressure through hole, the method further includes a step of forming a pad; the bonding pad is electrically connected with the conductive plug, and the orthographic projection area of the bonding pad on the front surface of the first standard unit is larger than zero.
As an example, referring to fig. 6-7, in one embodiment of the present application, after forming the conductive plug 71 in the back pressure via 70, a pad 72 is formed at an end of the conductive plug 71 away from the buried oxide layer 20, so as to provide a forward bias to the first standard cell via the pad 72.
As an example, in one embodiment of the present application, the first standard cell includes at least one of a standard cell, or a standard cell, a non-standard cell, a flip-flop standard cell, and a latch standard cell.
As an example, in one embodiment of the present application, the height of the first standard cell is any one of 6.5T, 7T, or 9T; the height of the second standard cell is any one of 7T, 9T or 12T.
As an example, referring to fig. 7, in one embodiment of the present application, the height of the first standard cell may be set to 6.5T, and the voltage value of the forward bias voltage applied to the first standard cell through the pad 72 is greater than 0 and less than or equal to 2Vdd, where Vdd is a rated voltage value in a certain process, for example, the rated voltage value in a 40 nm process is typically 1.1V, so that the switching speed of the first standard cell reaches the switching speed of the second standard cell, and the height of the second standard cell is 9T.
Further, in one embodiment of the present application, a standard cell is provided that is made using any of the standard cell preparation methods described in the embodiments of the present application.
In the standard cell in the above embodiment, the driving current of the standard cell is improved under the area of the equivalent silicon process cell library by utilizing the back pressure characteristic specific to the silicon on insulator process, so that the requirement of fully depleted silicon on insulator process design is effectively met under the area of the equivalent silicon process cell library when a user designs the standard cell.
As an example, referring to fig. 8, in one embodiment of the present application, an integrated circuit 200 is provided, including a first macroblock 201, a second macroblock 202, and at least one standard cell 100 as in any of the embodiments of the present application, the standard cell 100 being located between the first macroblock and the second macroblock. The first macroblock 201 and the second macroblock 202 may be various hard macro Intellectual Property (IP). Each of the hard macro IPs may refer to reusable blocks implemented with a fixed layout and interconnection for performing the desired electrical functions. For example, hard macro IP may be referred to as a hard macro or macro-cell. The standard cell library may include information about a plurality of standard cells and may be stored in a computer-readable storage medium. Standard cells may refer to integrated circuit cells whose layout sizes meet desired (or alternatively, predetermined) rules. The height of the standard cell may be constant and the width of the standard cell may vary according to the standard cell. Standard cells may include single-height cells arranged on a row and multi-height cells corresponding to multiple rows. The standard cell may include an input pin and an output pin, may process an input signal received by the input pin, and may output an output signal through the output pin. Due to the fact that the back pressure characteristic specific to the silicon-on-insulator process is utilized, the driving current of the standard unit is improved under the condition of the equivalent silicon process unit library area, when a user designs by utilizing the standard unit, the requirement of fully-depleted silicon-on-insulator process design is effectively met under the condition of the equivalent silicon process unit library area, and therefore the performance and stability of an integrated circuit manufactured by utilizing the standard unit are effectively improved.
In one embodiment of the present application, at least one of the first macroblock 201 and the second macroblock 202 may be a memory block (e.g., static Random Access Memory (SRAM)).
Further, in one embodiment of the present application, a system-on-chip is provided, comprising a memory and a processor, the processor comprising an integrated circuit as described in any of the embodiments of the present application. Due to the fact that the back pressure characteristic specific to the silicon-on-insulator process is utilized, the driving current of the standard unit is improved under the condition of the equivalent silicon process unit library area, when a user designs by utilizing the standard unit, the requirement of fully-depleted silicon-on-insulator process design is effectively met under the condition of the equivalent silicon process unit library area, and therefore the performance and stability of a system chip manufactured by utilizing the standard unit are effectively improved.
It should be understood that, although the steps in the flowcharts of fig. 1-4 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps of fig. 1-4 may include multiple steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the steps or stages are performed necessarily occur sequentially, but may be performed alternately or alternately with at least a portion of the steps or stages in other steps or other steps.
Note that the above embodiments are for illustrative purposes only and are not meant to limit the present invention.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. A method of making a standard cell comprising:
providing a first standard cell, wherein the first standard cell comprises at least one standard threshold voltage device, and the standard threshold voltage device is manufactured by adopting a fully-depleted silicon-on-insulator process;
forming a back pressure through hole which extends downwards along the thickness direction of the first standard unit through the back pressure applying position of the front surface of the first standard unit and penetrates through the buried oxide layer;
forming a conductive plug in the back pressure through hole, wherein one end of the conductive plug is electrically connected with one side of the bottom silicon layer, which is close to the buried oxide layer;
and applying a forward bias to the other end of the conductive plug so that the switching speed of the first standard cell reaches the switching speed of a second standard cell, wherein the height of the first standard cell is smaller than that of the second standard cell.
2. The method of claim 1, wherein the back pressure via is formed using a through silicon via technique.
3. The method of claim 1, wherein the first standard cell comprises at least one of a standard cell, or a standard cell, a non-standard cell, a trigger standard cell, and a latch standard cell.
4. A method of manufacturing a standard cell according to any one of claims 1 to 3, wherein the increase in forward bias voltage applied to the other end of the conductive plug is positively correlated with the increase in gate current of the first standard cell.
5. A method of manufacturing a standard cell according to any one of claims 1 to 3, further comprising the step of forming a bonding pad after forming a conductive plug in the back pressure via hole;
the bonding pad is electrically connected with the conductive plug, and the orthographic projection area of the bonding pad on the front surface of the first standard unit is larger than zero.
6. A standard cell preparation method according to any one of claims 1-3, wherein:
the height of the first standard unit is any one of 6.5T, 7T or 9T;
the height of the second standard cell is any one of 7T, 9T or 12T.
7. The method of claim 6, wherein if the height of the first standard cell is 6.5T and the height of the second standard cell is 9T, the voltage value of the forward bias voltage applied to the first standard cell is greater than 0 and less than or equal to 2Vdd, wherein Vdd is the nominal voltage value in the determined process.
8. A standard cell produced by the method of any one of claims 1 to 7.
9. An integrated circuit, comprising:
a first macroblock;
a second macroblock; and
at least one standard cell according to claim 8, the standard cell being located between the first macroblock and the second macroblock; the first macroblock and the second macroblock are hard macro intellectual property IP or memory blocks.
10. A system-on-chip, comprising:
a memory;
a processor comprising the integrated circuit of claim 9.
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| US8878303B2 (en) * | 2012-12-28 | 2014-11-04 | Broadcom Corporation | Geometric regularity in fin-based multi-gate transistors of a standard cell library |
| US9852252B2 (en) * | 2014-08-22 | 2017-12-26 | Samsung Electronics Co., Ltd. | Standard cell library and methods of using the same |
| WO2016179113A1 (en) * | 2015-05-07 | 2016-11-10 | Finscale Inc. | Super-thin channel transistor structure, fabrication, and applications |
| US20170162557A1 (en) * | 2015-12-03 | 2017-06-08 | Globalfoundries Inc. | Trench based charge pump device |
| CN107293513B (en) * | 2016-04-11 | 2020-12-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN112149380B (en) * | 2020-09-29 | 2023-05-12 | 海光信息技术股份有限公司 | Index analysis method and device for standard cell library |
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