CN112835440A - Server power-on method, device, equipment and medium - Google Patents

Server power-on method, device, equipment and medium Download PDF

Info

Publication number
CN112835440A
CN112835440A CN202110075070.3A CN202110075070A CN112835440A CN 112835440 A CN112835440 A CN 112835440A CN 202110075070 A CN202110075070 A CN 202110075070A CN 112835440 A CN112835440 A CN 112835440A
Authority
CN
China
Prior art keywords
data
bmc
preset
target
server
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110075070.3A
Other languages
Chinese (zh)
Inventor
张国磊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Inspur Electronic Information Industry Co Ltd
Original Assignee
Inspur Electronic Information Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inspur Electronic Information Industry Co Ltd filed Critical Inspur Electronic Information Industry Co Ltd
Priority to CN202110075070.3A priority Critical patent/CN112835440A/en
Publication of CN112835440A publication Critical patent/CN112835440A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/602—Providing cryptographic facilities or services
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/77—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in smart cards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • General Health & Medical Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Bioethics (AREA)
  • Mathematical Physics (AREA)
  • Power Sources (AREA)

Abstract

The application discloses a power-on method of a server, which comprises the following steps: when the BMC in the server is powered on, reading target data of the SPI FLASH in the BMC on a preset address; the SPI FLASH comprises an SPI FLASH body, an FPGA and a target encryption algorithm, wherein the SPI FLASH body fixedly stores preset data on a preset address, and the FPGA pre-stores preset encryption data for encrypting the preset data by using the target encryption algorithm; encrypting the target data by using a target encryption algorithm to obtain target encrypted data; and when the target encrypted data is consistent with the preset encrypted data, powering on the BMC. Obviously, according to the method, the FPGA can power up the BMC only after the SPI FLASH in the BMC passes the verification, so that the safety and the reliability of the server in the operation process can be further improved through the setting mode. Correspondingly, the power-on device, the equipment and the medium of the server have the beneficial effects.

Description

Server power-on method, device, equipment and medium
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a medium for powering on a server.
Background
In the prior art, when a server is powered on, a power-on timing sequence of a BMC (Baseboard Management Controller) in the server is generally controlled by an FPGA (Field Programmable Gate Array), and each chip in the BMC is sequentially powered on by the power-on timing sequence, so as to complete a power-on process of the server. However, because the power-on method does not detect the legality of the BMC, the BMC is directly powered on and started, and thus great potential safety hazards are left for stable operation of the server. At present, no effective solution exists for the technical problem.
Therefore, how to further improve the security and reliability of the server in the operation process is a technical problem to be solved urgently by those skilled in the art.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a method, an apparatus, a device and a medium for powering on a server, so as to further improve the security and reliability of the server during the operation process. The specific scheme is as follows:
a power-on method of a server is applied to an FPGA and comprises the following steps:
when the BMC in the server is powered on, reading target data of the SPI FLASH in the BMC on a preset address; the SPI FLASH is fixedly stored with preset data on the preset address, and the FPGA is pre-stored with preset encryption data for encrypting the preset data by using a target encryption algorithm;
encrypting the target data by using the target encryption algorithm to obtain target encrypted data;
and when the target encrypted data is consistent with the preset encrypted data, powering on the BMC.
Preferably, after the process of powering on the BMC, the method further includes:
and starting the BMC through the advanced chip of the BMC.
Preferably, the starting process of the BMC by the advanced chip of the BMC includes:
and loading a storage program in the SPI FLASH by using the aspect chip, and starting the BMC by using the storage program.
Preferably, the preset address is specifically 0-0x 2000.
Preferably, the target encryption algorithm is specifically MD 5.
Preferably, the method further comprises the following steps:
and when the target encrypted data is inconsistent with the preset encrypted data, the BMC is prohibited from being powered on.
Correspondingly, the invention also discloses a power-on device of the server, which is applied to the FPGA and comprises the following components:
the data reading module is used for reading target data of the SPI FLASH in the BMC on a preset address when the BMC in the server is powered on; the SPI FLASH is fixedly stored with preset data on the preset address, and the FPGA is pre-stored with preset encryption data for encrypting the preset data by using a target encryption algorithm;
the data encryption module is used for encrypting the target data by using the target encryption algorithm to obtain target encrypted data;
and the BMC power-on module is used for powering on the BMC when the target encrypted data is consistent with the preset encrypted data.
Correspondingly, the invention also discloses a power-on device of the server, which comprises:
a memory for storing a computer program;
a processor for implementing the steps of the power-on method of a server as disclosed in the foregoing when executing the computer program.
Accordingly, the present invention also discloses a computer readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the steps of the power-on method of a server as disclosed in the foregoing.
Therefore, in the invention, the preset data is fixedly stored in the preset address of the SPI FLASH in the server mainboard BMC in advance, the preset data is encrypted by using the target encryption algorithm to obtain the preset encrypted data, and then the preset encrypted data is stored in the FPGA. When the BMC is powered on, the FPGA firstly reads target data of the SPI FLASH in the BMC on a preset address, and encrypts the target data by using the target encryption data to obtain target encryption data, if the target encryption data is consistent with the preset encryption data stored in the FPGA in advance, the data stored in the SPI FLASH is not tampered, and the BMC can be powered on at the moment. Obviously, compared with the prior art, the method has the advantage that the FPGA can power up the BMC only after the SPI FLASH in the BMC is verified, so that the safety and reliability of the server in the operation process can be further improved by the setting mode. Correspondingly, the power-on device, the equipment and the medium of the server provided by the invention also have the beneficial effects.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a method for powering on a server according to an embodiment of the present invention;
fig. 2 is a structural diagram of a power-on device of a server according to an embodiment of the present invention;
fig. 3 is a structural diagram of a powered device of a server according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart of a power-on method of a server according to an embodiment of the present invention, where the power-on method includes:
step S11: when the BMC in the server is powered on, reading target data of the SPI FLASH in the BMC on a preset address;
the SPI FLASH comprises an SPI FLASH body, a target encryption algorithm and an FPGA, wherein preset data are fixedly stored in a preset address of the SPI FLASH body, and preset encryption data for encrypting the preset data by using the target encryption algorithm are stored in the FPGA in advance;
step S12: encrypting the target data by using a target encryption algorithm to obtain target encrypted data;
step S13: and when the target encrypted data is consistent with the preset encrypted data, powering on the BMC.
In this embodiment, a power-on method for a server is provided, by which the security and reliability of the server in the operation process can be further improved. The power-on method is explained by taking the FPGA as an execution main body.
Specifically, in the power-on method, preset data is fixedly stored in advance in a preset address of an SPI FLASH (Serial Peripheral Interface FLASH EEPROM, a storage device operated through a Serial Interface) in the BMC in the server, because in practical applications, the power-on timing of the BMC is usually stored in the SPI FLASH. It can be understood that after the preset data is fixedly stored in the preset address of the SPI FLASH, it is equivalent to marking the power-on time sequence in the SPI FLASH, and if the FPGA does not change the mark in the power-on process of the BMC, it indicates that the power-on time sequence stored in the SPI FLASH is legal, and if the mark is changed, it indicates that the power-on time sequence stored in the SPI FLASH is illegal.
After the preset data is fixedly stored on the preset address of the SPI FLASH in the BMC in advance, the preset data is encrypted by using a preset encryption algorithm to obtain preset encrypted data, and the preset encrypted data is stored in the FPGA. Obviously, the purpose of this operation is to store the preset data in the FPGA as a cipher text.
When the BMC in the server is powered on, the FPGA reads target data of the SPI FLASH in the BMC on a preset address, then encrypts the read target data by using a target encryption algorithm to obtain target encryption data, compares the target encryption data with the preset encryption data, and if the target encryption data is consistent with the preset encryption data, the data stored in the SPI FLASH is not tampered by illegal molecules, the data stored in the SPI FLASH is legal, and at the moment, the FPGA can power on the BMC.
It should be noted that, in this embodiment, the target encryption Algorithm may be a symmetric encryption Algorithm, an asymmetric encryption Algorithm, a SHA-1(Secure Hash Algorithm 1) Algorithm, an HMAC (Hash-based Message Authentication Code), and the like, and is not limited herein.
It can be seen that, in this embodiment, preset data is fixedly stored in advance at a preset address of the SPI FLASH in the server motherboard BMC, and the preset data is encrypted by using a target encryption algorithm to obtain preset encrypted data, and then the preset encrypted data is stored in the FPGA. When the BMC is powered on, the FPGA firstly reads target data of the SPI FLASH in the BMC on a preset address, and encrypts the target data by using the target encryption data to obtain target encryption data, if the target encryption data is consistent with the preset encryption data stored in the FPGA in advance, the data stored in the SPI FLASH is not tampered, and the BMC can be powered on at the moment. Obviously, compared with the prior art, the method has the advantage that the FPGA can power up the BMC only after the SPI FLASH in the BMC is verified, so that the safety and reliability of the server in the operation process can be further improved by the setting mode.
Based on the above embodiments, this embodiment further describes and optimizes the technical solution, and as a preferred implementation, the above steps: after the process of powering on the BMC, the method further includes:
and starting the BMC through an advanced chip of the BMC.
In practical application, after the BMC is powered up by the FPGA, the FPGA needs to transfer the operation control right to an asserted chip in the BMC, and the BMC is started through the asserted chip. It can be appreciated that since the asserted chip acts as a controller for the BMC, the BMC can be enabled using the asserted chip.
As a preferred embodiment, the above steps: the process of starting the BMC through the advanced chip of the BMC comprises the following steps:
and loading a storage program in the SPI FLASH by using the aspect chip, and starting the BMC by using the storage program.
Specifically, in the process that the asserted chip starts the BMC, the asserted chip starts the BMC by loading the storage program in the SPI FLASH and by running the storage program in the SPI FLASH. Obviously, by such an operation mode, the overall reliability of the BMC during the startup process can be further ensured.
Based on the above embodiments, this embodiment further describes and optimizes the technical solution, and as a preferred implementation, the preset address is specifically 0 to 0x 2000.
It can be understood that, in the embodiment, the preset data is fixedly stored on the 0-0x2000 of the SPI FLASH, because the data stored in the address of the SPI FLASH in the range of 0-0x2000 is easier to fix and store. Obviously, by means of the operation mode, the compiling difficulty of a programmer in fixedly storing the preset data in the SPI FLASH can be relatively reduced.
Based on the above embodiments, this embodiment further describes and optimizes the technical solution, and as a preferred implementation, the target encryption algorithm is specifically MD 5.
Specifically, in this embodiment, the FPGA encrypts the preset data by using an MD5(Message Digest Algorithm MD 5) to obtain the preset encrypted data. Since the calculated MD5 value changes if the preset data is tampered after the preset data is encrypted by MD5 once, the reliability of the preset data in encryption can be significantly improved by such an arrangement.
Furthermore, MD5 has the advantages of fast calculation speed and fast encryption speed, so in this embodiment, when preset data is encrypted by MD5, the encryption speed when preset data is encrypted can be relatively increased.
Based on the foregoing embodiment, this embodiment further describes and optimizes the technical solution, and as a preferred implementation, the power-on method of the server further includes:
and when the target encrypted data is inconsistent with the preset encrypted data, the BMC is prohibited from being powered on.
In the actual operation process, if the target encrypted data is judged to be inconsistent with the preset encrypted data by the FPGA, the target data read by the FPGA on the preset address of the SPI FLASH is tampered by an illegal molecule, that is, the data stored in the SPI FLASH is illegal and unreliable data.
In this case, if the FPGA continues to power on the BMC, a great potential safety hazard may exist in the server in a subsequent operation process. Therefore, in this embodiment, in order to avoid the above situation, the FPGA prohibits the BMC from being powered on, so that the server cannot complete the booting.
Obviously, the technical scheme provided by the embodiment can further ensure the safety of the server in the power-on process.
Referring to fig. 2, fig. 2 is a structural diagram of a power-on device of a server according to an embodiment of the present invention, where the power-on device includes:
the data reading module 21 is configured to read target data of the SPI FLASH in the BMC at a preset address when the BMC in the server is powered on; the SPI FLASH comprises an SPI FLASH body, a target encryption algorithm and an FPGA, wherein preset data are fixedly stored in a preset address of the SPI FLASH body, and preset encryption data for encrypting the preset data by using the target encryption algorithm are stored in the FPGA in advance;
the data encryption module 22 is configured to encrypt the target data by using a target encryption algorithm to obtain target encrypted data;
and the BMC powering-on module 23 is configured to power on the BMC when the target encrypted data is consistent with the preset encrypted data.
The power-on device of the server provided by the embodiment of the invention has the beneficial effects of the power-on method of the server disclosed in the foregoing.
Referring to fig. 3, fig. 3 is a structural diagram of a power-on device of a server according to an embodiment of the present invention, where the power-on device includes:
a memory 31 for storing a computer program;
a processor 32 for implementing the steps of the power-on method of a server as disclosed in the foregoing when executing the computer program.
The power-on equipment of the server provided by the embodiment of the invention has the beneficial effects of the power-on method of the server disclosed by the embodiment of the invention.
Correspondingly, the embodiment of the invention also discloses a computer readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the power-on method of the server are realized as disclosed in the foregoing.
The computer-readable storage medium provided by the embodiment of the invention has the beneficial effects of the power-on method of the server disclosed in the foregoing.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above detailed description is provided for a method, an apparatus, a device and a medium for powering on a server, and a specific example is applied in the present disclosure to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (9)

1. A power-on method of a server is applied to an FPGA and comprises the following steps:
when the BMC in the server is powered on, reading target data of the SPIFLASH in the BMC on a preset address; the SPI FLASH is fixedly stored with preset data on the preset address, and the FPGA is pre-stored with preset encryption data for encrypting the preset data by using a target encryption algorithm;
encrypting the target data by using the target encryption algorithm to obtain target encrypted data;
and when the target encrypted data is consistent with the preset encrypted data, powering on the BMC.
2. The power-on method of claim 1, wherein after the step of powering on the BMC, further comprising:
and starting the BMC through the advanced chip of the BMC.
3. The power-on method according to claim 2, wherein the starting up the BMC via an asserted chip of the BMC comprises:
and loading a storage program in the SPI FLASH by using the aspect chip, and starting the BMC by using the storage program.
4. The power-on method according to claim 1, wherein the predetermined address is specifically 0-0x 2000.
5. The power-on method according to claim 1, characterized in that the target encryption algorithm is specifically MD 5.
6. The power-on method according to any one of claims 1 to 5, further comprising:
and when the target encrypted data is inconsistent with the preset encrypted data, the BMC is prohibited from being powered on.
7. The utility model provides a power-on device of server which characterized in that, is applied to FPGA, includes:
the data reading module is used for reading target data of the SPI FLASH in the BMC on a preset address when the BMC in the server is powered on; the SPIFLASH fixedly stores preset data on the preset address, and preset encryption data for encrypting the preset data by using a target encryption algorithm are stored in the FPGA in advance;
the data encryption module is used for encrypting the target data by using the target encryption algorithm to obtain target encrypted data;
and the BMC power-on module is used for powering on the BMC when the target encrypted data is consistent with the preset encrypted data.
8. A powered device of a server, comprising:
a memory for storing a computer program;
a processor for implementing the steps of a method of powering up a server as claimed in any one of claims 1 to 6 when executing said computer program.
9. A computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the steps of a method for powering up a server according to any one of claims 1 to 6.
CN202110075070.3A 2021-01-20 2021-01-20 Server power-on method, device, equipment and medium Pending CN112835440A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110075070.3A CN112835440A (en) 2021-01-20 2021-01-20 Server power-on method, device, equipment and medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110075070.3A CN112835440A (en) 2021-01-20 2021-01-20 Server power-on method, device, equipment and medium

Publications (1)

Publication Number Publication Date
CN112835440A true CN112835440A (en) 2021-05-25

Family

ID=75928873

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110075070.3A Pending CN112835440A (en) 2021-01-20 2021-01-20 Server power-on method, device, equipment and medium

Country Status (1)

Country Link
CN (1) CN112835440A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107885998A (en) * 2017-11-03 2018-04-06 山东超越数控电子股份有限公司 A kind of server master board encryption system
CN110020528A (en) * 2019-04-11 2019-07-16 苏州浪潮智能科技有限公司 A kind of BMC starting method, apparatus and electronic equipment and storage medium
CN111125717A (en) * 2019-12-22 2020-05-08 苏州浪潮智能科技有限公司 Method, device, equipment and medium for safely running BIOS (basic input output System) driver
CN111339502A (en) * 2020-02-23 2020-06-26 苏州浪潮智能科技有限公司 Starting method, system, equipment and medium for kernel in FPGA

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107885998A (en) * 2017-11-03 2018-04-06 山东超越数控电子股份有限公司 A kind of server master board encryption system
CN110020528A (en) * 2019-04-11 2019-07-16 苏州浪潮智能科技有限公司 A kind of BMC starting method, apparatus and electronic equipment and storage medium
CN111125717A (en) * 2019-12-22 2020-05-08 苏州浪潮智能科技有限公司 Method, device, equipment and medium for safely running BIOS (basic input output System) driver
CN111339502A (en) * 2020-02-23 2020-06-26 苏州浪潮智能科技有限公司 Starting method, system, equipment and medium for kernel in FPGA

Similar Documents

Publication Publication Date Title
CN104995629B (en) The method, apparatus and system that trust for platform boot firmware continues
CN109669734B (en) Method and apparatus for starting a device
US8782801B2 (en) Securing stored content for trusted hosts and safe computing environments
US8239688B2 (en) Securely recovering a computing device
TWI436280B (en) Authentication method for accessing profile of basic input/output system
WO2021249359A1 (en) Data integrity protection method and apparatus
JP6391439B2 (en) Information processing apparatus, server apparatus, information processing system, control method, and computer program
CN108154025A (en) Method, the method and device of application program mirror image processing of embedded device startup
JP2015036847A (en) Semiconductor device
CN109814934B (en) Data processing method, device, readable medium and system
CN104866768A (en) Startup control method and device for ATM (Automatic Teller Machine) operating system
JP2019071053A (en) Generation of checksum on trusted storage device for accelerating authentication
CN112148314B (en) Mirror image verification method, device and equipment of embedded system and storage medium
WO2019059148A1 (en) Bios management device, bios management system, bios management method, and bios management program-stored recording medium
TW201931191A (en) Memory subsystem, secure client device, and authentication method thereof
TWI760752B (en) System for accelerating verification procedure for image file
JP5986897B2 (en) Terminal device, integrity verification system, and program
CN107924440B (en) Method, system, and computer readable medium for managing containers
CN114547618A (en) Safe starting method and device based on Linux system, electronic equipment and storage medium
CN108664280A (en) A kind of embedded system start method and device
JP2021149457A (en) Semiconductor device and control method of semiconductor device
US12056260B2 (en) Method for protecting device software integrity in continuity scenario
CN112835440A (en) Server power-on method, device, equipment and medium
CN110781527B (en) Control register protection method and device
CN112307481B (en) System trusted starting method, electronic equipment and computer readable storage medium

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20210525

RJ01 Rejection of invention patent application after publication