CN112834905A - Device for testing chip and method for testing chip by using device - Google Patents
Device for testing chip and method for testing chip by using device Download PDFInfo
- Publication number
- CN112834905A CN112834905A CN202011624970.0A CN202011624970A CN112834905A CN 112834905 A CN112834905 A CN 112834905A CN 202011624970 A CN202011624970 A CN 202011624970A CN 112834905 A CN112834905 A CN 112834905A
- Authority
- CN
- China
- Prior art keywords
- test
- circuit board
- carrier
- chip
- test circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 321
- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000010998 test method Methods 0.000 claims abstract description 7
- 238000003825 pressing Methods 0.000 claims description 7
- 238000010146 3D printing Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 230000008569 process Effects 0.000 abstract description 10
- 229910000679 solder Inorganic materials 0.000 description 15
- 238000004458 analytical method Methods 0.000 description 4
- 238000013473 artificial intelligence Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 101100498823 Caenorhabditis elegans ddr-2 gene Proteins 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000009533 lab test Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2818—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
Abstract
The present disclosure relates to an apparatus for chip testing and a method of testing a chip using the same. The chip is disposed on a test circuit board, and the apparatus for chip testing may include: a carrier for securing to a back side of the test circuit board; and a counter part provided on the carrier part and providing a counter force by abutting against the back surface when the carrier part is fixed to the back surface, wherein the counter force is used for counteracting a pressure on the test circuit board during a test. The device for testing the chip can solve the problem that the test fails due to poor contact in the long-time chip testing process in a laboratory.
Description
Technical Field
The present disclosure relates generally to the field of testing technology. More particularly, the present disclosure relates to an apparatus for chip testing and a method of testing a chip using the same.
Background
At present, with the rapid development of Artificial Intelligence (AI) technology, processors (IPUs) that can be highly Integrated with an Artificial Intelligence algorithm are rapidly developed, which also presents a corresponding challenge to the testing of Integrated circuit chips in the manufacturing process of large-scale Integrated circuits, especially in the stability of long-time pressure testing in the lab of chips.
Generally, a processor chip has the characteristics of high power consumption, large size, multiple solder balls (balls), and the like, and during Board level testing, a test fixture (Socket) for placing the chip is usually required to be mounted on a Printed Circuit Board (PCB) designed with a corresponding peripheral Circuit, and the Printed Circuit Board is connected with a test host to test the electrical characteristics of the chip.
The solder balls of the processor chip are connected with the printed circuit board through the Pogo-pins (Pogo-pins) of the test fixture, and in order to ensure that the solder balls of the processor chip can be effectively contacted with the Pogo-pins of the test fixture, a predetermined amount of pressure needs to be applied to the processor chip, and the predetermined amount of pressure can be applied by using a spiral lock catch installed on a hand-testing cover (Lid) of the test fixture.
Generally, the pressure between each solder ball and the pogo pin of the processor chip is required to be 30g, and the processor chip generally has about 3000 solder balls, so that the pressure applied to the processor chip as a whole may reach about 90Kg, so that the pressure applied to the printed circuit board for mounting the processor chip is also about 90 Kg.
However, since the thickness of the printed circuit board is usually only 2mm to 3mm, and the processor chip generates heat during a long time operation, the printed circuit board may be weakly deformed during the test process, so that a part of the solder balls of the chip may be in poor contact with the spring pins of the test fixture, and a failure (Fail) may occur during the test. In addition, the conventional pressure test period is generally more than 10 hours, once problems occur in the midway, the flow is required to be restarted, and manpower and test time are greatly wasted.
To this end, some test factories directly install the printed circuit board for testing on the metal test fixture (Change Kit) of the test machine, and the test fixture can play a role of fixing and supporting the printed circuit board, but under the laboratory test environment, the installation requirements of the placement and test fixture of the large machine cannot be met, thereby causing a great obstruction to the laboratory debugging in the early stage of testing and the customer return Analysis (RMA) in the later stage of testing.
Therefore, it is necessary to develop an apparatus for chip testing and a method for testing a chip using the same to improve the problem of test failure due to poor contact in a long-time chip testing process in a laboratory.
Disclosure of Invention
In order to solve one or more of the above-mentioned technical problems, the present disclosure provides an apparatus for chip testing and a method for testing a chip using the same, so as to improve the problem of test failure due to poor contact in a long-time chip testing process in a laboratory.
In a first aspect, exemplary embodiments of the present disclosure provide an apparatus for chip testing, the chip being disposed on a test circuit board, the apparatus may include: a carrier for securing to a back side of the test circuit board; and a counter part provided on the carrier part and providing a counter force by abutting against the back surface when the carrier part is fixed to the back surface, wherein the counter force is used for counteracting a pressure on the test circuit board during a test.
In a second aspect, exemplary embodiments of the present disclosure provide a method of testing a chip using the apparatus as described in the first aspect, the method may include: mounting a test seat on which a chip is to be placed on a test circuit board; placing the chip in the test socket and applying pressure; placing and fixing the carrier to a back surface of the test circuit board so that the counter part provides a counter force for counteracting the pressure force against the back surface; and starting a test program to test the chip.
The device for testing the chip can effectively improve the deformation of the test circuit board caused by pressure and high temperature in the long-time pressure test process of the chip, thereby avoiding the test failure caused by poor contact caused by deformation. In addition, this disclosed a device for chip test is through setting up the uide hole, can be applicable to the test circuit board of multiple conventional size, need not customize the testing arrangement of corresponding size respectively alone for the test circuit board of each specific size to can further practice thrift the cost, and then improve experimental efficiency.
Drawings
The above and other objects, features and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:
fig. 1 is a schematic view illustrating a test assembly to which an apparatus for chip testing according to an exemplary embodiment of the present disclosure is applied;
fig. 2 is a schematic diagram illustrating an apparatus for chip testing according to an exemplary embodiment of the present disclosure;
fig. 3 is a flowchart illustrating a method of testing a chip using the apparatus for chip testing according to an exemplary embodiment of the present disclosure;
fig. 4 is a view illustrating a test result without using the apparatus for chip testing according to an exemplary embodiment of the present disclosure; and
fig. 5 is a view illustrating a test result using the apparatus for chip testing according to an exemplary embodiment of the present disclosure.
Detailed Description
Technical solutions in embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
It should be understood that the terms "first," "second," "third," and "fourth," etc. in the claims, description, and drawings of the present disclosure are used to distinguish between different objects and are not used to describe a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.
As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
With the rapid development of Artificial Intelligence (AI) technology, processors (IPUs) that can be highly Integrated with an Artificial Intelligence algorithm have also been rapidly developed, which presents corresponding challenges to the testing of Integrated circuit chips in the manufacturing process of large-scale Integrated circuits, especially to the stability of long-time pressure testing in laboratories.
Generally, a processor chip has high power consumption, a large size, and a plurality of solder balls (balls). In board level testing, a test fixture (Socket) for placing a processor chip is generally mounted on a test circuit board, and the test circuit board is designed with peripheral circuits corresponding to the test fixture, and then the test of the electrical characteristics of the processor chip is realized by connecting the test circuit board with a test host.
Thus, the test circuit board and test fixture described above may constitute a test assembly for processor chip testing, which is described first below.
Fig. 1 is a schematic view illustrating a test assembly to which an apparatus for chip testing according to an exemplary embodiment of the present disclosure is applied. As shown in fig. 1, the Test assembly may include a Test Circuit Board 100 and a Test fixture 200, wherein the Test Circuit Board 100 may be a Printed Circuit Board (PCB) for System Level Test (SLT) of the processor chip 300, and the Test fixture 200 may be mounted at a central portion of the Test Circuit Board 100.
Further, the test fixture 200 may include a test Socket 210 and a hand test Lid (Socket Lid)220, wherein the test Socket 210 is located at a lower portion of the test fixture 200 and is used to connect with the test circuit board 100, so as to mount the processor chip 300 to be tested and connect the processor chip 300 with the test circuit board 100. The above-mentioned hand cover 220 is located at the upper portion of the test fixture 200, and is pivotably coupled to the test socket 210, so that the hand cover 220 can open and cover the test socket 210 by pivoting.
Further, the hand-side cover 220 may be provided with a heat dissipation fan 221 and a screw fastener 222, wherein the heat dissipation fan 221 is used for dissipating heat of the tested processor chip 300, and the screw fastener 222 is used for applying pressure to the processor chip 300 so as to make the solder balls of the processor chip 300 effectively contact with the Pogo-pins (Pogo-pins) of the test fixture 200.
Here, it is understood that the solder balls of the processor chip 300 can be connected to the test circuit board 100 through the pogo pins of the test fixture 200, and in order to ensure that the solder balls of the processor chip 300 can be effectively contacted with the pogo pins of the test fixture 200, a predetermined amount of pressure is required to be applied to the processor chip 300, and the predetermined amount of pressure can be applied using the screw catches 222 mounted on the hand cover 220 of the test fixture 200.
Further, after the above-mentioned pressure is applied to the processor chip 300, it may be dispersed to each pogo pin under the processor chip 300, and then the pogo pins may conduct the pressure to the test circuit board 100.
In some application scenarios, the pressure between each solder ball and the pogo pin is required to be 30g, and the processor chip 300 usually has about 3000 solder balls, so the pressure applied to the processor chip 300 as a whole may reach about 90Kg, and the pressure applied to the portion of the test circuit board 100 for mounting the processor chip 300 is also about 90 Kg.
However, since the thickness of the test circuit board 100 is usually only 2mm to 3mm, and the processor chip 300 generates heat during a long time operation, the test circuit board 100 may be slightly deformed during the test, and thus a part of the solder balls of the processor chip 300 may not be in good contact with the spring pins of the test fixture 200, so that a failure (Fail) occurs in the middle of the test. In addition, the conventional chip test period is generally over 10 hours, and once a problem occurs in the midway, the flow needs to be restarted, so that the test cost and the test time are greatly wasted.
To this end, some test factories directly install the test circuit board 100 for testing on the metal test fixture (Change Kit) of the test machine, which can play a role of fixing and supporting the test circuit board 100, but under the laboratory test environment, cannot meet the installation requirements of the placement and test fixture of the large machine, thereby causing a great hindrance to the laboratory debugging in the early stage of testing and the customer-return Analysis (RMA) in the later stage of testing.
In view of the above, the present disclosure provides an apparatus for testing a chip and a method for testing a chip using the same, which can be applied to a laboratory long-time test of a processor chip 300. The device and the method can effectively improve the contact problem caused by the deformation of the test circuit board 100 in the test processes of system level test, backing analysis and the like, thereby effectively improving the test efficiency and saving the test cost and the test time of manpower.
Specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
Fig. 2 is a schematic diagram illustrating an apparatus for chip testing according to an exemplary embodiment of the present disclosure.
As shown in fig. 2, an exemplary embodiment of the present disclosure provides an apparatus 400 for chip testing, which may be disposed on a test circuit board 100, the apparatus including: a carrier 410 for fixing to a rear surface of the test circuit board 100; and a counter part 420 provided on the above-mentioned carrier part 410, and when the carrier part 410 is fixed to the back surface of the test circuit board 100, the counter part 420 may provide a counter force by abutting against the back surface of the test circuit board 100, wherein the counter force is used to counter a pressure of the chip and/or the test fixture (e.g., a pogo pin in the test fixture) against the test circuit board 100 during the test.
Specifically, as shown in fig. 2, the above-mentioned carrier part 410 may have a rectangular plate-like structure, and its size may correspond to the size of the test circuit board 100 or be larger than the size of the test circuit board 100, so that the carrier part 410 may be fixed to the rear surface of the test circuit board 100. In an exemplary embodiment, the thickness of the carrier 410 may be in the range of 1-10 mm, preferably 4-6 mm, and more preferably 5 mm.
Further, as shown in fig. 2, the offset part 420 described above may have a cubic shape, and may be disposed at a central portion of the carrier part 410. Here, since the test socket 210 of the test fixture 200 may be installed at the central portion of the test circuit board 100, when the carrier part 410 is fixed to the rear surface of the test circuit board 100, the counteracting part 420 may be located at a position of the rear surface of the test circuit board 100 corresponding to the test socket 210, so that the pressure of the chip against the test circuit board 100 during the test may be counteracted. In an exemplary embodiment, the thickness of offset 420 may be in the range of 0.1-2 centimeters, preferably 0.5-1.5 centimeters, and more preferably 1 centimeter.
Therefore, it can be understood that, in the case of fixing the bearing part 410 to the back surface of the test circuit board 100, the above-mentioned counteracting part 420 may provide a counteracting force to the test circuit board 100 by abutting against the back surface of the test circuit board 100, and the above-mentioned counteracting force may be used to support the test circuit board 100 at the test socket 210, so that the pressing force of the springs in the test socket 210 of the test fixture 200 against the test circuit board 100 may be counteracted, thereby preventing the test circuit board 100 from being deformed.
Therefore, according to the apparatus for chip testing of the exemplary embodiments of the present disclosure, it is possible to effectively improve deformation due to a test circuit board that needs to endure a large pressure for a long time and a high temperature generated during chip testing in a long time chip pressure test in a laboratory, and thus it is possible to prevent a test failure due to a contact failure.
Further, in an exemplary embodiment, the bearing part 410 and the canceling part 420 may be made of a photosensitive resin material. The photosensitive resin material has the advantages of high strength, high temperature resistance, convenient storage and low cost. Further, in an exemplary embodiment, the bearing part 410 and the offset part 420 may be integrally formed by a 3D printing technique. Like this, can realize testing arrangement's rapid prototyping through 3D printing technology integrated into one piece to can improve production efficiency and reduction in production cost.
As further shown in fig. 2, in an exemplary embodiment, the apparatus 400 for chip testing of the present disclosure may further include a connector 430, and the connector 430 may be used to detachably fix the carrier 410 to the back surface of the test circuit board 100. And in another exemplary embodiment, the distance between the bearing part 410 and the back surface of the test circuit board 100 may be adjusted by adjusting the connection member 430, so that the counteracting part 420 provides an adjustable counter force.
Specifically, as shown in fig. 2, in an exemplary application scenario, a plurality of through holes 440 may be opened along a peripheral portion of the carrier 410, and the plurality of connectors 430 may be connected to the test circuit board 100 via the through holes 440, so as to fix the carrier 410 to a back surface of the test circuit board.
Further, as shown in fig. 2, in an exemplary embodiment, the above-mentioned connection member 430 may include a bolt and a nut used in a pair, wherein the bolt may be connected with the nut through the above-mentioned through hole 440 and the bolt hole on the test circuit board 100. Then, the distance between the carrier part 410 and the back surface of the test circuit board 100 may be adjusted by screwing the bolt and the nut, so that the magnitude of the counter force provided by the counter part 420 may be adjusted.
As further shown in fig. 2, in an exemplary embodiment, a plurality of guide openings 450 may be opened along the periphery of the carrier part 410, and the plurality of guide openings 450 may be at a predetermined angle with respect to the center of the carrier part 410 in the length direction thereof, so that the connection members 430 may adjust the connection positions in the guide openings 450, so that the carrier part 410 may be fixed to the back of the test circuit board 100 having different sizes.
Specifically, as shown in fig. 2, in an exemplary application scenario, the guide opening 450 may be formed by extending the through hole 440 to the center of the bearing part 410 at a predetermined angle for a predetermined distance. In addition, the above-mentioned connection member 430 may include a bolt and a nut used in a pair, wherein the bolt may be adjusted in position along the guide hole 450 to be aligned and connected with the nut through a bolt hole on the test circuit board 100, and the distance between the carrier 410 and the rear surface of the test circuit board 100 may be adjusted by screwing the nut.
Therefore, it can be understood that the apparatus 400 for chip testing of the present disclosure can be adapted to a plurality of different sizes of test circuit boards 100 by opening a plurality of guide openings 450 at the through hole 440, such that the through hole 440 can have a long hole shape, and one end of the long hole can extend toward the center of the carrier 410, such that the connector 430 can be connected to the test circuit board 100 at a plurality of positions.
Further, in another exemplary embodiment, a plurality of through-holes 440 may also be substituted for one or more of the plurality of guide ports 450 described above. For example, a plurality of through holes 440 may be arranged at intervals at one diagonal of the carrier 410 along a diagonal of the carrier 410, or a plurality of through holes 440 may be arranged at intervals at a plurality (e.g., two, three, or four) of the diagonals of the carrier 410, respectively, so that the apparatus of the present disclosure may be connected with the test circuit board 100 at a plurality of positions, thereby making the apparatus of the present disclosure applicable to a plurality of different sizes of test circuit boards 100.
Fig. 3 is a flowchart illustrating a method of testing a chip using the apparatus for chip testing according to an exemplary embodiment of the present disclosure.
In a second aspect, as shown in fig. 3, exemplary embodiments of the present disclosure provide a method for testing a chip using the apparatus as described in the first aspect and its various embodiments, which may include: mounting a test socket 210, on which a chip is to be placed, on a test circuit board 100 (S100); placing the chip in the test socket 210 and applying pressure (S200); placing and fixing the carrier part 410 to the back surface of the test circuit board 100 so that the counteracting part 420 provides a counter force for counteracting the pressing force against the back surface (S300); and starting a test program to test the chip (S400).
Further, in an exemplary embodiment, the spacing between the carrier 410 and the test circuit board 100 may be adjusted during testing by continuously adjusting the connector 430 until the counter force provided by the counter 420 counteracts the pressure. In addition, in an exemplary embodiment, the current connection position of the connection member 430 may also be recorded when the counter force provided by the counteracting part 420 counteracts the pressure of the chip on the test circuit board 100, so as to be used for the next pressure test of the chip.
Specifically, referring to fig. 1 and 2, in an exemplary embodiment, a method for testing a processor chip 300 using the apparatus for chip testing 400 of the present disclosure may include the following steps.
Step one, assembling the test fixture 200.
Aligning the plurality of fixing screw holes of the test fixture 200 with the plurality of screw holes on the test circuit board 100, respectively, and putting the plurality of screws into the plurality of fixing screw holes of the test fixture 200 and screwing each screw one by one, so that the lower surface of the test fixture 200 is flatly attached to the upper surface of the test circuit board 100, and then checking and confirming that the plurality of screws are all screwed.
And step two, connecting the test circuit board 100 with the host test system.
After the test fixture 200 is assembled, the test circuit board 100 is placed on the lab table, and the test circuit board 100 is connected to the test host using the test data line. In the process of connecting the test circuit board 100 to the test host, the test data line should be prevented from contacting the metal object to prevent a short circuit phenomenon from occurring, thereby preventing the test equipment from being damaged.
Step three, placing the processor chip 300.
After the connection of the test circuit board 100 to the host test system is completed, the screw latch 222 for releasing and locking the test fixture 200 is rotated, and the hand test cover 220 with the heat dissipation fan 221 of the test fixture 200 is opened, and then the pogo pins in the test fixture 200 are brushed with a nano brush, and then the processor chip 300 is placed in the test socket 210 of the test fixture 200 in parallel with the test circuit board 100.
And step four, locking the spiral lock catch 222 and applying corresponding pressure.
After placing processor chip 300 parallel to test circuit board 100 in test socket 210 of test fixture 200, check and confirm that processor chip 300 is not deflected, then snap hand cap 220 back into place and vertically onto test socket 210 of test fixture 200 and tighten screw lock 222 to apply test pressure to processor chip 300.
Step five, placing the apparatus for chip testing 400 of the present disclosure on the back side of the test circuit board 100, and fixing the apparatus for chip testing 400 of the present disclosure to the test circuit board 100.
Bolts are passed through the through-holes 440 of the carrier 410 of the apparatus for chip testing 400 of the present disclosure and through bolt holes (not shown) at four corners of the test circuit board 100. Here, since the through hole 440 of the carrier 410 is provided with the guide opening 450, it is possible to adjust the positions of the bolt and the nut according to the size of the test circuit board 100, then tighten the four nuts to connect the apparatus 400 for chip testing of the present disclosure with the test circuit board 100, and by adjusting the positions of the four nuts, to provide a reverse force to the test circuit board 100 at the back side of the test circuit board 100 to counteract the forward pressure of the manual cover 220 to the test circuit board 100.
And step six, test running of the test program.
When the test program is run in a trial mode, only the position between the bearing part 410 and the test circuit board 100 needs to be fixed, and the nut does not need to be adjusted too tightly, so that the test circuit board 100 is prevented from being deformed reversely.
And step seven, screwing the nut to adjust the reverse force.
The reverse force applied by the counteracting part 420 to the test fixture 200 of the test circuit board 100 is continuously increased by continuously tightening the nut of the connector 430, so that the forward pressure of the hand-test cover 220 on the test circuit board 100 is continuously counteracted, and finally, each spring pin is uniformly stressed by a predetermined pressure and the test circuit board 100 is not deformed.
And step eight, carrying out chip test.
The relative positions of the bolt and nut of the current connection 430 are maintained and the chip test is continued. Further, the length of the bolt screwed into the nut under the current pressure can be recorded, and the corresponding position is marked, so that a proper rotating position can be conveniently found in the next test, and the equipment debugging can be quickly completed.
Fig. 4 is a view showing a test result without using the apparatus for chip testing according to the exemplary embodiment of the present disclosure, and fig. 5 is a view showing a test result with using the apparatus for chip testing according to the exemplary embodiment of the present disclosure.
As shown in fig. 4, during the testing of the processor chip 300, the test circuit board 100 is subjected to a large pressure for a long time due to a long testing time, and the test circuit board 100 is deformed due to the pressure and heat due to a large heat dissipation of the processor chip 300 during the testing, so that a "DDR 2: ecc ear orror! "indicates that the test failed.
As further shown in fig. 5, since the device 400 for chip testing of the present disclosure is used during the testing process, the counteracting part 420 of the device can provide a reverse force to the board of the test circuit board 100 by abutting against the back surface of the test circuit board 100, so that the solder balls of the chip can be kept in effective contact with the spring pins of the test fixture. Therefore, no "DDR 2: ecc ear orror! "but rather shows a" no ecc "word indicating successful testing.
Therefore, the device for testing the chip is practically applied to the system level test and the backing analysis of the chip, and the problem of poor contact between the solder balls of the chip and the spring pins of the test fixture in the long-time pressure test process of a laboratory is effectively solved, so that a large amount of test time is saved, and the test period is shortened.
In connection with the various exemplary embodiments described above, those skilled in the art will appreciate that the present disclosure has at least several beneficial aspects as follows.
In a first aspect, the device for testing a chip of the present disclosure can effectively improve the deformation of the chip due to pressure and high temperature during a long-time pressure test process by providing a counter force to the test circuit board by using the counteracting part, so that the problem of test failure due to poor contact can be solved.
In a second aspect, the device for testing chips of the present disclosure is provided with the guide opening, so that the connection member of the device for testing chips of the present disclosure can be connected with the test circuit board at a plurality of positions, and therefore, the device of the present disclosure can be applied to the test circuit boards of various conventional sizes without individually customizing the chip testing device for each test circuit board of a specific size, thereby further saving the cost and improving the experimental efficiency.
Based on the above full disclosure of the present disclosure, those skilled in the art can understand that the present disclosure also discloses the technical solutions as set forth in the following clauses:
clause a1, an apparatus for chip testing, the chip being disposed on a test circuit board, the apparatus comprising:
a carrier for securing to a back side of the test circuit board; and
a counter part disposed on the carrier part and providing a counter force against the back surface when the carrier part is secured to the back surface, wherein the counter force is used to counter a pressure on the test circuit board during testing.
Clause a2, the device of clause a1, further comprising a connector for removably securing the carrier to the back face and adjusting the spacing of the carrier from the back face so that the counter portion provides an adjustable opposing force.
Clause A3, the apparatus of clause a2, wherein a plurality of through holes are opened along the periphery of the carrier, and a plurality of the connectors are connected with the test circuit board via the through holes so as to fix the carrier to the back surface.
Clause a4, the apparatus of clause A3, wherein the connector comprises a bolt and a nut used in pairs, wherein the bolt is connected to the nut through the through hole and a bolt hole on the test circuit board, wherein rotation of the nut is used to adjust a spacing of the carrier from the back face.
Clause a5, the device according to clause a2, wherein a plurality of guide openings are opened along the periphery of the carrying section, the plurality of guide openings forming a predetermined angle with the center of the carrying section in the length direction thereof, wherein the connecting member adjusts the connecting position through the guide openings so as to fix the carrying section to the back surface.
Clause a6, the apparatus of clause a5, wherein the connector comprises a bolt and nut used in pairs, wherein the bolt adjusts position along the guide opening to align and connect with the nut through a bolt hole on the test circuit board, wherein rotation of the nut is used to adjust the spacing of the carrier from the back face.
Clause a7, the device according to any one of clauses a1-a6, wherein the carrier has a thickness of 1-10 mm, preferably 4-6 mm, more preferably 5 mm.
Clause A8, the device of any one of clauses a1-a6, wherein the counter portion has a thickness of 0.1-2 centimeters, preferably 0.5-1.5 centimeters, more preferably 1 centimeter.
Clause a9, the device according to any one of clauses a1-a6, wherein the carrier and counter-part are made of a photosensitive resin material.
Clause a10, the apparatus of any one of clauses a1-a6, wherein the carrier and counter-part are integrally formed by 3D printing techniques.
Clause a11, the device according to any one of clauses a1-a6, wherein the carrier has a plate-like structure with a rectangular shape, the counter part being disposed in the center of the carrier.
Clause a12, a method of testing a chip using the apparatus of any one of clauses a1-a11, comprising:
mounting a test seat on which a chip is to be placed on a test circuit board;
placing the chip in the test socket and applying pressure;
placing and fixing the carrier to a back surface of the test circuit board so that the counter part provides a counter force for counteracting the pressure force against the back surface; and
and starting a test program to test the chip.
Clause a13, the method of clause a12, wherein the spacing between the carrier and test circuit board is adjusted during testing by continually adjusting the connector until the counter force provided by the counter part counters the pressure.
Clause a14, the method of clause a13, wherein the current connection position of the connector is recorded for use in a next die pressure test when the counter force provided by the counter part counters the pressure.
In the above description of the present specification, the terms "fixed," "mounted," "connected," or "connected," and the like, are to be construed broadly unless otherwise expressly specified or limited. For example, with the term "coupled", it can be fixedly coupled, detachably coupled, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship. Therefore, unless the specification explicitly defines otherwise, those skilled in the art can understand the specific meaning of the above terms in the present disclosure according to specific situations.
From the above description of the present specification, those skilled in the art will also understand the terms used below, terms indicating orientation or positional relationship such as "upper", "lower", "front", "rear", "left", "right", "length", "width", "thickness", "vertical", "horizontal", "top", "bottom", "inner", "outer", "axial", "radial", "circumferential", "center", "longitudinal", "lateral", "clockwise" or "counterclockwise" are based on the orientation or positional relationship shown in the drawings of the present specification, it is used for convenience in explanation of the disclosure and for simplicity in description, and does not explicitly show or imply that the devices or elements involved must be in a particular orientation, constructed and operated, therefore, the above terms of orientation or positional relationship should not be understood or interpreted as limitations to the disclosed aspects.
In addition, the terms "first" or "second", etc. used in this specification are used to refer to numbers or ordinal terms for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In the description of the present specification, "a plurality" means at least two, for example, two, three or more, and the like, unless specifically defined otherwise.
While various embodiments of the present disclosure have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Numerous modifications, changes, and substitutions will occur to those skilled in the art without departing from the spirit and scope of the present disclosure. It should be understood that various alternatives to the embodiments of the disclosure described herein may be employed in practicing the disclosure. It is intended that the following claims define the scope of the disclosure and that the module compositions, equivalents, or alternatives falling within the scope of these claims be covered thereby.
Claims (14)
1. An apparatus for testing a chip, the chip being disposed on a test circuit board, the apparatus comprising:
a carrier for securing to a back side of the test circuit board; and
a counter part disposed on the carrier part and providing a counter force against the back surface when the carrier part is secured to the back surface, wherein the counter force is used to counter a pressure on the test circuit board during testing.
2. The device of claim 1, further comprising a connector for removably securing the carrier to the back face and adjusting the spacing of the carrier from the back face so that the counter portion provides an adjustable counter force.
3. The apparatus of claim 2, wherein a plurality of through holes are opened along the periphery of the carrier, and a plurality of the connectors are connected with the test circuit board via the through holes so as to fix the carrier to the rear surface.
4. The apparatus of claim 3, wherein the connector comprises a bolt and nut used in pairs, wherein the bolt is connected to the nut through the through hole and a bolt hole on the test circuit board, wherein rotation of the nut is used to adjust the spacing of the carrier from the back surface.
5. The apparatus of claim 2, wherein a plurality of guide ports are formed along the periphery of the carrying portion, the plurality of guide ports forming a predetermined angle with the center of the carrying portion in the length direction thereof, wherein the connecting member adjusts the connecting position through the guide ports so as to fix the carrying portion to the rear surface.
6. The apparatus of claim 5, wherein the connector comprises a bolt and nut used in pairs, wherein the bolt adjusts position along the guide opening to align and connect with the nut through a bolt hole on the test circuit board, wherein rotation of the nut is used to adjust the spacing of the carrier from the back face.
7. A device according to any of claims 1-6, wherein the thickness of the carrier part is 1-10 mm, preferably 4-6 mm, more preferably 5 mm.
8. The device according to any of claims 1-6, wherein the offset has a thickness of 0.1-2 cm, preferably 0.5-1.5 cm, more preferably 1 cm.
9. The device of any one of claims 1-6, wherein the carrier and counter-portions are made of a photosensitive resin material.
10. The device of any one of claims 1-6, wherein the carrier and counter-portions are integrally formed by 3D printing techniques.
11. The device according to any one of claims 1-6, wherein the carrier part has a plate-like structure with a rectangular shape, the counteracting part being arranged in the centre of the carrier part.
12. A method of testing a chip using the apparatus of any one of claims 1-11, comprising:
mounting a test seat on which a chip is to be placed on a test circuit board;
placing the chip in the test socket and applying pressure;
placing and fixing the carrier to a back surface of the test circuit board so that the counter part provides a counter force for counteracting the pressure force against the back surface; and
and starting a test program to test the chip.
13. The method of claim 12, wherein the spacing between the carrier and test circuit board is adjusted during testing by continually adjusting the connector until the counter force provided by the counter part counters the compressive force.
14. The method of claim 13, wherein the current connection position of the connector is recorded for the next die pressure test when the counter force provided by the counter part counters the pressure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011624970.0A CN112834905A (en) | 2020-12-31 | 2020-12-31 | Device for testing chip and method for testing chip by using device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011624970.0A CN112834905A (en) | 2020-12-31 | 2020-12-31 | Device for testing chip and method for testing chip by using device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112834905A true CN112834905A (en) | 2021-05-25 |
Family
ID=75924390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011624970.0A Pending CN112834905A (en) | 2020-12-31 | 2020-12-31 | Device for testing chip and method for testing chip by using device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112834905A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113835015A (en) * | 2021-09-09 | 2021-12-24 | 电子科技大学 | Reusable microwave chip test fixture with water cooling structure |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0735777A (en) * | 1993-05-19 | 1995-02-07 | Tokyo Electron Ltd | Inspecting apparatus and connection method therein |
| CN2762104Y (en) * | 2004-06-22 | 2006-03-01 | 上海环达计算机科技有限公司 | Circuit board testing fixture |
| CN103454573A (en) * | 2012-06-04 | 2013-12-18 | 大陆汽车有限公司 | Test device for testing a flat module |
| CN105509696A (en) * | 2014-09-25 | 2016-04-20 | 环旭电子股份有限公司 | Spherical surface deflection strain test tool for circuit board |
| CN108925032A (en) * | 2018-09-20 | 2018-11-30 | 上海华岭集成电路技术股份有限公司 | Printed circuit board and its test method |
| CN110133473A (en) * | 2018-02-09 | 2019-08-16 | 矽利康实验室公司 | Semiconductor test system with flexible and steady form factor |
| CN209525206U (en) * | 2019-03-01 | 2019-10-22 | 河南工业大学 | The load end plate with adjustment height hanging plate suitable for Low-cycle Test |
| CN210037903U (en) * | 2019-05-15 | 2020-02-07 | 耐而达精密工程(苏州)有限公司 | Supporting mechanism for chip testing |
| US20200355725A1 (en) * | 2019-05-06 | 2020-11-12 | One Test Systems | Testing apparatus |
-
2020
- 2020-12-31 CN CN202011624970.0A patent/CN112834905A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0735777A (en) * | 1993-05-19 | 1995-02-07 | Tokyo Electron Ltd | Inspecting apparatus and connection method therein |
| CN2762104Y (en) * | 2004-06-22 | 2006-03-01 | 上海环达计算机科技有限公司 | Circuit board testing fixture |
| CN103454573A (en) * | 2012-06-04 | 2013-12-18 | 大陆汽车有限公司 | Test device for testing a flat module |
| CN105509696A (en) * | 2014-09-25 | 2016-04-20 | 环旭电子股份有限公司 | Spherical surface deflection strain test tool for circuit board |
| CN110133473A (en) * | 2018-02-09 | 2019-08-16 | 矽利康实验室公司 | Semiconductor test system with flexible and steady form factor |
| CN108925032A (en) * | 2018-09-20 | 2018-11-30 | 上海华岭集成电路技术股份有限公司 | Printed circuit board and its test method |
| CN209525206U (en) * | 2019-03-01 | 2019-10-22 | 河南工业大学 | The load end plate with adjustment height hanging plate suitable for Low-cycle Test |
| US20200355725A1 (en) * | 2019-05-06 | 2020-11-12 | One Test Systems | Testing apparatus |
| CN210037903U (en) * | 2019-05-15 | 2020-02-07 | 耐而达精密工程(苏州)有限公司 | Supporting mechanism for chip testing |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113835015A (en) * | 2021-09-09 | 2021-12-24 | 电子科技大学 | Reusable microwave chip test fixture with water cooling structure |
| CN113835015B (en) * | 2021-09-09 | 2023-09-29 | 电子科技大学 | Reusable microwave chip test fixture with water cooling structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8382503B2 (en) | Quick release retention mechanism for socketed microelectronic devices | |
| US20020181206A1 (en) | Reusable thermal solution attachment mechanism and methods of using same | |
| US20030032322A1 (en) | Semiconductor device-socket | |
| JP4397561B2 (en) | Parallel mounting inspection board for semiconductor memory devices | |
| US20080113528A1 (en) | Cartridge for contact terminals and semiconductor device socket provided with the same | |
| US20100295572A1 (en) | Universal test socket and semiconductor package testing apparatus using the same | |
| CN112834905A (en) | Device for testing chip and method for testing chip by using device | |
| US5546277A (en) | Computer component torsional latching mechanism and method | |
| CN210427632U (en) | High-efficiency thick film hybrid integrated circuit module metallized hole conduction test fixture | |
| JP3256175B2 (en) | Socket for IC package measurement | |
| JP2004184415A (en) | Device for inspecting semiconductor package and inspection method using it | |
| US11187634B2 (en) | Bending test device and bending mechanism thereof | |
| US6894523B2 (en) | System and method for testing semiconductor devices | |
| CN215239101U (en) | Hinge assembling equipment | |
| US20030104712A1 (en) | Socket for electrical parts | |
| US7199599B2 (en) | Integrated circuit socket with removable support | |
| CN210476977U (en) | Clamping and replacing connecting seat structure of multi-directional flange of manipulator | |
| JPH0933606A (en) | Jig for inspection of semiconductor element | |
| CN113834402B (en) | Comprehensive position degree inspection device for generator | |
| US7077665B2 (en) | Contact pin and socket for electrical parts | |
| CN212845765U (en) | PCB detection jig | |
| CN220400232U (en) | PCB detection device for SSD | |
| CN219532439U (en) | Detection jig and test platform with same | |
| US6037764A (en) | Rotatable mechanical hold-down finger for holding a circuit board in a test fixture | |
| US6929486B2 (en) | Socket for electrical parts and method for using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |