CN112834083A - Silicon chip process method of high-precision pressure sensor - Google Patents
Silicon chip process method of high-precision pressure sensor Download PDFInfo
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- CN112834083A CN112834083A CN202011631013.0A CN202011631013A CN112834083A CN 112834083 A CN112834083 A CN 112834083A CN 202011631013 A CN202011631013 A CN 202011631013A CN 112834083 A CN112834083 A CN 112834083A
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- 238000000034 method Methods 0.000 title claims abstract description 49
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 38
- 239000010703 silicon Substances 0.000 title claims abstract description 38
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 35
- 238000005530 etching Methods 0.000 claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000013078 crystal Substances 0.000 claims abstract description 8
- 238000001020 plasma etching Methods 0.000 claims description 36
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 238000006243 chemical reaction Methods 0.000 claims description 21
- 239000000377 silicon dioxide Substances 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 238000002161 passivation Methods 0.000 claims description 15
- 230000000873 masking effect Effects 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 10
- 238000001259 photo etching Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 229910052681 coesite Inorganic materials 0.000 claims description 8
- 229910052906 cristobalite Inorganic materials 0.000 claims description 8
- 229910052682 stishovite Inorganic materials 0.000 claims description 8
- 229910052905 tridymite Inorganic materials 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 7
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 6
- 239000002210 silicon-based material Substances 0.000 claims description 6
- 230000007797 corrosion Effects 0.000 claims description 5
- 238000005260 corrosion Methods 0.000 claims description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000000407 epitaxy Methods 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 102000052666 B-Cell Lymphoma 3 Human genes 0.000 claims description 3
- 108700009171 B-Cell Lymphoma 3 Proteins 0.000 claims description 3
- 101150072667 Bcl3 gene Proteins 0.000 claims description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 238000012544 monitoring process Methods 0.000 claims description 3
- 150000003376 silicon Chemical class 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 238000012545 processing Methods 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract description 2
- 238000011112 process operation Methods 0.000 abstract description 2
- 230000035945 sensitivity Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000006056 electrooxidation reaction Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L1/00—Measuring force or stress, in general
- G01L1/005—Measuring force or stress, in general by electrical means and not provided for in G01L1/06 - G01L1/22
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00349—Creating layers of material on a substrate
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00388—Etch mask forming
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00523—Etching material
- B81C1/00531—Dry etching
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Pressure Sensors (AREA)
Abstract
The invention discloses a silicon chip process method of a high-precision pressure sensor, which adopts a deep groove etching process commonly used in CMOS integrated circuits, improves the sensitivity of the chip, adopts a <110> crystal orientation silicon substrate material, reduces the thermal resistance coefficient of the chip, improves the parameter performance of a device and reduces the manufacturing cost compared with the conventional process of the pressure sensor, and simultaneously, the chip process is compatible with an MOS reference process, the process operation is simple, the processing cost is reduced, the method is safe and reliable, and the product process is easy to popularize and apply.
Description
Technical Field
The invention relates to the technical field of high-precision pressure sensor chip structures, in particular to a silicon chip process method of a high-precision pressure sensor.
Background
The silicon pressure sensor is widely used in many important fields of national economy and national defense construction as a measuring means of various mechanical quantities such as pressure, force, flow velocity, acceleration and the like, and has unique integration advantages, so that the application range of the silicon pressure sensor is wider and wider along with the high-speed development of a computer and the appearance of a system integration technology. The most common method for manufacturing the monocrystalline silicon pressure sensor at present is to obtain a pressure sensitive film by back corrosion by using a double-sided processing technology, and the defects of the process method and the structure are as follows: the alignment accuracy of the pressure-sensitive element and the pressure cavity is difficult to control accurately due to the requirement of double-sided processing, the alignment accuracy is influenced not only by a double-sided photoetching machine but also by electrochemical corrosion, and meanwhile, long-time back corrosion can influence the performances of the front pressure-sensitive element and the integrated circuit. The process method is difficult to manufacture a small pressure sensor, the utilization rate of the silicon wafer is low due to the fact that the back surface is corroded to occupy area, electrostatic fusion sealing is needed for improving the temperature characteristic, and the process is very complex; due to the complex process and low yield, the cost is high because a double-sided polishing sheet or a double-sided polishing epitaxial wafer is needed.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a silicon chip process method of a high-precision pressure sensor, which aims to solve the problems in the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides a silicon chip process method of a high-precision pressure sensor, which comprises the following steps:
(a) selecting a silicon material as a substrate;
(b) silicon epitaxy: forming an epitaxial layer on the substrate;
(c)PE-CVD SiO2SiN deposition: forming a passivation layer on the epitaxial layer;
(d) and (3) photoetching of a lead hole: forming an ohmic contact window;
(e) etching the dielectric layer: removing silicon nitride in RIE plasma etching equipment by adopting CF4/NF3/AR, removing silicon dioxide in the RIE plasma etching equipment by adopting CF4/CHF3/AR, and removing SiO by plasma chemical reaction etching2a/SiN dielectric layer, wherein the reaction end point is controlled on the silicon substrate interface;
(f) and (3) depositing a metal layer: sputtering an AL film and an epitaxial layer in plasma equipment by adopting an AL target/AR gas to form ohmic contact;
(g) metal photoetching: manufacturing an etching masking layer by using photoresist to form bonding PAD;
(h) metal corrosion: adopting BCL3/CL2/N2 to remove aluminum films in RIE plasma etching equipment, carrying out plasma chemical reaction etching, removing metal layers, and controlling a reaction end point in an SiN dielectric layer;
(i) etching and photoetching the deep groove: manufacturing an etching masking layer by using photoresist to form a required deep groove pattern of the silicon stress meter;
(j) etching the dielectric layer: removing silicon nitride in RIE plasma etching equipment by adopting CF4/NF3/AR, removing silicon dioxide in the RIE plasma etching equipment by adopting CF4/CHF3/AR, and removing SiO by plasma chemical reaction etching2a/SiN dielectric layer, wherein the reaction end point is controlled on the silicon substrate interface;
(k) deep groove reactive ion etching: using SiO2the/SiN dielectric layer is used as a hard shielding layer, silicon is etched in high-density plasma equipment by adopting C4F8 and SF6, and the deep groove reactive ion etching is used for forming a structure of a silicon stress meter;
(l) Hydrogen annealing: carrying out damage annealing on the metal layer alloy and the chemical reaction to form ohmic contact;
(m) thinning the back to 180 +/-6 microns.
As a further technical solution, the crystal orientation <110> of the silicon material in the step (a), type: p type, the resistivity is 10-20 ohm-cm, and the diameter is 125 +/-0.125 mm; the main cut and the <111> crystal orientation are parallel.
As a further technical scheme, in the step (B), the epitaxial layer is a B-doped epitaxial layer, the resistivity is 0.030-0.040 ohm-cm, and CPK is 1.5.
As a further technical proposal, TEOS and O are adopted in the step (c)2Growing 500nm silicon dioxide in a plasma device, and growing 700nm silicon nitride in the plasma device by adopting N2/NH3/SIH 4; depositing the film with the thickness of 500nm/700 nm; the thickness and the stress of the passivation layer are sampled in the manufacturing process, SPC statistics are used for monitoring the thickness and the stress of the passivation layer and the stress of the wafer passivation process layer<1E9 dyne/cm2。
As a further technical proposal, in the step (d), the photoresist with the thickness of 2.5um is adopted to manufacture an etching masking layer to form an ohmic contact window.
As a further technical solution, the thickness of the sputtered AL film in step (f) is 1000 nm.
As a further technical scheme, in the step (g), a photoresist with the thickness of 1.8um is adopted to manufacture an etching masking layer to form bonding PAD.
As a further technical scheme, in the step (k), the depth of the groove is 10-13 microns, and the depth comprises a passivation layer; CPK is 1.3, the transverse dimension tolerance in the whole sheet is controlled to be +/-0.2 microns, and CPK is 1.5.
By adopting the technical scheme, the invention has the following beneficial effects:
the invention adopts the common deep groove etching process in the CMOS integrated circuit, improves the sensitivity of the chip, adopts the <110> crystal orientation silicon substrate material, reduces the thermal resistance coefficient of the chip, improves the parameter performance of the device and reduces the manufacturing cost compared with the conventional process of the pressure sensor, and simultaneously, the chip process is compatible with the MOS reference process, the process operation is simple, the processing cost is reduced, the invention is safe and reliable, and the product process is easy to popularize and apply.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of a structure for forming an epitaxial layer on a substrate;
FIG. 2 is a schematic diagram of the structure after deposition of a passivation layer;
FIG. 3 is a schematic structural diagram after etching of a dielectric layer;
FIG. 4 is a schematic view of the structure after metal corrosion;
FIG. 5 is a schematic structural diagram after etching of a dielectric layer;
FIG. 6 is a schematic diagram of the structure after hydrogen annealing;
fig. 7 is a schematic structural view after the back surface is thinned.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
Referring to fig. 1 to 7, the present invention provides a silicon chip processing method for a high precision pressure sensor, which includes the following steps:
(a) selecting a silicon material as a substrate 1, wherein the crystal orientation of the silicon material is <110>, and the type is as follows: p type, the resistivity is 10-20 ohm-cm, and the diameter is 125 +/-0.125 mm; the main cut and the <111> crystal orientation are parallel.
(b) Silicon epitaxy forms an epitaxial layer 2, B doping epitaxy is carried out, the resistivity is 0.030-0.040 ohm-cm, and CPK is 1.5;
(c)PE-CVD SiO2deposition of/SiN with TEOS and O2500nm silicon dioxide was grown in a plasma apparatus and 700nm silicon nitride was grown in a plasma apparatus using N2/NH3/SIH 4. The deposition thickness was 500nm/700 nm. The thickness and the stress of the passivation layer 3 can be sampled in the manufacturing process, SPC statistics is used for monitoring the thickness and the stress of the passivation layer and the stress of the wafer passivation process layer<1E9 dyne/cm 2.
(d) And photoetching a lead hole. And (3) adopting the photoresist with the thickness of 2.5um to manufacture an etching masking layer to form an ohmic contact window 4, wherein the size is determined by the device parameter specification requirement.
(e) And etching the dielectric layer. Removing silicon nitride in RIE plasma etching equipment by adopting CF4/NF3/AR, removing silicon dioxide in the RIE plasma etching equipment by adopting CF4/CHF3/AR, and removing SiO by plasma chemical reaction etching2a/SiN dielectric layer, wherein the reaction end point is controlled on the silicon substrate interface;
(f) and depositing a metal layer. An AL film was sputtered in a plasma apparatus using an AL target/AR gas, 1000nm aluminum was deposited by magnetron sputtering, and an ohmic contact 5 was formed with the epitaxial layer.
(g) And (6) metal photoetching. Adopting photoresist with the thickness of 1.8um to manufacture an etching masking layer to form a bonding PAD, wherein the size meets the design rule and is determined by the device parameter specification requirement;
(h) and (6) corroding the metal. Adopting BCL3/CL2/N2 to remove aluminum films in RIE plasma etching equipment, carrying out plasma chemical reaction etching, removing metal layers, and controlling a reaction end point in an SiN dielectric layer;
(i) and etching and photoetching the deep groove. Using photoresist with the thickness of 2.5um to manufacture an etching masking layer to form a required silicon stress meter deep groove pattern 6;
(j) and etching the dielectric layer. Removing silicon nitride in RIE plasma etching equipment by adopting CF4/NF3/AR, removing silicon dioxide in the RIE plasma etching equipment by adopting CF4/CHF3/AR, carrying out plasma chemical reaction etching, removing a SiO2/SiN medium layer, and controlling a reaction end point at a silicon substrate interface;
(k) and (5) deep groove reactive ion etching. Silicon is etched in a high-density plasma device by using a SiO2/SiN dielectric layer as a hard masking layer and using C4F8 and SF6, and deep groove reactive ion etching is used for forming a structure of a silicon stress meter.
The depth (including the passivation layer) of the groove 7 is 10-13 microns, CPK is 1.3, and the tolerance of the transverse dimension in the whole chip is controlled to be +/-0.2 micron, and CPK is 1.5.
(l) And (5) hydrogen annealing. And carrying out damage annealing on the metal layer alloy and the chemical reaction to form ohmic contact and improve the bonding capability of the lead.
(m) thinning the back to 180 +/-6 microns.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. A silicon chip process method of a high-precision pressure sensor is characterized by comprising the following steps:
(a) selecting a silicon material as a substrate;
(b) silicon epitaxy: forming an epitaxial layer on the substrate;
(c)PE-CVD SiO2SiN deposition: forming a passivation layer on the epitaxial layer;
(d) and (3) photoetching of a lead hole: forming an ohmic contact window;
(e) etching the dielectric layer: by usingRemoving silicon nitride from CF4/NF3/AR in RIE plasma etching equipment, removing silicon dioxide from CF4/CHF3/AR in RIE plasma etching equipment, and performing plasma chemical reaction etching to remove SiO2a/SiN dielectric layer, wherein the reaction end point is controlled on the silicon substrate interface;
(f) and (3) depositing a metal layer: sputtering an AL film and an epitaxial layer in plasma equipment by adopting an AL target/AR gas to form ohmic contact;
(g) metal photoetching: manufacturing an etching masking layer by using photoresist to form bonding PAD;
(h) metal corrosion: adopting BCL3/CL2/N2 to remove aluminum films in RIE plasma etching equipment, carrying out plasma chemical reaction etching, removing metal layers, and controlling a reaction end point in an SiN dielectric layer;
(i) etching and photoetching the deep groove: manufacturing an etching masking layer by using photoresist to form a required deep groove pattern of the silicon stress meter;
(j) etching the dielectric layer: removing silicon nitride in RIE plasma etching equipment by adopting CF4/NF3/AR, removing silicon dioxide in the RIE plasma etching equipment by adopting CF4/CHF3/AR, and removing SiO by plasma chemical reaction etching2a/SiN dielectric layer, wherein the reaction end point is controlled on the silicon substrate interface;
(k) deep groove reactive ion etching: using SiO2the/SiN dielectric layer is used as a hard shielding layer, silicon is etched in high-density plasma equipment by adopting C4F8 and SF6, and the deep groove reactive ion etching is used for forming a structure of a silicon stress meter;
(l) Hydrogen annealing: carrying out damage annealing on the metal layer alloy and the chemical reaction to form ohmic contact;
(m) thinning the back to 180 +/-6 microns.
2. The silicon chip process method of the high-precision pressure sensor, according to the claim 1, wherein the crystal orientation of the silicon material in the step (a) is <110>, type: p type, the resistivity is 10-20 ohm-cm, and the diameter is 125 +/-0.125 mm; the main cut and the <111> crystal orientation are parallel.
3. The silicon chip process method of claim 1, wherein the epitaxial layer in step (B) is a B-doped epitaxial layer, the resistivity is 0.030-0.040 ohm-cm, and CPK is 1.5.
4. The silicon chip process method for high precision pressure sensor as claimed in claim 1, wherein TEOS and O are used in step (c)2Growing 500nm silicon dioxide in a plasma device, and growing 700nm silicon nitride in the plasma device by adopting N2/NH3/SIH 4; depositing the film with the thickness of 500nm/700 nm; the thickness and the stress of the passivation layer are sampled in the manufacturing process, SPC statistics are used for monitoring the thickness and the stress of the passivation layer and the stress of the wafer passivation process layer<1E9 dyne/cm2。
5. The silicon chip process method of the high precision pressure sensor according to claim 1, wherein in the step (d), the etching masking layer is made of photoresist with the thickness of 2.5um to form the ohmic contact window.
6. The silicon chip process method of the high precision pressure sensor according to claim 1, wherein the thickness of the sputtered AL film in step (f) is 1000 nm.
7. The silicon chip process method of the high precision pressure sensor as claimed in claim 1, wherein in step (g), the etching masking layer is made of photoresist with a thickness of 1.8um to form the bonding PAD.
8. The silicon chip process method of the high precision pressure sensor according to claim 1, wherein in the step (k), the depth of the groove is 10-13 μm, and the depth comprises a passivation layer; CPK is 1.3, the transverse dimension tolerance in the whole sheet is controlled to be +/-0.2 microns, and CPK is 1.5.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117326520A (en) * | 2023-10-09 | 2024-01-02 | 江苏致芯微电子技术有限公司 | Technological method of vehicle-gauge MEMS pressure sensor chip |
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| CN103557967A (en) * | 2013-11-22 | 2014-02-05 | 中国电子科技集团公司第四十九研究所 | Silicon micro-resonance mode pressure sensor core and manufacturing method |
| CN106373874A (en) * | 2015-07-21 | 2017-02-01 | 北大方正集团有限公司 | Manufacturing method of ohmic contact electrode based on AlGaN/GaN HEMT |
| CN111807318A (en) * | 2020-07-22 | 2020-10-23 | 中国人民解放军国防科技大学 | TGV substrate preparation method based on glass reflow process and MEMS device packaging method |
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2020
- 2020-12-30 CN CN202011631013.0A patent/CN112834083A/en active Pending
Patent Citations (5)
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|---|---|---|---|---|
| CN1065552A (en) * | 1992-05-11 | 1992-10-21 | 北京大学 | The deep etching technology of silicon |
| CN102190284A (en) * | 2010-03-11 | 2011-09-21 | 苏州敏芯微电子技术有限公司 | MEMS sensor and methods for manufacturing MEMS sensor, film, mass block and cantilever beam |
| CN103557967A (en) * | 2013-11-22 | 2014-02-05 | 中国电子科技集团公司第四十九研究所 | Silicon micro-resonance mode pressure sensor core and manufacturing method |
| CN106373874A (en) * | 2015-07-21 | 2017-02-01 | 北大方正集团有限公司 | Manufacturing method of ohmic contact electrode based on AlGaN/GaN HEMT |
| CN111807318A (en) * | 2020-07-22 | 2020-10-23 | 中国人民解放军国防科技大学 | TGV substrate preparation method based on glass reflow process and MEMS device packaging method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117326520A (en) * | 2023-10-09 | 2024-01-02 | 江苏致芯微电子技术有限公司 | Technological method of vehicle-gauge MEMS pressure sensor chip |
| CN117326520B (en) * | 2023-10-09 | 2024-05-28 | 江苏致芯微电子技术有限公司 | Technological method of vehicle-gauge MEMS pressure sensor chip |
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