CN112823422A

CN112823422A - Display panel and display device

Info

Publication number: CN112823422A
Application number: CN202180000543.1A
Authority: CN
Inventors: 先建波; 许晨; 李盼; 乔勇; 吴新银
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2021-03-22
Filing date: 2021-03-22
Publication date: 2021-05-18

Abstract

The present disclosure provides a display panel and a display device, wherein the display panel includes: the touch display panel comprises a substrate, a transistor array layer, a pixel limiting layer and a touch electrode, wherein the area of an opening region of a first color sub-pixel is smaller than that of an opening region of a third color sub-pixel, and the area of the opening region of a second color sub-pixel is smaller than that of the opening region of the third color sub-pixel; the orthographic projection of the second capacitor in the first color sub-pixel on the substrate and the orthographic projection of the touch electrode on the substrate have a first auxiliary overlapping area; the orthographic projection of a second capacitor in the second color sub-pixel on the substrate and the orthographic projection of the touch electrode on the substrate have a second auxiliary overlapping area; the orthographic projection of the second capacitor in the third color sub-pixel on the substrate and the orthographic projection of the touch electrode on the substrate have a third auxiliary overlapping area; at least one of the first auxiliary overlapping area and the second auxiliary overlapping area is larger than the third auxiliary overlapping area.

Description

Display panel and display device

Cross Reference to Related Applications

The present application claims priority from the chinese patent application filed on 17.08/2020, having application number 202010822808.3 and entitled "display panel and display device," the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

Electroluminescent Diodes such as Organic Light Emitting Diodes (OLEDs) and Quantum Dot Light Emitting Diodes (QLEDs) have the advantages of self-luminescence and low energy consumption, and are one of the hotspots in the application research field of current electroluminescent display devices.

Disclosure of Invention

The display panel provided by the embodiment of the disclosure comprises:

a substrate base plate;

the transistor array layer is positioned on the substrate base plate;

the pixel limiting layer is positioned on one side, away from the substrate, of the transistor array layer;

the touch electrode is positioned on one side, away from the substrate, of the pixel limiting layer;

the substrate base plate is provided with a display area, and the display area comprises a plurality of sub-pixels; the sub-pixel includes a pixel circuit and a light emitting element; the pixel circuit comprises a grid line graph, a data line graph and a power supply signal line graph;

the transistor array layer comprises a plurality of capacitive conductive portions, and the sub-pixels comprise the corresponding capacitive conductive portions; in the same sub-pixel, the capacitance conducting part and a data line pattern corresponding to the sub-pixel and/or a power supply signal line pattern corresponding to the sub-pixel have an overlapping area; the capacitance conducting part is at least coupled with a power supply signal line pattern corresponding to the sub-pixel or a data line pattern corresponding to the sub-pixel;

the pixel defining layer includes a plurality of opening regions, and the sub-pixels include the corresponding opening regions;

at least part of the touch electrode is in a grid in the orthographic projection of the substrate base plate;

wherein the plurality of sub-pixels further comprises a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; the area of the opening region of the first color sub-pixel is smaller than that of the opening region of the third color sub-pixel, and the area of the opening region of the second color sub-pixel is smaller than that of the opening region of the third color sub-pixel;

the orthographic projection of the capacitive conducting part in the first color sub-pixel on the substrate and the orthographic projection of the touch electrode on the substrate have a first auxiliary overlapping area;

the orthographic projection of the capacitive conducting part in the second color sub-pixel on the substrate and the orthographic projection of the touch electrode on the substrate have a second auxiliary overlapping area;

the orthographic projection of the capacitive conducting part in the third color sub-pixel on the substrate and the orthographic projection of the touch electrode on the substrate have a third auxiliary overlapping area;

at least one of the first auxiliary overlapping area and the second auxiliary overlapping area is larger than the third auxiliary overlapping area.

In some examples, the first auxiliary overlapping area is greater than the second auxiliary overlapping area; alternatively, the first and second electrodes may be,

the first auxiliary overlap area is substantially equal to the second auxiliary overlap area; alternatively, the third auxiliary overlapping area is substantially equal to the second auxiliary overlapping area.

In some examples, the transistor array layer includes:

a first conductive layer between the base substrate and the pixel defining layer; the first conducting layer comprises a plurality of data line patterns and a plurality of power signal line patterns;

a first insulating layer between the substrate base plate and the first conductive layer;

a second conductive layer between the substrate base and the first insulating layer, the second conductive layer comprising: a plurality of auxiliary conductive portions, the capacitive conductive portions of the sub-pixels including the auxiliary conductive portions; in the same sub-pixel, the orthographic projection of the first end of the auxiliary conductive part on the substrate and the orthographic projection of the power supply signal line pattern on the substrate have an overlapping region, and the orthographic projection of the second end of the auxiliary conductive part on the substrate and the orthographic projection of the data line pattern on the substrate have an overlapping region; the auxiliary conductive part is coupled with the power signal line pattern;

the first auxiliary overlapping area comprises an overlapping area between an orthographic projection of the auxiliary conductive part in the first color sub-pixel on the substrate and an orthographic projection of the touch electrode on the substrate;

the second auxiliary overlapping area comprises an overlapping area between an orthographic projection of the auxiliary conductive part in the second color sub-pixel on the substrate and an orthographic projection of the touch electrode on the substrate;

the third auxiliary overlapping area comprises an overlapping area between an orthographic projection of the auxiliary conductive part in the third color sub-pixel on the substrate and an orthographic projection of the touch electrode on the substrate.

In some examples, the auxiliary conductive portion in the first color sub-pixel includes a first auxiliary exposed portion, and an orthographic projection of the first auxiliary exposed portion on the substrate does not overlap with an orthographic projection of the data line pattern and the power supply signal line pattern on the substrate, respectively; the first auxiliary overlapping area comprises a first auxiliary sub-overlapping area, and the overlapping area of the first auxiliary exposure part between the orthographic projection of the substrate base plate and the orthographic projection of the touch electrode on the substrate base plate has the first auxiliary sub-overlapping area;

the auxiliary conductive part in the second color sub-pixel comprises a second auxiliary exposure part, and the orthographic projection of the second auxiliary exposure part on the substrate does not overlap with the orthographic projection of the data line pattern and the orthographic projection of the power supply signal line pattern on the substrate respectively; the second auxiliary overlapping area comprises a second auxiliary sub-overlapping area, and the overlapping area of the second auxiliary exposure part between the orthographic projection of the substrate base plate and the orthographic projection of the touch electrode on the substrate base plate has the second auxiliary sub-overlapping area;

the auxiliary conductive part in the third color sub-pixel comprises a third auxiliary exposure part, and the orthographic projection of the third auxiliary exposure part on the substrate does not overlap with the orthographic projection of the data line pattern and the orthographic projection of the power supply signal line pattern on the substrate respectively; and the third auxiliary overlapping area comprises a third auxiliary sub-overlapping area, and the third auxiliary exposure part has the third auxiliary sub-overlapping area in an overlapping area between the orthographic projection of the substrate base plate and the orthographic projection of the touch electrode on the substrate base plate;

the first auxiliary sub-overlapping area is larger than at least one of the second auxiliary sub-overlapping area and the third auxiliary sub-overlapping area.

In some examples, the second auxiliary sub-overlap area is greater than the third auxiliary sub-overlap area; alternatively, the third auxiliary sub overlapping area is substantially equal to the second auxiliary sub overlapping area.

In some examples, in the first color sub-pixel, an orthogonal projection of the first auxiliary exposure portion on the substrate base is located between an orthogonal projection of the data line pattern and the power supply signal line pattern on the substrate base; and/or the presence of a gas in the gas,

in the second color sub-pixel, the orthographic projection of the second auxiliary exposure part on the substrate is positioned between the orthographic projection of the data line pattern and the orthographic projection of the power supply signal line pattern on the substrate; and/or the presence of a gas in the gas,

in the third color sub-pixel, the orthographic projection of the third auxiliary exposure part on the substrate is positioned between the orthographic projection of the data line pattern and the orthographic projection of the power supply signal line pattern on the substrate.

In some examples, the auxiliary conductive portion has a total area in an orthographic projection of the substrate base plate;

the ratio range between the first auxiliary sub-overlapping area and the total area is: 1/3-2/3; and/or the presence of a gas in the gas,

the ratio range between the second auxiliary sub-overlapping area and the total area is: 0 to 1/4; and/or the presence of a gas in the gas,

the ratio range between the third auxiliary sub-overlapping area and the total area is: 0 to 1/16.

In some examples, in the first color sub-pixel, an orthographic projection of the touch electrode on the substrate base plate covers an orthographic projection of the first auxiliary exposure part on the substrate base plate; and/or the presence of a gas in the gas,

in the second color sub-pixel, the orthographic projection of the touch electrode on the substrate covers the orthographic projection of the second auxiliary exposure part on the substrate; and/or the presence of a gas in the gas,

in the third color sub-pixel, the orthographic projection of the touch electrode on the substrate covers the orthographic projection of the third auxiliary exposure part on the substrate.

In some examples, the auxiliary conductive portion in the first color sub-pixel further includes a first auxiliary shielding portion, and an orthogonal projection of the first auxiliary shielding portion on the substrate overlaps an orthogonal projection of at least one of the data line pattern and the power supply signal line pattern on the substrate; wherein the width of the first auxiliary exposure part in the column direction is smaller than the width of the first auxiliary shielding part in the column direction; and/or the presence of a gas in the gas,

the auxiliary conductive part in the second color sub-pixel further comprises a second auxiliary shielding part, and the orthographic projection of the second auxiliary shielding part on the substrate is overlapped with the orthographic projection of at least one of the data line pattern and the power supply signal line pattern on the substrate; wherein the width of the second auxiliary exposure part in the column direction is smaller than the width of the second auxiliary shielding part in the column direction; and/or the presence of a gas in the gas,

the auxiliary conductive part in the third color sub-pixel further comprises a third auxiliary shielding part, and the orthographic projection of the third auxiliary shielding part on the substrate is overlapped with the orthographic projection of at least one of the data line pattern and the power supply signal line pattern on the substrate; wherein a width of the third auxiliary exposing portion in a column direction is smaller than a width of the third auxiliary blocking portion in the column direction.

In some examples, the pixel circuit further includes a first capacitance;

the orthographic projection of a first capacitor in the first color sub-pixel on the substrate base plate and the orthographic projection of the touch electrode on the substrate base plate have a first storage overlapping area;

the orthographic projection of the first capacitor in the second color sub-pixel on the substrate and the orthographic projection of the touch electrode on the substrate have a second storage overlapping area;

the orthographic projection of the first capacitor in the third color sub-pixel on the substrate base plate and the orthographic projection of the touch electrode on the substrate base plate have a third storage overlapping area;

at least one of the first storage overlap area and the second storage overlap area is greater than the third storage overlap area.

In some examples, the first storage overlap area is greater than the second storage overlap area.

In some examples, the second conductive layer further includes a plurality of storage conductive portions disposed spaced apart from the auxiliary conductive portions; the sub-pixel includes the storage conductive part; the storage conductive part is used as a second polar plate of the first capacitor;

the first storage overlapping area comprises an overlapping area between an orthographic projection of the storage conductive part in the first color sub-pixel on the substrate and an orthographic projection of the touch electrode on the substrate;

the second storage overlapping area comprises an overlapping area between an orthographic projection of the storage conductive part in the second color sub-pixel on the substrate and an orthographic projection of the touch electrode on the substrate;

the third storage overlapping area comprises an overlapping area between an orthographic projection of the storage conductive part in the third color sub-pixel on the substrate and an orthographic projection of the touch electrode on the substrate.

In some examples, an orthographic projection of the touch electrode on the substrate base plate is in a grid shape, and the orthographic projection of the touch electrode on the substrate base plate does not overlap with the orthographic projection of the opening area on the substrate base plate.

In some examples, the touch electrode includes a first electrode portion and a second electrode portion; wherein an orthographic projection of the first electrode part on the substrate base plate and an orthographic projection of the auxiliary conductive part on the substrate base plate have an overlapping area, and an orthographic projection of the second electrode part on the substrate base plate and an orthographic projection of the auxiliary conductive part on the substrate base plate do not overlap;

the width of the first electrode portion is larger than the width of the second electrode portion.

In some examples, the display panel further comprises:

the light-emitting function layer is positioned between the pixel limiting layer and the touch electrode and comprises a plurality of first color light-emitting layers, a plurality of second color light-emitting layers and a plurality of third color light-emitting layers;

wherein the orthographic projection of the first color light emitting layer on the substrate covers the orthographic projection of the opening region in the first color sub-pixel on the substrate;

the orthographic projection of the second color light-emitting layer on the substrate covers the orthographic projection of the opening area in the second color sub-pixel on the substrate;

the orthographic projection of the third color light-emitting layer on the substrate covers the orthographic projection of the opening area in the third color sub-pixel on the substrate.

In some examples, an orthographic projection of the touch electrode positioned between the adjacent opening regions on the substrate overlaps with an orthographic projection of the light emitting layers of at least two different colors on the substrate.

In some examples, an orthographic projection of the touch electrode surrounding the opening region of the third color sub-pixel on the substrate base plate is positioned in an orthographic projection of the third color light emitting layer on the substrate base plate; and/or the presence of a gas in the gas,

the orthographic projection of the touch electrode surrounding the opening area of the second color sub-pixel on the substrate is positioned in the orthographic projection of the second color light-emitting layer on the substrate; and/or the presence of a gas in the gas,

the orthographic projection of the touch electrode surrounding the opening area of the first color sub-pixel on the substrate is positioned in the orthographic projection of the first color light-emitting layer on the substrate.

In some examples, the third color light emitting layer and the second color light emitting layer are adjacent, the third color light emitting layer has a first minimum distance between a boundary of an orthographic projection of the substrate base plate and a boundary of an orthographic projection of the touch electrode on the substrate base plate, the second color light emitting layer has a second minimum distance between a boundary of an orthographic projection of the substrate base plate and a boundary of an orthographic projection of the touch electrode on the substrate base plate;

the first minimum distance is greater than the second minimum distance.

In some examples, an area enclosed by orthographic projections of the touch electrodes surrounding the opening regions of the first color sub-pixels on the substrate is a first grid area;

the area surrounded by the orthographic projection of the touch electrode surrounding the opening area of the second color sub-pixel on the substrate is a second grid area;

the area surrounded by the orthographic projection of the touch electrode surrounding the opening area of the third color sub-pixel on the substrate is a third grid area;

the third grid area is larger than the second grid area and larger than the first grid area.

In some examples, the display panel includes a plurality of repeating units; the repeating unit includes the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel.

In some examples, the repeating unit further comprises a fourth color sub-pixel; the area surrounded by the orthographic projection of the touch electrode surrounding the opening area of the fourth color sub-pixel on the substrate is a fourth grid area;

the area of the first grid corresponding to the first color sub-pixel is larger than or approximately equal to the area of the fourth grid corresponding to the fourth color sub-pixel.

In some examples, in the same repeating unit, the opening regions of the third color sub-pixels and the opening regions of the first color sub-pixels are arranged in a first direction;

the area surrounded by the inner boundary of the touch electrode surrounding the opening area of the third color sub-pixel has a first width in the direction perpendicular to the first direction;

the area surrounded by the inner boundary of the touch electrode surrounding the opening area of the first color sub-pixel has a second width in the direction vertical to the first direction;

the first width is greater than the second width.

In some examples, in the same repeating unit, the opening regions of the second color sub-pixels and the opening regions of the fourth color sub-pixels are arranged in a first direction;

the area surrounded by the inner boundary of the touch electrode surrounding the opening area of the second color sub-pixel has a third width in the direction perpendicular to the first direction;

an area surrounded by an inner boundary of the touch electrode surrounding an opening area of the fourth color sub-pixel has a fourth width in a direction perpendicular to the first direction;

the third width is greater than the fourth width.

In some examples, an extending direction of grid lines of the touch electrode having an overlapping area with an orthographic projection of the auxiliary conductive part has an included angle β with a third direction; beta is more than or equal to 15 degrees and less than or equal to 60 degrees; wherein the third direction is substantially perpendicular to an extending direction of the data line pattern.

In some examples, tan β ═ a1/a 2; wherein a1 represents a width of the auxiliary conductive portion in a direction perpendicular to the third direction, and a2 represents a width of the auxiliary conductive portion in the third direction.

In some examples, the extending direction of the grid lines of the touch electrode having the overlapping area with the orthographic projection of the auxiliary conductive part in the first color sub-pixel has a first included angle with the third direction;

the extending direction of grid lines of the touch electrode with overlapped areas with the orthographic projection of the auxiliary conducting part in the second color sub-pixel and the third direction form a second included angle;

the extending direction of grid lines of the touch electrode with overlapped areas with the orthographic projection of the auxiliary conducting part in the sub-pixel of the third color and the third direction form a third included angle;

the first included angle is smaller than the second included angle and smaller than the third included angle.

In some examples, the opening regions of four adjacent sub-pixels are taken as an opening group, and the orthographic projection of the grid intersection points of the touch electrode on the substrate base plate is located in an area surrounded by the orthographic projection of the opening group on the substrate base plate.

In some examples, an orthographic projection of the grid intersection points of the touch electrodes on the substrate base plate is approximately located at the center of an area surrounded by the orthographic projection of the opening groups on the substrate base plate.

In some examples, the fourth color sub-pixel emits light of the same color as the first color sub-pixel.

In some examples, each of the sub-pixels further includes a first electrode;

the overlapping area of the first electrode in the first color sub-pixel between the orthographic projection of the substrate base plate and the orthographic projection of the touch electrode on the substrate base plate is provided with a first anode overlapping area;

the overlapping area of the first electrode in the second color sub-pixel between the orthographic projection of the substrate base plate and the orthographic projection of the touch electrode on the substrate base plate is provided with a second anode overlapping area;

the overlapping area of the first electrode in the third color sub-pixel between the orthographic projection of the substrate base plate and the orthographic projection of the touch electrode on the substrate base plate is provided with a third anode overlapping area;

at least one of the first anode overlap area and the second anode overlap area is greater than the third anode overlap area.

In some examples, the first anode overlap area is greater than the second anode overlap area; alternatively, the first and second electrodes may be,

the first anode overlap area is substantially equal to the second anode overlap area.

Another display panel provided in an embodiment of the present disclosure includes:

a substrate base plate;

the transistor array layer is positioned on the substrate base plate;

the transistor array layer further comprises a first conductive layer, and the capacitor conductive part is formed on the first conductive layer;

the pixel circuit includes a plurality of transistors, and at least some of the transistors have their sources and drains formed in the first conductive layer.

In some examples, the capacitive conductive portions are in an arc or irregular pattern.

In some examples, the capacitive conductive portion includes an auxiliary conductive portion at least partially overlapping each of the power signal line pattern, the data line pattern, and the touch electrode.

In some examples, the power signal line patterns of two adjacent columns of the sub-pixels are electrically connected through a power input line; or the power signal line patterns corresponding to the two adjacent columns of the sub-pixels with the same color are electrically connected through a power input line.

In some examples, the power input line is in a different layer than the power signal line pattern.

In some examples, a width of the power signal line pattern is greater than a width of the data line pattern.

In some examples, the data line pattern and the power signal line pattern are not disposed on the same conductive layer; or, the data line pattern and the power input line are not disposed on the same conductive layer.

In some examples, the first conductive layer includes a first sub-conductive layer and a second sub-conductive layer stacked with a first sub-insulating layer disposed therebetween.

In some examples, an overlapping area of the capacitive conductive part and the power supply signal line pattern is larger than an overlapping area of the capacitive conductive part and the data line pattern.

In some examples, the pixel circuit includes: a seventh transistor and a second transistor; a gate of the seventh transistor is coupled to a second reset signal line pattern, and a gate of the second transistor is coupled to a first reset signal line pattern; the first reset signal line pattern and the second reset signal line pattern transmit different signals.

In some examples, the pixel circuit includes: a data write transistor, a first transistor; the gate line pattern coupled to the gate of the data writing transistor transmits a different timing signal than the gate line pattern coupled to the gate of the first transistor.

The display device provided by the embodiment of the disclosure comprises the display panel.

Drawings

FIG. 1 is a schematic structural diagram of some display panels in an embodiment of the present disclosure;

FIG. 2 is a schematic view of the display panel shown in FIG. 1 along the direction AA';

FIG. 3 is a schematic diagram of some pixel circuits in an embodiment of the disclosure;

FIG. 4 is a timing diagram of some signals in an embodiment of the present disclosure;

FIG. 5a is a schematic diagram of a layout structure of some display panels in an embodiment of the present disclosure;

FIG. 5b is a schematic diagram of a layout structure of further display panels in the embodiment of the present disclosure;

FIG. 5c is a schematic cross-sectional view of the display panel shown in FIG. 5a along the AA';

FIG. 5d is a schematic cross-sectional view of the display panel shown in FIG. 5a along the direction BB';

FIG. 5e is a schematic cross-sectional view of the display panel shown in FIG. 5a along the direction CC';

FIG. 5f is a schematic cross-sectional view of the display panel shown in FIG. 5a along the DD' direction;

FIG. 5g is a schematic diagram of a layout structure in a first color sub-pixel according to an embodiment of the disclosure;

FIG. 5h is a schematic diagram of a layout structure in a second color sub-pixel in the embodiment of the disclosure;

FIG. 5i is a schematic diagram of a layout structure in a sub-pixel of a third color in the embodiment of the present disclosure;

FIG. 6a is a schematic structural view of some of the semiconductor layers in an embodiment of the present disclosure;

fig. 6b is a schematic structural diagram of some third conductive layers in an embodiment of the present disclosure;

fig. 6c is a schematic structural diagram of some second conductive layers in an embodiment of the present disclosure;

fig. 6d is a schematic structural diagram of some first conductive layers in an embodiment of the present disclosure;

FIG. 6e is a schematic structural diagram of some of the first electrode layers in an embodiment of the present disclosure;

FIG. 6f is a schematic structural diagram of some light-emitting functional layers in an embodiment of the present disclosure;

fig. 6g is a schematic structural diagram of some second touch electrodes in the embodiment of the present disclosure;

FIG. 7a is a schematic structural diagram of further semiconductor layers in an embodiment of the present disclosure;

fig. 7b is a schematic structural diagram of still other third conductive layers in the embodiment of the present disclosure;

FIG. 7c is a schematic structural diagram of further second conductive layers in an embodiment of the present disclosure;

FIG. 7d is a schematic structural diagram of still other first conductive layers in the embodiments of the present disclosure;

FIG. 7e is a schematic structural diagram of still other first electrode layers in the embodiment of the present disclosure;

fig. 7f is a schematic structural diagram of still other light-emitting functional layers in an embodiment of the present disclosure;

fig. 7g is a schematic structural diagram of still other first sub-conductive layers in the embodiment of the present disclosure;

fig. 7h is a schematic structural diagram of still other second sub-conductive layers in an embodiment of the disclosure;

fig. 8a is a schematic structural diagram of some touch electrodes in an embodiment of the disclosure;

fig. 8b is a schematic structural diagram of still other touch electrodes in the embodiment of the present disclosure;

fig. 8c is a schematic structural diagram of still other touch electrodes in the embodiment of the present disclosure;

FIG. 8d is a schematic cross-sectional view of the touch electrode shown in FIG. 8c along the AA';

FIG. 9a is a schematic diagram of a layout structure of further display panels in the embodiment of the present disclosure;

FIG. 9b is a schematic diagram of a layout structure of further display panels in the embodiment of the present disclosure;

FIG. 9c is a schematic diagram of a layout structure of further display panels in the embodiment of the present disclosure;

FIG. 10a is a schematic diagram of a layout structure of further display panels in the embodiment of the present disclosure;

FIG. 10b is a schematic diagram of a layout structure of further display panels in the embodiment of the present disclosure;

FIG. 11 is a schematic diagram of a layout structure of further display panels in the embodiment of the present disclosure;

FIG. 12 is a schematic diagram of a layout structure of further display panels in the embodiment of the present disclosure;

FIG. 13a is a schematic diagram of a layout structure of further display panels in the embodiment of the present disclosure;

FIG. 13b is a schematic diagram of a layout structure of further display panels in the embodiment of the present disclosure;

FIG. 14a is a schematic diagram of a layout structure of further display panels in the embodiment of the present disclosure;

FIG. 14b is a schematic diagram of a layout structure of further display panels in the embodiment of the present disclosure;

fig. 15 is a schematic layout structure of still other display panels in the embodiment of the disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. And the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the sizes and shapes of the various figures in the drawings are not to scale, but are merely intended to illustrate the present disclosure. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

As shown in fig. 1 and 2, the display panel provided in the embodiment of the present disclosure may include: the touch screen display device comprises a substrate 1000, a transistor array layer ZA located on the substrate 1000, a first electrode layer 500 located on one side of the transistor array layer ZA away from the substrate 1000, a pixel limiting layer 950 located on one side of the first electrode layer 500 away from the substrate 1000, a light-emitting functional layer 600 located on one side of the pixel limiting layer 950 away from the substrate 1000, a second electrode 700 located on one side of the light-emitting functional layer 600 away from the substrate 1000, a packaging layer FB located on one side of the second electrode 700 away from the substrate 1000, and a touch electrode 800 located on one side of the packaging layer FB away from the substrate 1000.

In some embodiments of the present disclosure, as shown in fig. 1, the substrate base plate 1000 has a display area AA and a non-display area surrounding the display area. The display area has a plurality of sub-pixels spx. The non-display area has a bank BK surrounding the display area AA. The non-display region may further include a circuit structure such as a driver circuit, for example: the structure of the Array substrate row Driver on Array (GOA) and the like is not described herein.

Exemplarily, the sub-pixel spx may include: a pixel circuit and a light emitting element. The pixel circuit has a transistor and a capacitor, and is used for driving the light-emitting element to emit light. It should be noted that one or more of the embodiments described herein correspond to a display panel having 7T2C (i.e., 7 thin film transistors and 2 capacitors) pixel circuits. In another embodiment, the display panel may include different pixel circuits, for example, more or less than 7 thin film transistors, and one or more capacitors.

As shown in fig. 3, in the display panel provided by the embodiment of the present disclosure, the sub-pixels may include: a GATE line pattern GATE (abbreviated GA), a first reset signal line pattern RST1, a first initialization signal line pattern VINT1, a DATA line pattern DATA (abbreviated DA), a light emission control signal line pattern EM, a power supply signal line pattern VDD, a second reset signal line pattern RST2, and a second initialization signal line pattern VINT 2.

For example, the first reset signal line pattern RST1 and the second reset signal line pattern RST2 may transmit different signals.

For example, the first reset signal line pattern RST1 and the second reset signal line pattern RST2 may be located at different layers. For example: the first reset signal line pattern RST1 is on the same layer as the gate line pattern GA, and the second reset signal line pattern RST2 is on the same layer as the data line pattern DA or the power source signal line pattern VDD.

Illustratively, the first initialization signal line pattern VINT1 and the second initialization signal line pattern VINT2 may transmit the same signal.

For example, the first and second initialization signal line patterns VINT1 and VINT2 may also transmit different signals. For example: VINT1 is V1, and VINT2 is V1 + -5V.

For example, the first and second initialization signal line patterns VINT1 and VINT2 may be located in different layers. For example: the first initialization signal line pattern VINT1 is in the same layer as the gate line pattern GA, and the second initialization signal line pattern VINT2 is in the same layer as the data line pattern DA or the first reset signal line pattern RST 1.

As shown in fig. 3, the pixel circuit in the sub-pixel may include: a first transistor T1, a second transistor T2, a third transistor T3, a data write transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor Cst, and a second capacitor C1.

Taking a pixel circuit as an example, each transistor included in the pixel circuit is a P-type transistor. The first transistor T1 may have a double gate structure, in which the gate 201g of the first transistor T1 is coupled to the gate line graph GA, the source S1 of the first transistor T1 is coupled to the drain D3 of the third transistor T3, and the drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3. Of course, the first transistor T1 may have a single-gate structure or a multi-gate structure, and is not limited herein.

The second transistor T2 may have a double gate structure, in which a gate 202g of the second transistor T2 is coupled to a first reset signal line pattern RST1, a source S2 of the second transistor T2 is coupled to a first initialization signal line pattern VINT1, and a drain D2 of the second transistor T2 is coupled to a gate 203g of the third transistor T3. Of course, the second transistor T2 may have a single-gate structure or a multi-gate structure, and is not limited herein.

The gate 204g of the data write transistor T4 is coupled to the gate line pattern GA, the source S4 of the data write transistor T4 is coupled to the data line pattern DA, and the drain D4 of the data write transistor T4 is coupled to the source S3 of the third transistor T3. For example, the gate line pattern GA coupled to the gate 204g of the data writing transistor T4 and the gate line pattern GA coupled to the gate 201g of the first transistor T1 may transmit different timing signals, which is not limited herein.

The gate 205g of the fifth transistor T5 is coupled to the emission control signal line pattern EM, the source S5 of the fifth transistor T5 is coupled to the power supply signal line pattern VDD, and the drain D5 of the fifth transistor T5 is coupled to the source S3 of the third transistor T3.

The gate 206g of the sixth transistor T6 is coupled to the light emission control signal line pattern EM, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is coupled to the anode of the light emitting element L. For example, the emission control signal line pattern EM coupled to the gate 205g of the fifth transistor T5 and the emission control signal line pattern EM coupled to the gate 206g of the sixth transistor T6 may transmit different timing signals, which is not limited herein.

The gate 207g of the seventh transistor T7 is coupled to the second reset signal line pattern RST2, the drain D7 of the seventh transistor T7 is coupled to the anode of the light emitting element L, and the source S7 of the seventh transistor T7 is coupled to the second initialization signal line pattern VINT 2.

The first plate Cst1 of the first capacitor Cst is coupled to the gate electrode 203g of the third transistor T3, and the second plate Cst2 of the first capacitor Cst is coupled to the power signal line pattern VDD.

The first terminal (i.e., the first plate C11) of the second capacitor C1 is coupled to the first terminal (e.g., the data line pattern DA) of the data writing transistor, and the second terminal (e.g., the second plate C12) of the second capacitor C1 is coupled to the power signal line pattern VDD. For example: the first plate C11 of the second capacitor C1 is coupled to the data line pattern DA and/or the data write transistor T4, and the second plate C12 of the second capacitor C1 is coupled to the power signal line pattern VDD.

Alternatively, the second plate C12 of the second capacitor C1 may be electrically connected to the power signal line pattern VDD, and the first plate C11 of the second capacitor C1 may extend below or above the data line pattern DA, such that the first plate C12 overlaps the data line pattern DA in an orthographic projection on the substrate.

Optionally, the first terminal of the data write transistor T4 may also be the source (or source region, e.g., S4 of fig. 3), or the drain (or drain region, e.g., D4 of fig. 3), or the gate (e.g., 204g of fig. 3) of the data write transistor T4. It should be noted that S and D in fig. 3 are only one reference numeral for the purpose of distinguishing and explaining.

Alternatively, the first terminal of the data writing transistor T4 may also be a connection structure of the source electrode of the data writing transistor T4 and the data line pattern DA.

As shown in fig. 4, exemplarily, the pixel circuit of the above-described structure is in operation, in which one duty cycle includes a first reset period P1, a write compensation period P2, a second reset period P3, and a light emission period P4.

In the first reset period P1, the first reset signal inputted from the first reset signal line pattern RST1 is at an active level, the second transistor T2 is turned on, the initialization signal transmitted from the first initialization signal line pattern VINT1 is inputted to the gate 203g of the third transistor T3, and the gate 203g of the third transistor T3 is reset. For example: so that the gate-source voltage Vgs held on the third transistor T3 for the previous frame is cleared.

In the write compensation period P2, the first reset signal is at a non-active level, the second transistor T2 is turned off, the gate scan signal inputted from the gate line pattern GA is at an active level, the first transistor T1 and the data write transistor T4 are controlled to be turned on, the data line pattern DA writes the data signal and is transmitted to the source S3 of the third transistor T3 via the data write transistor T4, at the same time, the first transistor T1 and the data write transistor T4 are turned on, so that the third transistor T3 is formed as a diode structure, therefore, the threshold voltage compensation of the third transistor T3 is achieved by the cooperation of the first transistor T1, the third transistor T3 and the data write transistor T4, and when the compensation time is sufficiently long, the gate 203g of the third transistor T3 can be controlled to eventually reach Vdata + Vth, where Vdata represents a data signal voltage value and Vth represents a threshold voltage of the third transistor T3.

In the second reset period P3, the gate scan signal is at the inactive level, both the first transistor T1 and the data write transistor T4 are turned off, the second reset signal inputted from the second reset signal line RST2 is at the active level, the seventh transistor T7 is controlled to be turned on, the initialization signal transmitted from the second initialization signal line pattern VINT2 is inputted to the anode of the light emitting element L, and the light emitting element L is controlled not to emit light.

In the light emitting period P4, the light emitting control signal written by the light emitting control signal line pattern EM is at an active level, the fifth transistor T5 and the sixth transistor T6 are controlled to be turned on, so that the power supply signal transmitted by the power supply signal line pattern VDD is input to the source S3 of the third transistor T3, and at the same time, the third transistor T3 is turned on because the gate 203g of the third transistor T3 is maintained at Vdata + Vth, the gate-source voltage corresponding to the third transistor T3 is Vdata + Vth-VDD, where VDD is a voltage value corresponding to the power supply signal, and the drain current generated based on the gate-source voltage flows to the anode of the corresponding light emitting element L, driving the corresponding light emitting element L to emit light.

When the transistor is a P-type transistor, the active level may be a low level, and the inactive level may be a high level. When the transistor is an N-type transistor, the active level may be a high level and the inactive level may be a low level. The transistors of the pixel circuit may be both P-type transistors or N-type transistors, or may include both P-type transistors and N-type transistors, for example: the T3 transistor is a P-type transistor and the T1 is an N-type transistor. It is understood that fig. 4 is only an exemplary description of the operation timing of the pixel circuit, and the signals RST1, RST2, Ga, EM, Da, etc. may be adaptively adjusted according to the transistor type of the pixel circuit and the actual situation.

As shown in fig. 5a to 5i, in manufacturing the transistor array layer ZA, the layout of each film layer is as follows: the semiconductor layer 400, the gate insulating layer 910, the third conductive layer 300, the interlayer dielectric layer 920, the second conductive layer 200, the first interlayer insulating layer 930, the first conductive layer 100, and the second interlayer insulating layer 940 are sequentially stacked in a direction away from the substrate 1000. It is understood that other metal layers or insulating layers may also be included between the substrate base plate 1000 and the semiconductor layer 400. For example: at least one buffer layer or organic insulating layer is further included between the substrate 1000 and the semiconductor layer 400, for example, the buffer layer may be silicon oxide or silicon nitride, and the organic insulating layer may be polyimide.

As shown in FIGS. 5a to 5i, 6a and 7a, the semiconductor layer 400 is used to form a channel region (e.g., 101pg to 107pg), a source formation region (e.g., 101ps to 107ps), a drain formation region (e.g., 101pd to 107pd), a connection formation region (e.g., 101px, 102px), etc., of each transistor in the pixel circuit; of course, other structures may also be formed as desired, such as: LDD regions doped with low-concentration impurities are formed between at least one drain formation region (e.g., 101 to 107pd) of the transistor and a channel region (e.g., 101 to 107pg) of the transistor, and between a source formation region (e.g., 101 to 107ps) of the transistor and a channel region (e.g., 101 to 107pg) of the transistor. The conductivity of the semiconductor layer 400 corresponding to the source formation region and the drain formation region is better than that of the semiconductor layer 400 corresponding to the channel region due to the doping effect. Alternatively, the semiconductor layer 400 may be amorphous silicon, polycrystalline silicon, a combination thereof, or the like; for example: the semiconductor layer 400 is Low Temperature Polysilicon (LTPS), the semiconductor layer 400 includes an Oxide semiconductor material (e.g., Indium Gallium Zinc Oxide (IGZO)), and the semiconductor layer 400 includes a Low Temperature Polycrystalline Oxide material (LTPO); for example, as shown in FIG. 3: the semiconductor layer 400 of T3 is low temperature polysilicon LTPS, and the semiconductor layer 400 of T1 includes oxide semiconductor material LTPO.

The source formation region, the drain formation region, and the connection formation region may be formed in a conductor region of a semiconductor layer doped with an n-type impurity or a p-type impurity, and the source formation region, the drain formation region, and the connection formation region may be electrically connected to each other by using the connection structure of the semiconductor layer. Illustratively, the semiconductor layer corresponding to the source formation region and the drain formation region may directly serve as a source or a drain of the corresponding transistor. Alternatively, the source electrode in contact with the source electrode formation region may be formed using a conductive material (e.g., a metal material), and the drain electrode in contact with the drain electrode formation region may be formed using a conductive material (e.g., a metal material).

As shown in fig. 5a to 5i, 6b, and 7b, the third conductive layer 300 is used to form at least one of the gate electrodes (e.g., 201g to 207g) of the transistors in the pixel circuits, and the gate line pattern GA, the emission control signal line pattern EM, the first reset signal line pattern RST1, and the second reset signal line pattern RST2 included in the display panel. Optionally, the gates 203g of the third transistors T3 in the pixel circuit are multiplexed as the first plate Cst1 of the first capacitor Cst in the pixel circuit. Of course, the gates 203g of the third transistors T3 in the pixel circuit may also be multiplexed as the second plate Cst2 of the first capacitor Cst in the pixel circuit.

As shown in fig. 5a to 5i, 6c, and 7c, second conductive layer 200 has a plurality of auxiliary conductive portions WD, a plurality of memory conductive portions WCst2 spaced apart from auxiliary conductive portions WD, and first and second initialization signal line patterns VINT1 and VINT2 included in the display panel. Wherein the sub-pixel includes an auxiliary conductive portion; in the same sub-pixel, the orthogonal projection of the first end of the auxiliary conductive portion WD on the substrate 1000 and the orthogonal projection of the power signal line pattern on the substrate 1000 have an overlapping region, and the orthogonal projection of the second end of the auxiliary conductive portion WD on the substrate 1000 and the orthogonal projection of the data line pattern on the substrate 1000 have an overlapping region. Optionally, the auxiliary conductive portion WD at least partially overlaps with each of the power signal line pattern, the data line pattern, and the touch electrode.

Also, the sub-pixel includes a storage conductive part Cst2, a second electrode Cst2 for forming the first capacitor Cst, i.e. the storage conductive part Cst2 is used as the second electrode Cst2 of the first capacitor Cst. Of course, the storage conductive part Cst2 may also serve as the first plate Cst1 of the first capacitor Cst. The shape and structure of the auxiliary conductive portion WD are not limited, and may be a regular rectangle or an irregular pattern having at least one side in an arc shape. Illustratively, one end of the auxiliary conductive portion WD extends to the other end of the auxiliary conductive portion in the row direction F4.

As shown in fig. 3, 5a to 5i, 6D, and 7D, the first conductive layer 100 is used to form a source (e.g., S1 to S7) and a drain (e.g., D1 to D7) of each transistor in the pixel circuit, and a data line pattern (e.g., DA1, DA2, DA3, DA4, and DA5) and a power signal line pattern VDD included in the display panel. Alternatively, the width of the power signal line pattern VDD is greater than the width of the data line patterns (e.g., DA1, DA2, DA3, DA4, and DA 5). It should be noted that the

connection lines

401, 402, 403, and 404 in fig. 6d and fig. 7d may be formed by the first conductive layer, and the specific layout is shown in fig. 5a to fig. 5i, fig. 6d, and fig. 7 d.

Of course, in practical applications, the data line pattern DA and the power signal line pattern VDD may not be disposed on the same conductive layer, for example, as shown in fig. 7g and 7h, the first conductive layer 100 may include a first sub-conductive layer 111 and a second sub-conductive layer 112 stacked, and a first sub-insulating layer (not shown) is disposed between the first sub-conductive layer 111 and the second sub-conductive layer 112. Illustratively, at least one of the

connection lines

401, 402, 403, and 404 is disposed in the same layer as the data line pattern (e.g., DA1, DA2) or the power signal line pattern VDD. For example: the data line pattern (e.g., DA1, DA2), the

connection lines

401, 402, and 403 may be disposed on the first sub-conductive layer 111, and the power signal line pattern VDD may be disposed on the second sub-conductive layer 112. That is, the data line pattern (e.g., DA1, DA2) and the power signal line pattern VDD are not disposed on the same conductive layer.

Illustratively, the first sub-conductive layer 111 where the data line pattern (e.g., DA1, DA2) is located is closer to the base substrate 1000 than the second sub-conductive layer where the power signal line pattern VDD is located.

Illustratively, the connection line 404, which is a connection structure between adjacent initialization signal line patterns, may be located in the sub-pixel or in the non-display region. For example: the connection line 404 connects the first and second initialization signal line patterns VINT1 and VINT 2.

In more detail, referring to fig. 3, 5a to 5i to 7D, the gate 201g of the first transistor T1 overlaps the first channel region 101pg, the source S1 of the first transistor T1 is located in the first source formation region 101ps, and the drain D1 of the first transistor T1 is located in the first drain formation region 101 pd.

The gate 202g of the second transistor T2 overlaps the second channel region 102pg, the source S2 of the second transistor T2 is located at the second source formation region 102ps, and the drain D2 of the second transistor T2 is located at the second drain formation region 102 pd.

The gate 203g of the third transistor T3 overlaps the third channel region 103pg, the source S3 of the third transistor T3 is located at the third source formation region 103ps, and the drain D3 of the third transistor T3 is located at the third drain formation region 103 pd.

The gate 204g of the data writing transistor T4 overlaps the fourth channel region 104pg, the source S4 of the data writing transistor T4 is located in the fourth source formation region 104ps, and the drain D4 of the data writing transistor T4 is located in the fourth drain formation region 104 pd.

The gate 205g of the fifth transistor T5 overlaps the fifth channel region 105pg, the source S5 of the fifth transistor T5 is located at the fifth source formation region 105ps, and the drain D5 of the fifth transistor T5 is located at the fifth drain formation region 105 pd.

The gate 206g of the sixth transistor T6 overlaps the sixth channel region 106pg, the source S6 of the sixth transistor T6 is located at the sixth source formation region 106ps, and the drain D6 of the sixth transistor T6 is located at the sixth drain formation region 106 pd.

The gate 207g of the seventh transistor T7 overlaps the seventh channel region 107pg, the source S7 of the seventh transistor T7 is located at the seventh source formation region 107ps, and the drain D7 of the seventh transistor T7 is located at the seventh drain formation region 107 pd.

The gate electrode 203g of the third transistor T3 is multiplexed into the first plate Cst1 of the first capacitor Cst, and the second plate Cst2 of the first capacitor Cst is coupled to the power signal line pattern VDD.

Optionally, the capacitor conductive part comprises an auxiliary conductive part WD, which may comprise the second plate C12 of the second capacitor C1, i.e. the auxiliary conductive part may partially or fully function as the second plate C12 of the second capacitor C1. For example: in the same sub-pixel, the auxiliary conductive part WD serves as the second plate C12 of the second capacitor C1, and the data line pattern DA serves as the first plate C11 of the second capacitor C1; alternatively, the data line pattern DA having an overlapping area with the second plate C12 of the second capacitor C1 is used as the first plate C11 of the second capacitor C1.

As shown in fig. 5a to 5i, 6e, and 7e, the first electrode layer 500 is used to form first electrodes (e.g., 510, 520, 530, 540) of the light emitting element L. Illustratively, the first electrode is an anode (e.g., 510, 520, 530, 540) of the light-emitting element L. It should be noted that the pixel defining layer 950 includes a plurality of opening regions (e.g., KK1, KK2, KK3, KK 4). Wherein, one first electrode corresponds to one opening region, and the orthographic projection of the opening region on the substrate 1000 is located in the orthographic projection of the corresponding first electrode on the substrate 1000. For example, the opening region KK1 corresponds to the first electrode 510, the opening region KK2 corresponds to the first electrode 520, the opening region KK3 corresponds to the first electrode 530, and the opening region KK4 corresponds to the first electrode 540. Illustratively, the first electrode may be directly electrically connected to the semiconductor layer; alternatively, the first electrode may be electrically connected to the semiconductor layer through another conductive layer, for example: a first conductive layer 100.

As shown in fig. 5a to 5i, 6f, and 7f, the light-emitting functional layer 600 is used to form a light-emitting layer of the light-emitting element L. For example, a first color luminescent layer 610, a second color luminescent layer 620, a third color luminescent layer 630, and a fourth color luminescent layer 640. Further, the light emitting function layer 600 may further include a film layer such as a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer. Wherein, the boundaries of the first color luminescent layer 610, the second color luminescent layer 620, the third color luminescent layer 630 and the fourth color luminescent layer 640 may overlap or not overlap. For example, at least two of the first color luminescent layer 610, the second color luminescent layer 620, the third color luminescent layer 630, and the fourth color luminescent layer 640 have an overlap region, for example: the first color emissive layer 610 boundary extends into the second color emissive layer 620.

As shown in fig. 2, the encapsulation layer FB may exemplarily include at least one or more layers of FB1, FB2, FB3, wherein at least one layer of FB1, FB2, FB3 is an inorganic, organic or organic-inorganic composite material, the inorganic material may be at least one selected from silicon nitride (SiNx), silicon oxide (SiOX), silicon oxynitride (SiON), and the like, and the organic material may be Polyimide (PI), and the like. For example: the encapsulation layer FB may include a first inorganic encapsulation layer FB1, an organic encapsulation layer FB2, and a second inorganic encapsulation layer FB3, which are stacked; the organic encapsulation layer FB2 is located at the inner periphery of the retaining wall 110 and covers the display area AA; the first inorganic encapsulation layer FB1 and the second inorganic encapsulation layer FB3 cover the display area AA, the retaining wall 110 and the peripheral area of the retaining wall 110; wherein an orthogonal projection of the first inorganic encapsulation layer FB1 on the substrate base plate 1000 overlaps an orthogonal projection of the second inorganic encapsulation layer FB3 on the substrate base plate 1000. Thus, the first inorganic encapsulation layer FB1 and the second inorganic encapsulation layer FB3 extend to the peripheral region of the retaining wall 110, so that the organic encapsulation layer FB and the display region can be well blocked from water and oxygen.

As shown in fig. 2, 6g, 8a, and 8b, the touch electrode 800 may include a plurality of first touch electrodes 810 and a plurality of second touch electrodes 820 arranged in a crossing manner, so that the shape of the orthographic projection of the touch electrode 800 on the substrate 1000 is a grid. Exemplarily, an orthographic projection of the touch electrode 800 on the substrate base 1000 does not overlap with an orthographic projection of the opening regions (e.g., KK1, KK2, KK3, KK4) on the substrate base 1000. It is understood that in the display panel, the touch electrode 800 may be at least one of the plurality of first touch electrodes 810 and second touch electrodes 820, for example: in a partial display area of the display panel. For example: the first color, the second color, the third color and the fourth color at least partially correspond to the sub-pixel regions, and the touch electrode only includes a plurality of first touch electrodes 810 or a plurality of second touch electrodes 820.

Illustratively, the first touch electrodes 810 are disposed on the same conductive film layer, and the second touch electrodes 820 are disposed on the same conductive film layer. Moreover, the layer where the first touch electrode 810 is located on the side, away from the substrate 1000, of the packaging layer FB, and the layer where the second touch electrode 820 is located on the side, away from the substrate 1000, of the layer where the first touch electrode 810 is located. And an electrode insulating layer 830 is disposed between the layer where the first touch electrode 810 is located and the layer where the second touch electrode 820 is located. Exemplarily, the electrode insulating layer 830 may be positioned at and cover the display region. Alternatively, the electrode insulating layer 830 may cover not only the display region but also the non-display region. Alternatively, the edge of the electrode insulating layer 830 is positioned between the two bank walls BK. Of course, in practical applications, the design may be performed according to practical applications, and is not limited herein.

Illustratively, one or more insulating layers (not shown) may be further disposed between the first touch electrode 810 and the encapsulation layer FB. At least one of the insulating layers may be an inorganic, organic, or organic-inorganic composite material, the inorganic material may be at least one selected from silicon nitride (SiNx), silicon oxide (SiOX), silicon oxynitride (SiON), and the like, and the organic material may be Polyimide (PI), and the like. For example: at least one touch electrode substrate made of silicon nitride (SiNx), silicon oxide (SiOX), or Polyimide (PI) is disposed between the first touch electrode 810 and the packaging layer FB 3.

Illustratively, the touch electrode substrate may be located in and cover the display area. Alternatively, the electrode insulating layer 830 may cover not only the display region but also the non-display region. Or, the edge of the touch electrode substrate is located between the two retaining walls BK. Of course, in practical applications, the design may be performed according to practical applications, and is not limited herein.

In some examples, as shown in fig. 8a, an orthogonal projection of the first touch electrode 810 on the substrate base 1000 and an orthogonal projection of the second touch electrode 820 on the substrate base 1000 may be in the shape of a bar. Since the first touch electrode 810 and the second touch electrode 820 are arranged in an intersecting manner, the orthographic projection of the first touch electrode 810 on the substrate 1000 and the orthographic projection of the second touch electrode 820 on the substrate 1000 can form a grid shape. Alternatively, as shown in fig. 8b, the orthographic projection of the first touch electrode 810 on the substrate 1000 and the orthographic projection of at least one partial structure of the second touch electrode 820 on the substrate 1000 may be in a grid shape.

Illustratively, the first touch electrode 810 and the second touch electrode 820 are arranged in an intersecting manner, and an orthogonal projection of the first touch electrode 810 on the substrate 1000 and an orthogonal projection of the second touch electrode 820 on the substrate 1000 form a grid shape. Alternatively, at least a portion of the first touch electrode 810 and the second touch electrode 820 are overlapped, and an orthogonal projection of the first touch electrode 810 on the substrate 1000 overlaps an orthogonal projection of the second touch electrode 820 on the substrate 1000.

Of course, this disclosure includes but is not limited to such. In practical application, the design may be performed according to practical application requirements, and is not limited herein. The second touch electrode 820 shown in fig. 8b is taken as an example for explanation.

In some examples, as shown in fig. 8c and 8d, the first touch electrode 810 may be electrically connected using a first bridge portion 811. A first end of the first bridging portion 811 may be electrically connected to one first touch electrode 810 through a via 831 penetrating through the electrode insulating layer 830, and a second end of the first bridging portion 811 may be electrically connected to another first touch electrode 810 through a via 832 penetrating through the electrode insulating layer 830. Similarly, as shown in fig. 8c and 8d, the second touch electrode 820 may be electrically connected by using a second bridge portion 821. A first end of the second bridge portion 821 may be electrically connected to one second touch electrode 820 through a via hole penetrating through the electrode insulating layer 830, and a second end of the second bridge portion 821 may be electrically connected to another second touch electrode 820 through a via hole penetrating through the electrode insulating layer 830.

Note that the Light-Emitting element may be provided as an electroluminescent Diode, for example, at least one of an Organic Light Emitting Diode (OLED) and a Quantum Dot Light Emitting Diode (QLED). The light-emitting element may include a first electrode 500 (e.g., an anode of the light-emitting element), a light-emitting functional layer 600, and a second electrode 700 (e.g., a cathode of the light-emitting element) stacked on one another. Of course, this disclosure includes but is not limited to such. In practical application, the design may be performed according to practical application requirements, and is not limited herein.

In practical applications, the materials of the third conductive layer 300, the second conductive layer 200, the first conductive layer 100, the second touch electrode 820, and the first touch electrode 810 may be the same or different. At least one of the third conductive layer 300, the second conductive layer 200, the first conductive layer 100, the second touch electrode 820, and the first touch electrode 810 includes a metal material or an alloy material or other conductive materials, for example: at least one of metallic Aluminum (AL), titanium (Ti), molybdenum (Mo), molybdenum-niobium alloy, aluminum-neodymium alloy, graphene, and the like.

Optionally, at least one of the third conductive layer 300, the second conductive layer 200, the first conductive layer 100, the second touch electrode 820, and the first touch electrode 810 may form a single-layer structure, or a stacked-layer structure formed by forming sub-layers of mo/al/mo, ti/al/ti.

Optionally, at least one of the third conductive layer 300, the second conductive layer 200, the first conductive layer 100, the second touch electrode 820 and the first touch electrode 810 has a thickness ranging from 100nm to 500 nm.

Exemplarily, the following steps are carried out: the third conductive layer 300, the second conductive layer 200, and the first conductive layer 100 may be selected from at least one of metal Aluminum (AL), titanium (Ti), molybdenum (Mo), and the like; or at least one of the second touch electrode 820 and the first touch electrode 810 is a laminated junction formed by titanium/aluminum/titanium sub-layers; alternatively, at least one of the materials of the second touch electrode 820 and the first touch electrode 810 includes graphene. Because the surface reflectivity of the conductive layer is high, for example: the molybdenum metal material has a high surface reflectivity, which easily causes the second capacitor C1 to reflect the external ambient light or the light emitted by the light-emitting functional layer 600 to the adjacent opening area, thereby causing the problem of light-emitting crosstalk or poor light mixing effect.

In view of the above, the embodiments of the present disclosure provide display panels, as shown in fig. 5a to 5i to 7f, including a plurality of repeating units; the repeating unit may include a plurality of sub-pixels, for example, the plurality of sub-pixels may include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. That is, the repeating unit may be made to include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. Therefore, the display panel can adopt the first color sub-pixel, the second color sub-pixel and the third color sub-pixel to mix light so as to realize color display. In some examples, the first color, the second color, and the third color may be selected from red, green, and blue. For example, the second color is red, the first color is green, and the third color is blue. Of course, embodiments of the present disclosure include, but are not limited to, this. The first, second, and third colors described above may also be other colors.

Optionally, the repeating unit may further include a fourth color sub-pixel. Therefore, the display panel can mix light by adopting the first color sub-pixel, the second color sub-pixel, the third color sub-pixel and the fourth color sub-pixel to realize color display. In some examples, the fourth color sub-pixel may be a green sub-pixel, or may also be a white sub-pixel, or may also be a yellow sub-pixel, or may also be another color, which is not limited herein.

The following description will be given taking an example in which the repeating unit includes a first color sub-pixel, a second color sub-pixel, a third color sub-pixel, and a fourth color sub-pixel, and the first color and the fourth color are green, the second color is red, and the third color is blue.

In some examples, as shown in fig. 5a to 5i to 7f, the first color sub-pixel has the pixel circuit, the first electrode 510, the first color light emitting layer 610, and the opening region KK1 of any of the above embodiments. The orthographic projection of the first color light emitting layer 610 on the substrate 1000 covers the orthographic projection of the opening region KK1 in the first color sub-pixel on the substrate 1000, and the light emitting region of the first color sub-pixel comprises the opening region KK 1. Illustratively, the opening region KK1 may serve as a light emitting region of the first color sub-pixel.

The second color sub-pixel has the pixel circuit, the first electrode 520, the second color light-emitting layer 620, and the opening region KK2 of any of the above embodiments. The orthographic projection of the second color light-emitting layer 620 on the substrate 1000 covers the orthographic projection of the opening region KK2 in the second color sub-pixel on the substrate 1000, and the light-emitting region of the second color sub-pixel comprises the opening region KK 2. Illustratively, the opening region KK2 may serve as a light emitting region of the second color sub-pixel.

The third color sub-pixel includes the pixel circuit, the first electrode 530, the third color light-emitting layer 630, and the opening region KK3 according to any of the embodiments described above. Wherein, the orthographic projection of the third color light emitting layer 630 on the substrate 1000 covers the orthographic projection of the opening region KK3 in the third color sub-pixel on the substrate 1000, and the light emitting region of the third color sub-pixel includes the opening region KK 3. Illustratively, the opening region KK3 may serve as a light emitting region of the third color sub-pixel.

The fourth color sub-pixel includes the pixel circuit, the first electrode 540, the fourth color light-emitting layer 640, and the opening region KK4 in any of the embodiments described above. Wherein an orthographic projection of the fourth color light emitting layer 640 on the substrate 1000 covers an orthographic projection of the opening region KK4 in the fourth color sub-pixel on the substrate 1000, and a light emitting region of the fourth color sub-pixel includes the opening region KK 4. Exemplarily, the opening region KK4 may be a light emitting region of the fourth color sub-pixel.

The area of the opening region KK1 in the first color sub-pixel is smaller than the area of the opening region KK3 in the third color sub-pixel. The area of the opening region KK2 in the second color sub-pixel is smaller than the area of the opening region KK3 in the third color sub-pixel. The area of the opening region KK4 in the fourth color sub-pixel is smaller than the area of the opening region KK3 in the third color sub-pixel.

Illustratively, when the light emission efficiency of the green light emitting element and the red light emitting element is higher than that of the blue light emitting element, the influence on the adjacent sub-pixels is large, and therefore the area of the opening region of the green sub-pixel can be made smaller than that of the blue sub-pixel, and the area of the opening region of the red sub-pixel can be made smaller than that of the blue sub-pixel, so that the emission of blue light can be improved. In addition, the parts of the second capacitors C1 of the green and red sub-pixels, which are not covered by the opening regions, are increased, so that the second capacitors C1 are exposed, and the light emitting interference and the light mixing effect are poor.

In particular implementation, in the embodiment of the present disclosure, as shown in fig. 3 to 6g, the transistor array layer includes a plurality of capacitive conductive portions R, and at least a portion of the sub-pixels include the capacitive conductive portions R; in the same sub-pixel, the overlapping area exists between the capacitance conductive part R and the power signal line pattern VDD and/or the data line pattern. For example, in the same sub-pixel, the capacitance conductive part R has an overlapping region with the power supply signal line pattern VDD and the data line pattern. Alternatively, in the same sub-pixel, there is an overlapping area between the capacitive conductive part R and the power supply signal line pattern VDD. Or, in the same sub-pixel, the overlapping area exists between the capacitance conductive part R and the data line pattern. Alternatively, the overlapping area of the capacitive conductive part R and the power signal line pattern VDD is larger than the overlapping area of the capacitive conductive part R and the data line pattern DA.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 3 to 6g, an orthogonal projection of the capacitive conductive part R in the first color sub-pixel on the substrate 1000 and an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000 have a first auxiliary overlapping area S1. The orthographic projection of the capacitive conductive part R in the second color sub-pixel on the substrate 1000 and the orthographic projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000 have a second auxiliary overlapping area S2. The orthographic projection of the capacitive conductive part R in the sub-pixel of the third color on the substrate 1000 and the orthographic projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000 have a third auxiliary overlapping area S3. The orthographic projection of the capacitive conductive part R in the fourth color sub-pixel on the substrate 1000 and the orthographic projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000 have a fourth auxiliary overlapping area S4. Wherein at least one of the first and second auxiliary overlapping areas S1 and S2 and the fourth auxiliary overlapping area S4 is greater than the third auxiliary overlapping area S3. For example: the first auxiliary overlapping area S1 is greater than the second auxiliary overlapping area S2, and the second auxiliary overlapping area S2 is greater than the third auxiliary overlapping area S3; alternatively, the first auxiliary overlapping area S1 is greater than the second auxiliary overlapping area S2, and the second auxiliary overlapping area S2 is equal to the third auxiliary overlapping area S3; or the first auxiliary overlapping area S1 is substantially equal to the second auxiliary overlapping area S2, and the second auxiliary overlapping area S2 is larger than the third auxiliary overlapping area S3. In this way, the second capacitor C1 can be shielded by the touch electrode 800, so that the problems of light emitting interference and poor light mixing effect caused by the second capacitor C1 can be solved.

Illustratively, as shown in fig. 3 to 6g, the transistor array layer ZA includes a plurality of data line patterns (e.g., DA1, DA2) and a plurality of power supply signal line patterns (e.g., VDD), and the transistor array layer ZA includes a plurality of capacitive conductive parts R, the sub-pixel includes a capacitive conductive part R, and the capacitive conductive part R has an overlapping region with the power supply signal line patterns VDD and/or the data line patterns DA; for example: a plurality of capacitive conductive portions R are formed in the second conductive layer 200. Of course, other conductive layers may be formed, such as: a first conductive layer.

Optionally, at least a part of the capacitor conductive part R forms a capacitor with the power signal line pattern VDD or the data line pattern DA, that is; at least one insulating layer is present between the capacitive conductive part R and the power signal line pattern VDD or the data line pattern DA. For example: the capacitive conducting part R forms one capacitive plate of the second capacitor C1. Specifically, part or all of the capacitive conductive portion forms the first plate C11 or the second plate C12 of the second capacitor.

Alternatively, the capacitive conductive part R may be in an arc shape or an irregular pattern.

Alternatively, the capacitive conductive part R includes an auxiliary conductive part WD formed on the second conductive layer 200, the auxiliary conductive part WD being located below the data line pattern (e.g., DA1, DA2), and a first end of the auxiliary conductive part WD being connected to the power supply signal line pattern VDD, for example: a first end of the auxiliary conductive portion WD is connected to the power signal line pattern VDD through the via hole of the first interlayer insulating layer 930; the second end of the auxiliary conductive portion WD extends to below the data line pattern, and the auxiliary conductive portion WD has an overlapping region with the power signal line pattern and/or the data line pattern, that is, the second plate C12 of the second capacitor C1 is formed on the auxiliary conductive portion WD, and the first plate of the second capacitor C1 is formed on the corresponding sub-pixel data line pattern DA (for example, DA1, DA 2); or the first plate of the second capacitor C1 is formed on the corresponding sub-pixel data line pattern DA (e.g., DA1, DA2) having an overlapping region with the auxiliary conductive portion WD.

Optionally, the capacitive conductive part R may further include a second auxiliary conductive part WN2 (not shown), the second auxiliary conductive part WN2 is formed on the second conductive layer 200, the second auxiliary conductive part WN2 is located under the data line pattern (e.g., DA1, DA2) of the corresponding sub-pixel, and the first end of the second auxiliary conductive part WD2 is connected to the data line pattern (e.g., data line pattern DA1) corresponding to each sub-pixel, for example: the first end of the second auxiliary conductive part WD2 is connected to the data line pattern (e.g., data line pattern DA1) corresponding to each sub-pixel through the via hole of the first interlayer insulating layer 930; a second end of the second auxiliary conductive part WN2 extends to a position below the power signal line pattern, and an overlapping region exists between the second auxiliary conductive part WN2 and the power signal line pattern and/or the data line pattern, that is, a first plate of the second capacitor C1 is formed on the second auxiliary conductive part WD2, and a second plate of the second capacitor C1 is the power signal line pattern VDD; or the second plate of the second capacitor C1 is formed at the corresponding sub-pixel power signal line pattern VDD having an overlapping region with the second auxiliary conductive part WD 2.

For ease of understanding, at least some of the following embodiments will be described with the capacitive conductive portion R as the auxiliary conductive portion WD. Illustratively, since the area of the opening region KK1 in the first color sub-pixel is smaller than the area of the opening region KK3 in the third color sub-pixel, the portion of the capacitive conductive part R in the first color sub-pixel that is blocked by the opening region is smaller, and the portion of the capacitive conductive part R in the third color sub-pixel that is blocked by the opening region is larger, which results in a stronger effect of emitting light by the capacitive conductive part R in the first color sub-pixel. By making the first auxiliary overlapping area S1 larger than the third auxiliary overlapping area S3, the embodiment of the disclosure can make more portions of the capacitive conductive part R in the first color sub-pixel shielded by the touch electrode 800, thereby reducing the problems of light emitting interference and poor light mixing effect caused by the capacitive conductive part R in the first color sub-pixel.

Illustratively, since the area of the opening region KK2 in the second color sub-pixel is smaller than the area of the opening region KK3 in the third color sub-pixel, the portion of the capacitive conductive part R in the second color sub-pixel that is blocked by the opening region is smaller, and the portion of the capacitive conductive part R in the third color sub-pixel that is blocked by the opening region is larger, which results in a stronger effect of emitting light by the capacitive conductive part R in the second color sub-pixel. By making the second auxiliary overlapping area S2 larger than the third auxiliary overlapping area S3, the embodiment of the disclosure can make more portions of the capacitive conductive part R in the second color sub-pixel shielded by the touch electrode 800, thereby reducing the problems of light emitting interference and poor light mixing effect caused by the capacitive conductive part R in the second color sub-pixel.

Illustratively, since the area of the opening region KK4 in the fourth color sub-pixel is smaller than the area of the opening region KK3 in the third color sub-pixel, the portion of the capacitive conductive part R in the fourth color sub-pixel that is blocked by the opening region is smaller, and the portion of the capacitive conductive part R in the third color sub-pixel that is blocked by the opening region is larger, which results in a stronger effect of emitting light by the capacitive conductive part R in the fourth color sub-pixel. In the embodiment of the disclosure, the fourth auxiliary overlapping area S4 is larger than the third auxiliary overlapping area S3, so that the portion of the capacitive conductive part R in the fourth color sub-pixel, which is shielded by the touch electrode 800, is more, and the problems of light emitting interference and poor light mixing effect caused by the capacitive conductive part R in the fourth color sub-pixel can be reduced.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 6e, the area of the opening region KK1 in the first color sub-pixel may be made smaller than the area of the opening region KK2 in the second color sub-pixel. For example, the area of the opening region of the green sub-pixel may be made smaller than the area of the opening region of the red sub-pixel. In this way, compared with the second color sub-pixel, the first color sub-pixel has less part of the capacitance conductive part R which is blocked by the opening region, and the first auxiliary overlapping area S1 is approximately equal to the second auxiliary overlapping area S2; or, the first auxiliary overlapping area S1 is larger than the second auxiliary overlapping area S2, so that compared with the second color sub-pixel, the part of the capacitive conductive part R shielded by the touch electrode 800 is more in the first color sub-pixel, and thus the problems of light emitting interference and poor light mixing effect caused by the capacitive conductive part R in the first color sub-pixel can be further reduced.

In particular implementation, in the embodiment of the present disclosure, the area of the opening region KK1 of the first color sub-pixel may be 100 μm²～130μm²The shape of opening region KK1 is not limited, for example: can be as follows: polygonal, rectangular, square, diamond, oval, circular, and the like; of course, other irregular patterns are also possible, such as: and the closed graph is formed by at least 2 arc line segments and 1 straight line segment. For example: the opening region KK1 of the first color sub-pixel has a rectangular shape, a first side length of 12 μm to 13 μm, and a second side length of the opening region KK1 of the first color sub-pixel is 9 μm to 10 μm.

Optionally, the opening area of the opening region KK1 of the first color sub-pixel is 10 × 10 μm²～12*10μm²Or 11 x 10 μm²～12*10μm². Optionally, the opening area of the opening region KK1 of the further first color sub-pixel is 13 × 9 μm²～12*10μm². For example, the area of the opening region KK1 of the first color sub-pixel may be 13 × 9 μm²(length x width), or the area of the opening region KK1 of the first color sub-pixel may be 12 x 10 μm²(length x width). Of course, in practical application, the method can be performed according to the requirements of practical application environmentThe line design is determined and not limited herein.

In particular implementation, in the embodiment of the present disclosure, the area of the opening region KK2 of the second color sub-pixel may be 120 μm²～200μm²The shape of opening region KK2 is not limited, and may be, for example: rectangular, square, rhombic, oval, circular, etc.; of course, other irregular patterns are also possible, such as: and the closed graph is formed by at least 2 arc line segments and 1 straight line segment. For example: the opening region KK2 of the second color sub-pixel is square with sides of 13 μm-15 μm. Optionally, the opening area of the opening region KK2 of the second color sub-pixel is 13 × 10 μm²～19*10μm²Or 13 x 15 μm²～18*11μm². Alternatively, the opening area of the opening region KK1 of the first color sub-pixel may be 13 × 13 μm²～14*14μm². For example, the area of the opening region KK2 of the second color sub-pixel may be 13 × 13 μm²Alternatively, the area of the opening region KK2 of the second color sub-pixel may be 14 × 14 μm². Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

In practical implementation, in the embodiment of the present disclosure, the area of the opening region KK3 of the sub-pixel of the third color is 180 μm²～230μm²The shape of opening region KK3 is not limited, and may be, for example: rectangular, square, rhombic, oval, circular, etc.; of course, other irregular patterns are also possible, such as: and the closed graph is formed by at least 2 arc line segments and 1 straight line segment. For example: the opening region KK3 of the third color sub-pixel has a rectangular shape, a first side length of 15 μm to 16 μm, and a second side length of the opening region KK1 of the first color sub-pixel is 13 μm to 14 μm. Optionally, the opening area of the opening region KK3 of the third color sub-pixel is 18 × 10 μm²～23*10μm²Or 20 x 10 μm²～22*10μm². Alternatively, the opening area of the opening region KK1 of the first color sub-pixel may be 15 × 13 μm²～16*14μm²(length x width). For example, the area of the opening region KK3 of the third color sub-pixel may be 15 × 13 μm²(length x width). Alternatively, the area of the opening region KK3 of the third color sub-pixel may be 16 × 13 μm²(length x width). Alternatively, the area of the opening region KK3 of the third color sub-pixel may be 16 × 14 μm²(length x width). Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

In practical implementation, in the embodiment of the present disclosure, the area of the opening region KK4 of the fourth color sub-pixel may be 100 μm²～230μm²The shape of opening region KK4 is not limited, and may be, for example: rectangular, square, rhombic, oval, circular, etc.; of course, other irregular patterns are also possible, such as: and the closed graph is formed by at least 2 arc line segments and 1 straight line segment. For example: the opening region of the fourth color sub-pixel is elliptical and may have an area of 100 μm²～130μm²(ii) a Alternatively, opening region KK4 of the fourth color sub-pixel has a rectangular shape with a first side length of 12 μm-13 μm and a second side length of 9 μm-10 μm of opening region KK4 of the fourth color sub-pixel. Optionally, the opening area of the opening region KK1 of the first color sub-pixel is 13 × 9 μm²～12*10μm². For example, the area of the opening region KK4 of the fourth color sub-pixel may be 13 × 9 μm²(length x width), or the area of the opening region KK4 of the fourth color sub-pixel may be 12 x 10 μm²(length x width). Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

In particular implementation, in the disclosed embodiments, the first auxiliary overlapping area S1 may be 3 μm²～40μm². Alternatively, the first auxiliary overlapping area S1 may be 6 μm²～20μm². For example, the first auxiliary overlapping area S1 may be 3 μm². Alternatively, the first auxiliary overlapping area S1 may be 6 μm². Alternatively, the first auxiliary overlapping area S1 may be 10 μm². Alternatively, the first auxiliary overlapping area S1 may be 20 μm². Alternatively, the first auxiliary overlapping area S1 may be 30 μm². Of course, in practiceIn the application, the design and determination may be performed according to the requirements of the actual application environment, and is not limited herein.

In particular implementation, in the embodiment of the present disclosure, the second auxiliary overlapping area S2 may be 0-10 μm². Optionally, the second auxiliary overlapping area S2 may be 0-5 μm². For example, the second auxiliary overlapping area S2 may be 0 μm². Alternatively, the second auxiliary overlapping area S2 may be 5 μm². Alternatively, the second auxiliary overlapping area S2 may be 10 μm². Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

In particular implementation, in the embodiment of the disclosure, the third auxiliary overlapping area S3 may be 0-6 μm². Optionally, the third auxiliary overlapping area S3 may be 0-3 μm². For example, the third auxiliary overlapping area S3 may be 0 μm². Alternatively, the third auxiliary overlapping area S3 may be 3 μm². Alternatively, the third auxiliary overlapping area S3 may be 6 μm². Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

In particular implementation, in the embodiment of the disclosure, the fourth auxiliary overlapping area S4 may be 0-40 μm². Optionally, the fourth auxiliary overlapping area S4 may be 0-15 μm². For example, the fourth auxiliary overlapping area S4 may be 0 μm². Alternatively, the fourth auxiliary overlapping area S4 may be 5 μm². Alternatively, the fourth auxiliary overlapping area S4 may be 15 μm². Alternatively, the fourth auxiliary overlapping area S4 is substantially equal to at least one of the first auxiliary overlapping area S3, the second auxiliary overlapping area S2, and the third auxiliary overlapping area S3; alternatively, the fourth auxiliary overlapping area S4 is larger than at least one of the first auxiliary overlapping area S3, the second auxiliary overlapping area S2, and the third auxiliary overlapping area S3 is equal. Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 6g, the area of the opening region KK1 in the first color sub-pixel may be made larger than the area of the opening region KK4 in the fourth color sub-pixel. The area of the opening region KK1 in the first color sub-pixel may be made substantially equal to the area of the opening region KK4 in the fourth color sub-pixel. These may be designed according to the requirements of practical application, and are not limited herein.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 6g, the second conductive layer 200 may include a capacitive conductive portion R (WD) (described by taking the auxiliary conductive portion WD as the capacitive conductive portion R), and the first auxiliary overlapping area S1 may include an overlapping area between an orthographic projection of the auxiliary conductive portion in the first color sub-pixel on the substrate 1000 and an orthographic projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000. The second auxiliary overlapping area S2 may include an overlapping area between an orthogonal projection of the auxiliary conductive portion in the second color sub-pixel on the substrate 1000 and an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000. The third auxiliary overlapping area S3 includes an overlapping area between an orthogonal projection of the auxiliary conductive portion in the sub-pixel of the third color on the substrate 1000 and an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000. The fourth auxiliary overlapping area S4 includes an overlapping area between an orthogonal projection of the auxiliary conductive portion in the fourth color sub-pixel on the substrate 1000 and an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000. In this way, the auxiliary conductive part can be shielded by the touch electrode (e.g., the second touch electrode 820), so that the problems of light emitting interference and poor light mixing effect caused by the light reflected by the auxiliary conductive part can be reduced.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 9c, the auxiliary conductive portion WD in the first color sub-pixel includes the first auxiliary exposing portion WD1, and an orthogonal projection of the first auxiliary exposing portion WD1 on the substrate board 1000 does not overlap with an orthogonal projection of the data line pattern DA2 and the power signal line pattern VDD on the substrate board 1000, respectively. The first auxiliary overlapping area S1 includes a first auxiliary sub overlapping area S11, and the first auxiliary exposure portion WD1 has a first auxiliary sub overlapping area S11 between an orthogonal projection of the substrate base plate 1000 and an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the substrate base plate 1000.

Exemplarily, in the first color sub-pixel, the orthographic projection of the first auxiliary exposure part WD1 on the substrate base plate 1000 is located between the orthographic projection of the data line pattern DA2 and the power supply signal line pattern VDD on the substrate base plate 1000.

Alternatively, the orthographic projection of the first auxiliary exposure portion WD1 on the substrate board 1000 may be positioned on the orthographic projection side of the data line pattern DA2 on the substrate board 1000 away from the power signal line pattern VDD on the substrate board 1000. Alternatively, the orthographic projection of the first auxiliary exposure portion WD1 on the substrate board 1000 may be positioned on the orthographic projection side of the power signal line pattern VDD on the substrate board 1000 away from the data line pattern DA2 on the substrate board 1000.

It is understood that the first auxiliary exposure WD1 may include at least one (not shown) of the first auxiliary exposure first region WD11 (not shown), the first auxiliary exposure second region WD12 (not shown), the first auxiliary exposure third region WD 13; the first auxiliary exposed portion first region WD11 is a first region where the orthographic projection of the auxiliary conductive portion WD on the substrate 1000 is located between the orthographic projection of the data line pattern DA2 and the orthographic projection of the power signal line pattern VDD on the substrate 1000, the first auxiliary exposed portion second region WD12 is a second region where the orthographic projection of the auxiliary conductive portion WD on the substrate 1000 is located on the orthographic projection side of the data line pattern DA2 on the substrate 1000 away from the power signal line pattern VDD on the substrate 1000, and the first auxiliary exposed portion third region WD13 is a third region where the orthographic projection of the auxiliary conductive portion WD on the substrate 1000 is located on the orthographic projection side of the power signal line pattern VDD on the substrate 1000 away from the data line pattern DA2 on the substrate 1000.

In particular implementation, in the disclosed embodiments, the first auxiliary sub-overlapping area S11 may be 2 μm²～10μm². Alternatively, the first auxiliary sub-overlapping area S11 may be 3 μm²～6μm². Illustratively, the first auxiliary sub-overlap area S11 may be 2 μm². Alternatively, the first auxiliary sub-overlapping area S11 may be 3 μm². Alternatively, the first auxiliary sub-overlapping area S11 may be 5 μm². Alternatively, the first auxiliary sub-overlapping area S11 may be 6 μm². Alternatively, the first auxiliary sub-overlapping area S11 may be 10 μm²And is not limited herein. Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 6d, in the same sub-pixel, the orthographic projection of the auxiliary conductive portion WD on the substrate 1000 has a total area Sm. Wherein, the ratio range between the first auxiliary overlapping area S1 and the total area Sm can be 1/6-3/4. Alternatively, the range of the ratio between the first auxiliary overlapping area S1 and the total area Sm may be: 1/3-2/3, namely 1/3 is less than or equal to S1/Sm is less than or equal to 2/3. For example, S1/Sm may be set to 1/3, S1/Sm may be set to 2/3, and S1/Sm may be set to 1/2. Of course, in practical applications, the specific value of S1/Sm may be set according to the requirements of practical applications, and is not limited herein.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 6d, in the same sub-pixel, the orthographic projection of the auxiliary conductive portion WD on the substrate 1000 has a total area Sm. Wherein, the ratio range between the first auxiliary sub-overlapping area S11 and the total area Sm may be: 1/8-2/3. Alternatively, the ratio range between the first auxiliary sub-overlapping area S11 and the total area Sm may be: 1/6-1/3, namely 1/6 is less than or equal to S11/Sm is less than or equal to 1/3. For example, S11/Sm may be set to 1/6, S11/Sm may be set to 1/4, and S11/Sm may be set to 1/3. Of course, in practical applications, the specific value of S11/Sm may be set according to the requirements of practical applications, and is not limited herein.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 9a to 9c, in the first color sub-pixel, an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000 may also be covered on an orthogonal projection of the first auxiliary exposure portion WD1 on the substrate 1000. This makes it possible to cover the first auxiliary exposing portion WD1, which may reflect light, as much as possible.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 9b and 9c, the auxiliary conductive portion WD in the first color sub-pixel may further include a first auxiliary shielding portion WZ1, and an orthogonal projection of the first auxiliary shielding portion WZ1 on the substrate board 1000 overlaps an orthogonal projection of at least one of the data line pattern DA2 and the power supply signal line pattern VDD on the substrate board 1000. Here, the first auxiliary shield portion WZ1 and the first auxiliary exposure portion WD1 of the same auxiliary conductive portion are integrally provided, thereby forming an auxiliary conductive portion. For example, as shown in fig. 9b, the width of the first auxiliary exposing portion WD1 in the column direction F3 may be made substantially equal to the width of the first auxiliary shielding portion WZ1 in the column direction F3. This can reduce the difficulty of manufacturing the auxiliary conductive portion in the first color sub-pixel. As shown in fig. 9c, the width of the first auxiliary exposing portion WD1 in the column direction F3 may be made smaller than the width of at least a part of the first auxiliary shielding portion WZ1 in the column direction F3. This may further shield the first auxiliary exposing portion WD 1. For example, the width of the first auxiliary exposing portion WD1 in the row direction F4 may be smaller than the width of at least a part of the first auxiliary shielding portion WZ1 in the row direction F4, so that the exposed area of the auxiliary conductive portion WD may be smaller, which is beneficial to reducing the reflected light generated by the auxiliary conductive portion WD.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 9c, the auxiliary conductive portion WD in the sub-pixel of the second color includes the second auxiliary exposing portion WD2, and an orthogonal projection of the second auxiliary exposing portion WD2 on the substrate board 1000 does not overlap with an orthogonal projection of the data line pattern DA3 and the power signal line pattern VDD on the substrate board 1000, respectively; and the second auxiliary overlapping area S2 includes a second auxiliary sub overlapping area S12, and the second auxiliary exposure portion WD2 has a second auxiliary sub overlapping area S12 between the orthographic projection of the substrate base plate 1000 and the orthographic projection of the touch electrode (e.g., the second touch electrode 820) on the substrate base plate 1000. Exemplarily, in the second color sub-pixel, the orthographic projection of the second auxiliary exposure part WD2 on the substrate base plate 1000 is located between the orthographic projection of the data line pattern DA3 and the power supply signal line pattern VDD on the substrate base plate 1000. Alternatively, the orthographic projection of the second auxiliary exposing portion WD2 on the base substrate 1000 is located on the orthographic projection side of the data line pattern DA3 on the base substrate 1000 away from the power signal line pattern VDD on the base substrate 1000. Alternatively, the orthographic projection of the second auxiliary exposure portion WD2 on the base substrate 1000 is located on the orthographic projection side of the power signal line pattern VDD on the base substrate 1000 away from the data line pattern DA3 on the base substrate 1000.

In practical implementation, in the embodiment of the present disclosure, the second auxiliary sub-overlapping area S12 may be 0-4.5 μm². Optionally, the second auxiliary sub-overlapping area S12 may be 0-2.2 μm². For example, the second auxiliary sub-overlapping area S12 may be 0 μm². Alternatively, the second auxiliary sub-overlapping area S12 may be 1.5 μm². Alternatively, the second auxiliary sub-overlapping area S12 may be 2.2 μm². Alternatively, the second auxiliary sub-overlapping area S12 may be 3.5 μm². Alternatively, the second auxiliary sub-overlapping area S12 may be 4.5 μm². Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 6d, in the same sub-pixel, for example: the second color sub-pixel, the orthogonal projection of the auxiliary conductive portion WD to the substrate 1000 has a total area Sm. In the same sub-pixel, the ratio range between the second auxiliary overlapping area S2 and the total area Sm (second color sub-pixel) may be: 1/20-3/4. Alternatively, the range of the ratio between the second auxiliary overlapping area S2 and the total area Sm (second color sub-pixel) may be: 1/10-7/20, namely 1/10 is less than or equal to S2/Sm is less than or equal to 7/20. For example, S2/Sm may be set to 1/10, S2/Sm may be set to 1/5, and S2/Sm may be set to 7/20. Of course, in practical applications, the specific value of S2/Sm may be set according to the requirements of practical applications, and is not limited herein.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 6d, in the same sub-pixel, for example: the second color sub-pixel, the orthogonal projection of the auxiliary conductive portion WD to the substrate 1000 has a total area Sm. Wherein, the ratio range between the second auxiliary sub-overlapping area S12 and the total area Sm may be: 1/10-1/2. The ratio range between the second auxiliary sub-overlapping area S12 and the total area Sm may be: 1/5-1/4, namely 1/5 is less than or equal to S12/Sm is less than or equal to 1/4. For example, S12/Sm may be set to 1/4, S12/Sm may be set to 1/5, and S12/Sm may be set to 9/40. Of course, in practical applications, the specific value of S12/Sm may be set according to the requirements of practical applications, and is not limited herein.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 9a to 9c, in the second color sub-pixel, an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000 may also be covered on an orthogonal projection of the second auxiliary exposure portion WD2 on the substrate 1000. This makes it possible to cover the second auxiliary exposing portion WD2, which may reflect light, as much as possible.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 9b and 9c, the auxiliary conductive portion WD in the second color sub-pixel may further include a second auxiliary shielding portion WZ 2. And an orthogonal projection of the second auxiliary shielding portion WZ2 on the base substrate 1000 overlaps with an orthogonal projection of at least one of the data line pattern and the power signal line pattern VDD on the base substrate 1000. Wherein the second auxiliary shield portion WZ2 and the second auxiliary exposure portion WD2 of the same auxiliary conductive portion are integrally provided, thereby forming an auxiliary conductive portion. For example, as shown in fig. 9b, the width of the second auxiliary exposing portion WD2 in the column direction F3 may be made substantially equal to the width of the second auxiliary shielding portion WZ2 in the column direction F3. This can reduce the difficulty of manufacturing the auxiliary conductive part in the second color sub-pixel. As shown in fig. 9c, the width of the second auxiliary exposing portion WD2 in the column direction F3 may be made smaller than the width of at least a portion of the second auxiliary shielding portion WZ2 in the column direction F3. This may further shield the second auxiliary exposing portion WD 2. Illustratively, the width of the second auxiliary exposing portion WD2 in the row direction F4 is smaller than the width of at least a part of the second auxiliary shielding portion WZ2 in the row direction F4.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 6g, the auxiliary conductive portion WD in the sub-pixel of the third color includes the third auxiliary exposing portion WD3, and an orthogonal projection of the third auxiliary exposing portion WD3 on the substrate board 1000 does not overlap with an orthogonal projection of the data line pattern DA1 and the power signal line pattern VDD on the substrate board 1000, respectively; and the third auxiliary overlapping area S3 includes a third auxiliary sub overlapping area S13, and the third auxiliary exposure portion WD3 has a third auxiliary sub overlapping area S13 between the orthographic projection of the substrate base plate 1000 and the orthographic projection of the touch electrode (e.g., the second touch electrode 820) on the substrate base plate 1000. Exemplarily, in the third color sub-pixel, the orthographic projection of the third auxiliary exposure part WD3 on the base substrate 1000 is located between the orthographic projection of the data line pattern DA1 and the power supply signal line pattern VDD on the base substrate 1000.

In practical implementation, in the embodiment of the present disclosure, the third auxiliary sub-overlapping area S13 may be 0-2.5 μm². Optionally, the third auxiliary sub-overlapping area S13 may be 0-1.2 μm². For example, the third auxiliary sub-overlapping area S13 may be 0 μm². Alternatively, the third auxiliary sub-overlapping area S13 may be 0.5 μm². Alternatively, the third auxiliary sub-overlapping area S13 may be 1.0 μm². Alternatively, the third auxiliary sub-overlapping area S13 may be 1.2 μm². Alternatively, the third auxiliary sub-overlapping area S13 may be 2.5 μm². Of course, in practical application, the design may be determined according to the requirements of the practical application environment, and the details are not limited herein.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 6d, in the same sub-pixel, for example: the third color sub-pixel, the orthogonal projection of the auxiliary conductive portion WD to the substrate 1000 has a total area Sm. Wherein, the ratio range between the third auxiliary overlapping area S3 and the total area Sm may be: 0 to 1/2; alternatively, the range of the ratio between the third auxiliary overlapping area S3 and the total area Sm may be: 0-1/4, i.e., 0 is not less than S3/Sm is not more than 1/4. For example, S3/Sm may be set to 0, S3/Sm may be set to 1/16, or S3/Sm may be set to 1/4. Of course, in practical applications, the specific value of S3/Sm may be set according to the requirements of practical applications, and is not limited herein.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 6d, in the same sub-pixel, for example: the third color sub-pixel, the orthogonal projection of the auxiliary conductive portion WD to the substrate 1000 has a total area Sm. Wherein, the ratio range between the third auxiliary sub-overlapping area S13 and the total area Sm may be: 0 to 1/8; alternatively, the ratio range between the third auxiliary sub-overlap area S13 and the total area Sm may be: 0-1/16, i.e., 0 is not less than S13/Sm is not more than 1/16. For example, S13/Sm may be set to 0, S13/Sm may be set to 1/16, or S13/Sm may be set to 1/32. Of course, in practical applications, the specific value of S13/Sm may be set according to the requirements of practical applications, and is not limited herein.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 9a to 9c, in the sub-pixel of the third color, an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000 may be covered with an orthogonal projection of the third auxiliary exposure portion WD3 on the substrate 1000. This makes it possible to cover the third auxiliary exposing portion WD3, which may reflect light, as much as possible.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 9b and 9c, the auxiliary conductive portion WD in the sub-pixel of the third color may further include a third auxiliary shielding portion WZ 3. And an orthogonal projection of the third auxiliary shielding portion WZ3 on the base substrate 1000 overlaps with an orthogonal projection of at least one of the data line pattern and the power signal line pattern VDD on the base substrate 1000. Wherein the third auxiliary shield portion WZ3 and the third auxiliary exposure portion WD3 of the same auxiliary conductive portion are integrally provided, thereby forming an auxiliary conductive portion. For example, as shown in fig. 9b, the width of the third auxiliary exposing portion WD3 in the column direction F3 may be made substantially equal to the width of the third auxiliary shielding portion WZ3 in the column direction F3. This can reduce the difficulty of manufacturing the auxiliary conductive part in the sub-pixel of the third color. As shown in fig. 9c, the width of the third auxiliary exposing portion WD3 in the column direction F3 may be made smaller than the width of at least a portion of the third auxiliary shielding portion WZ3 in the column direction F3. This may further shield the third auxiliary exposing portion WD 3. Illustratively, the width of the third auxiliary exposing portion WD3 in the row direction F4 is smaller than the width of at least a part of the third auxiliary shielding portion WZ3 in the row direction F4.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 6g, the auxiliary conductive portion WD in the sub-pixel of the fourth color includes the fourth auxiliary exposing portion WD4, and an orthogonal projection of the fourth auxiliary exposing portion WD4 on the substrate board 1000 does not overlap with an orthogonal projection of the data line pattern DA4 and the power signal line pattern VDD on the substrate board 1000, respectively. And the fourth auxiliary overlapping area S4 includes a fourth auxiliary sub overlapping area S14, and the fourth auxiliary exposure portion WD4 has a fourth auxiliary sub overlapping area S14 between the orthographic projection of the substrate base plate 1000 and the orthographic projection of the touch electrode (e.g., the second touch electrode 820) on the substrate base plate 1000. Exemplarily, in the fourth color sub-pixel, the orthographic projection of the fourth auxiliary exposure part WD4 on the substrate base plate 1000 is located between the orthographic projection of the data line pattern DA4 and the power supply signal line pattern VDD on the substrate base plate 1000.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 6d, in the same sub-pixel, for example: the fourth color sub-pixel, the orthogonal projection of the auxiliary conductive portion WD to the substrate 1000 has a total area Sm. Wherein, the ratio range between the fourth auxiliary overlapping area S4 and the total area Sm may be: 1/6-5/6, namely 1/6 is less than or equal to S4/Sm is less than or equal to 5/6. For example, S4/Sm may be set to 1/6, S4/Sm may be set to 2/3, and S4/Sm may be set to 5/6. Of course, in practical applications, the specific value of S4/Sm may be set according to the requirements of practical applications, and is not limited herein.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 6d, in the same sub-pixel, for example: the fourth color sub-pixel, the orthogonal projection of the auxiliary conductive portion WD to the substrate 1000 has a total area Sm. Wherein, the ratio range between the fourth auxiliary sub-overlapping area S14 and the total area Sm may be: 1/3-2/3, namely 1/3 is less than or equal to S14/Sm is less than or equal to 2/3. For example, S14/Sm may be set to 1/3, S14/Sm may be set to 2/3, and S14/Sm may be set to 1/2. Of course, in practical applications, the specific value of S14/Sm may be set according to the requirements of practical applications, and is not limited herein.

In particular implementation, in the embodiment of the present disclosure, the fourth auxiliary sub-overlapping area S14 may be 2 μm²～10μm². Alternatively, the fourth auxiliary sub-overlapping area S14 may be 3 μm²～6μm². Illustratively, the fourth auxiliary sub-overlap area S14 may be 2 μm². Alternatively, the fourth auxiliary sub-overlapping area S14 may be 3 μm². Alternatively, the first and second electrodes may be,the fourth auxiliary sub-overlapping area S14 may be 5 μm². Alternatively, the fourth auxiliary sub-overlapping area S14 may be 6 μm². Alternatively, the fourth auxiliary sub-overlapping area S14 may be 10 μm²And is not limited herein. Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 9a to 9c, in the fourth color sub-pixel, an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000 may be covered with an orthogonal projection of the fourth auxiliary exposure portion WD4 on the substrate 1000. This makes it possible to cover the fourth auxiliary exposing portion WD4, which may reflect light, as much as possible.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 9b and 9c, the auxiliary conductive portion in the fourth color sub-pixel may further include a fourth auxiliary shielding portion WZ 4. And an orthogonal projection of the fourth auxiliary shielding portion WZ4 on the base substrate 1000 overlaps with an orthogonal projection of at least one of the data line pattern and the power signal line pattern VDD on the base substrate 1000. Wherein the fourth auxiliary shield portion WZ4 and the fourth auxiliary exposure portion WD4 of the same auxiliary conductive portion are integrally provided, thereby forming an auxiliary conductive portion. For example, as shown in fig. 9b, the width of the fourth auxiliary exposing portion WD4 in the column direction F3 may be made substantially equal to the width of the fourth auxiliary shielding portion WZ4 in the column direction F3. This can reduce the difficulty of manufacturing the auxiliary conductive part in the sub-pixel of the fourth color. As shown in fig. 9c, the width of the fourth auxiliary exposing portion WD4 in the column direction F3 may be made smaller than the width of at least a portion of the fourth auxiliary shielding portion WZ4 in the column direction F3. This may further shield the fourth auxiliary exposing portion WD 4. Illustratively, the width of the fourth auxiliary exposing portion WD4 in the row direction F4 is smaller than the width of at least a part of the fourth auxiliary shielding portion WZ4 in the row direction F4.

In particular implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 6d, the first auxiliary sub-overlapping area S11 may be made larger than the second auxiliary sub-overlapping area S12. In this way, the number of the auxiliary conductive portions in the first color sub-pixel shielded by the touch electrode (e.g., the second touch electrode 820) is larger in the first color sub-pixel than in the second color sub-pixel, so that the problems of light emission interference and poor light mixing effect caused by light reflected by the first auxiliary exposure portion WD1 can be reduced.

In particular implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 6d, the first auxiliary sub overlapping area S11 may be made larger than the third auxiliary sub overlapping area S13. In this way, the number of the auxiliary conductive portions in the first color sub-pixel shielded by the touch electrode (e.g., the second touch electrode 820) is larger than that of the third color sub-pixel, so that the problems of light emission interference and poor light mixing effect caused by the light reflected by the first auxiliary exposure portion WD1 can be reduced.

In particular implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 6d, the fourth auxiliary sub overlapping area S14 may be made larger than the second auxiliary sub overlapping area S12. In this way, the number of auxiliary conductive portions in the fourth color sub-pixel shielded by the touch electrode (e.g., the second touch electrode 820) is larger than that of the second color sub-pixel, so that the problems of light emission interference and poor light mixing effect caused by light reflected by the fourth auxiliary exposure portion WD4 can be reduced.

In particular implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 6d, the fourth auxiliary sub overlapping area S14 may be made larger than the third auxiliary sub overlapping area S13. In this way, the number of auxiliary conductive portions in the fourth color sub-pixel shielded by the touch electrode (e.g., the second touch electrode 820) is larger than that of the third color sub-pixel, so that the problems of light emission interference and poor light mixing effect caused by light reflected by the fourth auxiliary exposure portion WD4 can be reduced.

In particular implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 6d, the second auxiliary sub-overlapping area S12 may be made larger than the third auxiliary sub-overlapping area S13, so that the first auxiliary sub-overlapping area S11 is larger than the second auxiliary sub-overlapping area S12, and the second auxiliary sub-overlapping area S12 is larger than the third auxiliary sub-overlapping area S13. Thus, the areas of the first auxiliary exposure portion WD1, the second auxiliary exposure portion WD2, and the third auxiliary exposure portion WD3, which are shielded by the touch electrodes (e.g., the second touch electrodes 820), are sequentially increased, so that the problems of light emission interference and poor light mixing effect caused by light reflected by the first auxiliary exposure portion WD1, the second auxiliary exposure portion WD2, and the third auxiliary exposure portion WD3, can be further reduced. Of course, the second auxiliary sub-overlapping area S12 may be substantially equal to the third auxiliary sub-overlapping area S13, for example: the second auxiliary sub-overlap area S12 is equal to the third auxiliary sub-overlap area S13, which is equal to 0; or, the fourth auxiliary sub-overlapping area S14 is equal to at least one of the first auxiliary sub-overlapping area S11, the second auxiliary sub-overlapping area S12, and the third auxiliary sub-overlapping area S13; alternatively, the fourth auxiliary sub-overlapping area S14 is larger than at least one of the first auxiliary sub-overlapping area S11, the second auxiliary sub-overlapping area S12, and the third auxiliary sub-overlapping area S13.

In particular implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 6d, the fourth auxiliary sub overlapping area S14 may be made larger than the first auxiliary sub overlapping area S11. In this way, the fourth auxiliary exposure part WD4 shielded by the touch electrode (e.g., the second touch electrode 820) is larger than the first auxiliary exposure part WD1, so that the problems of light emission interference and poor light mixing effect caused by light reflected by the fourth auxiliary exposure part WD4 can be further reduced. Of course, it is also possible that the fourth auxiliary sub overlapping area S14 is substantially equal to the first auxiliary sub overlapping area S11.

In specific implementation, as shown in fig. 5a to fig. 5i to fig. 7f and fig. 10a and fig. 10b, in the embodiment of the present disclosure, an orthogonal projection of the first capacitor (for example, the second plate Cst2 of the first capacitor) in the first color sub-pixel on the substrate 1000 and an orthogonal projection of the touch electrode (for example, the second touch electrode 820) on the substrate 1000 have a first storage overlapping area SC 1. Illustratively, the first storage overlap area SC1 includes an overlap area between an orthogonal projection of the storage conductive part Cst2 in the first color sub-pixel on the substrate 1000 and an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000.

For example, as shown in fig. 5a to 5i to 7f and fig. 10a and 10b, the grid structure formed by the touch electrode in at least one sub-pixel includes at least 5 internal angles, wherein at least 2 obtuse angles and 2 acute angles are included. For example: 5-10 interior angles, wherein at least 2 obtuse angles and 2 acute angles are provided.

Optionally, at least 4 internal angles of the grid structure formed by the touch electrode in at least one sub-pixel are not equal. For example: in the first color sub-pixel, the second touch electrode 820 forms a 1-a 5 internal angles, wherein a1 is equal to 90 °, a2 and a5 are acute angles, and the angle is 30-80 °; a3 and A4 are continuous obtuse angles, and the angle is 95-150 degrees.

Of course, the above case is not limited. For example, alternatively, a2 and a5 are at equal acute angles and A3 and a4 are at equal obtuse angles. Alternatively, the internal angles forming the grid are all equal, for example: forming a regular pentagon, or hexagon.

Exemplarily, as shown in fig. 5a to 5i to 7f and fig. 10a and 10b, the mesh structure formed by the touch electrode in at least one sub-pixel includes at least 5 sides, wherein at least 2 sides have unequal lengths. For example: in the first color sub-pixel, the second touch electrode 820 forms 5 sides of inner angles a 1-a 5. For example: the lengths of a1 to a5 are all different.

Exemplarily, as shown in fig. 5a to 5i to 7f and fig. 10a and 10b, the structure formed by the touch electrode in at least one sub-pixel includes at least 4 sides, wherein at least 2 sides have unequal widths. Optionally, the width of at least one of the edges of the touch electrode in at least one of the corresponding sub-pixels is gradually reduced. For example: the side a4 has a width decreasing from the start of the angle A4 to the end of the angle A5. Optionally, the touch electrode includes three portions with different widths in at least one of the edges corresponding to one of the sub-pixels. For example: as shown in fig. 9b, one side of the touch electrode includes at least 3 portions with unequal widths, DC1 is greater than DC2, and DC1 is greater than DC 4. The width of the DC4 is small, so that the overlapping of the DC4 and a power signal line can be reduced, and the influence on a touch signal is reduced.

Of course, the above case is not limited. For example, the touch electrodes may alternatively form a polygonal structure with equal sides or widths. For example: regular pentagon, regular hexagon.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 7f and fig. 10a and 10b, an orthogonal projection of the first capacitor in the second color sub-pixel on the substrate 1000 and an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000 have the second storage overlapping area SC 2. Illustratively, the second storage overlap area SC2 includes an overlap area between an orthogonal projection of the storage conductive part Cst2 in the second color sub-pixel on the substrate 1000 and an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 7f and fig. 10a and 10b, an orthogonal projection of the first capacitor in the third color sub-pixel on the substrate 1000 and an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000 have a third storage overlapping area SC 3. Illustratively, the third storage overlap area SC3 includes an overlap area between an orthogonal projection of the storage conductive part Cst2 in the third color sub-pixel on the substrate 1000 and an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 7f and fig. 10a and 10b, an orthogonal projection of the first capacitor in the fourth color sub-pixel on the substrate 1000 and an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000 have a fourth storage overlapping area SC 4. Illustratively, the fourth storage overlap area SC4 includes an overlap area between an orthogonal projection of the storage conductive part Cst2 in the fourth color sub-pixel on the substrate 1000 and an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000.

In particular implementation, in the presently disclosed embodiments, as shown in fig. 5a to 5i to 7f and fig. 10a and 10b, at least one of first storage overlap area SC1, second storage overlap area SC2, and fourth storage overlap area SC4 may be made larger than third storage overlap area SC 3. For example, first storage overlap area SC1, second storage overlap area SC2, and fourth storage overlap area SC4 may each be made larger than third storage overlap area SC 3; alternatively, at least one of first storage overlap area SC1 or fourth storage overlap area SC4 is greater than second storage overlap area SC2, and second storage overlap area SC2 is equal to third storage overlap area SC 3.

In particular implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i to 7f and fig. 10a and 10b, the first storage overlapping area SC1 may be made larger than the second storage overlapping area SC 2. This allows the first capacitor in the first color sub-pixel to be shielded by the touch electrode (e.g., the second touch electrode 820) as much as possible.

In particular implementation, in the presently disclosed embodiments, as shown in fig. 5 a-5 i-9 b, the touch electrode (e.g., the second touch electrode 820) includes a first electrode portion DC1 and a second electrode portion DC 2; the orthographic projection of the first electrode part DC1 on the substrate 1000 and the orthographic projection of the auxiliary conductive part on the substrate 1000 have an overlapping area, and the orthographic projection of the second electrode part DC2 on the substrate 1000 and the orthographic projection of the auxiliary conductive part on the substrate 1000 do not overlap. Here, the width of the first electrode portion DC1 may be made larger than the width of the second electrode portion DC 2. Therefore, the touch electrode can better shield the auxiliary conductive part.

Alternatively, as shown in fig. 5a to 5i to 9b, the touch electrode (e.g., the second touch electrode 820) includes at least 3 portions having different widths, and the touch electrode includes a first electrode portion DC1, a second electrode portion DC2, and a third electrode portion DC3 (not shown); for example: the orthographic projection of the first electrode part DC1 on the substrate base plate 1000 and the orthographic projection of the auxiliary conductive part on the substrate base plate 1000 have an overlapping region, the orthographic projection of the second electrode part DC2 on the substrate base plate 1000 and the orthographic projection of the auxiliary conductive part on the substrate base plate 1000 do not overlap, and the orthographic projection of the third electrode part DC3 on the substrate base plate 1000 and the orthographic projection of the storage conductive part on the substrate base plate 1000 have an overlapping region. Alternatively, the width of the first electrode portions DC1 is smaller than the width of the second electrode portions DC2, and the width of the second electrode portions DC2 is smaller than the width of the third electrode portions DC 3.

Optionally, as shown in fig. 5a to 5i to 9b, the touch electrode has a protrusion at least in a corresponding one of the sub-pixel regions; for example: DC 1. The touch electrode is provided with a convex part in at least two corresponding sub-pixel areas, and the convex directions of the convex parts are different or the widths of the convex parts are different.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i, 6f and 6g, an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) located between adjacent opening regions on the substrate 1000 overlaps an orthogonal projection of the at least two light emitting layers with different colors on the substrate 1000. Optionally, an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) located between the adjacent opening regions on the substrate 1000 is covered by an orthogonal projection of the light emitting layers of at least two different colors on the substrate 1000.

Illustratively, the orthographic projection of the touch electrode (e.g., the second touch electrode 820) positioned between the adjacent opening regions on the substrate 1000 may be covered by the orthographic projection of the light emitting layers of two different colors on the substrate 1000. The orthographic projection of the touch electrode (e.g., the second touch electrode 820) positioned between the adjacent opening regions on the substrate 1000 can also be covered by the orthographic projection of the light-emitting layers of three different colors on the substrate 1000.

Illustratively, in the same sub-pixel, an overlapping region (e.g., SC1) exists between a touch electrode (e.g., 820) and a storage conductive part WCst2, the touch electrode (e.g., 820) is overlapped by at least three luminescent layers of different colors in the orthographic projection of the substrate 1000, the area of the orthographic projection of the storage conductive part WCst2 on the substrate 1000 is Sn, wherein SC1/Sn is approximately 1/5-4/5.

Optionally, in the same sub-pixel, the ratio of the area of the touch electrode covered by the orthographic projection of the light emitting layers of at least three different colors on the substrate 1000 to the area of the orthographic projection of the corresponding conductive storage portion WCst2 on the substrate 1000 is approximately 3/10-2/5. For example, the ratio of the area of the touch electrode covered by the orthographic projection of the light emitting layers of at least three different colors on the base substrate 1000 to the area of the orthographic projection of the corresponding conductive storage portion WCst2 on the base substrate 1000 is substantially 1/5. Alternatively, the ratio of the area of the touch electrode covered by the orthographic projection of the light emitting layers of at least three different colors on the base substrate 1000 to the area of the orthographic projection of the corresponding conductive storage portion WCst2 on the base substrate 1000 is substantially 3/10. Alternatively, the ratio of the area of the touch electrode covered by the orthographic projection of the light emitting layers of at least three different colors on the base substrate 1000 to the area of the orthographic projection of the corresponding conductive storage portion WCst2 on the base substrate 1000 is substantially 2/5. Alternatively, the ratio of the area of the touch electrode covered by the orthographic projection of the light emitting layers of at least three different colors on the base substrate 1000 to the area of the orthographic projection of the corresponding conductive storage portion WCst2 on the base substrate 1000 is substantially 1/2. Of course, in practical application, the design may be performed according to the requirements of the practical application environment, and is not limited herein.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i, 6f, 6g and 11, an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) surrounding the opening region KK1 in the first color sub-pixel on the substrate 1000 may be located within an orthogonal projection of the first color light-emitting layer 610 on the substrate 1000. On one hand, the area of the first color light-emitting layer 610 can be increased to ensure the light-emitting effect.

Alternatively, the auxiliary conductive portion is further shielded by covering at least part of the boundary ES1 of the first color light emitting layer 610 with the auxiliary conductive portion.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i, 6f, 6g and 11, an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) surrounding the opening region KK2 in the second color sub-pixel on the substrate 1000 may be located within an orthogonal projection of the second color light-emitting layer 620 on the substrate 1000. This can increase the area of the second color light emitting layer 620 to secure the light emitting effect.

Alternatively, the auxiliary conductive portion is further shielded by covering at least part of the boundary ES2 of the second color light emitting layer 620 with the auxiliary conductive portion.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i, 6f, 6g and 11, an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) surrounding the opening region KK3 in the third color sub-pixel on the substrate 1000 may be located within an orthogonal projection of the third color light-emitting layer 630 on the substrate 1000. This can increase the area of the third color luminescent layer 630 to ensure the luminescent effect.

Alternatively, the auxiliary conductive portion is further shielded by covering at least part of the boundary ES3 of the third color light-emitting layer 630 with the auxiliary conductive portion.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i, 6f, 6g and 11, an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) surrounding the opening region KK4 in the fourth color sub-pixel on the substrate 1000 may be located within an orthogonal projection of the fourth color light-emitting layer 640 on the substrate 1000. This can increase the area of the fourth color light emitting layer 640 to ensure the light emitting effect.

Alternatively, the auxiliary conductive portion is further shielded by covering at least part of the boundary ES4 of the fourth color light emitting layer 640 with the auxiliary conductive portion.

It is to be understood that, in the region where the light emitting layers of at least two colors overlap, the lamination position of the light emitting layers is not limited to the illustrated case of the present embodiment, and may be adjusted according to actual situations or process conditions, for example: the different color light emitting layers are manufactured in a synchronous step or in different steps. For example: the lamination position of the light emitting layer is not limited to fig. 5e, and the order is 610, 620, and 630 from the pixel defining layer 950, but may be 630, 620, 610 or 610, 630, 620, or 630, 610, 620, or the like from the pixel defining layer 950.

In particular implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i, 6f, 6g and 11, for the adjacent third color luminescent layer 630 and the second color luminescent layer 620, a first minimum distance W0S1 exists between the boundary ES3 of the orthographic projection of the third color luminescent layer 630 on the substrate 1000 and the boundary CK3 of the orthographic projection of the touch electrode (e.g., the second touch electrode 820) surrounding the third color sub-pixel on the substrate 1000, and a second minimum distance W0S2 exists between the boundary ES2 of the orthographic projection of the substrate 1000 and the boundary CK1 of the orthographic projection of the touch electrode (e.g., the second touch electrode 820) surrounding the second color sub-pixel on the substrate 1000. Wherein the first minimum distance W0S1 is greater than the second minimum distance W0S 2. On one hand, the area of the third color luminescent layer 630 can be further increased to ensure the luminescent effect. On the other hand, at least a part of the boundary ES3 of the third color luminescent layer 630 covers the auxiliary conductive portion, thereby further shielding the auxiliary conductive portion. Also, since the light emitting area of the second color sub-pixel is small, the influence on the light emitting effect of the second color sub-pixel is small when the third color light emitting layer 630 extends into the second color light emitting layer 620.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i, 6f, 6g and 11, an area surrounded by an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) surrounding the opening region KK1 in the first color sub-pixel on the substrate 1000 is the first grid area WG 1. An area surrounded by an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) surrounding the opening region KK2 in the second color sub-pixel on the substrate 1000 is a second grid area WG 2. An area enclosed by an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) surrounding the opening region KK3 in the third color sub-pixel on the substrate 1000 is a third grid area WG 3. Wherein the third grid area WG3 is greater than the second grid area WG2 is greater than the first grid area WG 1. This makes it possible to make the third mesh area WG3, the second mesh area WG2, and the first mesh area WG1 proportional to the opening area KK3 in the third color sub-pixel, the opening area KK2 in the second color sub-pixel, and the opening area KK1 in the first color sub-pixel, respectively, so that the light transmittance can be improved.

It is understood that in the embodiment of the disclosure, the first touch electrode 810 and/or the second touch electrode are not required to be all closed grids, and the touch electrodes corresponding to local regions or individual sub-pixels may be notched or disconnected. For example: with reference to fig. 1-2, and fig. 5 a-5 i, 6f, 6 g-11: the touch electrodes corresponding to the display area AA near the non-display area, or the individual sub-pixels are notched or disconnected.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i, 6f, 6g and 11, an area enclosed by an orthogonal projection of the touch electrode (e.g., the second touch electrode 820) surrounding the opening region KK4 in the fourth color sub-pixel on the substrate 1000 is a fourth grid area WG 4. The first grid area WG1 corresponding to the first color sub-pixel may be made larger than the fourth grid area WG4 corresponding to the fourth color sub-pixel. Alternatively, the first mesh area WG1 corresponding to the first color sub-pixel may be substantially equal to the fourth mesh area WG4 corresponding to the fourth color sub-pixel, which is not limited herein.

In particular implementation, in the disclosed embodiment, the first grid area WG1 may be 850-920 μm². Alternatively, the first grid area WG1 may be 860 μm²～910μm². For example, the first grid area WG1 may be 850 μm². Alternatively, the first grid area WG1 may be 860 μm². Alternatively, the first grid area WG1 may be 900 μm². Alternatively, the first grid area WG1 may be 910 μm². Alternatively, the first mesh area WG1 may be 920 μm². Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

Alternatively, in particular implementations, in embodiments of the present disclosure, the first grid area WG1 may also be 30.5 × 28.5 μm²～35.5*30.5μm². Alternatively, the first mesh area WG1 may be 30.5 × 28.5 μm². For example, the first mesh area WG1 may be 31.5 × 29.5 μm². Alternatively, the first mesh area WG1 may be 32.5 × 29.1 μm². Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

In particular implementations, in embodiments of the present disclosure, the second grid area WG2 may be 950-1050 μm². Alternatively, the second grid area WG2 may be 960-1040 μm². For example, the second grid area WG2 may be 950 μm². Alternatively, the second grid area WG2 may be 960 μm². Alternatively, the second grid area WG2 may be 980 μm². Alternatively, the second grid area WG2 may be 1000 μm². Alternatively, the second grid area WG2 may be 1040 μm². Alternatively, the second grid area WG2 may be 1050 μm². Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

Alternatively, when embodied, in embodiments of the present disclosure, the second mesh area WG2 may be 30.1 × 30.1 μm²～32.1*32.1μm². Alternatively, the second mesh area WG2 may be 30.5 x 30.5 μm²～32.0*32.0μm². For example, the second grid area WG2 may be 30.1 x 30.1 μm². Alternatively, the second mesh area WG2 may be 30.5 x 30.5 μm². Alternatively, the second mesh area WG2 may be 31.6 x 31.6 μm². Alternatively, the second mesh area WG2 may be 32.0 x 32.0 μm². Alternatively, the second mesh area WG2 may be 32.1 x 32.1 μm². Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

In particular implementation, in embodiments of the present disclosure, the third grid area WG3 may be 1100 μm²～1300μm². Alternatively, the third grid area WG3 may be 1150 μm²～1250μm². For example, the third grid area WG3 may be 1100 μm². Alternatively, the third grid area WG3 may be 1150 μm². Alternatively, the third grid area WG3 may be 1200 μm². Alternatively, the third grid area WG3 may be 1225 μm². Alternatively, the third mesh area WG3 may be 1300 μm². Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

Alternatively, when embodied, in embodiments of the present disclosure, the third mesh area WG3 may be 32 × 32 μm²～37*37μm². Alternatively, the third mesh area WG3 may be 33 x 33 μm²～36*36μm². For example, the third grid area WG3 may be 32 x 32 μm². Alternatively, the third mesh area WG3 may be 33 x 33 μm². Alternatively, the third mesh area WG3 may be 34 x 34 μm^2.. Alternatively, the third mesh area WG3 may be 35 x 35 μm². Alternatively, the third mesh area WG3 may be 36 × 36 μm². Alternatively, the third mesh area WG3 may be 37 × 37 μm². Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

In particular implementation, in the disclosed embodiment, the fourth grid area WG4 may be 850-920 μm². Alternatively, the fourth grid area WG4 may be 860 μm²～910μm². For example, the fourth grid area WG4 may be 850 μm². Alternatively, the fourth grid area WG4 may be 860 μm². Alternatively, the fourth grid area WG4 may be 900 μm². Alternatively, the fourth grid area WG4 may be 910 μm². Alternatively, the fourth grid area WG4 may be 920 μm². Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

Alternatively, in particular implementations, in embodiments of the present disclosure, the fourth grid area WG4 may also be 30.5 × 28.5 μm²～35.5*30.5μm². Alternatively, the fourth mesh area WG4 may be 30.5 × 28.5 μm². For example, the fourth mesh area WG4 may be 31.5 × 29.5 μm². Alternatively, the fourth mesh area WG4 may be 32.5 × 29.1 μm². Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i and fig. 11, in the same repeating unit, the opening region KK3 in the third color sub-pixel and the opening region KK1 in the first color sub-pixel may be arranged in the first direction F1. The opening region KK2 in the second color sub-pixel and the opening region KK4 in the fourth color sub-pixel may also be aligned in the first direction F1. Wherein, an area surrounded by an inner boundary NS3 of the touch electrode (e.g., the second touch electrode 820) surrounding the opening area KK3 in the third color sub-pixel has a first width WK1 in a direction perpendicular to the first direction F1. An area surrounded by an inner boundary NS1 of a touch electrode (e.g., the second touch electrode 820) surrounding an opening area KK1 in the first color sub-pixel has a second width WK2 in a direction perpendicular to the first direction F1. An area surrounded by an inner boundary NS2 of a touch electrode (e.g., the second touch electrode 820) surrounding an opening area KK2 in the second color sub-pixel has a third width WK3 in a direction perpendicular to the first direction F1. An area surrounded by an inner boundary NS4 of a touch electrode (e.g., the second touch electrode 820) surrounding an opening area KK4 in the fourth color sub-pixel has a fourth width WK4 in a direction perpendicular to the first direction F1.

Alternatively, the first direction F1 may form an angle with the row direction F3 direction, for example, the angle may be greater than 0 degrees and less than 90 degrees. Optionally, the first direction F1 and the row direction F3 may form 25-75 degrees. Optionally, the first direction F1 and the row direction F3 may form 30-60 degrees. For example, the first direction F1 and the row direction F3 direction may form 25 degrees. Alternatively, the first direction F1 and the row direction F3 direction may form 30 degrees. Alternatively, the first direction F1 and the row direction F3 direction may form 45 degrees. Alternatively, the first direction F1 and the row direction F3 may form 60 degrees. Alternatively, the first direction F1 and the row direction F3 direction may form 75 degrees. Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

In particular implementations, in embodiments of the present disclosure, the first width WK1 may be 34.0 μm to 35.0 μm. Alternatively, the first width WK1 may be 34.1 μm to 34.9 μm. For example, the first width WK1 may be 34.0 μm. Alternatively, the first width WK1 may be 34.1 μm. Alternatively, the first width WK1 may be 34.4 μm. Alternatively, the first width WK1 may be 34.8 μm. Alternatively, the first width WK1 may be 34.9 μm. Alternatively, the first width WK1 may be 35.0 μm. Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

In particular implementations, in embodiments of the present disclosure, the second width WK2 may be 30.5 μm to 31.5 μm. Alternatively, the second width WK2 may be 30.7 μm to 31.4 μm. For example, the second width WK2 may be 30.5 μm. Alternatively, the second width WK2 may be 30.7 μm. Alternatively, the second width WK2 may be 31.2 μm. Alternatively, the second width WK2 may be 31.4 μm. Alternatively, the second width WK2 may be 31.5 μm. Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

In particular implementations, the third width WK3 may be 30.8 μm to 32.5 μm in embodiments of the present disclosure. Alternatively, the third width WK3 may be 31.0 μm to 32.0 μm. For example, the third width WK3 may be 30.8 μm. Alternatively, the third width WK3 may be 31.0 μm. Alternatively, the third width WK3 may be 31.6 μm. The third width WK3 may be 31.8 μm. Alternatively, the third width WK3 may be 32.0 μm. Alternatively, the third width WK3 may be 32.5 μm. Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

In particular implementations, in embodiments of the present disclosure, the fourth width WK4 may be 28.8-31.5 μm. Alternatively, the fourth width WK4 may be 29.2 μm to 30.5 μm. For example, the fourth width WK4 may be 28.8 μm. Alternatively, the fourth width WK4 may be 29.2 μm. Alternatively, the fourth width WK4 may be 29.9 μm. Alternatively, the fourth width WK4 may be 30.5 μm. Alternatively, the fourth width WK4 may be 31.5 μm. Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

Illustratively, as shown in fig. 11, the first width WK1 may be made larger than the second width WK 2. This can ensure that the opening region KK3 in the third color sub-pixel and the opening region KK1 in the first color sub-pixel improve light transmittance. Illustratively, the difference between the first width WK1 and the second width WK2 may be 3.0 μm to 4.0 μm. Alternatively, the difference between the first width WK1 and the second width WK2 may be 3.1 μm to 3.9 μm. For example, the difference between the first width WK1 and the second width WK2 may be 3.0 μm. Alternatively, the difference between the first width WK1 and the second width WK2 may be 3.3 μm. Alternatively, the difference between the first width WK1 and the second width WK2 may be 3.6 μm. Alternatively, the difference between the first width WK1 and the second width WK2 may be 3.8 μm. Alternatively, the difference between the first width WK1 and the second width WK2 may be 3.9 μm. Alternatively, the difference between the first width WK1 and the second width WK2 may be 4.0 μm. Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

Illustratively, as shown in fig. 11, the third width WK3 may be made larger than the fourth width WK 4. This can ensure that the opening region KK2 in the second color sub-pixel and the opening region KK4 in the fourth color sub-pixel improve light transmittance. Illustratively, the difference between the third width WK3 and the fourth width WK4 may be 1.0 μm to 2.0 μm. Alternatively, the difference between the third width WK3 and the fourth width WK4 may be 1.2 μm to 1.8 μm. For example, the difference between the third width WK3 and the fourth width WK4 may be 1.0 μm. Alternatively, the difference between the third width WK3 and the fourth width WK4 may be 1.2 μm. Alternatively, the difference between the third width WK3 and the fourth width WK4 may be 1.5 μm. Alternatively, the difference between the third width WK3 and the fourth width WK4 may be 1.7 μm. Alternatively, the difference between the third width WK3 and the fourth width WK4 may be 1.8 μm. Alternatively, the difference between the third width WK3 and the fourth width WK4 may be 2.0 μm. Of course, in practical applications, the design may be determined according to the requirements of practical application environments, and is not limited herein.

In practical implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i and fig. 12, the extending direction F0 of the grid lines of the touch electrode (e.g., the second touch electrode 820) having the overlapping area with the orthogonal projection of the auxiliary conductive portion has an included angle β with the third direction; beta is more than or equal to 15 degrees and less than or equal to 60 degrees; optionally, the included angle β is 20 ≦ β ≦ 50. The third direction is substantially perpendicular to the extending direction of the data line pattern, for example, the third direction may be a row direction F4. Exemplarily, tan β ═ a1/a 2; where a1 represents the width of the auxiliary conductive portion in the direction perpendicular to the third direction, and a2 represents the width of the auxiliary conductive portion in the third direction. For example, β may be set to 15 °, β may be set to 25 °, β may be set to 35 °, β may be set to 45 °, β may be set to 50 °, and β may be set to 60 °. Of course, in practical applications, the specific value of β may be determined according to the requirements of practical applications, and is not limited herein.

In specific implementation, as shown in fig. 5a to 5i and fig. 12, in the embodiment of the present disclosure, the extending direction of the grid lines of the touch electrode (e.g., the second touch electrode 820) having an overlapping area with the orthographic projection of the auxiliary conductive portion in the first color sub-pixel and the third direction have a first included angle β 1. The extending direction of the grid lines of the touch electrode (e.g., the second touch electrode 820) having the overlapping area with the orthographic projection of the auxiliary conductive part in the second color sub-pixel has a second included angle β 2 with the third direction. The extending direction of the grid lines of the touch electrode (e.g., the second touch electrode 820) having the overlapping area with the orthographic projection of the auxiliary conductive part in the sub-pixel of the third color and the third direction have a third included angle β 3. The first included angle may be smaller than the second included angle and smaller than the third included angle, so that the touch electrode (e.g., the second touch electrode 820) may cover the auxiliary conductive layer as much as possible. Of course, depending on the actual situation, at least two angles β 1, β 2, β 3 may be the same.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 5a to 5i, 9a, and 10a, the opening regions of the adjacent four sub-pixels are taken as an opening group, and the orthogonal projection of the grid intersection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000 is located in the area surrounded by the orthogonal projection of the opening group on the substrate 1000. Further, the orthographic projection of the grid intersection points of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000 is approximately located at the center of the area enclosed by the orthographic projection of the opening group on the substrate 1000. This makes it possible to disperse the grid intersections uniformly in the display area, further improving the display uniformity.

In particular implementation, in the embodiment of the present disclosure, as shown in fig. 13a and 13b, an overlapping region between the orthographic projection of the first electrode 510 (e.g., anode) in the first color sub-pixel on the substrate 1000 and the orthographic projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000 has a first anode overlapping area BS 1; the overlap region between the orthographic projection of the first electrode 520 in the second color sub-pixel on the substrate 1000 and the orthographic projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000 has a second anode overlap area BS 2; the overlap region between the orthographic projection of the first electrode 530 in the third color sub-pixel on the substrate 1000 and the orthographic projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000 has a third anode overlap area BS 3; the overlap region between the orthographic projection of the first electrode 540 in the fourth color sub-pixel on the substrate 1000 and the orthographic projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000 has a fourth anode overlap area BS 4. Wherein at least one of the first anode overlap area BS1, the second anode overlap area BS2, and the fourth anode overlap area BS4 is greater than the third anode overlap area BS 3.

Illustratively, the first anode overlap area BS1 may be made larger than the third anode overlap area BS 3. The second anode overlap area BS2 may also be made larger than the third anode overlap area BS 3. The fourth anode overlap area BS4 may also be made larger than the third anode overlap area BS 3.

In particular implementation, in the disclosed embodiments, the first anode overlap area BS1 may be made larger than the second anode overlap area BS2, as shown in fig. 13a and 13 b. Alternatively, the first anode overlap area BS1 may be made substantially equal to the second anode overlap area BS 2.

In particular implementation, in the presently disclosed embodiments, as shown in fig. 13a and 13b, the first anode overlap area BS1 is greater than the fourth anode overlap area BS 4. Alternatively, the first anode overlap area BS1 may be made substantially equal to the fourth anode overlap area BS 4.

In particular implementation, in the presently disclosed embodiments, as shown in fig. 13a and 13b, the fourth anode overlap area BS4 is greater than the second anode overlap area BS 2. Alternatively, the fourth anode overlap area BS4 may be made substantially equal to the second anode overlap area BS 2.

Optionally, the first anode overlap area BS1 is 2.5 μm²-35μm². Optionally, the first anode overlap area BS1 is 3 μm²-25μm². Alternatively, the first anode overlap area BS1 may be set to 6 μm²-20μm²。

Optionally, the second anode overlap area BS2 is 0 μm²-30μm². Optionally, the second anode overlap area BS2 is 1.5 μm²-25μm². Alternatively, the second anode overlap area BS2 may be set to 6 μm²-20μm²。

Optionally, the third anode overlap area BS3 is 0 μm²-25μm². Optionally, the third anode overlap area BS3 is 1.5 μm²-25μm². Alternatively, the third anode overlap area BS3 may be set to 5 μm²-20μm²。

Optionally, the fourth anode overlap area BS4 is 0 μm²-30μm². Optionally, the fourth anode overlap area BS4 is 1.5 μm²-25μm². Alternatively, the first anode overlap area BS4 may be set to 6 μm²-20μm²。

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 14a and 14b, and with reference to fig. 8a to 8d, an auxiliary insulating layer may be further disposed on a side of the second touch electrode 820 facing away from the substrate 1000. An auxiliary electrode 840 may also be provided on the side of the auxiliary insulating layer facing away from the substrate base 1000. Illustratively, the auxiliary electrode 840 is in a floating state and does not transmit signals. Of course, the auxiliary electrode 840 may be formed in the same layer and/or the same material as the first touch electrode 810.

It is understood that as shown in fig. 14a and 14b and in conjunction with fig. 8 a-8 d, an insulating layer 830 is disposed on a side of the first touch electrode 810 facing away from the substrate 1000. An auxiliary electrode 840 may be further disposed on a side of the substrate 830 away from the substrate 1000, the auxiliary electrode 840 is in a floating state and does not transmit signals, and the auxiliary electrode 840 and the second touch electrode 820 (or 811) may be fabricated in the same layer and/or formed of the same material.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 15, the display panel further includes a power supply input line VDDIN in the non-display region. The power signal line pattern VDD in the display area is electrically connected to the power input line VDDIN. Illustratively, the power signal line patterns VDD of two adjacent columns of sub-pixels are electrically connected through the power input line VDDIN; or, the power signal line patterns VDD corresponding to two adjacent columns of sub-pixels with the same color are electrically connected through the power input line VDDIN. Illustratively, the power input line VDDIN may be disposed in the same layer as the power signal line pattern VDD. Alternatively, the power input line VDDIN may be disposed in a different layer from the power signal line pattern VDD, which also requires that the power signal line pattern VDD and the power input line VDDIN be electrically connected through a via. The data line pattern DA and the power supply input line VDDIN may not be provided on the same conductive layer.

It is understood that the above disclosed embodiments can be adaptively combined as required, and the numerical ranges can be adjusted accordingly.

The embodiment of the present disclosure further provides a display device, including the display panel provided in the embodiment of the present disclosure, for example: an Organic Light Emitting Diode (OLED). The principle of the display device to solve the problem is similar to the display panel, so the implementation of the display device can be referred to the implementation of the display panel, and repeated details are not repeated herein.

In specific implementation, in the embodiment of the present disclosure, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a watch, a bracelet and the like. Other essential components of the display device are components that one of ordinary skill in the art should understand to have, and are not described herein nor should be taken as limitations to the present disclosure.

While preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the disclosure.

It will be apparent to those skilled in the art that various changes and modifications may be made to the disclosed embodiments without departing from the spirit and scope of the disclosed embodiments. Thus, if such modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to encompass such modifications and variations.

Claims

1. A display panel, comprising:

a substrate base plate;

the transistor array layer is positioned on the substrate base plate;

2. The display panel of claim 1, wherein the first auxiliary overlapping area is larger than the second auxiliary overlapping area; alternatively, the first and second electrodes may be,

the first auxiliary overlap area is substantially equal to the second auxiliary overlap area; alternatively, the first and second electrodes may be,

the third auxiliary overlapping area is substantially equal to the second auxiliary overlapping area.

3. The display panel of claim 1, wherein the transistor array layer comprises:

4. The display panel of claim 3, wherein the auxiliary conductive portion in the first color sub-pixel comprises a first auxiliary exposed portion, and an orthographic projection of the first auxiliary exposed portion on the substrate does not overlap with an orthographic projection of the data line pattern and the power supply signal line pattern on the substrate, respectively; the first auxiliary overlapping area comprises a first auxiliary sub-overlapping area, and the overlapping area of the first auxiliary exposure part between the orthographic projection of the substrate base plate and the orthographic projection of the touch electrode on the substrate base plate has the first auxiliary sub-overlapping area;

5. The display panel of claim 4, wherein the second auxiliary sub-overlap area is larger than the third auxiliary sub-overlap area; alternatively, the third auxiliary sub overlapping area is substantially equal to the second auxiliary sub overlapping area.

6. The display panel of claim 4, wherein in the first color sub-pixel, an orthogonal projection of the first auxiliary exposure portion on the substrate base plate is located between an orthogonal projection of the data line pattern and the power signal line pattern on the substrate base plate; and/or the presence of a gas in the gas,

7. The display panel of claim 6, wherein an orthographic projection of the auxiliary conductive portion on the substrate base plate has a total area;

8. The display panel of claim 7, wherein in the first color sub-pixel, an orthographic projection of the touch electrode on the base substrate covers an orthographic projection of the first auxiliary exposure portion on the base substrate; and/or the presence of a gas in the gas,

9. The display panel according to any one of claims 4 to 8, wherein the auxiliary conductive portion in the first color sub-pixel further includes a first auxiliary shielding portion, and an orthogonal projection of the first auxiliary shielding portion on the substrate overlaps with an orthogonal projection of at least one of the data line pattern and the power supply signal line pattern on the substrate; wherein the width of the first auxiliary exposure part in the column direction is smaller than the width of the first auxiliary shielding part in the column direction; and/or the presence of a gas in the gas,

10. The display panel of claim 3, wherein the pixel circuit further comprises a first capacitor;

11. The display panel of claim 10, wherein the first storage overlap area is larger than the second storage overlap area.

12. The display panel according to claim 10, wherein the second conductive layer further comprises a plurality of storage conductive portions provided apart from the auxiliary conductive portion; the sub-pixel includes the storage conductive part; the storage conductive part is used as a second polar plate of the first capacitor;

13. The display panel according to claim 1, wherein an orthographic projection of the touch electrode on the substrate is in a grid shape, and the orthographic projection of the touch electrode on the substrate does not overlap with an orthographic projection of the opening region on the substrate.

14. The display panel according to claim 13, wherein the touch electrode includes a first electrode portion and a second electrode portion; wherein the orthographic projection of the first electrode part on the substrate base plate and the orthographic projection of the auxiliary conducting part on the substrate base plate have an overlapping area, and the orthographic projection of the second electrode part on the substrate base plate and the orthographic projection of the auxiliary conducting part on the substrate base plate do not overlap;

15. The display panel of claim 1, wherein the display panel further comprises:

16. The display panel of claim 15, wherein orthographic projections of the touch electrodes positioned between adjacent opening regions on the substrate overlap with orthographic projections of the at least two light emitting layers of different colors on the substrate.

17. The display panel of claim 15, wherein an orthographic projection of the touch electrode surrounding the open area of the third color sub-pixel on the base substrate is within an orthographic projection of the third color light emitting layer on the base substrate; and/or the presence of a gas in the gas,

18. The display panel of claim 15, wherein for the third color light emitting layer and the second color light emitting layer being adjacent, the third color light emitting layer has a first minimum distance between a boundary of an orthogonal projection of the substrate base plate and a boundary of an orthogonal projection of the touch electrode on the substrate base plate, and the second color light emitting layer has a second minimum distance between a boundary of an orthogonal projection of the substrate base plate and a boundary of an orthogonal projection of the touch electrode on the substrate base plate;

the first minimum distance is greater than the second minimum distance.

19. The display panel of claim 13, wherein an area defined by orthographic projections of the touch electrodes surrounding the open areas of the first color sub-pixels on the substrate is a first grid area;

20. The display panel of claim 19, wherein the display panel comprises a plurality of repeating units; the repeating unit includes the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel.

21. The display panel of claim 20, wherein the repeating unit further comprises a fourth color sub-pixel; the area surrounded by the orthographic projection of the touch electrode surrounding the opening area of the fourth color sub-pixel on the substrate is a fourth grid area;

22. The display panel of claim 21, wherein in the same repeating unit, the open region of the third color sub-pixel and the open region of the first color sub-pixel are arranged in a first direction;

an area surrounded by an inner boundary of the touch electrode surrounding an opening area of the third color sub-pixel has a first width in a direction perpendicular to the first direction;

an area surrounded by an inner boundary of the touch electrode surrounding the opening area of the first color sub-pixel has a second width in a direction perpendicular to the first direction;

the first width is greater than the second width.

23. The display panel of claim 21 or 22, wherein in the same repeating unit, the open regions of the second color sub-pixels and the open regions of the fourth color sub-pixels are arranged in a first direction;

an area surrounded by an inner boundary of the touch electrode surrounding the opening area of the second color sub-pixel has a third width in a direction perpendicular to the first direction;

the third width is greater than the fourth width.

24. The display panel according to claim 13, wherein an extending direction of grid lines of the touch electrode having an overlapping area with an orthogonal projection of the auxiliary conductive portion has an angle β with a third direction; beta is more than or equal to 15 degrees and less than or equal to 60 degrees; wherein the third direction is substantially perpendicular to an extending direction of the data line pattern.

25. The display panel of claim 24, wherein tan β ═ a1/a 2; wherein a1 represents a width of the auxiliary conductive portion in a direction perpendicular to the third direction, and a2 represents a width of the auxiliary conductive portion in the third direction.

26. The display panel of claim 24, wherein the extending direction of the grid lines of the touch electrode having an overlapping area with the orthographic projection of the auxiliary conductive part in the first color sub-pixel has a first angle with the third direction;

27. The display panel of claim 24, wherein the open area of four adjacent sub-pixels is an opening group, and the orthographic projection of the grid intersection points of the touch electrode on the substrate base plate is located in an area surrounded by the orthographic projection of the opening group on the substrate base plate.

28. The display panel of claim 27, wherein an orthographic projection of the grid intersection of the touch electrode on the substrate base is approximately at a center of an area enclosed by the orthographic projection of the opening group on the substrate base.

29. The display panel of claim 21, wherein the fourth color sub-pixel emits light of the same color as the first color sub-pixel.

30. The display panel of claim 1, wherein each of the sub-pixels further comprises a first electrode;

31. The display panel of claim 30, wherein the first anode overlapping area is larger than the second anode overlapping area; alternatively, the first and second electrodes may be,

32. A display panel, comprising:

a substrate base plate;

the transistor array layer is positioned on the substrate base plate;

33. The display panel of claim 32, wherein the capacitive conductive portions are in an arc shape or an irregular pattern.

34. The display panel of claim 32, wherein the capacitive conductive portion comprises an auxiliary conductive portion at least partially overlapping the power signal line pattern, the data line pattern, and the touch electrode.

35. The display panel of claim 32, wherein the power signal line patterns of two adjacent columns of the sub-pixels are electrically connected through a power input line; or the power signal line patterns corresponding to the two adjacent columns of the sub-pixels with the same color are electrically connected through a power input line.

36. The display panel of claim 35, wherein the power input line and the power signal line pattern are located at different layers.

37. The display panel of claim 32, wherein the width of the power signal line pattern is greater than the width of the data line pattern.

38. The display panel of claim 35, wherein the data line pattern and the power signal line pattern are not disposed on the same conductive layer; or, the data line pattern and the power input line are not disposed on the same conductive layer.

39. The display panel according to claim 32, wherein the first conductive layer comprises a first sub-conductive layer and a second sub-conductive layer which are stacked, and a first sub-insulating layer is provided between the first sub-conductive layer and the second sub-conductive layer.

40. The display panel of claim 32, wherein an overlapping area of the capacitive conductive part and the power signal line pattern is larger than an overlapping area of the capacitive conductive part and the data line pattern.

41. The display panel of claim 32, wherein the pixel circuit comprises: a seventh transistor and a second transistor; a gate of the seventh transistor is coupled to a second reset signal line pattern, and a gate of the second transistor is coupled to a first reset signal line pattern; the first reset signal line pattern and the second reset signal line pattern transmit different signals.

42. The display panel of claim 32, wherein the pixel circuit comprises: a data write transistor, a first transistor; the gate line pattern coupled to the gate of the data writing transistor transmits a different timing signal than the gate line pattern coupled to the gate of the first transistor.

43. A display device comprising the display panel according to any one of claims 1 to 42.