CN112821987A - Data processing method in channel coding, computer device and storage medium - Google Patents
Data processing method in channel coding, computer device and storage medium Download PDFInfo
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Abstract
The invention relates to the technical field of communication, and discloses a data processing method, computer equipment and a storage medium in channel coding, which comprises the steps of respectively converting each equal-length sub code block of a signal to be processed into a first data segment according to a fixed data bit width, and acquiring an effective bit in tail position data in the first data segment; counting and numbering each equal-length sub-code block, and determining a classification judgment factor of each equal-length sub-code block according to the number and the effective bits of each equal-length sub-code block; classifying the sub code blocks with the same length according to the classification judgment factors and the effective bits of the sub code blocks with the same length; and performing corresponding data recombination on each equal-length sub code block according to the classification condition so as to complete code block cascade of the signals to be processed. When the data processing method is applied to a system with fixed data bit width, the system can complete the cascade operation of the equal-length sub code blocks with any bit length, and simultaneously, the cascade operation is simpler and clearer.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a data processing method in channel coding, a computer device, and a storage medium.
Background
When the PDSCH in the physical downlink shared channel in the 5G NR system is channel coded, a series of operations are performed on code blocks, including the operation of code block concatenation. The basic flow of channel coding mainly adds CRC to each transmission block to detect transmission errors, then carries out code block segmentation, channel coding and rate matching processing, and then carries out code block concatenation on all code blocks to form a bit sequence based on the transmission blocks. The last step in the channel coding process involves the concatenation of fixed-length sub-code blocks.
The processing of data by chips such as an FPGA (field programmable gate array) chip, a DSP (digital signal processing chip) and the like has a fixed data bit width, and certain complexity and challenges exist when code block cascading is performed on equal-length sub code blocks with any bit length by using the system with the fixed data bit width. This is because the sub-code blocks of the same length with any bit length may not be integer multiples of the fixed data bit width, so that when each sub-code block is converted into data with the fixed data bit width, some bits of the data at the end position of each sub-code block may be invalid, and the invalid bits at the end position of each sub-code block must be removed when the sub-code blocks are concatenated. However, in the process of concatenating multiple equal-length sub-code blocks, there are multiple invalid bits to be removed, so that it becomes quite complicated and difficult for a processing system based on a fixed data bit width to perform concatenation operation of multiple equal-length sub-code blocks.
Disclosure of Invention
Based on this, it is necessary to provide a data processing method, a computer device, and a storage medium in channel coding, which are directed to the problem that code block concatenation is complex and difficult when an equal-length sub-code block with an arbitrary bit length is performed by using a system with a fixed data bit width.
A data processing method in channel coding is applied to a wireless communication system, the wireless communication system has a fixed data bit width when processing signals, the method comprises the steps of respectively converting sub code blocks with equal length of signals to be processed into first data segments according to the fixed data bit width, and acquiring effective bits in tail position data in the first data segments; counting and numbering each sub code block with the same length, and determining a classification judgment factor of each sub code block with the same length according to the number and the effective bit of each sub code block with the same length; classifying each sub code block with the same length according to the classification judgment factor and the effective bit of each sub code block with the same length; and performing corresponding data recombination on each equal-length sub code block according to the classification condition so as to complete code block cascade of the signals to be processed.
According to the data processing method in the channel coding, each equal-length sub code block in the signal to be processed is converted into a first data segment according to the fixed data bit width when the system processes the signal, and the effective bit of the tail position of the first data segment is judged according to the division condition. And counting and numbering each equal-length sub-code block, and determining a classification judgment factor of each equal-length sub-code block according to the number and the effective bit at the tail position of the first data segment. And classifying the equal-length sub-code blocks according to the classification judgment factors and the effective bits, and performing data recombination on the equal-length sub-code blocks according to the classification conditions, so that code block cascade of the signals to be processed is realized. When the data processing method is applied to a system with a fixed data bit width, the system can complete the cascade operation of the sub-code blocks with the same length and any bit length by converting the sub-code blocks with the same length into the first data segment according to the fixed data bit width and recombining the data according to the condition that the effective bit and the ineffective bit appear in the tail position of the first data segment, and meanwhile, the cascade operation is simpler and clearer.
In one embodiment, the converting each equal-length sub-code block of the signal to be processed into a first data segment according to the fixed data bit width, and the obtaining the effective bit in the tail position data in the first data segment includes obtaining a bit length of the equal-length sub-code block and a fixed data bit width of a system; dividing the equal-length sub code blocks by taking the fixed data bit width as a unit to obtain the first data segment; and acquiring the effective bit of the tail position data in the first data segment and the number of data in the first data segment according to the dividing condition.
In one embodiment, the counting and numbering each of the equal-length sub-code blocks, and determining the classification judgment factor of each of the equal-length sub-code blocks according to the number and the significant bits of each of the equal-length sub-code blocks includes counting and numbering each of the equal-length sub-code blocks from zero; and substituting the serial number and the valid bit of each sub code block with the same length into a calculation formula of a classification judgment factor, and calculating the classification judgment factor of each sub code block with the same length.
In one embodiment, the classifying each of the equal-length sub-code blocks according to the classification decision factor and the significant bits of each of the equal-length sub-code blocks includes dividing the equal-length sub-code blocks into a first set when the classification decision factor of the equal-length sub-code blocks is equal to 0; when the classification judgment factor of the equal-length sub-code blocks is larger than the valid bits, dividing the equal-length sub-code blocks into a second set; when the classification judgment factor of the equal-length sub-code blocks is equal to the valid bits, dividing the equal-length sub-code blocks into a third set; and when the classification judgment factor of the sub code blocks with the same length is smaller than the valid bits, dividing the sub code blocks with the same length into a fourth set.
In one embodiment, the corresponding data rearrangement of the equal-length sub-code blocks of the first set includes placing the significant bit at the lower position in the pre-rearrangement end position data at the lower position of the post-rearrangement end position data, and placing the data at the lower position in the data one bit after the pre-rearrangement end position data at the upper position in the post-rearrangement end position data; and directly mapping the non-end position data before the reorganization to the non-end position data after the reorganization.
In one embodiment, the corresponding data rearrangement of the equal-length sub-code blocks of the second set includes placing the last high bit of the data at the non-end position before rearrangement at the low bit of the data at the end position after rearrangement, placing the low bit of the data at the end position before rearrangement at the middle position, and placing the data at the low bit of the data one bit after the data at the end position before rearrangement at the high bit of the data at the end position after rearrangement; and placing the high order bit of the non-end position data before the recombination on the low order bit of the non-end position data after the recombination, and placing the low order bit of the next data on the high order bit of the non-end position data after the recombination.
In one embodiment, the corresponding data rearrangement of the equal-length sub-code blocks of the third set includes placing the last high bit of the data at the non-end position before rearrangement at the low bit of the data at the end position after rearrangement, and placing the data at the low bit of the data at the end position before rearrangement at the high bit of the data at the end position after rearrangement; and placing the high order bit of the non-end position data before the recombination on the low order bit of the non-end position data after the recombination, and placing the low order bit of the next data on the high order bit of the non-end position data after the recombination.
In one embodiment, the corresponding data rearrangement of the equal-length sub-code blocks of the fourth set includes placing the upper bits of the significant bits of the end position data before rearrangement at the lower bits of the end position data after rearrangement, and placing the data at the lower bits of the next data of the end position data before rearrangement at the upper bits of the end position data after rearrangement; and placing the high order bit of the non-end position data before the recombination on the low order bit of the non-end position data after the recombination, and placing the low order bit of the next data on the high order bit of the non-end position data after the recombination.
A computer device comprising a memory and a processor, the memory storing a computer program, wherein the processor when executing the computer program implements the steps of the data processing method in channel coding as described in any one of the above embodiments.
A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the data processing method in channel coding as set forth in any one of the preceding embodiments.
Drawings
In order to more clearly illustrate the embodiments of the present specification or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the specification, and other drawings can be obtained by those skilled in the art without inventive labor.
Fig. 1 is a flowchart illustrating a method of processing data in channel coding according to an embodiment of the present invention;
fig. 2 is a flowchart illustrating a method for converting an equal-length sub-code block into a first data segment according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a method for obtaining a classification determination factor according to an embodiment of the present invention;
fig. 4 is a data schematic diagram of obtaining classification judgment factors with equal length sub code block bit lengths Lb =36bit in a signal to be processed according to an embodiment of the present invention;
fig. 5 is a data schematic diagram of obtaining classification judgment factors with equal length sub code block bit lengths Lb =42bit in a signal to be processed in an embodiment of the present invention;
fig. 6 is a flowchart illustrating a method for classifying each of the equal-length sub-code blocks according to an embodiment of the present invention;
fig. 7 is a flowchart illustrating a method for performing data reassembly on equal-length sub-code blocks of the first set according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of data reorganization of the case 1 data reorganization method according to an embodiment of the present invention;
fig. 9 is a flowchart illustrating a method for performing data reassembly on equal-length sub-code blocks of the second set according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of data reorganization in case 2 according to an embodiment of the present invention;
fig. 11 is a flowchart illustrating a method for performing data reassembly on equal-length sub-code blocks of the third set according to an embodiment of the present invention;
FIG. 12 is a schematic diagram of data reorganization in case 3 according to an embodiment of the present invention;
fig. 13 is a flowchart illustrating a method for performing data reassembly on equal-length sub-code blocks of the fourth set according to an embodiment of the present invention;
FIG. 14 is a diagram illustrating data reassembly according to scenario 4 of the present invention.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
When a plurality of equal-length sub-code blocks are processed in a code block cascade processing operation, if each bit is processed, the delay and the processing time of the system are increased. And the system based on the fixed data bit width performs code block cascade operation on a plurality of equal-length sub code blocks, so that the processing speed is improved, and the system delay is reduced. However, there are certain complexities and challenges to performing bit-level processing operations based on a fixed data bit width system. This is because the sub-code blocks of equal length of any bit segment may not be integer multiples of the fixed data bit width, so that when each sub-code block is converted into data of the fixed data bit width, some bits may be invalid in the data at the end position, and the invalid bits cannot exist in the data stream. When the sub-code blocks are concatenated, the invalid bits at the end of each sub-code block must be removed, and the removed invalid bits must be filled by the following valid bits, so that the data at other positions in the data stream will be changed. In the process of cascading a plurality of equal-length sub-code blocks, a plurality of invalid bits need to be removed, so that the operation of cascading the plurality of equal-length sub-code blocks based on a system with a fixed data bit width becomes quite complex and difficult.
Aiming at the difficulties in the prior art, the invention provides a data processing method applied to a system with fixed data bit width for channel coding. Fig. 1 is a flowchart illustrating a method of processing data in channel coding according to an embodiment of the present invention, wherein the method includes the following steps S100 to S400.
Step S100: and respectively converting each equal-length sub code block of the signal to be processed into a first data segment according to the fixed data bit width, and acquiring the effective bit in the tail position data in the first data segment.
Chips such as an FPGA (field programmable gate array chip) and a DSP (digital signal processing chip) all have a fixed data bit width when processing data, and the data processing method of this embodiment is applied to such systems having a fixed data bit width, and can implement a cascade operation on equal-length sub-code blocks of any bit segment length.
The signal to be processed comprises one or more equal-length sub-code blocks, and the lengths of the bit sections containing data in the equal-length sub-code blocks are the same. When the system respectively converts each equal-length sub code block of the signal to be processed into a first data segment according to the fixed data bit width when the system processes data, the division condition of each equal-length sub code block is the same. And when the equal-length sub code blocks are converted into the first data segment, the length of the effective bit in the tail position data is obtained according to the dividing condition.
Step S200: and counting and numbering each equal-length sub-code block, and determining a classification judgment factor of each equal-length sub-code block according to the number and the effective bits of each equal-length sub-code block.
And counting and numbering each equal-length sub code block in the signal to be processed according to the sequence of arrangement. The position of each sub code block with the same length in the signal to be processed can be judged according to the corresponding number of the sub code block with the same length, and the valid bit at the tail position of each sub code block with the same length determines the length of the invalid bit which needs to be processed in the data stream when the signal to be processed is subjected to data recombination subsequently. In this embodiment, after analyzing the operation of code block concatenation on a large number of equal-length sub-code blocks of different lengths, it is found that the operation of recombining data of any length can be divided into a limited number of operation cases. The obtained classification judgment factors can be used as classification bases of recombination operation of the equal-length sub-code blocks during data recombination by integrating the positions of the equal-length sub-code blocks in the signal to be processed and the lengths of invalid bits needing to be processed at the tail positions of the equal-length sub-code blocks.
Step S300: and classifying the sub code blocks with the same length according to the classification judgment factors and the effective bits of the sub code blocks with the same length.
When each equal-length subcode block is subjected to data reorganization, the number of new data segments after the reorganization may change, and the reorganization operation performs different modes of data reorganization according to whether the data is at the tail position or the non-tail position. But for data with any length, the operation rule during data reorganization is traceable. And dividing each equal-length sub-code block into different data recombination types according to the classification judgment factor and the effective bit of each equal-length sub-code block. When the system carries out data recombination on the equal-length sub-code blocks divided into the same type, the division arrangement conditions of the data are the same, so that the operation can be simplified, the data processing efficiency can be improved, and the cascading operation is simpler and clearer by classifying the equal-length sub-code blocks.
Step S400: and performing corresponding data recombination on each equal-length sub code block according to the classification condition so as to complete code block cascade of the signals to be processed.
And according to the classification condition of each equal-length sub-code block, performing data recombination on different types of equal-length sub-code blocks according to corresponding data recombination modes. Through data recombination, invalid bits in the equal-length sub-code blocks with the invalid bits at each tail position can be removed, and therefore code block cascade of all the equal-length sub-code blocks in the signal to be processed is achieved. When the data processing method provided by this embodiment is applied to a system with a fixed data bit width, the system can perform a concatenation operation on sub code blocks with equal length and any bit segment length based on the fixed data bit width, and the concatenation operation of the system is also simpler and clearer.
Fig. 2 is a flowchart illustrating a method for converting equal-length sub-code blocks into a first data segment according to an embodiment of the present invention, where in an embodiment, converting each equal-length sub-code block of a signal to be processed into a first data segment according to a fixed data bit width, and acquiring valid bits in end position data in the first data segment includes the following steps S110 to S130.
Step S110: and acquiring the bit length of the sub code blocks with the same length and the fixed data bit width of the system.
The system determines the fixed data bit width 2 when it processes datanAnd obtaining the bit length Lb of each equal-length sub code block in the signal to be processed. Wherein n is an exponent number of 2, and the value of n is an integer greater than 0. The maximum representation bit width m available for the equal-length sub-code block can be obtained according to the bit length Lb of the equal-length sub-code block, and then m-1:0 can be used]Represents the value of Lb, i.e., using Lb [ m-1: 0]]To represent the length value of the bit length Lb of an equal-length sub-code block.
In this embodiment, in order to describe the process of code block concatenation of the equal-length sub-code blocks in more detail, the processing procedure of the code block concatenation processing method is described using the bit lengths of the equal-length sub-code blocks as shown in table 1. As can be seen from table 1, the bit length of the selected equal-length subblock block is Lb =36 bits.
Table 1 data table of equal length subblock block bit segment lengths
Step S120: and dividing the equal-length sub-code block by taking the fixed data bit width as a unit to obtain a first data segment.
With a fixed data bit width of 2nAnd dividing the equal-length sub-code blocks into units, and converting the equal-length sub-code blocks into a first data segment. Every 2 in an equal length sub-code block bit segmentnThe bits are divided into one data, which is divided into a first data segment composed of a plurality of data.
Step S130: and acquiring the effective bit of the tail position data in the first data segment and the number of data in the first data segment according to the dividing condition.
According to the division, the effective bit R contained in the data at the tail position of the first data segment and the data number Ld contained in the first data segment can be obtained, thereby obtaining R = Lb [ n-1:0]]. In the bookIn the embodiment, the value of the data number Ld is determined in two cases according to whether the valid bit R in the data at the end position of the first data segment is 0 or not. When R is 0, i.e. when the bit length of the equal-length sub-code block is the fixed data bit width 2 of the systemnIf the number of data Ld is an integer multiple, Ld = Lb [ m: n ] is the number of data Ld]. When R is not 0, i.e. when the bit length of the equal-length sub-code block is not the fixed data bit width 2 of the systemnIf the number of data Ld is an integer multiple, then one is added, Ld = Lb [ m: n]+1。
In this embodiment, the fixed data bit width 2 of the systemnFor example, 16 bits, the data conversion process is described, i.e. n takes a value of 4. When the system converts an equal-length sub-code block with the bit length of 36 bits shown in table 1 by taking 16 bits as a unit, a data table of the data number and the data valid bit at the tail position of the equal-length sub-code block shown in table 2 can be obtained. According to the conversion condition shown in table 2, it can be known that the valid bit R =4 bits of the data at the end position of the converted first data segment, and the number of data in the converted first data segment is Ld = 3.
During conversion, each 16 bits in a bit length segment of a sub code block with the same length are sequentially converted into one datum according to the sequence of arrangement, and when the data is converted into the last 16-bit datum, only the effective bit of R = Lb [ n-1:0] =4 is obtained, namely, the 4-bit at the lower position in the datum is the effective bit, and the bit at the upper position (16-R) =12 is the invalid bit.
TABLE 2 data table of the valid bit R of data at the end position of the first data segment and the number Ld of data of the first data segment
Fig. 3 is a flowchart illustrating a method for obtaining a classification judgment factor according to an embodiment of the present invention, where in an embodiment, counting and numbering each of the equal-length sub-code blocks, and determining the classification judgment factor of each of the equal-length sub-code blocks according to the numbering and the valid bits of each of the equal-length sub-code blocks includes the following steps S210 to S220.
Step S210: each equal-length sub-code block is count-numbered from zero.
And counting each equal-length sub code block in the signal to be processed from zero according to the sequence of the arrangement, wherein the counting number is cnt. That is, the first equal-length sub-code block is numbered cnt =0, the second equal-length sub-code block is numbered cnt =1, and so on, the nth equal-length sub-code block is numbered cnt = N-1 until the counting numbering of all equal-length sub-code blocks in the signal to be processed is completed.
Step S220: and substituting the serial number and the valid bit of each equal-length sub-code block into a calculation formula of the classification judgment factor to calculate the classification judgment factor of each equal-length sub-code block.
In this embodiment, the system is still at a fixed data bit width of 2nThe calculation process of the classification judgment factor will be described with 16 bits as an example. After a large number of equal-length sub-code blocks with different lengths are respectively subjected to code block cascade, different data recombination phenomena are induced and summarized to obtain the classification judgment factor P, and the classification judgment factor P can be expressed as (16-cnt R%16)%16 by using a calculation formula. Where cnt is the number of the equal-length sub-code block, and R is the valid bit of the data at the end position of the first data segment.
In this embodiment, after code block concatenation operation is performed on a large number of equal-length sub-code blocks with different lengths, analysis shows that only four different cases occur when data with any bit length is subjected to recombination operation, and the four cases can be classified according to the summarized classification judgment factor P. Here, two different equal-length sub-code blocks with bit lengths Lb =36bit and Lb =42bit are randomly selected as an example, and an operation situation when code blocks of signals to be processed with different equal-length sub-code blocks are concatenated is described.
Fig. 4 is a data diagram illustrating the classification decision factors for obtaining the bit lengths of equal-length sub code blocks in the signal to be processed, which are Lb =36 bits according to an embodiment of the present invention. Fig. 5 is a data diagram illustrating the classification decision factors for obtaining the bit lengths of equal-length sub code blocks in the signal to be processed, which are Lb =42bit according to an embodiment of the present invention. As can be seen from fig. 4 and fig. 5, for signals to be processed with different bit lengths in equal-length sub-code blocks, the calculated classification decision factors P = (16-cnt × R%16)%16 for each equal-length sub-code block are different from each other.
Fig. 6 is a flowchart illustrating a method for classifying each sub-code block of equal length according to an embodiment of the present invention, wherein in an embodiment, classifying each sub-code block of equal length according to the classification decision factor and the significant bits of each sub-code block of equal length includes the following steps S310 to S340.
Step S310: when the classification decision factor of the equal-length sub-code blocks is equal to 0, the equal-length sub-code blocks are divided into a first set.
And classifying the conditions of the equal-length sub code blocks according to the comparison condition of the classification judgment factor P and the effective bit R of the data at the tail position of the first data segment. When the classification decision factor P is equal to 0, belonging to case 1, all the equally long sub-code blocks of classification decision factor P =0 are divided into a first set. When the code blocks of equal-length sub-code blocks belonging to the first set are concatenated, they are subjected to a corresponding data reassembly operation as in case 1.
Step S320: and when the classification judgment factor of the equal-length sub-code blocks is larger than the effective bits, dividing the equal-length sub-code blocks into a second set.
When the classification judgment factor P is larger than the valid bit R of the data at the end position of the first data segment, which belongs to case 2, all the equal-length sub-code blocks of the classification judgment factor P > R are divided into a second set. When the equal-length sub-code block code blocks belonging to the second set are concatenated, they are subjected to the corresponding data re-assembly operation as per case 2.
Step S330: when the classification decision factor of the equal-length sub-code blocks is equal to the significant bits, the equal-length sub-code blocks are divided into a third set.
When the classification decision factor P is equal to the significant bit R of the data at the end position of the first data segment, belonging to case 3, all equally long sub-code blocks of the classification decision factor P = R are divided into a third set. When the equal-length sub-code block code blocks belonging to the third set are concatenated, they are subjected to the corresponding data re-assembly operation as per case 3.
Step S340: and when the classification judgment factor of the equal-length sub-code blocks is smaller than the effective bits, dividing the equal-length sub-code blocks into a fourth set.
When the classification decision factor P is smaller than the significant bit R of the data at the end position of the first data segment, which belongs to case 4, the equal-length sub-code blocks of all classification decision factors P < R are divided into a fourth set. When the equal-length sub-code block code blocks belonging to the fourth set are concatenated, they are subjected to the corresponding data re-assembly operation as per case 4.
As can be seen from fig. 4 and fig. 5, for signals to be processed with different bit lengths in sub code blocks of equal length, the classification decision factor P = (16-cnt × R%16)%16 and the significant bit R obtained by calculation can be used to classify different situations of data reconstruction.
Fig. 7 is a flowchart illustrating a method for performing data reassembly on the equal-length sub-code blocks of the first set in an embodiment of the present invention, where performing corresponding data reassembly on the equal-length sub-code blocks of the first set in an embodiment of the present invention includes the following steps S401 to S403.
In the present embodiment, data at the end position in the first data segment is defined as EP, the rest of data at the non-end position is defined as NEP, the data at the end position after the reassembly is defined as EP ', and the rest of data at the non-end position after the reassembly is defined as NEP'. When each equal-length subblock block is subjected to data reorganization, the number of data after reorganization may change, and the data reorganization operation needs to be performed in different manners according to whether the data is located at the end position EP or the non-end position NEP.
Step S401: and placing the effective bit at the low position in the tail position data before the recombination on the low position of the tail position data after the recombination, and placing the data at the low position in the data at the one position after the tail position data before the recombination on the high position in the tail position data after the recombination.
When the classification judgment factor P =0 of the equal-length sub code block, corresponding data reorganization operation needs to be performed on the equal-length sub code block according to the data reorganization mode in case 1, and the number of data subjected to data reorganization according to case 1 is consistent with the number of data before reorganization. End position data EP' of the reconstructed dataR bits at the lower order in the data EP at the group leading end position, and 2 bits at the lower order in the next data of the re-grouped leading end position data EPn-R bits. The low-order R bit in the before-and-after-reorganization position data EP is placed at the low order of the after-and-reorganization position data EP', and the next number of the before-and-after-reorganization position data EP is lower by 2nthe-R bits are placed in the upper bits of the data EP' at the post-reassembly end position.
Step S403: and directly mapping the non-end position data before the reorganization to the non-end position data after the reorganization.
The non-end position data NEP 'after the reorganization is directly composed of 2 in the non-end position NEP' before the reorganizationnAnd acquiring data mapping of bit.
In this embodiment, in order to better illustrate the data reassembly process in step S401 and step S403, the data reassembly method in case 1 is described by taking, as an example, the bit length Lb =36 bits of the equal-length sub-code block and the number cnt =0 of the equal-length sub-code block. FIG. 8 is a schematic diagram of data reconstruction in case 1 according to an embodiment of the present invention. As shown in fig. 8, the number Ld of data of the first data segment converted from the equal-length sub code block is 3. The data in the first table in fig. 8 is the original data of equal-length sub-code blocks. Wherein the first two data belong to the non-end position data NEP before the re-assembly, the third data belong to the end position data EP before the re-assembly, and the effective bit R in the end position data EP is 4.
The data in the second table in fig. 8 is obtained by data rearrangement of long-length sub code blocks having a bit length of Lb =36bit and a number of cnt =0 according to the data rearrangement method of case 1. Wherein, the first two data belong to the non-end position NEP' after the reorganization, and are obtained by directly mapping the non-end position NEP before the reorganization. The third data is the end position data EP' after the reassembly, and is composed of R =4 bits at the lower order in the end position data EP before the reassembly and 2 bits at the lower order in the data next to the end position data EP before the reassemblyn-R =12 bits. The low-order R =4 bits of the end position data EP before the reassembly are placed after the reassemblyLower order of the end position data EP', lower order 2 of the data next to the end position data EP before the rearrangementnR =12 bits are placed in the upper bits of the end position data EP'.
Fig. 9 is a flowchart illustrating a method for performing data reassembly on the equal-length sub-code blocks of the second set in an embodiment of the present invention, wherein performing corresponding data reassembly on the equal-length sub-code blocks of the second set includes the following steps S405 to S407.
Step S405: and placing the last high bit of the data at the non-tail position before the recombination at the low bit of the data at the tail position after the recombination, placing the low bit of the data at the tail position before the recombination at the middle position, and placing the data at the low bit of the data at the tail position after the data at the tail position before the recombination at the high bit of the data at the tail position after the recombination.
When the classification judgment factor P of the equal-length sub-code block>And R, performing corresponding data recombination operation according to the data recombination mode of the condition 2, wherein the number of the data subjected to data recombination according to the condition 2 is one less than that of the data before recombination. The last position data EP' after the reassembly, the last 2 at the high order in the non-end position NEP before the reassemblyn-P bits, R bits in the lower order in the pre-reassembly end position EP, and P-R bits in the lower order in the data subsequent to the pre-reassembly end position EP. 2 at high position in the non-end position NEP of the last before recombinationn-P bits are placed at the lower bits of the post-reassembly end position data EP ', R bits at the lower bits of the post-reassembly end position EP are placed at the middle positions of the post-reassembly end position data EP ', and P-R bits at the lower bits of the post-reassembly end position EP data are placed at the upper bits of the post-reassembly end position data EP '.
Step S407: and placing the high order bit of the non-end position data before the recombination on the low order bit of the non-end position data after the recombination, and placing the low order bit of the next data on the high order bit of the non-end position data after the recombination.
The non-end position data NEP' after the reorganization is composed of the non-end position data N before the reorganizationHigh in EP 2n-P bits, and P bits at lower order in the data next to the non-end position data NEP before the reassembly. 2 at high position in non-end position data NEP before recombinationn-P bits are placed in the lower bits of the post-reassembly non-end position data NEP ', and P bits in the lower bits of the pre-reassembly non-end position data NEP are placed in the upper bits of the post-reassembly non-end position data NEP'.
In this embodiment, in order to better illustrate the data reassembly process in step S405 and step S407, the data reassembly method in case 2 is described by taking, as an example, the bit length Lb =36 bits of the equal-length sub-code block and the number cnt =1 of the equal-length sub-code block. FIG. 10 is a diagram illustrating data reassembly according to scenario 2 of an embodiment of the present invention. As shown in fig. 10, the number Ld of data of the first data segment into which the equal-length sub code block is converted is 3. The data in the first table in fig. 10 is the original data of equal-length sub-code blocks. Wherein the first two data belong to the non-end position data NEP before the reassembly, the third data belong to the end position data EP before the reassembly, and the end position valid bit R is 4.
The data in the second table in fig. 10 is obtained by data rearrangement of long sub code blocks having a bit length Lb =36bit and a cnt =1 number according to the data rearrangement method of case 2. Since the equal-length sub-code block has a number cnt =1 and R =4, P =12 is calculated according to the formula P = (16-cnt × R%16)%16, and then P > R belongs to case 2. In case 2, the number of the data after the reassembly is one less than the number of the data before the reassembly, that is, the data after the reassembly is only two data, the first data after the reassembly belongs to the non-end position data NEP ', and the second data after the reassembly belongs to the end position data EP'.
The non-end position data NEP' after the reassembly is composed of the 2 bits in the non-end position data NEP before the reassemblyn-P =4 bits, and P =12 bits at the lower order in the data next to the non-end position data NEP before the reassembly. 2 at high position in non-end position data NEP before recombinationn-P =4 bits are placed in the lower bits of the non-end position data NEP' after the reassembly, and are to be repeatedThe lower bits P =12 bits of the data next to the group front non-end position data NEP are placed in the upper bits of the reorganized non-end position data NEP'.
The last position data EP' after the reassembly, the last 2 at the high position in the non-end position NEP before the reassemblynP =4 bits, R =4 bits which are lower in the reassembly front-end position EP, and P-R =8 bits which are lower in the data subsequent to the reassembly front-end position EP. 2 at high position in the non-end position NEP of the last before recombinationn-P =4 bits are placed in the lower bits of the post-reassembly end position data EP ', R =4 bits which are lower in the post-reassembly end position EP are placed in the middle positions of the post-reassembly end position data EP ', and P-R =8 bits which are lower in the post-reassembly end position EP post-data are placed in the upper bits of the post-reassembly end position data EP '.
Fig. 11 is a flowchart illustrating a method for performing data rearrangement on the third set of equal-length sub-code blocks according to an embodiment of the present invention, where in an embodiment, performing corresponding data rearrangement on the third set of equal-length sub-code blocks includes the following steps S409 to S411.
Step S409: and placing the high bit of the last data which is not at the tail position before the recombination on the low bit of the recombined tail position data, and placing the data which is at the low bit in the tail position data before the recombination on the high bit of the recombined tail position data.
When the classification judgment factor P = R of the equal-length sub code block is larger than the classification judgment factor P = R, the corresponding data reorganization operation needs to be performed on the equal-length sub code block according to the data reorganization mode in case 3, and the number of the data subjected to data reorganization according to case 3 is one less than that before the grouping. The last position data EP' after the reassembly, the last position data NEP before the reassembly, which is at the high order 2n-P bits, and P bits at the lower bits in the re-assembly front-end position data EP. The last data NEP in the non-end position before recombination is in the high order 2n-P bits are placed at the lower bits of the post-reassembly end position data EP', and the P bits at the lower bits of the pre-reassembly end position data EP are placed at the lower bitsThe upper bits of the end position data EP' after the reassembly. Since P = R in the present embodiment, P here may also be regarded as R.
Step S411: and placing the high order bit of the non-end position data before the recombination on the low order bit of the non-end position data after the recombination, and placing the low order bit of the next data on the high order bit of the non-end position data after the recombination.
The non-end position data NEP' after the reassembly is composed of the 2 bits in the non-end position NEP before the reassemblyn-P bits, and P bits at lower order bits in the data next to the non-end position NEP before reassembly. 2 at high position in the non-end position NEP before recombinationn-P bits are placed at the lower bits of the non-end position data NEP 'after the reassembly, and P bits at the lower bits of the data next to the non-end position NEP before the reassembly are placed at the upper bits of the non-end position data NEP' after the reassembly.
In this embodiment, in order to better illustrate the data reassembly process in step S409 and step S411, the data reassembly method in case 3 is described by taking, as an example, the bit length Lb =36 bits of the equal-length sub-code block and the number cnt =3 of the equal-length sub-code block. FIG. 12 is a diagram illustrating data reassembly according to scenario 3 of the present invention. As shown in fig. 12, the number Ld of data of the first data segment into which the equal-length sub code block is converted is 3. The data in the first table in fig. 12 is the original data of equal-length sub-code blocks. Wherein, the first two data belong to the non-end position NEP before the reorganization, the third data belong to the end position EP before the reorganization, and the effective bit R of the end position is 4.
The data in the second table in fig. 12 is obtained by data rearrangement of long sub code blocks having a bit length Lb =36bit and a cnt =3 number according to the data rearrangement method of case 3. Since the equal-length sub-code block has a number cnt =3 and R =4, P =4 is calculated according to the formula P = (16-cnt × R%16)%16, and P = R belongs to case 3. In case 3, the number of the data after the reassembly is one less than the number of the data before the reassembly, that is, the data after the reassembly is only two data, the first data after the reassembly belongs to the non-end position data NEP ', and the second data after the reassembly belongs to the end position data EP'.
The non-end position data NEP' after the reassembly is composed of the 2 bits in the non-end position NEP before the reassemblyn-P =12 bits, and P =4 bits at the lower order in the data of the next bit of the non-end position NEP before the reassembly. 2 at high position in the non-end position NEP before recombinationnP =12 bits are placed in the lower order of the non-end position data NEP 'after the reassembly, and P =4 bits, which are the lower order bits in the data next to the non-end position NEP before the reassembly, are placed in the upper order of the non-end position data NEP' after the reassembly.
The last position data EP' after the reassembly, the last position data NEP before the reassembly, which is at the high order 2nP =12 bits, and P =4 bits at the lower order in the re-set front-end position data EP. The last data NEP in the non-end position before recombination is in the high order 2nP =12 bits are placed in the lower order of the post-reassembly end position data EP ', and P =4 bits that are in the lower order in the post-reassembly end position data EP are placed in the upper order of the post-reassembly end position data EP'.
Fig. 13 is a flowchart illustrating a method for performing data reassembly on equal-length sub-code blocks of the fourth set in an embodiment of the present invention, wherein performing corresponding data reassembly on equal-length sub-code blocks of the fourth set in an embodiment includes the following steps S413 to S415.
Step S413: and placing the high order bit in the effective bit of the tail position data before recombination on the low order bit of the tail position data after recombination, and placing the data which is at the low order bit in the next data of the tail position data before recombination on the high order bit of the tail position data after recombination.
When the classification judgment factor P of the equal-length sub-code block<And R, performing corresponding data recombination operation according to the data recombination mode of the condition 4, wherein the number of the data subjected to data recombination according to the condition 4 is consistent with that of the data before the recombination. The re-arranged end position data EP' is composed of R-P bits at a higher order in the effective bits of the re-arranged end position data EP and a lower order in the data next to the re-arranged end position data EP2n-R + P bits. Placing the R-P bit at the high position in the effective bit of the before-and-after-reassembly position data EP at the low position of the after-reassembly position data EP', and placing the 2bit at the low position in the data next to the before-and-after-reassembly position data EPnthe-R + P bits are placed at the upper bits of the reassembled end position data EP'.
Step S411: and placing the high order bit of the non-end position data before the recombination on the low order bit of the non-end position data after the recombination, and placing the low order bit of the next data on the high order bit of the non-end position data after the recombination.
The non-end position data NEP' after the reassembly is composed of the 2 bits in the non-end position data NEP before the reassemblyn-P bits, and P bits at lower order in the data next to the non-end position data NEP before the reassembly. 2 at high position in non-end position data NEP before recombinationn-P bits are placed at the lower bits of the non-end position data NEP 'after the reassembly, and P bits at the lower bits of the data next to the non-end position data NEP before the reassembly are placed at the upper bits of the non-end position data NEP' after the reassembly.
In this embodiment, in order to better illustrate the data reassembly process in step S413 and step S415, the data reassembly method in case 4 is described by taking, as an example, the bit length Lb =42 bits of the equal-length sub-code block and the number cnt =1 of the equal-length sub-code block. The reason why the bit length Lb =36bit of the equal-length sub code block is not taken as an example here is that the data reassembly operation of case 4 does not exist when the bit length Lb =36bit of the equal-length sub code block is subjected to code block concatenation. FIG. 14 is a diagram illustrating data reassembly according to scenario 4 of the present invention. As shown in fig. 14, the number Ld of data of the first data segment into which the equal-length sub code block is converted is 3. The data in the first table in fig. 14 is the original data of equal-length sub-code blocks. Wherein, the first two data belong to the non-end position NEP before the reorganization, the third data belong to the end position EP before the reorganization, and the effective bit R of the end position is 10.
The data in the second table in fig. 14 is obtained by data rearrangement of long-length sub code blocks having a bit length of Lb =42bit and a number of cnt =1 according to the data rearrangement method of case 4. Since the equal-length sub-code block has a number cnt =1 and R =10, P =6 is calculated according to the formula P = (16-cnt × R%16)%16, and P < R belongs to case 4. In case 4, the number of data after the reassembly is the same as the number of data before the reassembly, that is, there are 3 data after the reassembly, the 1 st and 2 nd numbers after the reassembly belong to the non-end position data NEP ', and the 3 rd number belongs to the end position data EP' after the reassembly.
The non-end position data NEP' after the reassembly is composed of the 2 bits in the non-end position data NEP before the reassemblyn-P =10 bits, and P =6 bits at the lower order in the data next to the non-end position data NEP before the reassembly. 2 at high position in non-end position data NEP before recombinationnThe P =10 bits are placed in the lower order of the non-end position data NEP 'after the reassembly, and the P =6 bits that are the lower order of the data next to the non-end position data NEP before the reassembly are placed in the upper order of the non-end position data NEP' after the reassembly.
The re-arranged end position data EP' is composed of R-P =4 bits at the upper position in the effective bit of the re-arranged end position data EP and 2 bits at the lower position in the data next to the re-arranged end position data EPn-R + P =12 bits. Placing the high-order bits R-P =4 bits of the effective bits of the before-and-after-reassembly position data EP 'at the low order bits of the after-reassembly position data EP', and placing the low-order bits 2 of the data next to the before-and-after-reassembly position data EPn-R + P =12 bits are placed in the upper order of the reorganized end position data EP'.
It should be understood that although the steps in the flowcharts of fig. 1, 2, 3, 6, 7, 9, 11, 13 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 1, 2, 3, 6, 7, 9, 11, and 13 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or alternatingly with other steps or at least some of the other steps.
A computer device comprising a memory and a processor, the memory storing a computer program, wherein the processor when executing the computer program implements the steps of the data processing method in channel coding as described in any one of the above embodiments.
A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the data processing method in channel coding as set forth in any one of the preceding embodiments.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical storage, or the like. Volatile Memory can include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others.
In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A data processing method in channel coding, applied to a wireless communication system, wherein the wireless communication system has a fixed data bit width when processing signals, the method comprising:
converting each equal-length sub code block of the signal to be processed into a first data segment according to the fixed data bit width, and acquiring an effective bit in tail position data in the first data segment;
counting and numbering each sub code block with the same length, and determining a classification judgment factor of each sub code block with the same length according to the number and the effective bit of each sub code block with the same length;
classifying each sub code block with the same length according to the classification judgment factor and the effective bit of each sub code block with the same length;
and performing corresponding data recombination on each equal-length sub code block according to the classification condition so as to complete code block cascade of the signals to be processed.
2. The method of claim 1, wherein the converting each equal-length sub-code block of the signal to be processed into a first data segment according to the fixed data bit width, and obtaining the valid bit in the data of the last position in the first data segment comprises:
acquiring the bit length of the equal-length sub-code block and the fixed data bit width of a system;
dividing the equal-length sub code blocks by taking the fixed data bit width as a unit to obtain the first data segment;
and acquiring the effective bit of the tail position data in the first data segment and the number of data in the first data segment according to the dividing condition.
3. The method according to claim 1 or 2, wherein said counting each of said sub-code blocks of equal length and determining a classification decision factor for each of said sub-code blocks of equal length based on the numbering and the significance of each of said sub-code blocks of equal length comprises:
counting and numbering each equal-length sub-code block from zero;
and substituting the serial number and the valid bit of each sub code block with the same length into a calculation formula of a classification judgment factor, and calculating the classification judgment factor of each sub code block with the same length.
4. The method according to claim 1, wherein said classifying each of the equal-length sub-code blocks according to its classification decision factor and its significance comprises:
when the classification judgment factor of the equal-length sub-code blocks is equal to 0, dividing the equal-length sub-code blocks into a first set;
when the classification judgment factor of the equal-length sub-code blocks is larger than the valid bits, dividing the equal-length sub-code blocks into a second set;
when the classification judgment factor of the equal-length sub-code blocks is equal to the valid bits, dividing the equal-length sub-code blocks into a third set;
and when the classification judgment factor of the sub code blocks with the same length is smaller than the valid bits, dividing the sub code blocks with the same length into a fourth set.
5. The method according to claim 4, wherein the respective data reassembly of the equal-length sub-code blocks of the first set comprises:
placing the effective bit position at the low position in the tail position data before recombination on the low position of the tail position data after recombination, and placing the data at the low position in the data at the one position after the tail position data before recombination on the high position in the tail position data after recombination;
and directly mapping the non-end position data before the reorganization to the non-end position data after the reorganization.
6. The method according to claim 4, wherein the respective data reassembly of the equal-length sub-code blocks of the second set comprises:
placing the last high bit of the data at the non-tail position before the recombination on the low bit of the data at the tail position after the recombination, placing the low bit of the data at the tail position before the recombination on the middle position, and placing the data at the low bit of the data at the tail position after the data at the tail position before the recombination on the high bit of the data at the tail position after the recombination;
and placing the high order bit of the non-end position data before the recombination on the low order bit of the non-end position data after the recombination, and placing the low order bit of the next data on the high order bit of the non-end position data after the recombination.
7. The method according to claim 4, wherein the respective data reassembly of the equal-length sub-code blocks of the third set comprises:
placing the last high bit of the data at the non-tail position before the recombination on the low bit of the data at the tail position after the recombination, and placing the data at the low bit in the data at the tail position before the recombination on the high bit of the data at the tail position after the recombination;
and placing the high order bit of the non-end position data before the recombination on the low order bit of the non-end position data after the recombination, and placing the low order bit of the next data on the high order bit of the non-end position data after the recombination.
8. The method according to claim 4, wherein the respective data reassembly of the equal-length sub-code blocks of the fourth set comprises:
placing the high order in the effective bit of the tail position data before recombination on the low order of the tail position data after recombination, and placing the data at the low order in the next data of the tail position data before recombination on the high order of the tail position data after recombination;
and placing the high order bit of the non-end position data before the recombination on the low order bit of the non-end position data after the recombination, and placing the low order bit of the next data on the high order bit of the non-end position data after the recombination.
9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor realizes the steps of the method of any one of claims 1 to 8 when executing the computer program.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 8.
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