CN112821904A - Device for realizing 5G signal interference filtering aiming at Beidou signals - Google Patents
Device for realizing 5G signal interference filtering aiming at Beidou signals Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/21—Interference related issues ; Issues related to cross-correlation, spoofing or other methods of denial of service
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/38—Determining a navigation solution using signals transmitted by a satellite radio beacon positioning system
- G01S19/39—Determining a navigation solution using signals transmitted by a satellite radio beacon positioning system the satellite radio beacon positioning system transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/42—Determining position
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
- H04B1/1027—Means associated with receiver for limiting or suppressing noise or interference assessing signal quality or detecting noise/interference for the received signal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0202—Channel estimation
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Abstract
The invention relates to a device for filtering 5G signal interference aiming at Beidou signals, which comprises a signal receiving unit, a Beidou interference signal filtering unit and a signal generating unit, wherein the signal receiving unit is used for acquiring a Beidou and 5G composite digital baseband signal, the Beidou interference signal filtering unit is used for extracting the 5G signal, estimating a channel, restoring the 5G signal, removing the 5G interference signal and restoring the Beidou signal, and the signal generating unit is used for converting the interference-removed Beidou signal into an analog signal and sending the analog signal to a Beidou receiver. By adopting the device for filtering the 5G signal interference aiming at the Beidou signal, the digital baseband data is quickly acquired by simplifying a receiving scheme, and the real-time processing of the data is realized by the ping-pong operation of the DSP, the FPGA and the two-stage DDR3, so that the real-time performance of the baseband data processing is realized and the possibility of data loss is avoided; the channel estimation algorithm through optimization ensures that the Beidou signals are restored without distortion while the 5G interference signals are removed.
Description
Technical Field
The invention relates to the field of Beidou signal analysis and processing, in particular to the field of 5G interference filtering, and particularly relates to a device for realizing 5G signal interference filtering aiming at Beidou signals.
Background
With the rapid increase of 5G construction and the mass deployment of base stations, due to the problems of adjacent channel interference and overlapping coverage of a 5G NR (2.6GHz) system on the RDSS service frequency band of the beidou system, the beidou receiver, especially a ground receiving station, is seriously interfered in a specific frequency band and cannot normally receive beidou signals, so that the research and development of a device capable of filtering 5G interference at the front end of the beidou receiver is urgent.
The invention provides a Beidou signal 5G interference filtering device, which is characterized in that a signal receiving unit obtains a composite digital signal in which Beidou and 5G signals coexist through down-conversion, a broadband demodulator and an ADC (analog-to-digital converter); extracting a 5G signal of a current frequency point from a Beidou signal interference filtering unit, and then performing channel estimation through LMMSE (Bayesian estimation theory) to restore the 5G signal; removing the restored 5G signal by using the composite digital signal extracted from the signal receiving unit to obtain a relatively pure Beidou signal; through the signal generation unit, the big dipper digital signal data after the reduction are sent into DAC (digital-to-analog converter), and the power and the frequency of receiving signal are reduced to the broadband modulator and one-level frequency conversion, send and accomplish the 5G interference filtering of big dipper signal for big dipper receiver.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides the device for filtering the 5G signal interference aiming at the Beidou signal, which has the advantages of good reducibility, simple and convenient operation and wide application range.
In order to achieve the purpose, the device for filtering the 5G signal interference aiming at the Beidou signal comprises the following components:
the device for filtering the 5G signal interference aiming at the Beidou signal is mainly characterized by comprising a signal receiving unit, a Beidou interference signal filtering unit and a signal generating unit, wherein the output end of the signal receiving unit is connected with the input end of the Beidou interference signal filtering unit, the output end of the Beidou interference signal filtering unit is connected with the input end of the signal generating unit, the signal receiving unit is used for acquiring a Beidou and 5G composite digital baseband signal, the Beidou interference signal filtering unit is used for extracting the 5G signal, estimating a channel, reducing the 5G signal and removing the 5G interference signal and reducing the Beidou signal, and the signal generating unit is used for converting the interference-removed Beidou signal into an analog signal and sending the analog signal to a Beidou receiver.
Preferably, the signal receiving unit includes a first low noise amplifier, a band pass filter, a second low noise amplifier, a mixer, a first phase-locked loop, an intermediate frequency amplifier, an intermediate frequency band pass filter, a wideband demodulator, a second phase-locked loop, a digital-to-analog converter, and a DDS clock; the first low-noise amplifier receives signals, the output end of the first low-noise amplifier is connected with the input end of the band-pass filter bank, the output end of the band-pass filter bank is connected with the frequency mixer through the second low-noise amplifier, the output end of the first phase-locked loop is connected with the input end of the frequency mixer, the output end of the frequency mixer is connected with the input end of the broadband demodulator through the intermediate frequency amplifier and the intermediate frequency band pass filter, the output end of the second phase-locked loop is connected with the input end of the broadband demodulator, the output end of the broadband demodulator is connected with the input end of the digital-to-analog converter, the input end of, the first low-noise amplifier is used for improving the receiving sensitivity and ensuring the normally received Beidou signals with smaller power, the band-pass filter bank is used for receiving signals without interference of channel stray and image frequency, and the second low-noise amplifier is used for compensating signal attenuation brought by the filter bank.
Preferably, the reference clocks of the first phase-locked loop, the second phase-locked loop and the DDS clock are all 19.2 MHz.
Preferably, the Beidou interference signal filtering unit comprises a digital signal processor, an FPGA, a first DDR3 and a second DDR3, the input and output ends of the DSP are connected with the input and output ends of the FPGA through a PCIe interface, the input and output ends of the digital signal processor are respectively connected with the input and output ends of the first DDR3 and the second DDR3, the input and output ends of the FPGA are respectively connected with the input ends of the first DDR3 and the second DDR3,
the FPGA stores the sampling data in a first DDR3, the digital signal processor extracts a digital baseband signal from the first DDR3, the baseband data are processed in parallel by utilizing a plurality of processing cores of the digital signal processor, 5G signal extraction and GNSS signal restoration are carried out, the baseband data are stored in a designated address of a second DDR3, and the FPGA transmits the baseband data to the signal generating unit after 5G signal elimination; the FPGA also stores the sampled data in a designated address of the second DDR3, the digital signal processor processes the baseband data and stores the baseband data in the designated address of the first DDR3, and the baseband data are transmitted to the signal generating unit after being processed by the FPGA.
Preferably, the signal generating unit includes a second wideband modulator, a second analog-to-digital converter, a second DDS clock, an intermediate frequency band-pass filter, an intermediate frequency amplifier, a mixer, a third phase-locked loop, a fourth phase-locked loop, a two-stage amplifier, and a one-stage low-pass filter, an input end of the second wideband modulator is connected to an output end of the second analog-to-digital converter, an input end of the second analog-to-digital converter is connected to an input end of the second DDS clock, an output end of the second wideband modulator is connected to an input end of the mixer through the intermediate frequency band-pass filter and the intermediate frequency amplifier, an output end of the third phase-locked loop is connected to an input end of the second wideband modulator, an input end of the mixer is connected to an output end of the fourth phase-locked loop, an output end of the mixer is connected to an output end through the two-stage amplifier and the, the low-pass filter is used for suppressing the mixed high-frequency component.
Preferably, the sampling clock of the second DDS clock is 491.52MHz, and the output frequency of the third phase locked loop is 1070 MHz.
By adopting the device for filtering the 5G signal interference aiming at the Beidou signal, the digital baseband data is quickly acquired by simplifying a receiving scheme, and the real-time processing of the data is realized by the ping-pong operation of the DSP, the FPGA and the two-stage DDR3, so that the real-time performance of the baseband data processing is realized and the possibility of data loss is avoided; the channel estimation algorithm through optimization ensures that the Beidou signals are restored without distortion while the 5G interference signals are removed.
Drawings
Fig. 1 is a schematic block diagram of a device for filtering 5G signal interference for a beidou signal according to the present invention.
Fig. 2 is a schematic block diagram of a signal receiving unit of the device for filtering 5G signal interference for Beidou signals according to the present invention.
Fig. 3 is a schematic block diagram of a Beidou signal interference filtering unit of the device for realizing 5G signal interference filtering aiming at the Beidou signal.
Fig. 4 is a schematic block diagram of a signal generating unit of the device for filtering 5G signal interference for Beidou signals according to the present invention.
Detailed Description
In order to more clearly describe the technical contents of the present invention, the following further description is given in conjunction with specific embodiments.
The device for realizing the 5G signal interference filtering aiming at the Beidou signals comprises a signal receiving unit, a Beidou interference signal filtering unit and a signal generating unit, wherein the output end of the signal receiving unit is connected with the input end of the Beidou interference signal filtering unit, the output end of the Beidou interference signal filtering unit is connected with the input end of the signal generating unit, the signal receiving unit is used for obtaining a Beidou and 5G composite digital baseband signal, the Beidou interference signal filtering unit is used for extracting the 5G signal, estimating a channel, reducing the 5G signal, removing the 5G signal and reducing the Beidou signal, and the signal generating unit is used for converting the interference-removed Beidou signal into an analog signal and sending the analog signal to a Beidou receiver.
As a preferred embodiment of the present invention, the signal receiving unit includes a first low noise amplifier, a band pass filter, a second low noise amplifier, a mixer, a first phase-locked loop, an intermediate frequency amplifier, an intermediate frequency band pass filter, a wideband demodulator, a second phase-locked loop, a digital-to-analog converter, and a DDS clock; the first low-noise amplifier receives signals, the output end of the first low-noise amplifier is connected with the input end of the band-pass filter bank, the output end of the band-pass filter bank is connected with the frequency mixer through the second low-noise amplifier, the output end of the first phase-locked loop is connected with the input end of the frequency mixer, the output end of the frequency mixer is connected with the input end of the broadband demodulator through the intermediate frequency amplifier and the intermediate frequency band pass filter, the output end of the second phase-locked loop is connected with the input end of the broadband demodulator, the output end of the broadband demodulator is connected with the input end of the digital-to-analog converter, the input end of, the first low-noise amplifier is used for improving the receiving sensitivity and ensuring the normally received Beidou signals with smaller power, the band-pass filter bank is used for receiving signals without interference of channel stray and image frequency, and the second low-noise amplifier is used for compensating signal attenuation brought by the filter bank.
In a preferred embodiment of the present invention, the reference clocks of the first phase-locked loop, the second phase-locked loop and the DDS clock are all 19.2 MHz.
As a preferred embodiment of the present invention, the Beidou interference signal filtering unit includes a digital signal processor, an FPGA, a first DDR3 and a second DDR3, an input/output end of the DSP is connected to an input/output end of the FPGA through a PCIe interface, an input/output end of the digital signal processor is connected to input/output ends of the first DDR3 and the second DDR3, an input/output end of the FPGA is connected to input ends of the first DDR3 and the second DDR3,
the FPGA stores the sampling data in a first DDR3, the digital signal processor extracts a digital baseband signal from the first DDR3, the baseband data are processed in parallel by utilizing a plurality of processing cores of the digital signal processor, 5G signal extraction and GNSS signal restoration are carried out, the baseband data are stored in a designated address of a second DDR3, and the FPGA transmits the baseband data to the signal generating unit after 5G signal elimination; the FPGA also stores the sampled data in a designated address of the second DDR3, the digital signal processor processes the baseband data and stores the baseband data in the designated address of the first DDR3, and the baseband data are transmitted to the signal generating unit after being processed by the FPGA.
As a preferred embodiment of the present invention, the signal generating unit includes a second wideband modulator, a second analog-to-digital converter, a second DDS clock, an intermediate frequency band-pass filter, an intermediate frequency amplifier, a mixer, a third phase-locked loop, a fourth phase-locked loop, a two-stage amplifier, and a one-stage low-pass filter, an input end of the second wideband modulator is connected to an output end of the second analog-to-digital converter, an input end of the second analog-to-digital converter is connected to an input end of the second DDS clock, an output end of the second wideband modulator is connected to an input end of the mixer through the intermediate frequency band-pass filter and the intermediate frequency amplifier, an output end of the third phase-locked loop is connected to an input end of the second wideband modulator, an input end of the mixer is connected to an output end of the fourth phase-locked loop, and an output end of, the two-stage amplifier is used for compensating signal loss brought by the mixer, and the low-pass filter is used for suppressing high-frequency components of the mixed frequency.
In a preferred embodiment of the present invention, the sampling clock of the second DDS clock is 491.52MHz, and the output frequency of the third phase-locked loop is 1070 MHz.
The invention relates to Beidou signal 5G interference filtering equipment, which comprises a signal receiving unit, a signal generating unit and a Beidou interference signal filtering unit, wherein the output end of the signal receiving unit is connected with the input end of the Beidou interference signal filtering unit; the output end of the Beidou interference signal filtering unit is connected with the input end of the signal generating unit. Due to the fact that the Beidou and 5G signals are overlapped in a specific frequency band, the Beidou signals cannot be received normally, and composite digital signals of the Beidou and the 5G signals which coexist are obtained through a signal receiving unit through down-conversion, a broadband demodulator and an ADC (analog-to-digital converter); extracting a 5G signal of a current frequency point from a Beidou interference signal filtering unit, and then performing channel estimation through LMMSE (Bayesian estimation theory) to restore the 5G signal; removing the restored 5G signal by using the composite digital signal extracted from the signal receiving unit to obtain a relatively pure Beidou signal; through the signal generation unit, the big dipper digital signal data after the reduction are sent into DAC (digital-to-analog converter), and the power and the frequency of receiving signal are reduced to the broadband modulator and one-level frequency conversion, send and accomplish the 5G interference filtering of big dipper signal for big dipper receiver.
As shown in fig. 1, the Beidou signal 5G interference filtering device includes a signal receiving unit, a signal generating unit and a Beidou interference signal filtering unit; the output end of the signal receiving unit is connected with the input end of the Beidou interference signal filtering unit; the output end of the Beidou interference signal filtering unit is connected with the input end of the signal generating unit.
As shown in fig. 2, the signal receiving unit is configured to obtain the beidou plus 5G composite digital baseband signal, and a processing process of the signal receiving unit is as follows:
1) the signal is connected with the input end of the band-pass filter bank through a low-noise amplifier 1 with the gain of 15 dB; the low-noise amplifier 1 is used for improving the receiving sensitivity and ensuring normally received Beidou signals with smaller power; the band-pass filter bank is used for preventing the received signal from being interfered by channel stray and image frequency.
2) The output end of the band-pass filter bank is connected with the mixer through a low noise amplifier 2 of 10 dB; the output end of a PLL1 (phase-locked loop) is connected with the input end of the mixer, wherein the output frequency of the PLL1 is the signal receiving frequency RF +240MH, and 240MHz intermediate frequency signals are guaranteed to be output; the low noise amplifier 2 is to compensate for the signal attenuation caused by the filter bank.
3) The output end of the mixer is connected with the input end of the broadband demodulator through a 15dB intermediate frequency amplifier and an intermediate frequency band-pass filter with 240MHz passband and 100 MHz; the output end of the PLL2 (phase-locked loop) is connected with the input end of the broadband demodulator; the output frequency of the PLL2 is 480 MHz;
4) the output end of the broadband demodulator is connected with the input end of an ADC (digital-to-analog converter), the input end of the ADC (digital-to-analog converter) is connected with the input end of a DDS clock, and the DDS provides a sampling clock of 491.52 MHz.
As shown in fig. 3, the reference clocks of the PPL1, PLL2, and DDS are guaranteed to be homologous and are all 19.2 MHz.
Big dipper interference signal filtering unit for draw 5G signal, channel estimation, 5G signal reduction and 5G interference signal and get rid of, reduce big dipper signal, its processing procedure as follows:
1) the input and output ends of the DSP are connected with the input and output ends of the FPGA through a PCIe interface; the input and output ends of the DSP are respectively connected with the input and output ends of a first DDR3 and a second DDR 3; the input and output ends of the FPGA are respectively connected with the input and output ends of a first DDR3 and a second DDR 3;
2) the FPGA stores ADC sampled data in a first DDR3, the DSP extracts a digital baseband signal from the first DDR3, the DSP performs parallel processing on the baseband data by using the DSP multi-processing kernel, 5G signal extraction and restoration are guaranteed to be performed at low delay, the baseband data is stored in a second DDR3 designated address, and after the FPGA performs 5G signal elimination, the digital-to-analog conversion is performed on the DAC of the signal generation unit.
3) In the data processing process, the FPGA stores the data sampled by the ADC in the designated address of the second DDR3, the DSP processes the baseband data and stores the baseband data in the designated address of the first DDR3, and the FPGA processes the baseband data and then sends the baseband data to the DAC.
As shown in fig. 4, the signal generating unit is configured to convert the interference-removed beidou signal into an analog signal and send the analog signal to the beidou receiver, and a processing process of the signal generating unit is as follows:
1) the input end of the broadband modulator is connected with the output end of a DAC (analog-to-digital converter), the input end of the DAC (analog-to-digital converter) is connected with the input end of a DDS clock, and the DDS provides a sampling clock of 491.52 MHz.
2) The output end of the broadband modulator is connected with the input end of the mixer through a 20dB intermediate frequency amplifier and an intermediate frequency band-pass filter with 1070MHz passband 100 MHz; the output end of the PLL3 (phase-locked loop) is connected with the input end of the broadband modulator; the output frequency of the PLL3 is 1070 MHz;
3) the mixer input is connected to the PLL4 (phase locked loop) output; wherein the output frequency of the PLL4 is the signal final output frequency RF1+1070 MHz;
4) the output end of the mixer is connected with the output end through the forgiveness amplifier and the first-level low-pass filtering; the two-stage amplification is to compensate for the signal loss caused by the mixer, and the low-pass filtering is to suppress the high-frequency components of the mixing.
The reference clocks of the PPL3, the PLL4 and the DDS are guaranteed to be homologous and are all 19.2 MHz.
By adopting the device for filtering the 5G signal interference aiming at the Beidou signal, the digital baseband data is quickly acquired by simplifying a receiving scheme, and the real-time processing of the data is realized by the ping-pong operation of the DSP, the FPGA and the two-stage DDR3, so that the real-time performance of the baseband data processing is realized and the possibility of data loss is avoided; the channel estimation algorithm through optimization ensures that the Beidou signals are restored without distortion while the 5G interference signals are removed.
In this specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (6)
1. The utility model provides a realize carrying out device of 5G signal interference filtering to big dipper signal, its characterized in that, the device include signal reception unit, big dipper interference signal filtering unit and signal generation unit, the output of signal reception unit be connected with big dipper interference signal filtering unit's input, big dipper interference signal filtering unit's output link to each other and be connected with signal generation unit's input, signal reception unit be used for acquireing big dipper and 5G compound digital baseband signal, big dipper interference signal filtering unit be used for drawing 5G signal, channel estimation, 5G signal reduction and 5G interference signal get rid of to restore big dipper signal, signal generation unit for convert the big dipper signal of interference removal into analog signal and send for big dipper receiver.
2. The device for realizing 5G signal interference filtering for Beidou signals according to claim 1, wherein the signal receiving unit comprises a first low noise amplifier, a band-pass filter, a second low noise amplifier, a mixer, a first phase-locked loop, an intermediate frequency amplifier, an intermediate frequency band-pass filter, a broadband demodulator, a second phase-locked loop, a digital-to-analog converter and a DDS clock; the first low-noise amplifier receives signals, the output end of the first low-noise amplifier is connected with the input end of the band-pass filter bank, the output end of the band-pass filter bank is connected with the frequency mixer through the second low-noise amplifier, the output end of the first phase-locked loop is connected with the input end of the frequency mixer, the output end of the frequency mixer is connected with the input end of the broadband demodulator through the intermediate frequency amplifier and the intermediate frequency band pass filter, the output end of the second phase-locked loop is connected with the input end of the broadband demodulator, the output end of the broadband demodulator is connected with the input end of the digital-to-analog converter, the input end of, the first low-noise amplifier is used for improving the receiving sensitivity and ensuring the normally received Beidou signals with smaller power, the band-pass filter bank is used for receiving signals without interference of channel stray and image frequency, and the second low-noise amplifier is used for compensating signal attenuation brought by the filter bank.
3. The device for realizing 5G signal interference filtering for Beidou signals according to claim 2, wherein reference clocks of the first phase-locked loop, the second phase-locked loop and the DDS clock are all 19.2 MHz.
4. The device for realizing 5G signal interference filtering for Beidou signals according to claim 1, wherein the Beidou interference signal filtering unit comprises a digital signal processor, an FPGA, a first DDR3 and a second DDR3, the input and output ends of the DSP are connected with the input and output ends of the FPGA through a PCIe interface, the input and output ends of the digital signal processor are respectively connected with the input and output ends of the first DDR3 and the second DDR3, the input and output ends of the FPGA are respectively connected with the input ends of the first DDR3 and the second DDR3,
the FPGA stores the sampling data in a first DDR3, the digital signal processor extracts a digital baseband signal from the first DDR3, the baseband data are processed in parallel by utilizing a plurality of processing cores of the digital signal processor, 5G signal extraction and GNSS signal restoration are carried out, the baseband data are stored in a designated address of a second DDR3, and the FPGA transmits the baseband data to the signal generating unit after 5G signal elimination; the FPGA also stores the sampled data in a designated address of the second DDR3, the digital signal processor processes the baseband data and stores the baseband data in the designated address of the first DDR3, and the baseband data are transmitted to the signal generating unit after being processed by the FPGA.
5. The device according to claim 1, wherein the signal generating unit comprises a second wideband modulator, a second analog-to-digital converter, a second DDS clock, an intermediate frequency band-pass filter, an intermediate frequency amplifier, a mixer, a third PLL, a fourth PLL, a two-stage amplifier and a one-stage low-pass filter, the input end of the second wideband modulator is connected to the output end of the second ADC, the input end of the second ADC is connected to the input end of the second DDS clock, the output end of the second wideband modulator is connected to the input end of the mixer through the intermediate frequency band-pass filter and the intermediate frequency amplifier, the output end of the third PLL is connected to the input end of the second wideband modulator, the input end of the mixer is connected to the output end of the fourth PLL, the output end of the mixer is connected to the output end through the two-stage amplifier and the one-stage low-pass filter, the two-stage amplifier is used for compensating signal loss brought by the mixer, and the low-pass filter is used for suppressing high-frequency components of the mixed frequency.
6. The apparatus according to claim 5, wherein the sampling clock of the second DDS clock is 491.52MHz, and the output frequency of the third phase-locked loop is 1070 MHz.
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