CN112821897B - Digital gain control and frequency conversion circuit - Google Patents
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Abstract
The invention discloses a digital gain control and frequency conversion circuit. The system comprises an intermediate frequency gain control module, a complex frequency conversion module, a channel filtering module and a channel gain control module; the intermediate frequency gain control module detects the signal power of the complex intermediate frequency signals, feeds back and controls the gain of an intermediate frequency channel and sends the gain to the controller; the complex frequency conversion module and the channel filtering module respectively carry out frequency conversion and filtering on the complex intermediate-frequency signals, down-convert the complex intermediate-frequency signals into complex baseband signals and carry out channel filtering; the channel gain control module performs channel gain control on the complex baseband signals to eliminate signal amplitude fluctuation caused by interference. The invention realizes the automatic gain control and frequency conversion processing of intermediate frequency digitization, can adapt to large dynamic range signal fluctuation, can also meet the channel gain and frequency conversion control of various carrier frequency signals, and has the advantages of strong universality and transportability.
Description
Technical Field
The invention relates to the technical field of wireless communication, in particular to a digital gain control and frequency conversion circuit.
Background
For receiving a satellite navigation wireless communication signal, a received radio frequency signal is usually demodulated after being analog-converted into an intermediate frequency signal or a baseband signal. However, the frequency conversion implementation manner of the analog channel usually occupies a large circuit volume, is greatly influenced by differences of analog devices, has low universality, and is not beneficial to implementation on a unified hardware platform.
For example, chinese patent CN107809258A, published 2018, 3, 16, an automatic gain control method and circuit for a wireless communication receiver. The wireless communication system uses continuous phase modulation, a radio frequency front-end module is of a low-intermediate frequency structure, an antenna receives an aerial wireless signal, and after a mixed signal in-phase branch and a quadrature branch pass through a multi-phase wave filter, one signal in the in-phase branch or the quadrature branch is discarded; and the other path of signal is input to a digital receiver after passing through a programmable gain amplifier and an analog-to-digital converter. The automatic gain control method of a digital receiver includes two steps. Firstly, detecting saturation according to a single-path input signal; secondly, according to the relation between the absolute value of the input signal and the power of the input signal, the strength of the input signal is calculated and the gain of the radio frequency channel is adjusted. Compared with the traditional two-path input automatic gain control circuit, the input of the automatic gain control circuit is only one path of signal, a programmable gain amplifier, an analog-to-digital converter and a compensation circuit which is not matched between an in-phase branch and an orthogonal path are omitted, and the design, the area and the power consumption of the radio frequency front-end module are simplified. The problem of universality is not considered, and the function of integrating digital frequency conversion and channel gain control is lacked.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the prior frequency conversion circuit is lack of integration of digital frequency conversion and channel gain control, and has poor universality. A digital gain control and frequency conversion circuit capable of realizing integration of digital frequency conversion and channel gain control is provided.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows: a kind of digitized gain control and frequency conversion circuit, including intermediate frequency gain control module, complex frequency conversion module, channel filter module and channel gain control module; the intermediate frequency gain control module inputs two paths of complex intermediate frequency signals after AD sampling, detects signal power and outputs a digitalized intermediate frequency channel gain control signal to control the gain of an intermediate frequency channel in a feedback manner, and simultaneously sends the intermediate frequency channel gain control signal to the controller; the complex frequency conversion module and the channel filtering module respectively carry out frequency conversion and filtering on the two paths of complex intermediate-frequency signals subjected to AD sampling, down-convert the complex intermediate-frequency signals into complex baseband signals and carry out channel filtering, and filter signals in a blank frequency band to prevent interference; the channel gain control module performs channel gain control on the complex baseband signals output by the channel filtering module, eliminates signal amplitude fluctuation caused by interference, further outputs the complex baseband signals subjected to the channel gain control, and sends channel gain control information to the controller. A digital gain control and frequency conversion circuit comprises an intermediate frequency gain control module, a complex frequency conversion module, a channel filtering module and a channel gain control module, wherein the intermediate frequency gain control module is used for detecting the signal power of complex intermediate frequency signals and feeding back and controlling the intermediate frequency channel gain to a controller, the complex frequency conversion module is used for carrying out frequency conversion on the complex intermediate frequency signals, the channel filtering module is used for filtering the complex intermediate frequency signals, and the channel gain control module is used for eliminating the influence of interference on the signal amplitude.
Preferably, in the intermediate frequency gain control module, after two paths of complex intermediate frequency signals subjected to AD sampling are respectively input into the corresponding I-path truncating register and Q-path truncating register, both of the complex intermediate frequency signals only output part of high bits to the square addition operation circuit; the two paths of signals respectively correspond to an I path of overrun register and a Q path of overrun register and respectively correspond to an I path of overrun mark and a Q path of overrun mark which are output to a square addition operation circuit; the result of the operation in the square addition operation circuit is subtracted from the first reference value, and the result is input into the accumulation circuit; the accumulated result of the accumulation circuit is used as an intermediate frequency channel gain control signal, on one hand, the accumulated result is sent to a serial DA (digital-to-analog) converter to control the intermediate frequency channel amplification gain after passing through a time sequence adaptation circuit, and on the other hand, the accumulated result is sent to a controller to control and monitor the intermediate frequency gain. The intermediate frequency gain control module comprises a square addition operation unit, an accumulation unit and a time sequence adaptation unit, wherein an I path truncation register and a Q path truncation register which receive complex intermediate frequency signals after AD sampling output high bits to the square addition operation unit, the corresponding I path overrun register and Q path overrun register output an I path overrun identifier and a Q path overrun identifier to the square addition operation unit, the square addition operation unit outputs operation results to the accumulation unit, and the accumulation unit respectively transmits the accumulation results to the time sequence adaptation unit and the controller.
Preferably, the square addition operation of the square addition operation circuit is:
the I _ cacu and the Q _ cacu are respectively corresponding to calculated values output to the square addition operation circuit by the I rounding register and the Q rounding register, and the symbol [ ] represents rounding and rounding.
Preferably, the intermediate frequency gain control module further comprises a control circuit for performing overflow protection on the accumulation circuit. The intermediate frequency gain control module also comprises a control unit for performing overflow protection on the accumulation unit.
Preferably, the complex frequency conversion module and the channel filtering module comprise a complex frequency converter, a numerically controlled oscillator, a phase-amplitude converter and a low-pass filter; the two paths of complex intermediate frequency signals after AD sampling are respectively input into a complex frequency converter, and are subjected to complex frequency conversion with a local carrier signal from a phase-amplitude converter, the phase-amplitude converter correspondingly converts a carrier phase value output by a numerical control oscillator into a carrier amplitude value, and then two paths of complex baseband signals after the complex frequency conversion are subjected to low-pass filtering through two low-pass filters and are output. The complex frequency conversion module comprises a complex frequency converter, a numerical control oscillator and a phase amplitude converter, wherein the numerical control oscillator outputs a carrier phase value to the phase amplitude converter, the phase amplitude converter outputs a carrier amplitude value converted from the carrier phase value to the complex frequency converter, and the complex frequency converter performs complex frequency conversion on a received complex intermediate frequency signal subjected to AD sampling and a local carrier signal of the phase amplitude converter. The channel filtering module comprises a low-pass filter for performing low-pass filtering on the complex baseband signals after the complex frequency conversion, and the low-pass filter is connected with the complex frequency converter. And the channel filtering module respectively performs low-pass filtering on the two paths of complex baseband signals after the complex frequency conversion through two low-pass filters and then outputs the complex baseband signals.
Preferably, the complex frequency conversion method correspondingly completed by the complex frequency conversion module is as follows: the input signal is
Wherein, I and Q respectively represent two paths of complex intermediate frequency signals, and the local oscillator signal is
Wherein C and S respectively represent two paths of local carrier signals with the same frequency and orthogonal phase output by the phase-amplitude converter, and the output signal is
The output signal being an input signal
And local oscillator signal
And (4) performing complex multiplication, wherein one path of output is C.I-S.Q, and the other path of output is I.S + C.Q.
Preferably, the channel gain control module multiplies the two paths of complex baseband signals output by the channel filtering module by the amplitude coefficient output by the bit truncator respectively, the multiplied results are input to an automatic amplitude limiting and rounding bit truncating circuit, the two paths of results output by the circuit after amplitude limiting are further subjected to square summation, then the two paths of results are added with a second reference value and then accumulated by an accumulator, and the accumulated result of the accumulator is truncated and output by the bit truncator. The channel gain control module comprises an automatic amplitude limiting and rounding bit truncating unit, a bit truncator and an accumulator, wherein two paths of complex baseband signals output by the channel filtering module are multiplied by amplitude coefficients output by the bit truncator respectively and then output to the automatic amplitude limiting and rounding bit truncating unit, the automatic amplitude limiting and rounding bit truncating unit outputs an amplitude-limited result to the accumulator after squaring and adding with a second reference value, and the accumulator outputs an accumulation result to the bit truncator.
The substantial effects of the invention are as follows: the invention discloses a digital gain control and frequency conversion circuit. The device comprises an intermediate frequency gain control module, a complex frequency conversion module, a channel filtering module and a channel gain control module; the intermediate frequency gain control module detects the signal power of the complex intermediate frequency signals, feeds back and controls the gain of an intermediate frequency channel and sends the gain to the controller; the complex frequency conversion module and the channel filtering module respectively carry out frequency conversion and filtering on the complex intermediate frequency signals, and carry out down-conversion on the complex intermediate frequency signals into complex baseband signals and carry out channel filtering; the channel gain control module performs channel gain control on the complex baseband signals to eliminate signal amplitude fluctuation caused by interference. The invention realizes the automatic gain control and frequency conversion processing of intermediate frequency digitization, can adapt to large dynamic range signal fluctuation, can also meet the channel gain and frequency conversion control of various carrier frequency signals, and has the advantages of strong universality and transportability.
Drawings
Fig. 1 is a schematic composition diagram of the present embodiment.
Fig. 2 is a schematic diagram of a circuit composition of the if gain control module according to the present embodiment.
Fig. 3 is a graph showing the relationship between the if gain control according to the present embodiment.
Fig. 4 is a schematic circuit diagram of the complex frequency conversion module and the channel filtering module according to this embodiment.
Fig. 5 is a schematic diagram illustrating analysis of the phase quantization error and the amplitude quantization error in the present embodiment.
Fig. 6 is a schematic diagram of a circuit configuration of a channel gain control module according to the present embodiment.
Wherein: 1. the device comprises an intermediate frequency gain control module, a complex frequency conversion module, a channel filtering module, a channel gain control module, a square addition operation unit, an accumulation unit, a time sequence adaptation unit, a square addition operation unit, a control unit, a square addition operation unit, an automatic amplitude limiting and rounding unit and an automatic amplitude limiting and rounding unit, wherein the automatic amplitude limiting and rounding unit is 9.
Detailed Description
In order to facilitate an understanding of the invention, the invention is described in more detail below with reference to the accompanying drawings and specific examples. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It is to be noted that, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Fig. 1 is a flow chart of an embodiment of the digital gain control and frequency conversion circuit of the present invention. In fig. 1, the circuit includes an intermediate frequency gain control module 1MAGC, a complex frequency conversion module 2, a channel filtering module 3, and a channel gain control module 4 CAGC; the intermediate frequency gain control module 1MAGC inputs two paths of complex intermediate frequency signals after AD sampling, including detection signal power. For power detection, the module comprises two paths of outputs, wherein one path of output is to output a digitized intermediate frequency channel gain control signal to control the gain of an intermediate frequency channel in a feedback manner, namely AGC control in fig. 1, and is used for controlling the gain of the intermediate frequency channel, and the AGC module mainly controls the gain of the intermediate frequency channel in a feedback manner after converting the intermediate frequency channel gain control signal into an analog voltage through a serial DA converter; and the other output is used for sending an intermediate frequency channel gain control signal to the controller MCU.
The complex frequency conversion module 2 and the channel filtering module 3 respectively carry out frequency conversion and filtering on the two paths of complex intermediate frequency signals subjected to AD sampling, down-convert the complex intermediate frequency signals into complex baseband signals and carry out channel filtering, and filter signals in a blank frequency band to prevent interference;
the channel gain control module 4CAGC performs channel gain control on the complex baseband signal output by the channel filtering module 3, eliminates signal amplitude fluctuation caused by interference, further outputs the complex baseband signal subjected to the channel gain control, and sends channel gain control information to the controller MCU.
Preferably, the complex if signal is a spread spectrum signal subjected to direct sequence spread spectrum, so the sampled data output by the if gain control module 1MAGC is further subjected to pseudo-random code (PN) correlation de-spreading and FFT conversion, and is subjected to FFT conversion and a modulus value square of the conversion result is sent to the controller MCU for spectrum output and interference signal monitoring, because there is an interference signal in the received signal, which needs to be detected.
Further, fig. 2 shows a preferred embodiment of the if gain control module 1MAGC, in this embodiment, two paths of AD-sampled complex if signals respectively correspond to an I path sample point signal (sample point _ I) and a Q path sample point signal (sample point _ Q), preferably, the two paths of sample point signals are both 10-bit signals, and after being respectively input to the corresponding I path truncating register and Q path truncating register, both of the two paths of sample point signals only output a part of high bits, for example, 4 bits high, to the square addition operation unit 5. In addition, the two paths of sampling point signals are respectively corresponding to an I path overrun register and a Q path overrun register, and respectively corresponding to and outputting an I path overrun mark and a Q path overrun mark, wherein the I path overrun mark and the Q path overrun mark are both 1bit, namely, after the value of an input sampling point signal is greater than a set threshold, the overrun mark outputs a corresponding mark, for example, when the value of the sampling point signal is less than the threshold, the overrun mark outputs 0 to indicate no overrun, and when the value of the sampling point signal is greater than or equal to the threshold, the overrun mark outputs 1 to indicate overrun.
Furthermore, the 4-bit signal value output by the I-path truncation register and the Q-path truncation register and the overrun identifier of the corresponding input 1bit are input into the square addition operation unit 5 for operation, the operation result is different from the first reference value, and the result is input into the accumulation unit 6.
Preferably, the bit number of the maximum accumulation result of the accumulation unit 6 is 36 bits, the accumulated high 8-bit accumulation result is output as an intermediate frequency channel gain control signal, on one hand, the intermediate frequency channel gain control signal is sent to the sequential adaptation unit 7 and then converted into an analog voltage through a serial DA to control the intermediate frequency channel amplification gain, so as to realize the AGC function of the intermediate frequency channel, and on the other hand, the intermediate frequency channel gain control signal is sent to the controller MCU to perform intermediate frequency gain control monitoring.
Preferably, the operation method of the square addition operation unit 5 includes: the input address is respectively an I-way input overrun identifier I _ DOR, an I-way sampling point I _ smp (3:0), a Q-way input overrun identifier Q _ DOR and a Q-way sampling point Q _ smp (3:0) from the most significant bit MSB to the least significant bit LSB. The I path and the Q path have the same operation rule, and any path meets the following table, wherein X represents I or Q.
TABLE 1 squaring addition operation Unit operation Table
Outputting the data
Here, the decimal obtained by calculating the sum of squares of the outputs from the input data, multiplied by 32, can be expressed as an integer, where the symbol [ 2 ], [ herein]Indicating rounding, I, Q the sample values of the two inputs are 4 bits each.
Further, the output data of the square addition operation unit 5 has 18 bits, and the following table shows from the most significant bit MSB to the least significant bit LSB:
TABLE 2 squaring addition Unit output data Table
| Bit17 | Bit16 | Bit15 | Bit14 | Bit13 | Bit12 | Bit11～Bit0 |
| I_dt(2) | I_dt(1) | I_dt(0) | Q_dt(2) | Q_dt(1) | Q_dt(0) | Sqr_add(11:0) |
It can be seen that the high 6 bits output by the square addition operation unit 5 correspond to the 3-bit I-path signals I _ dt (2), I _ dt (1), I _ dt (0), and the 3-bit Q-path signals Q _ dt (2), Q _ dt (1), Q _ dt (0), respectively. The input data of 10 bits in the I path and Q path is changed into data of 3 bits in the I path and Q path, so that the effect of compressing data bits and calculating the amplitude of the input signal is realized.
Preferably, the first reference value in fig. 2 is determined by assuming that the input signal is dominated by gaussian noise, the output noise σ is 2.333 and the total power is
Thus, the reference value ref is 32 × p 348, and is denoted by 15C in 16.
Further, fig. 2 also includes a control unit 8 for performing overflow protection on the accumulation unit 6: when the high 4 bits output by the accumulation unit 6 are all 1, the input accumulation amount is accumulated only when the input accumulation amount is a negative value; when the output of the accumulation unit 6 is 0 at 8 high bits, the input accumulation amount is accumulated only if the input accumulation amount is a positive value. That is, the effect that the amplification value will not be increased when it is maximized and will not be decreased when it is minimized can be achieved by the control unit 8.
Further, fig. 3 shows the measured input complex if signal power versus the MAGC control value, where the abscissa x is the 16-ary reading of the MAGC output to the controller, and the ordinate y represents the input complex if signal power dBm, where the test points exhibit linear characteristics in the range of-65 dBm to-15 dBm and satisfy the relationship:
y＝0.4362×x-102.25
102.25 is the first reference value selected.
Further, fig. 4 shows a preferred embodiment of the complex frequency conversion module 2 and the channel filtering module 3, in which the preferred embodiment includes a complex frequency converter, a numerically controlled oscillator NCO, a phase-amplitude converter and a low-pass filter LPF, wherein two complex intermediate frequency signals smp _ I and smp _ Q after AD sampling are respectively input to the complex frequency converter, and are subjected to complex frequency conversion with a local carrier signal from the phase-amplitude converter, and the phase-amplitude converter is used for correspondingly converting a carrier phase value output by the numerically controlled oscillator into a carrier amplitude value, and then respectively performing low-pass filtering on the two complex baseband signals after complex frequency conversion through the two low-pass filters and outputting the complex baseband signals.
Preferably, the phase data input by the NCO shown in fig. 4 for the amplitude converter is represented by 11 bits, and the amplitude data output after the phase-to-amplitude conversion by the amplitude converter is represented by 9 bits, in order to reduce the data amount and balance the phase quantization error and the amplitude quantization error. As shown in fig. 5, NCO is usually implemented by table look-up to generate an oscillating sine wave signal, i.e. dividing a cycle of the sine wave signal into a plurality of different phases, if the division is finer, the number of correspondingly selected phases is larger, and the quantization error of the corresponding phases is smaller. In fig. 5, the smaller the interval between the first phase XW1 and the second phase XW2, the smaller the quantization error of the selected phases, and the denser the corresponding phases, which when expressed by 11 bits, is equivalent to dividing a sinusoidal cycle into 211 different phase points, where the interval between any two phase points is 2/211. It is obvious that the larger the quantization bit number, the smaller the error, but the larger the data amount. Further, for each selected phase point, it needs to be further converted into an amplitude value corresponding to the phase, for example, the amplitude value FZ1 corresponding to the first phase XW1 and the amplitude value FZ2 corresponding to the second phase XW1 in fig. 5 also have a quantization precision problem for the amplitude value, and if the amplitude quantization error is small, the number of amplitude quantization bits needs to be larger, and conversely, the number of amplitude quantization bits is smaller. As shown in fig. 5, if the selection of the quantization error of the phase is relatively small in the horizontal axis, that is, the number of quantization bits of the phase is relatively large, but the selection of the quantization error of the amplitude is relatively large in the vertical axis, that is, the number of quantization bits of the amplitude is relatively small, the discrimination of the amplitude values corresponding to different phases is not obvious, or the quantization error of the amplitude values is relatively large, so that the overall error of the output digitized sine wave is relatively large. Similarly, if the selection of the quantization error of the phase in the horizontal axis is relatively large, that is, the number of quantization bits of the phase is relatively small, the number of selectable phases is relatively small, and even if the selection of the quantization error of the amplitude in the vertical axis is relatively small, that is, the number of quantization bits of the amplitude is relatively large, the overall error of the output digitized sine wave is relatively large. Therefore, the selection of the phase quantization bit number and the selection of the amplitude quantization bit number are close to or balanced with each other, and the data amount is not too large, otherwise, the consumption of hardware resources is large. The phase data is 11 bits, the amplitude data is 9 bits, and the phase data and the amplitude data are different by 2 bits to respectively indicate that the phase data and the amplitude data are relatively balanced. Otherwise, if the phase data is 11 bits and the amplitude data is 4 bits, it is obvious that there is a gap, which results in a large overall quantization error.
Therefore, the amplitude data output by the phase-amplitude converter is 9 bits, so that the error adaptation can be better carried out on the phase data, the data size is reduced, the consumption of hardware resources by calculation is saved, the amplitude data is 9 bits and is also adapted to the sampling point data 10 bits entering the complex frequency converter, and the large frequency conversion error cannot be introduced.
Preferably, the complex frequency conversion method correspondingly completed by the complex frequency conversion module 2 is as follows: the input signals are:
wherein I and Q respectively represent two paths of complex intermediate frequency signals smp _ I and smp _ Q, and the local oscillator signal is
Wherein C and S respectively represent two paths of local carrier signals with the same frequency and orthogonal phase output by the phase-amplitude converter, and the output signal is
The output signal is the input signal
And local oscillator signal
And (4) performing complex multiplication, wherein one path of output is C.I-S.Q, and the other path of output is I.S + C.Q.
The numerically controlled oscillator NCO can be selectively set according to different main clocks and carriers, and if the system clock is f mclk The complex frequency converter has a phase accumulation word length of 28 bits and a frequency resolution of f mclk /2 28 . Carrier frequency configuration word of
If f is mclk At 80MHz, the frequency resolution is 0.298 Hz. If the carrier frequency is 6.602M, the corresponding frequency allocation word is M if 0x152,05 BC. In addition, the bandwidth of the low-pass filter can be selected and designed according to actual needs, so that out-of-band interference signals can be suppressed. Therefore, the digitalized complex frequency conversion module 2 and the channel filtering module 3 have strong universality and application flexibility, and corresponding design parameters can be reasonably selected according to conditions such as carrier waves, bandwidth and the like of communication signals, so that the method is suitable for various application requirements.
Further, fig. 6 shows a preferred embodiment of the channel gain control module 4CAGC, in which the reason for setting the channel gain control module 4CAGC is that the amplitude of the output signal of the channel filtering module 3 is fluctuated in the presence of out-of-band interference and no out-of-band interference, and the CAGC control is required to stabilize the fluctuation. Specifically, the module comprises two paths of complex baseband signals in _ I and in _ Q output by a channel filtering module 3, which are respectively multiplied by amplitude coefficients output by a bit truncator, the multiplied results are input to an automatic amplitude limiting and rounding bit truncating unit 9, the circuit outputs two paths of output results Out _ I and Out _ Q of 3 bits after amplitude limiting, the two results are further summed up by squares, the sum is added with a second reference value and then accumulated by an accumulator, and the accumulated result of the accumulator is truncated and output by the bit truncator.
Therefore, the invention discloses a digital gain control and frequency conversion circuit. The device comprises an intermediate frequency gain control module 1, a complex frequency conversion module 2, a channel filtering module 3 and a channel gain control module 4; the intermediate frequency gain control module 1 detects the signal power of the complex intermediate frequency signals, feeds back and controls the gain of an intermediate frequency channel and sends the gain to the controller; the complex frequency conversion module 2 and the channel filtering module 3 respectively carry out frequency conversion and filtering on the complex intermediate frequency signals, and carry out down-conversion on the complex intermediate frequency signals into complex baseband signals and carry out channel filtering; the channel gain control module 4 performs channel gain control on the complex baseband signals to eliminate signal amplitude fluctuation caused by interference. The invention realizes the automatic gain control and frequency conversion processing of intermediate frequency digitization, can adapt to large dynamic range signal fluctuation, can also meet the channel gain and frequency conversion control of various carrier frequency signals, and has the advantages of strong universality and transportability.
The above description is only an embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent structural changes made by using the contents of the present specification and the drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (6)
1. A digital gain control and frequency conversion circuit is characterized by comprising an intermediate frequency gain control module (1), a complex frequency conversion module (2), a channel filtering module (3) and a channel gain control module (4); the intermediate frequency gain control module (1) inputs two paths of complex intermediate frequency signals after AD sampling, detects signal power and outputs a digitized intermediate frequency channel gain control signal to control the gain of an intermediate frequency channel in a feedback manner, and simultaneously sends the intermediate frequency channel gain control signal to the controller; the complex frequency conversion module (2) and the channel filtering module (3) respectively carry out frequency conversion and filtering on the two paths of complex intermediate frequency signals subjected to AD sampling, down-convert the complex intermediate frequency signals into complex baseband signals and carry out channel filtering, and filter signals in a blank frequency band to prevent interference; the channel gain control module (4) performs channel gain control on the complex baseband signals output by the channel filtering module (3), eliminates signal amplitude fluctuation caused by interference, further outputs the complex baseband signals subjected to the channel gain control, and sends channel gain control information to the controller;
in the intermediate frequency gain control module (1), after two paths of complex intermediate frequency signals subjected to AD sampling are respectively input into corresponding I-path truncation registers and Q-path truncation registers, the two paths of complex intermediate frequency signals only output partial high bits to a square addition operation unit (5); the two paths of signals are respectively corresponding to an I path of overrun register and a Q path of overrun register and respectively output an I path of overrun mark and a Q path of overrun mark to a square addition operation unit (5); the result of the operation in the square addition operation unit (5) is subtracted from the first reference value, and the result is input into the accumulation unit (6); the accumulated result of the accumulation unit (6) is used as an intermediate frequency channel gain control signal, on one hand, the signal is sent to the time sequence adaptation unit (7) and then is converted into analog voltage through a serial DA to control the intermediate frequency channel amplification gain, and on the other hand, the signal is sent to the controller to control and monitor the intermediate frequency gain.
2. A digital gain control and frequency conversion circuit according to claim 1, characterized in that the square addition operation of the square addition operation unit (5) is:
wherein, I _ cacu and Q _ cacu are respectively corresponding to the calculated values output to the square addition operation unit (5) by the I rounding register and the Q rounding register, and the symbol [ ] represents rounding and rounding.
3. The digital gain control and frequency conversion circuit according to claim 2, further comprising a control unit (8) for performing overflow protection on the accumulation unit (6) in the if gain control module (1).
4. A digital gain control and frequency conversion circuit according to claim 1 or 3, characterized in that the complex frequency conversion module (2) and the channel filtering module (3) comprise a complex frequency converter, a numerically controlled oscillator, a phase-amplitude converter and a low-pass filter; the two paths of complex intermediate frequency signals after AD sampling are respectively input into a complex frequency converter, and are subjected to complex frequency conversion with a local carrier signal from a phase-amplitude converter, the phase-amplitude converter correspondingly converts a carrier phase value output by a numerical control oscillator into a carrier amplitude value, and then two paths of complex baseband signals after the complex frequency conversion are subjected to low-pass filtering through two low-pass filters and are output.
5. The digital gain control and frequency conversion circuit according to claim 4, wherein the complex frequency conversion module (2) performs the complex frequency conversion method by: the input signal is
Wherein, I and Q respectively represent two paths of complex intermediate frequency signals, and the local oscillator signal is
Wherein C and S respectively represent two paths of local carrier signals with the same frequency and orthogonal phase output by the phase-amplitude converter, and the output signal is
The output signal being an input signal
And local oscillator signal
And (4) performing complex multiplication, wherein one path of output is C.I-S.Q, and the other path of output is I.S + C.Q.
6. A digital gain control and frequency conversion circuit according to claim 1 or 5, characterized in that the channel gain control module (4) comprises two paths of complex baseband signals output from the channel filtering module (3) are respectively multiplied by the amplitude coefficient output by the bit truncator, the multiplied result is input to the automatic amplitude limiting and rounding bit truncating unit (9), the two paths of results output by the circuit after amplitude limiting are further summed up by square, then are added with the second reference value and are accumulated by the accumulator, and the accumulated result of the accumulator is truncated and output by the bit truncator.
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| CN107919881B (en) * | 2017-12-27 | 2019-03-01 | 中国人民解放军陆军工程大学 | A kind of automatic growth control receiver |
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