CN112820828B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
- Publication number
- CN112820828B CN112820828B CN201911120346.4A CN201911120346A CN112820828B CN 112820828 B CN112820828 B CN 112820828B CN 201911120346 A CN201911120346 A CN 201911120346A CN 112820828 B CN112820828 B CN 112820828B
- Authority
- CN
- China
- Prior art keywords
- layer
- conductive pattern
- conductive
- silicon
- conductive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
Abstract
The present invention provides a semiconductor device including: a substrate; a conductive pattern extending upward from the substrate, the conductive pattern having a hollow structure; a first conductive layer covering the conductive pattern; and a dielectric layer covering at least the first conductive layer.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a capacitor having a lower electrode with a multi-layered electrical structure and a method for manufacturing the same.
Background
As the size of semiconductor devices continues to shrink, the capacitance of the memory is limited due to the structure of the capacitor. In a metal-insulator-metal (MIM) structure, the limited effective area of the lower electrode reduces the efficiency of the memory device.
Disclosure of Invention
In view of this, it is necessary to provide a capacitor with an increased effective area and a method of manufacturing the same.
The present invention provides a semiconductor device including: a substrate; a conductive pattern extending upward from the substrate, the conductive pattern having a hollow structure; a first conductive layer covering the conductive pattern; and a dielectric layer covering at least the first conductive layer.
In some embodiments of the present invention, the conductive pattern is electrically connected to the contact region of the substrate and the conductive pattern comprises titanium nitride, titanium silicon nitride, tungsten nitride or a compound of a material selected from titanium, tungsten, oxygen, nitrogen and silicon.
In some embodiments of the present invention, the semiconductor device further includes an etch stop layer formed on the substrate and contacting the conductive pattern, wherein the etch stop layer comprises a material selected from the group consisting of silicon nitride, silicon boron nitride, silicon carbon nitride, silicon carbide, silicon oxynitride, and silicon oxycarbide
In some embodiments of the present invention, the semiconductor device further comprises a second conductive layer covering the dielectric layer, wherein the conductive layer comprises a compound selected from titanium nitride, titanium aluminum silicon nitride, tungsten nitride, or a material selected from titanium, tungsten, oxygen, nitrogen, and silicon.
In some embodiments of the invention, the first conductive layer comprises tungsten, tungsten nitride, a material with tungsten, or a material with nitrogen.
In some embodiments of the present invention, the conductive pattern has a thickness of 150 a or less and the first conductive layer has a thickness of 50 a or less.
In some embodiments of the present invention, the combination of the conductive pattern and the first conductive layer is used as a lower electrode of a capacitor in a dynamic random access memory, the effective value of the lower electrode is less than or equal to 20 nanometers, and the resistivity of the lower electrode is less than or equal to 150 micro-ohm-cm.
The present invention also provides a method of manufacturing a semiconductor device, the method comprising: providing a conductive pattern extending upward from a substrate, the conductive pattern having a hollow structure; forming a first conductive layer covering the conductive pattern; and forming a dielectric layer at least covering the first conductive layer
In some embodiments of the invention, the providing a conductive pattern extending upward from the substrate includes: forming an etch stop layer on the substrate; forming a sacrificial layer on the etch stop layer; forming a hole penetrating the sacrificial layer and the etching stop layer; forming the conductive layer in the hole; and removing the sacrificial layer with a wet etching process.
In some embodiments of the invention, the forming a first conductive layer overlying the conductive pattern includes selectively depositing the first conductive layer on the conductive pattern with a selective deposition process including atomic layer deposition, chemical vapor deposition, or continuous flow deposition.
Drawings
Fig. 1 to 4 are schematic views of a method of manufacturing a conductive pattern protruding from a semiconductor device according to an embodiment of the present invention.
Fig. 5 to 6 are schematic views of a method of manufacturing a capacitor having a lower electrode of a multi-layered structure in a semiconductor device according to an embodiment of the present invention.
Description of the main reference signs
Semiconductor device 100
Substrate 110
Dielectric region 111
Contact region 112
Etch stop layer 120
Sacrificial layer 131
Hole 140
Conductive pattern 160
First conductive layer 161
Dielectric layer 162
Second conductive layer 163
The invention will be further described in the following detailed description in conjunction with the above-described figures.
Detailed Description
The technical scheme of the present invention will be clearly and completely described below with reference to specific embodiments and drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, are intended to fall within the scope of the present invention. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
In the description of embodiments of the present invention, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," etc. indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of embodiments of the present invention and to simplify description, and do not indicate or imply that the devices or components referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting embodiments of the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless explicitly defined otherwise.
Referring to fig. 1 to 4, an embodiment of the present invention provides a method of manufacturing a conductive pattern protruding from a semiconductor device 100. In this embodiment, as shown in fig. 1, the semiconductor device 100 includes a substrate 110, an etching stop layer 120 formed on the substrate, and a sacrificial layer 131 formed on the etching stop layer 120. The semiconductor device 100 may be a Dynamic Random Access Memory (DRAM). The substrate 110 includes a dielectric region 111 and a contact region 112. The dielectric region 111 may be made of a dielectric material, such as silicon nitride (SiN). The contact region 112 may be made of a metallic material, such as tungsten (W), titanium (Ti), or tantalum (Ta). In some embodiments, the substrate 110 is a silicon wafer.
In some embodiments, the etch stop layer 120 may include a material selected from silicon nitride (SiN), silicon boron nitride (SiBN), silicon carbon nitride (SiCN), silicon carbide (SiC), silicon oxynitride (SiON), or silicon oxycarbide (SiOC). The sacrificial layer 131 may be made of a silicon oxide substrate, such as silicon oxide (SiOx), plasma Enhanced Oxide (PEOX), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), tetraethoxysilane (TEOS), borotetraethoxysilane (BTEOS), inorganic siloxane (PTEOS), or silicon oxide impregnated with boron and phosphorus impurities (BPTEOS).
As shown in fig. 2, a hole 140 is formed through the sacrificial layer 131 and the etching stop layer 120 by an etching process to expose the substrate 110. For example, a dry etching process, such as a plasma etching process, an Inductively Coupled Plasma (ICP) process, a pressure swing coupled plasma (TCP) process, or a Reactive Ion Etching (RIE), may be used. Next, the conductive pattern 160 is formed on the sacrificial layer 131 in a deposition process including Atomic Layer Deposition (ALD), plasma-assisted atomic layer deposition (PAALD), chemical Vapor Deposition (CVD), plasma Enhanced Chemical Vapor Deposition (PECVD), low Pressure Chemical Vapor Deposition (LPCVD), high density plasma chemical vapor deposition (HDP-CVD), spin coating, sputtering, etc. The conductive pattern 160 covers the surface of the hole 140 and the top of the sacrificial layer 131. The conductive pattern 160 may be made of metal, such as titanium nitride (TiN), titanium aluminum silicon nitride (TiSiN), tungsten nitride (WN), or a compound of materials selected from titanium, tungsten, oxygen, nitrogen, and silicon. In one embodiment, the conductive pattern 160 is electrically connected to the conductive region 112.
As shown in fig. 3, a portion of the conductive pattern 160 is removed to expose the upper surface of the sacrificial layer 131 with a planarization process including deep etching (etch-back) or Chemical Mechanical Polishing (CMP). As shown in fig. 4, the sacrificial layer 131 is removed using a wet etch.
Referring to fig. 5 to 6, an embodiment of the present invention provides a method for manufacturing a capacitor having a lower electrode with a multi-layered structure in a semiconductor device 100. In this embodiment, as shown in fig. 5, the first conductive layer 161 is formed to cover the conductive pattern 160 in a deposition process including Atomic Layer Deposition (ALD), chemical Vapor Deposition (CVD), or continuous flow deposition (SFD). For example, the first conductive layer 161 is selectively deposited on the exposed surface of the conductive pattern 160. In some embodiments, the conductive pattern 160 has a hollow cylindrical structure extending vertically upward from the substrate 110. The first conductive layer 161 covers the surface of the hollow cylindrical structure, including a bottom region, an inner sidewall, a top region, and a region where the outer sidewall is sub-exposed. In some examples, the first conductive layer 161 may be in contact with the etch stop layer 120. In some embodiments, the first conductive layer 161 includes tungsten, tungsten nitride, a material having tungsten, or a material having nitrogen.
As shown in fig. 6, a dielectric layer 162 is formed to cover the first conductive layer 161 and the etch stop layer 120. Next, a second conductive layer 163 is formed to cover the dielectric layer 162. The dielectric layer 162 includes an oxide such as ZrxOy, hfxOy, taxOy, zrHfSiOx, tixOy, laxOy, alxOy, hfxSiyOz or ZrxSiyOz. The second conductive layer 163 may include titanium nitride (TiN), titanium aluminum silicon nitride (TiSiN), tungsten nitride (WN), or a compound of a material selected from titanium, tungsten, oxygen, nitrogen, and silicon.
In some embodiments, the conductive pattern 160 has a thickness of 150 a or less, and the first conductive layer 161 has a thickness of 50 a or less. The combination of the conductive pattern 160 and the first conductive layer 161 serves as a lower electrode of a capacitor in a Dynamic Random Access Memory (DRAM), the effective value (RMS) of the lower electrode is 20 nanometers (nm) or less, and the resistivity of the lower electrode is 150 micro-ohm-cm or less.
It is to be understood that the above examples are illustrative of the present invention and are not to be construed as limiting the invention. Various other corresponding changes and modifications made in accordance with the technical idea of the present invention will fall within the scope of the claims of the present invention for those of ordinary skill in the art.
Claims (7)
1. A semiconductor device, comprising:
a substrate;
a conductive pattern extending vertically upward from the substrate, the conductive pattern having a hollow cylindrical structure, the conductive pattern including a compound composed of titanium, tungsten, oxygen, nitrogen, and silicon, the conductive pattern having a thickness of 150 angstroms or less;
a first conductive layer covering the bottom region, the inner sidewall, the top region and the sub-exposed region of the outer sidewall of the conductive pattern, wherein the thickness of the first conductive layer is less than or equal to 50 angstroms;
a dielectric layer covering at least the first conductive layer; and
and a second conductive layer covering the dielectric layer, the combination of the conductive pattern and the first conductive layer serving as a lower electrode of a capacitor in a Dynamic Random Access Memory (DRAM).
2. The semiconductor device according to claim 1, further comprising an etch stop layer formed on the substrate and contacting the conductive pattern, the etch stop layer comprising a material selected from the group consisting of silicon nitride (SiN), silicon boron nitride (SiBN), silicon carbon nitride (SiCN), silicon carbide (SiC), silicon oxynitride (SiON), and silicon oxycarbide (SiOC).
3. The semiconductor device according to claim 1, wherein the second conductive layer comprises a compound of a material selected from titanium, tungsten, oxygen, nitrogen, and silicon.
4. The semiconductor device according to claim 1, wherein the first conductive layer comprises a material having tungsten or a material having nitrogen.
5. The semiconductor device according to claim 1, wherein a resistivity of the lower electrode is 150 μΩ -cm or less.
6. A method of manufacturing a semiconductor device, the method comprising:
forming an etch stop layer on a substrate;
forming a sacrificial layer on the etch stop layer;
forming a hole penetrating the sacrificial layer and the etching stop layer;
forming a conductive pattern extending vertically upward from the substrate in the hole, the conductive pattern having a hollow cylindrical structure, the conductive pattern including a compound composed of titanium, tungsten, oxygen, nitrogen, and silicon, the conductive pattern having a thickness of 150 angstroms or less;
removing a portion of the conductive pattern to expose an upper surface of the sacrificial layer;
removing the sacrificial layer by a wet etching process;
forming a first conductive layer covering the bottom region, the inner side wall, the top region and the sub-exposed region of the outer side wall of the conductive pattern, wherein the thickness of the first conductive layer is less than or equal to 50 angstroms;
forming a dielectric layer at least covering the first conductive layer; and
a second conductive layer is formed overlying the dielectric layer, the combination of the conductive pattern and the first conductive layer acting as a bottom electrode of a capacitor in a Dynamic Random Access Memory (DRAM).
7. The method of claim 6, wherein the first conductive layer is selectively deposited on the conductive pattern in a selective deposition process comprising atomic layer deposition, chemical vapor deposition, or continuous flow deposition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911120346.4A CN112820828B (en) | 2019-11-15 | 2019-11-15 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911120346.4A CN112820828B (en) | 2019-11-15 | 2019-11-15 | Semiconductor device and method for manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112820828A CN112820828A (en) | 2021-05-18 |
| CN112820828B true CN112820828B (en) | 2023-08-04 |
Family
ID=75851616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911120346.4A Active CN112820828B (en) | 2019-11-15 | 2019-11-15 | Semiconductor device and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112820828B (en) |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19914905A1 (en) * | 1999-04-01 | 2000-10-05 | Bosch Gmbh Robert | Electrochemical etching cell for etching silicon wafers uses electrode materials that do not contaminate and/or damage the etching body after etching |
| KR100630666B1 (en) * | 2000-08-09 | 2006-10-02 | 삼성전자주식회사 | Method of manufacturing semiconductor device including metal contact and capacitor |
| KR100553839B1 (en) * | 2003-11-27 | 2006-02-24 | 삼성전자주식회사 | Capacitor, Method for manufacturing the capacitor, Semiconductor device including the capacitor, and Method for manufacturing the semiconductor device |
| KR100558010B1 (en) * | 2004-04-14 | 2006-03-06 | 삼성전자주식회사 | capacitor device having metal electrode and fabrication method thereof |
| KR100587686B1 (en) * | 2004-07-15 | 2006-06-08 | 삼성전자주식회사 | Method for forming TiN and method for manufacturing capacitor used the same |
| KR100589078B1 (en) * | 2004-11-29 | 2006-06-12 | 삼성전자주식회사 | Method for manufacturing of capacitor and DRAM device having the same |
| KR100712502B1 (en) * | 2004-11-30 | 2007-05-02 | 삼성전자주식회사 | Metal-Insulator-Metal capacitor and method for manufacturing the same |
| KR100703965B1 (en) * | 2004-12-31 | 2007-04-05 | 삼성전자주식회사 | Fabrication method of semiconductor device capacitor having dielectric barrier layer and semiconductor device capacitor fabricated thereby |
| KR100653713B1 (en) * | 2005-02-21 | 2006-12-05 | 삼성전자주식회사 | semiconductor device having cylinder storage nodes and fabrication methods thereof |
| KR100650632B1 (en) * | 2005-11-10 | 2006-11-27 | 삼성전자주식회사 | Method for manufacturing a capacitor and method for manufacturing a semiconductor device using the same |
| KR100673015B1 (en) * | 2005-11-14 | 2007-01-24 | 삼성전자주식회사 | Semiconductor device having capacitor and method of forming the same |
| TWI306306B (en) * | 2006-08-25 | 2009-02-11 | Promos Technologies Inc | Capacitor structure and method for preparing the same |
| TWI440140B (en) * | 2011-01-31 | 2014-06-01 | Inotera Memories Inc | Capacitor structure and fabrication method thereof |
-
2019
- 2019-11-15 CN CN201911120346.4A patent/CN112820828B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN112820828A (en) | 2021-05-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11751377B2 (en) | Semiconductor device and method fabricating the same | |
| US7285813B2 (en) | Metal-insulator-metal capacitor and method for manufacturing the same | |
| US6259127B1 (en) | Integrated circuit container having partially rugged surface | |
| US5946567A (en) | Method for making metal capacitors for deep submicrometer processes for semiconductor integrated circuits | |
| JPH10163453A (en) | Manufacture of stack capacitor | |
| US20050082592A1 (en) | Compact capacitor structure having high unit capacitance | |
| US20020167090A1 (en) | Dual damascene structure having capacitors | |
| US11659706B2 (en) | Semiconductor device and method for fabricating the same | |
| US20030197215A1 (en) | A dual stacked metal-insulator-metal capacitor and method for making same | |
| CN112820828B (en) | Semiconductor device and method for manufacturing the same | |
| US6153901A (en) | Integrated circuit capacitor including anchored plug | |
| US11302774B2 (en) | Semiconductor device and method fabricating the same | |
| US20090051034A1 (en) | Semiconductor device and method for the same | |
| US7018903B2 (en) | Method of forming semiconductor device with capacitor | |
| CN111341728A (en) | Semiconductor device and method for manufacturing the same | |
| CN1110851C (en) | Method for mfg. capacitor of stack type dynamic random access memory device | |
| US7439150B2 (en) | Method of manufacturing a semiconductor device | |
| US11164874B2 (en) | Semiconductor device and method for fabricating the same | |
| US6191469B1 (en) | Overhanging separator for self-defining discontinuous film | |
| CN111326655B (en) | Semiconductor device and method for manufacturing the same | |
| US6177308B1 (en) | Method for manufacturing stacked capacitor | |
| US20020009877A1 (en) | Method for forming via holes by using retardation layers to reduce overetching | |
| CN100373546C (en) | Manufacturing method of metal-insulating layer-metal capacitor | |
| KR100532851B1 (en) | Method for fabricating capacitor of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |