CN112820341A - Memory checking method, memory checking device and memory checking system - Google Patents
Memory checking method, memory checking device and memory checking system Download PDFInfo
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- CN112820341A CN112820341A CN202110236924.1A CN202110236924A CN112820341A CN 112820341 A CN112820341 A CN 112820341A CN 202110236924 A CN202110236924 A CN 202110236924A CN 112820341 A CN112820341 A CN 112820341A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
Abstract
The invention provides a memory checking method, a memory checking device and a memory checking system. The method comprises the following steps: generating an error detection file according to source program codes, wherein the error detection file is provided with symbol (symbol) information related to description information in the source program codes; receiving memory data generated by the memory storage device running firmware; loading the error detection file to automatically analyze the memory data; and presenting an analysis result through an application program interface, wherein the analysis result reflects the state of the firmware with the aid of the symbolic information. Therefore, the work efficiency of executing the memory check on the memory storage device can be improved.
Description
Technical Field
The present invention relates to a memory checking technology, and more particularly, to a memory checking method, a memory checking device, and a memory checking system.
Background
After the memory storage device is shipped, if an abnormality occurs in the firmware (e.g., boot code) of the memory storage device, it is generally necessary to obtain data of the memory storage device by a specific device and analyze the data by using the device. For example, a common memory data acquisition device includes an In-Circuit Emulator (ICE). An online emulator may simulate the operation of the processor and communicate naturally with the memory storage device. However, the in-line emulator must be used to directly connect to the motherboard on which the memory storage device is mounted and access the memory storage device through the communication port of the motherboard. In addition, the memory data obtained by the on-line simulator can only be analyzed by the on-line simulator, and the on-line simulator is not flexible in use and is not suitable for the increasingly popular remote debugging operation.
Disclosure of Invention
The invention provides a memory checking method, a memory checking device and a memory checking system, which can improve the work efficiency of executing memory checking on a memory storage device.
An exemplary embodiment of the present invention provides a memory checking method for checking firmware in a memory storage device. The memory checking method comprises the following steps: generating an error detection file according to source program codes, wherein the error detection file is provided with symbol (symbol) information related to description information in the source program codes; receiving memory data generated by the memory storage device running the firmware; loading the error detection file to automatically analyze the memory data; and presenting an analysis result through an application program interface, wherein the analysis result reflects the state of the firmware with the aid of the symbolic information.
In an exemplary embodiment of the present invention, the step of generating the error detection file according to the source code comprises: the source program code is processed by a compiler to generate the error detection file, and the symbolic information is not presented in a machine language or a combined language.
In an exemplary embodiment of the invention, the memory checking method further includes: receiving an adjusting instruction issued by a user through the application program interface; and updating at least part of firmware codes in the firmware according to the adjusting instruction.
An exemplary embodiment of the present invention further provides a memory checking apparatus for checking firmware in a memory storage device. The memory checking device comprises a storage circuit and a processor. The storage circuit is used for storing source program codes and error detection files. The processor is connected to the memory circuit. The processor is used for generating the error detection file according to the source program code. The error detection file carries symbolic information about the description information in the source program code. The processor is also to receive memory data generated by the memory storage device running the firmware. The processor is also configured to load the error detection file to automatically analyze the memory data. The processor is also configured to present the analysis results through an application program interface. The analysis result reflects the state of the firmware with the aid of the symbolic information.
In an exemplary embodiment of the invention, the memory checking device further includes an input/output interface. The input/output interface is connected to the processor. The processor receives the memory data from the memory storage device through the input/output interface.
In an exemplary embodiment of the invention, the processor is further configured to receive an adjustment command issued by a user through the application program interface. The processor is further configured to update at least part of firmware codes in the firmware according to the adjustment instruction.
An exemplary embodiment of the present invention further provides a memory checking system, which includes a memory storage device and a host system. The memory storage has firmware. The host system is connected to the memory storage device. The host system is used for generating an error detection file according to the source program code. The error detection file carries symbolic information about the description information in the source program code. The host system is also configured to receive memory data generated by the memory storage device running the firmware. The host system is also used to load the error detection file to automatically analyze the memory data. The host system is further configured to present the analysis results through an application program interface. The analysis result reflects the state of the firmware with the aid of the symbolic information.
In an exemplary embodiment of the present invention, the operation of generating the error detection file according to the source code comprises: the source program code is processed by a compiler to generate the error detection file, and the symbolic information is not presented in a machine language or a combined language.
In an exemplary embodiment of the invention, the symbol information is used to associate the description information in the source code to a specific symbol in the firmware.
In an exemplary embodiment of the invention, the memory data is obtained by reading at least one memory module in the memory storage device by an analog circuit connected to the memory storage device.
In an exemplary embodiment of the invention, the analog circuit includes an in-line emulator.
In an example embodiment of the present invention, the memory data is received by the host system from the memory storage device.
In an exemplary embodiment of the invention, the host system is further configured to receive an adjustment command issued by a user through the application program interface. The host system is further used for updating at least part of firmware codes in the firmware according to the adjusting instruction.
Based on the above, the error detection file may be generated from source program code. In particular, the error detection file may carry symbolic information about the description information in the source code. Upon receiving memory data generated by a memory storage device running firmware, the error detection file may be executed to automatically analyze the memory data. The analysis results can then be presented through an application program interface to reflect the state of the firmware with the aid of the symbolic information. Therefore, the work efficiency of executing the memory check on the memory storage device can be improved.
Drawings
FIG. 1 is a schematic diagram of a memory checking system according to an exemplary embodiment of the present invention;
FIG. 2 is a schematic block diagram of a host system shown in accordance with an exemplary embodiment of the present invention;
FIG. 3 is a diagram illustrating generation of an error detection file according to source code according to an exemplary embodiment of the present invention;
FIG. 4 is a diagram illustrating description information according to an exemplary embodiment of the present invention;
FIG. 5 is a diagram illustrating a memory check operation according to an exemplary embodiment of the present invention;
FIG. 6 is a schematic block diagram of a memory storage device shown in accordance with an exemplary embodiment of the present invention;
fig. 7 is a flowchart illustrating a memory checking method according to an exemplary embodiment of the present invention.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
FIG. 1 is a schematic diagram of a memory checking system according to an exemplary embodiment of the present invention. Referring to fig. 1, a memory checking system 10 includes a host system 11 and a memory storage device 12. The host system 11 is used to check the firmware in the memory storage 12. For example, the firmware may include boot code installed in memory storage device 12 and/or other firmware code required during operation of memory storage device 12. For example, the checking includes debugging, modifying, or adjusting at least a portion of firmware code of the firmware in memory storage 12. For example, the host system 11 may include a computer system with a computing function, such as a notebook computer, a desktop computer, a tablet computer, an industrial computer, or a server. In an example embodiment, the host system 11 is also referred to as a firmware checking device or a memory checking device.
The memory storage 12 may include a U disk, a memory card, a Solid State Drive (SSD), or a wireless memory storage. In addition, the memory storage device 12 may include embedded Multi-Media Card (eMMC) or embedded Multi-Chip Package (eMCP) storage devices of various types for directly connecting the memory module to the embedded storage device on the motherboard.
In an example embodiment, the host system 11 may receive memory data 101 generated by the memory storage device 12 running the firmware. That is, memory data 101 may reflect the results of the execution of the firmware on memory storage 12. Host system 11 may automatically analyze memory data 101 to check the firmware in memory storage 12.
Fig. 2 is a schematic block diagram of a host system shown in accordance with an exemplary embodiment of the present invention. Referring to fig. 2, the host system 11 includes a processor 21, a memory circuit 22 and an input/output interface 23. The processor 21 is responsible for the overall or partial operation of the host system 11. For example, the Processor 21 may include a Central Processing Unit (CPU), or other Programmable general purpose or special purpose microprocessor, Digital Signal Processor (DSP), Programmable controller, Application Specific Integrated Circuit (ASIC), Programmable Logic Device (PLD), or other similar Device or combination thereof.
The memory circuit 22 is connected to the processor 21 and stores data. For example, the storage circuit 22 may include a conventional Hard Disk Drive (HDD) and/or a solid state Drive (ssd). The input/output interface 23 is connected to the processor 21 and serves to receive or transmit signals. For example, the input/output interface 23 may include various connection interfaces such as a mouse, a keyboard, a touch pad, a screen, a speaker, a microphone, a network interface card, and/or a Universal Serial Bus (USB).
In an exemplary embodiment, the storage circuit 22 stores an error detection file 201, memory data 202, a debugging program 203, and an application program interface 204. Error detection file 201 contains debug information related to the firmware in memory storage 12 of FIG. 1. Memory data 202 may be stored in storage circuitry 22 according to memory data 101 of FIG. 1. The processor 21 may load the error detection file 201 and the memory data 202 into the debugging program 203. After loading the error detection file 201 and the memory data 202, the processor 21 may run a debugging program 203 to automatically analyze the memory data 202. The processor 21 may then present the results of the analysis of the memory data 202 through the application program interface 204. Based on the analysis, the processor 21 may automatically or with the assistance of a debugging person check (e.g., debug) the state of the firmware in the memory storage 12.
In an exemplary embodiment, processor 21 may generate error detection file 201 according to a source code. The source code carries description information. For example, this description information may be used to describe the declaration, definition, or function of at least some of the source code. It should be noted that the error detection file 201 may have symbol (symbol) information associated with the description information in the source code.
FIG. 3 is a diagram illustrating generation of an error detection file according to source code according to an exemplary embodiment of the present invention. Referring to fig. 3, in an example embodiment, the processor 21 includes a compiler (compiler) 31. Compiler 31 may be used to process (e.g., compile) source code 32 to generate error detection file 33. Error check file 32 may be the same or similar to error check file 201 of FIG. 2. It should be noted that the source code 32 carries description information 321. The description information 321 can be used to describe the declaration, definition, or function of at least some of the source code 32.
In an exemplary embodiment, error detection file 33 includes an execution file 331 and an additional file 332. The execution file 331 and the additional file 332 are generated by the compiler 31 processing the source code 32. The execution file 331 is a file rendered in a machine language (or a combination of languages) and can be considered a main program generated by compiling the source code 32. The attached file 332 is used to carry symbol information related to the description information 321. In particular, the additional files 332 are not presented in a machine language (or a combined language). In an example embodiment, the additional files 332 may be considered description files between the source code 32 and the execution files 331 that are presented in the machine language (or combination language). In an exemplary embodiment, the symbol information carried by the attached file 332 can be used to associate (or map) the description information 321 to a specific symbol in the firmware of the memory storage device 12 of FIG. 1.
Fig. 4 is a diagram illustrating description information according to an exemplary embodiment of the present invention. Referring to fig. 4, the description information 401 may be included in the description information 321 of fig. 3. The description information 401 may be used to describe the declaration, definition, or function of at least some of the source code 32 of FIG. 3.
In an exemplary embodiment, the memory data 101 of FIG. 1 is obtained by an analog circuit coupled to the memory storage device 12 reading at least one memory module in the memory storage device 12. For example, the at least one memory module may include a volatile memory module and/or a non-volatile memory module. For example, the volatile Memory module may include a Dynamic Random Access Memory (DRAM) module and/or a Static Random Access Memory (SRAM) module, and the nonvolatile Memory module may include a flash Memory module. Further, the analog circuit may not be provided in the host system 11.
In an example embodiment, the analog Circuit may include an In-Circuit Emulator (ICE). The in-line emulator may be connected to a motherboard on which the memory storage device 12 is mounted. After the memory storage device 12 executes its internal firmware, the on-line emulator can read the memory data 101 from the at least one memory module in the memory storage device 12 through the communication interface of the host board. The read memory data 101 may be carried or transmitted to the host system 11 for analysis. In an exemplary embodiment, the host system 11 may also read the memory data 101 from the memory storage device 12 through other types of reading devices or by the host system 11 itself, which is not limited by the invention.
FIG. 5 is a diagram illustrating a memory check operation according to an exemplary embodiment of the present invention. Referring to fig. 5, after the error detection file 201 (e.g., the execution file 331 and the additional file 332 of fig. 3) and the memory data 202 are loaded into the debug program 203, the debug program 203 may analyze the memory data 202 according to the debug information in the error detection file 201 related to the firmware in the memory storage device 12 of fig. 1 and generate an analysis result 501. The analysis results 501 may be presented through the application program interface 204, for example, on a display of the host system 11 of FIG. 1.
In an example embodiment, the analysis result 501 may reflect the state of the firmware (e.g., possible exceptions in the firmware) with the aid of the symbolic information carried by the error detection file 201. For example, after the debugger 203 is running, the debugger 203 may associate (or map) the symbol corresponding to one or more firmware codes in the firmware with the symbol information in the error detection file 201. According to this association result (or mapping result), the associated description (e.g., announcement, definition, or function description related to a certain program code) originally described in the description information 321 of fig. 3 can be presented in the application program interface 204.
In an example embodiment, when the debug program 203 detects an exception event corresponding to a certain firmware code in the memory storage device 12, the debug program 203 may present the exception event (or the firmware code or memory location where the exception occurred) and associated description information in the API 204 at the same time. In particular, similar to the description information in the original program code (e.g., description information 321 of FIG. 3), the description information presented in the API 204 is presented in a human-readable manner, thereby facilitating error locking and elimination for the exception event by the debugger.
In an exemplary embodiment, the debugging process 203 may receive the adjustment command 502 issued by the user through the API 204. The adjustment command 502 can be input to the API 204 through the I/O interface 23 of FIG. 2. The debugger 203 may update at least a portion of firmware code in the firmware according to the adjustment instructions 502. For example, the debugging personnel may issue the adjustment command 502 according to the exception event presented by the API 204. The debug program 203 may update the firmware code associated with the exception in the memory storage device 12 of fig. 1 according to the adjustment instruction 502 to attempt to eliminate the exception.
FIG. 6 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to FIG. 6, the memory storage device 62 may be the same as or similar to the memory storage device 12 of FIG. 1. In an exemplary embodiment, the memory storage device 62 includes a connection interface unit 621, a memory control circuit unit 622, a rewritable nonvolatile memory module 623, and a volatile memory module 624.
In an exemplary embodiment, the connection interface unit 621 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 621 may also conform to Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, High-Speed Peripheral Component connection interface (PCI) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed (UHS-I) interface standard, Ultra High Speed (UHS-II) interface standard, Memory Stick (Memory Stick, MS) interface standard, MCP, MMC interface standard, eMMC interface standard, Universal Flash Memory (Flash) interface standard, CF interface standard, and Electronic drive interface (Electronic drive interface), IDE) standard or other suitable standard. The connection interface unit 621 may be packaged in a chip with the memory control circuit unit 622, or the connection interface unit 621 is disposed outside a chip including the memory control circuit unit 622.
The memory control circuit unit 622 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware, and performing operations such as writing, reading, and erasing data in the rewritable nonvolatile memory module 623 according to commands of the host system.
The rewritable nonvolatile memory module 623 is connected to the memory control circuit unit 622 and is used for storing data. The rewritable nonvolatile memory module 623 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 623 stores one or more bits with a change in voltage (hereinafter also referred to as threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. Each memory cell in the rewritable non-volatile memory module 406 has multiple memory states as the threshold voltage changes. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.
The volatile memory module 624 is connected to the memory control circuit unit 622 and serves to temporarily store data. For example, the volatile memory module 624 may include a DRAM module and/or an SRAM module.
In an exemplary embodiment, the memory control circuit unit 622 can store the firmware code including the boot code in the rewritable nonvolatile memory module 623. When the memory storage device 62 is powered on or otherwise operating, the corresponding firmware code may be read into the volatile memory module 624 for execution. In addition, the transient data generated by executing the firmware code is also temporarily stored in the volatile memory module 624. In an exemplary embodiment, the memory data 101 of FIG. 1 includes the transient data. In an exemplary embodiment, by comparing the information in the error detection file 201 of fig. 2 with the transient data and performing an equal analysis, a corresponding abnormal event can be detected and presented to the api 204 of fig. 2.
FIG. 7 is a flowchart illustrating a memory checking method according to an exemplary embodiment of the invention. Referring to fig. 7, in step S701, an error detection file is generated according to the source code. The error detection file carries symbolic information about the description information in the source program code. In step S702, memory data generated by the memory storage device running the firmware is received. In step S703, the error detection file is loaded to automatically analyze the memory data. In step S704, an analysis result is presented through an application program interface, wherein the analysis result reflects the state of the firmware with the aid of the symbolic information.
However, the steps in fig. 7 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 7 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 7 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.
In summary, the error detection file may be generated based on the source code. In particular, the error detection file may carry symbolic information about the description information in the source code. Upon receiving memory data generated by a memory storage device running firmware, the error detection file may be executed to automatically analyze the memory data. The analysis results can then be presented through an application program interface to reflect the state of the firmware with the aid of the symbolic information. Therefore, the work efficiency of executing the memory check on the memory storage device can be improved.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (21)
1. A memory checking method for checking firmware in a memory storage device, the memory checking method comprising:
generating an error detection file according to the source program code, wherein the error detection file carries symbol information related to description information in the source program code;
receiving memory data generated by the memory storage device running the firmware;
loading the error detection file to automatically analyze the memory data; and
presenting an analysis result through an application program interface, wherein the analysis result reflects the state of the firmware with the aid of the symbolic information.
2. The memory checking method of claim 1, wherein the generating the error detection file according to the source program code comprises:
the source program code is processed by a compiler to generate the error detection file, and the symbolic information is not presented in a machine language or a combined language.
3. The memory checking method of claim 1, wherein the symbol information is used to associate the description information in the source code to a specific symbol in the firmware.
4. The memory checking method according to claim 1, wherein the memory data is obtained by reading at least one memory module in the memory storage device by an analog circuit connected to the memory storage device.
5. The memory checking method of claim 4, wherein the analog circuit comprises an in-line emulator.
6. The memory checking method of claim 1, wherein the memory data is received by a host system from the memory storage device.
7. The memory checking method of claim 1, further comprising:
receiving an adjusting instruction issued by a user through the application program interface; and
and updating at least part of firmware codes in the firmware according to the adjusting instruction.
8. A memory checking device for checking firmware in a memory storage device, the memory checking device comprising:
the storage circuit is used for storing the source program code and the error detection file; and
a processor coupled to the memory circuit,
wherein the processor is configured to generate the error detection file according to the source program code, the error detection file carrying symbolic information related to the description information in the source program code,
the processor is also to receive memory data generated by the memory storage device running the firmware,
the processor is further configured to load the error detection file to automatically analyze the memory data, and
the processor is also configured to present an analysis result through an application program interface, wherein the analysis result reflects a state of the firmware with the aid of the symbolic information.
9. The memory check device of claim 8, wherein generating the error detection file from the source program code comprises:
the source program code is processed by a compiler to generate the error detection file, and the symbolic information is not presented in a machine language or a combined language.
10. The memory check device of claim 8, wherein the symbol information is used to associate the description information in the source code to a particular symbol in the firmware.
11. The memory check device of claim 8, wherein the memory data is obtained by an analog circuit connected to the memory storage device reading at least one memory module in the memory storage device.
12. The memory checking device of claim 11, wherein the analog circuit comprises an in-line emulator.
13. The memory check device of claim 8, wherein the memory check device further comprises an input/output interface connected to the processor, and
the processor receives the memory data from the memory storage device through the input/output interface.
14. The memory check device of claim 8, wherein the processor is further configured to receive user-issued adjustment commands through the application program interface, and
the processor is further configured to update at least part of firmware codes in the firmware according to the adjustment instruction.
15. A memory checking system, comprising:
a memory storage having firmware; and
a host system connected to the memory storage device,
wherein the host system is used for generating an error detection file according to the source program code, the error detection file carries symbol information related to the description information in the source program code,
the host system is also configured to receive memory data generated by the memory storage device running the firmware,
the host system is further configured to load the error detection file to automatically analyze the memory data, and
the host system is also configured to present an analysis result through an application program interface, wherein the analysis result reflects a state of the firmware with the aid of the symbolic information.
16. The memory checking system of claim 15, wherein generating the error detection file from the source program code comprises:
the source program code is processed by a compiler to generate the error detection file, and the symbolic information is not presented in a machine language or a combined language.
17. The memory checking system of claim 15, wherein the symbol information is used to associate the description information in the source code to a particular symbol in the firmware.
18. The memory checking system of claim 15, wherein the memory data is obtained by an analog circuit connected to the memory storage device reading at least one memory module in the memory storage device.
19. The memory checking system of claim 18, wherein the analog circuit comprises an in-line emulator.
20. The memory checking system of claim 15, wherein the memory data is received by the host system from the memory storage device.
21. The memory check system of claim 15, wherein the host system is further configured to receive user-issued adjustment commands through the application program interface, and
the host system is further used for updating at least part of firmware codes in the firmware according to the adjusting instruction.
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