CN112817521B - Flash memory abrasion method and device, readable storage medium and electronic equipment - Google Patents
Flash memory abrasion method and device, readable storage medium and electronic equipment Download PDFInfo
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- CN112817521B CN112817521B CN202110034314.3A CN202110034314A CN112817521B CN 112817521 B CN112817521 B CN 112817521B CN 202110034314 A CN202110034314 A CN 202110034314A CN 112817521 B CN112817521 B CN 112817521B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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- G06F3/0604—Improving or facilitating administration, e.g. storage management
- G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
- G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
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Abstract
The invention discloses a flash memory wear method, a flash memory wear device, a readable storage medium and electronic equipment, wherein when data is written in each flash memory block, a corresponding preset fixed value is written in each page of each flash memory block, random data is usually written in each page of the flash memory block in the prior art, and each page is written in the corresponding preset fixed value, so that each page can be in a corresponding fixed level value, all storage units are written in a fixed state, the wear rate of the flash memory can be increased, and the wear time before flash memory test is shortened; the LDPC coding function and the correction function are closed when the flash memory is worn, and the subsequent writing of preset fixed data into the flash memory is guaranteed not to be interfered by coding and correction, so that the fixed numerical value can be written into each page, and the wear of the flash memory is accelerated.
Description
Technical Field
The present invention relates to the field of data storage technologies, and in particular, to a flash memory wear method and apparatus, a readable storage medium, and an electronic device.
Background
Flash memory (Nand flash), a nonvolatile memory, is an important component of SSD (solid state drive), so for solid state drive development companies, in order to make their products more competitive, the characteristics of flash memory need to be mastered thoroughly enough, so that flash memory can be used better, the life and stability of flash memory are improved, and therefore, a series of research on flash memory is not needed. Such as lifetime-related research, it is often necessary to perform some wear-related experiments on flash memory. In addition, some flashes are unstable when the first few or the first ten and several pecs (erase counts) are used, so that the flash memory needs to spend this stage before being used normally to ensure the stability of the SSD firmware (SSD firmware) operation.
The lifetime of a 3D TLC (triple level cell, 3D refers to a process in a stacked manner, in order to store more data amount per unit area, TLC is the minimum unit for storing data, and one memory cell in TLC type can store 3 bits) is about 2500 pecs. If one wants to study the characteristics of flash memory later in its life, the flash memory must first be worn down to a fixed erase-write number. Referring to fig. 1, in the conventional flash memory wear, a flash memory block is erased, after the flash memory block is erased, random data to be written is prepared in a static random access memory, and the random data is written into a corresponding memory cell until all flash memory blocks are worn to a fixed number of times of erasing, by the above method, a time of about 43 days is required from the whole flash memory to 2500 flash memory wear, and the time required for different main control or flash memories is different. Therefore, the flash memory abrasion work in the previous stage consumes a lot of labor cost, and the work efficiency is low.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the flash memory wear method and device, the readable storage medium and the electronic equipment are provided, the flash memory can be worn out at an accelerated speed, and the testing efficiency is improved.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a flash wear method, comprising the steps of:
receiving a wear instruction, and closing the LDPC coding function and the correction function of the flash memory;
erasing each flash memory block, and writing a corresponding preset fixed value into each page in each flash memory block after erasing until the writing of each page in each flash memory block is completed;
and circularly erasing and writing each flash memory block until the erasing and writing times of each flash memory block reach the preset erasing and writing times.
In order to solve the technical problem, the invention adopts another technical scheme as follows:
a flash wear device, comprising:
the initialization module is used for receiving a wear instruction and closing the LDPC coding function and the correction function of the flash memory;
the erasing module is used for erasing each flash memory block and writing a corresponding preset fixed value into each page of each erased flash memory block until the writing of each page of each flash memory block is completed;
and the circulating module is used for circulating the erasing and writing operations on each flash memory block until the erasing and writing times of each flash memory block reach the preset erasing and writing times.
In order to solve the technical problem, the invention adopts another technical scheme as follows:
a computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the above-mentioned flash wear method.
In order to solve the technical problem, the invention adopts another technical scheme as follows:
an electronic device comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor executes the computer program to realize the steps of the flash memory wear method.
The invention has the beneficial effects that: when data is written in each flash memory block, a corresponding preset fixed value is written in each page of each flash memory block, random data is usually written in each page of the flash memory block in the prior art, and the corresponding preset fixed value is written in each page, so that each page can be in a corresponding fixed level value, all memory units are written in a fixed state, the wear rate of the flash memory can be increased, and the wear time of a flash memory test can be shortened; the LDPC coding function and the correction function are closed when the flash memory is worn, and the follow-up writing of preset fixed data into the flash memory is guaranteed not to be interfered by coding and correction, so that the fixed value can be written into each page, the wear speed of the flash memory is accelerated, and the test efficiency is improved.
Drawings
FIG. 1 is a prior art flash wear flow diagram;
FIG. 2 is a flowchart illustrating steps of a flash wear method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a flash wear apparatus according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;
FIG. 5 is a distribution diagram of memory cells after erasing flash blocks according to the flash wear method of the embodiment of the present invention;
FIG. 6 is a flowchart illustrating steps of a flash wear method according to an embodiment of the present invention;
FIG. 7 is a distribution diagram of memory cells with different threshold voltages for TLC type flash of the flash wear method of the present invention;
fig. 8 is a distribution diagram of memory cells of a TLC type flash memory at a maximum threshold voltage for the flash wear method of an embodiment of the present invention.
Detailed Description
In order to explain technical contents, achieved objects, and effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
Referring to fig. 2, an embodiment of the invention provides a flash wear method, including:
receiving a wear instruction, and closing the LDPC coding function and the correction function of the flash memory;
erasing each flash memory block, and writing a corresponding preset fixed value into each page in each erased flash memory block until the writing of each page in each flash memory block is completed;
and circularly erasing and writing each flash memory block until the erasing and writing times of each flash memory block reach the preset erasing and writing times.
From the above description, the beneficial effects of the present invention are: when data is written in each flash memory block, a corresponding preset fixed value is written in each page of each flash memory block, random data is usually written in each page of the flash memory block in the prior art, and the corresponding preset fixed value is written in each page, so that each page can be in a corresponding fixed level value, all memory units are written in a fixed state, the wear rate of the flash memory can be increased, and the wear time before testing the flash memory can be shortened; the LDPC coding function and the correction function are closed when the flash memory is worn, and the subsequent writing of preset fixed data into the flash memory is guaranteed not to be interfered by coding and correction, so that the fixed numerical value can be written into each page, and the wear of the flash memory is accelerated.
Further, the preset fixed value is a level value of each bit of the corresponding memory cell when the threshold voltage applied to the flash memory is the maximum.
As can be seen from the above description, the threshold voltage applied to the flash memory corresponds to the level values of different memory cells, and the difference in threshold voltage also causes different degrees of flash memory wear, usually a random value is written into each page of the flash memory block.
Further, the writing of the corresponding preset fixed value to each page in each erased flash memory block comprises:
all 1's are written into the corresponding pages of the most significant bit and the least significant bit of all memory cells in each flash memory block after erasing, and all 0's are written into the corresponding pages of the middle significant bit of all memory cells.
As can be seen from the above description, in the flash memory with three layers of memory cells, all 1 s are written into the corresponding pages of the most significant bit and the least significant bit in each flash block, all 0 s are written into the corresponding pages of the middle significant bit, and all memory cells can be written into "101", that is, all the memory cells correspond to the level value corresponding to the maximum threshold voltage applied to the flash memory, and the wear rate of the level value is seven times that of the existing wear rate, so that all the memory cells are ensured to be in a fixed state, the wear rate is increased, and the wear time is shortened.
Further, the writing of the corresponding preset fixed value to each page in each erased flash memory block comprises:
caching a preset fixed value to be written into each page in the flash memory block;
and writing a corresponding preset fixed value of the cache into each page in each flash memory block after erasing.
As can be seen from the above description, the preset fixed value to be written into each page of the flash memory block is cached, and the preset fixed value of the corresponding cache is written into each page of the erased flash memory block, so that each erased flash memory block can be automatically and quickly written into.
Further, the wear instruction comprises the number of times of erasing and writing;
and determining the preset erasing times according to the required erasing times and a preset fixed value.
According to the description, the wear instruction comprises the required erasing times, the preset erasing times can be determined according to the required erasing times and the preset fixed value, the erasing times can be reduced in accelerated wear through the determination of the preset fixed value, and the flash memory wear time before testing is saved.
Further, the erasing each flash memory block, and writing a corresponding preset fixed value into each page of each erased flash memory block until the writing into each page of each flash memory block is completed includes:
and erasing and writing the corresponding preset fixed values one by one for each flash memory block according to a preset sequence until each flash memory block is erased and written once.
According to the description, each flash memory block is erased one by one according to the preset data until all the flash memory blocks are erased, so that the memory blocks of the whole disk can be erased orderly, and the reliability and comprehensiveness of the abrasion process are ensured.
Further, the foregoing erasing and writing operations on each flash memory block in a loop until the number of times of erasing and writing of each flash memory block reaches a preset number of times of erasing and writing further includes the following steps:
and starting the LDPC coding function and the correction function of the flash memory.
From the above description, after the number of times of erasing of each flash memory block reaches the preset number of times of erasing, the LDPC coding function and the correction function of the flash memory are turned on, and it is ensured that the coding and correction functions can be normally used after accelerated wear.
Referring to fig. 3, another embodiment of the present invention provides a flash memory wear device, including:
the initialization module is used for receiving a wear instruction and closing the LDPC coding function and the correction function of the flash memory;
the erasing module is used for erasing each flash memory block and writing a corresponding preset fixed value into each page of each erased flash memory block until the writing of each page of each flash memory block is completed;
and the circulating module is used for circulating the erasing and writing operations of each flash memory block until the erasing and writing times of each flash memory block reach the preset erasing and writing times.
Another embodiment of the present invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps in the above-described flash wear method.
Referring to fig. 4, another embodiment of the present invention provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the flash wear method when executing the computer program.
The flash memory wear method, the flash memory wear device, the computer-readable storage medium and the electronic device of the invention can be applied to the flash memory wear of various types of flash memories during testing, and are described in the following by specific embodiments:
example one
Referring to fig. 2, a flash memory wear method includes the steps of:
s1, receiving a wear instruction, and closing an LDPC coding function and a correcting function of the flash memory;
specifically, in this embodiment, after receiving the wear instruction, the LDPC function and the scrambler (scrambler) are turned off, so as to prevent the LDPC from generating check data and prevent the scrambler from scrambling when writing data, thereby ensuring that fixed data can be written subsequently when writing data into the flash memory;
s2, erasing each flash memory block, and writing a corresponding preset fixed value into each page in each erased flash memory block until the writing of each page in each flash memory block is completed;
erasing and writing corresponding preset fixed values into each flash memory block one by one according to a preset sequence until each flash memory block is erased and written once;
wherein, writing a corresponding preset fixed value into each page of each erased flash memory block comprises:
caching a preset fixed value to be written into each page in the flash memory block;
writing a preset fixed value of the corresponding cache into each page in each erased flash memory block;
specifically, in this embodiment, each flash memory block is sequentially erased one by one, please refer to fig. 5, after erasing, the data inside the memory cell is all 1;
storing a corresponding preset fixed value to be written into each page in an SRAM (Static Random-Access Memory), and writing the preset fixed value in the corresponding SRAM into each page in each flash Memory block after erasing until each flash Memory block is erased and written once;
s3, the erasing and writing operations of each flash memory block are circulated until the erasing times of each flash memory block reach the preset erasing times;
wherein the wear instruction comprises the number of times of erasing and writing;
determining the preset erasing times according to the required erasing times and a preset fixed value;
specifically, in this embodiment, the required erasing frequency and the preset fixed value can determine the preset erasing frequency, and the higher the applied voltage corresponding to the level value of the preset fixed value is, the less the preset erasing frequency is;
wherein, the above-mentioned erasing and writing operations to each flash memory block are circulated until the erasing times of each flash memory block reach the preset erasing times, and the method comprises the following steps:
starting the LDPC coding function and the correction function of the flash memory;
specifically, referring to fig. 6, when the flash memory starts to wear, the LDPC encoding and scrambling device is turned off, the encoding and scrambling functions are prevented from performing encoding correction on the written numerical values, each flash memory block is erased, a preset fixed value is written into each page of each flash memory block until each flash memory block is erased once, the erasing operation on each flash memory block is cycled until all flash memory blocks are worn to reach a fixed erasing frequency, the LDPC encoding and correcting functions of the flash memory are turned on, and the wear of the full-disk flash memory is finished.
Example two
The difference between this embodiment and the first embodiment is that how to determine the preset fixed value is specifically defined:
the preset fixed value is a level value of each bit of a corresponding storage unit when the threshold voltage applied to the flash memory is maximum;
in this embodiment, please refer to fig. 7, generally, in the writing process, no matter what data is written, after the scrambler module at the main control end scrambles the writing operation, the 0 value and the 1 value of each page in the flash memory block are uniformly distributed, and the memory cells of the whole page are uniformly distributed in 8 states in fig. 7, the abscissa in fig. 7 is the read threshold voltage Vr, the ordinate is the number of cells, the larger the voltage is towards the right, the larger the voltage applied in the writing process is, the larger the wear of the memory cells is, the 8 states in fig. 7 are sequentially marked as L0 (level 0), L1 (level 1), L2 (level 2), \\ 8230; \\ 8230, L7 (level 7) from left to right, and the used flash memories are different and the codes of the memory cell distribution maps are different;
in order to accelerate wear of the flash memory, in this embodiment, all the memory cells of the flash memory are written into a fixed state, in this embodiment, a TLC type cache is selected, 3 bits in one memory cell are mapped into 3 different logical pages, and different fixed values are preset in each logical page, so that each memory cell is fixed in the same state;
wherein, writing a corresponding preset fixed value into each page of each erased flash memory block comprises:
writing all 1 into the most significant bit and the least significant bit of all the memory cells in each flash memory block after erasing, and writing all 0 into the middle significant bit of all the memory cells, wherein the written value is the level value of the L7 state in FIG. 7, and the abrasion speed of one erasing and L7 writing, namely the abrasion speed of the existing seven common erasures can be realized;
specifically, referring to fig. 8, in this embodiment, all the memory cells are selected to be fixed in the "101" state, so that 3 logical pages (pages) in this embodiment are MSB (most significant bit) page, CSB (middle significant bit) page and LSB (least significant bit) page, all 1 s are written in MSB page and LSB page, all 0 s are written in CSB page, so that all the memory cells are written with 101 level values, and fixed in the L7 state, the wear level in the erasing process is 7 times of the wear level of random writing, that is, the level values of 1 erasing to the flash block and writing all the flash blocks into the L7 state are equal to the wear level of the existing 7 times of random erasing, but the time used by the two is substantially the same, so the wear efficiency of writing all the memory cells into the L7 state is 7 times of the existing random erasing wear efficiency at the same time;
specifically, in this embodiment, the number of times of erasing is 2500pec, so that when all flash memory blocks are worn down to 357, the abrasion degree of 2500 ordinary erasing can be satisfied, and the time for wearing the whole flash memory is shortened from 43 days before to about 6 days; in addition, level values corresponding to different threshold voltages can be set, corresponding preset erasing times can be obtained, and the larger the threshold voltage is, the fewer the preset erasing times are.
EXAMPLE III
Referring to fig. 3, a flash wear device includes:
the initialization module is used for receiving a wear instruction and closing the LDPC coding function and the correction function of the flash memory;
the erasing module is used for erasing each flash memory block and writing a corresponding preset fixed value into each page of each erased flash memory block until the writing of each page of each flash memory block is completed;
and the circulating module is used for circulating the erasing and writing operations on each flash memory block until the erasing and writing times of each flash memory block reach the preset erasing and writing times.
Example four
A computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, implements the steps in a flash wear method in any one of the first to second embodiments.
EXAMPLE five
Referring to fig. 4, an electronic device includes a memory, a processor, and a computer program stored in the memory and capable of running on the processor, where the processor executes the computer program to implement the steps of a flash wear method in any one of the first to second embodiments.
In summary, according to the flash memory wear method, the flash memory wear device, the readable storage medium and the electronic device provided by the present invention, the LDPC encoding function and the scrambler are first turned off, each flash memory block is erased, and when data is written into each flash memory block, a corresponding preset fixed value is written into each page of each flash memory block, and random data is usually written into each page of the flash memory block in the prior art; different bit bits in the storage units of the flash memory are mapped into corresponding logical pages, different fixed values are preset in each logical page, so that each storage unit is fixed in the same state, all 1 are written into the most significant bit and the least significant bit of all the storage units in each erased flash memory block, all 0 are written into the middle significant bit of all the storage units, namely, a level value 101 is written into all the storage units, the abrasion degree is 7 times that of the storage units when random data is written, the erasing time of the storage units is basically consistent with that of the random data, and finally, the LDPC coding function and the scrambler are started, so that the abrasion to the flash memory can be accelerated, the test efficiency is improved, and the reliability and the comprehensiveness of the abrasion process of the flash memory are ensured.
In the above embodiments provided in the present application, it should be understood that the disclosed method, apparatus, computer-readable storage medium, and electronic device may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is only one logical division, and other divisions may be realized in practice, for example, a plurality of components or modules may be combined or integrated into another apparatus, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or components or modules, and may be in an electrical, mechanical or other form.
The components described as separate parts may or may not be physically separate, and parts displayed as components may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the components can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional modules in the embodiments of the present invention may be integrated into one processing module, or each component may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.
The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present invention, which is substantially or partly contributed by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It should be noted that, for the sake of simplicity, the above-mentioned method embodiments are described as a series of acts or combinations, but those skilled in the art should understand that the present invention is not limited by the described order of acts, as some steps may be performed in other orders or simultaneously according to the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no acts or modules are necessarily required of the invention.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The above description is only an embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent modifications made by the present invention and the contents of the accompanying drawings, which are directly or indirectly applied to the related technical fields, are included in the scope of the present invention.
Claims (8)
1. A flash memory wear method, comprising the steps of:
receiving a wear instruction, and closing the LDPC coding function and the correction function of the flash memory;
erasing each flash memory block, and writing a corresponding preset fixed value into each page in each erased flash memory block until the writing of each page in each flash memory block is completed;
circularly erasing and writing each flash memory block until the erasing and writing times of each flash memory block reach the preset erasing and writing times;
the preset fixed value is a level value of each bit of a corresponding storage unit when the threshold voltage applied to the flash memory is maximum;
the writing of the corresponding preset fixed value into each page in each erased flash memory block comprises:
all 1's are written to the corresponding pages of the most significant bit and the least significant bit of all memory cells in each flash block after erasing, and all 0's are written to the corresponding pages of the middle significant bit of all memory cells.
2. The method of claim 1, wherein writing a corresponding predetermined fixed value to each page of each flash block after erasing comprises:
caching a preset fixed value to be written into each page in the flash memory block;
and writing a corresponding preset fixed value of the cache into each page in each flash memory block after erasing.
3. A method as claimed in claim 1 or 2, wherein the wear instruction comprises a required erase/write count;
and determining the preset erasing times according to the required erasing times and a preset fixed value.
4. The flash memory wear method according to claim 1 or 2, wherein the erasing each flash memory block and writing each page of each erased flash memory block with a corresponding preset fixed value until the writing of each page of each flash memory block is completed comprises:
and erasing and writing the corresponding preset fixed values into each flash memory block one by one according to a preset sequence until each flash memory block is erased and written once.
5. A flash wear method in accordance with claim 1 or 2, wherein said cycling said erasing and writing operations on each flash block until the number of erasing times of each flash block reaches a predetermined number of erasing times further comprises:
and starting the LDPC coding function and the correction function of the flash memory.
6. A flash wear device, comprising:
the initialization module is used for receiving a wear instruction and closing the LDPC coding function and the correction function of the flash memory;
the erasing module is used for erasing each flash memory block and writing a corresponding preset fixed value into each page of each erased flash memory block until the writing of each page of each flash memory block is completed, wherein the preset fixed value is a level value of each bit of a corresponding storage unit when the threshold voltage applied to the flash memory is maximum;
the writing of the corresponding preset fixed value into each page of each erased flash memory block comprises:
writing all 1 in corresponding pages of most significant bits and least significant bits of all memory cells in each flash memory block after erasing, and writing all 0 in corresponding pages of middle significant bits of all memory cells;
and the circulating module is used for circulating the erasing and writing operations on each flash memory block until the erasing and writing times of each flash memory block reach the preset erasing and writing times.
7. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the flash wear method according to any one of claims 1 to 5.
8. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of the flash wear method according to any one of claims 1 to 5 when executing the computer program.
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| CN202110034314.3A CN112817521B (en) | 2021-01-12 | 2021-01-12 | Flash memory abrasion method and device, readable storage medium and electronic equipment |
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| CN202110034314.3A CN112817521B (en) | 2021-01-12 | 2021-01-12 | Flash memory abrasion method and device, readable storage medium and electronic equipment |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108829358A (en) * | 2018-06-29 | 2018-11-16 | 郑州云海信息技术有限公司 | The bad block management method and solid state hard disk of solid state hard disk |
| CN108847267A (en) * | 2018-05-23 | 2018-11-20 | 武汉忆数存储技术有限公司 | A kind of service life of flash memory test method based on error pattern |
| CN111192623A (en) * | 2018-11-14 | 2020-05-22 | 慧荣科技股份有限公司 | Method, computer device and user interface for automated testing |
| CN111192620A (en) * | 2019-12-31 | 2020-05-22 | 山东华芯半导体有限公司 | Method for optimizing NAND Flash read reference voltage in SSD |
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| WO2011036228A1 (en) * | 2009-09-23 | 2011-03-31 | Conor Maurice Ryan | A flash memory device and control method |
| US20110072192A1 (en) * | 2009-09-24 | 2011-03-24 | Agiga Tech Inc. | Solid state memory wear concentration |
| US10079068B2 (en) * | 2011-02-23 | 2018-09-18 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Devices and method for wear estimation based memory management |
| US8627158B2 (en) * | 2011-12-08 | 2014-01-07 | International Business Machines Corporation | Flash array built in self test engine with trace array and flash metric reporting |
| CN111104342B (en) * | 2018-10-29 | 2023-08-04 | 伊姆西Ip控股有限责任公司 | Method, electronic device and computer program product for storage |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108847267A (en) * | 2018-05-23 | 2018-11-20 | 武汉忆数存储技术有限公司 | A kind of service life of flash memory test method based on error pattern |
| CN108829358A (en) * | 2018-06-29 | 2018-11-16 | 郑州云海信息技术有限公司 | The bad block management method and solid state hard disk of solid state hard disk |
| CN111192623A (en) * | 2018-11-14 | 2020-05-22 | 慧荣科技股份有限公司 | Method, computer device and user interface for automated testing |
| CN111192620A (en) * | 2019-12-31 | 2020-05-22 | 山东华芯半导体有限公司 | Method for optimizing NAND Flash read reference voltage in SSD |
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