CN112804740B

CN112804740B - Method and device for adjusting antenna transmitting power and communication equipment

Info

Publication number: CN112804740B
Application number: CN202110293351.6A
Authority: CN
Inventors: 黄金煌
Original assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Current assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Priority date: 2021-03-19
Filing date: 2021-03-19
Publication date: 2021-07-09
Anticipated expiration: 2041-03-19
Also published as: CN112804740A

Abstract

The application relates to the technical field of communication, and discloses a method for adjusting antenna transmitting power, which comprises the following steps: acquiring a first clock signal; the first clock signal is used for triggering the antenna to transmit signals; adjusting a voltage amplitude of the first clock signal; and adjusting the transmitting power of the antenna according to the adjusted first clock signal. Compared with the existing method for adjusting the transmitting power of the antenna, the method for adjusting the transmitting power of the antenna has the advantages that the power adjustment can be realized without changing the parallel connection quantity of the power tubes, and is more convenient. The application also discloses a device and communication equipment for adjusting the transmitting power of the antenna.

Description

Method and device for adjusting antenna transmitting power and communication equipment

Technical Field

The present application relates to the field of wireless communication technologies, and for example, to a method and an apparatus for adjusting antenna transmission power, and a communication device.

Background

Wireless communication devices are now increasingly used in life. The antenna of the wireless communication device has different coupling coefficients at different distances, and the communication between the devices is very dependent on the field intensity and the transmitting power of the electromagnetic field, so that the communication distance and the communication quality can be effectively adjusted by adjusting the transmitting power of the wireless communication device. The power amplifier of the conventional wireless communication device adjusts the transmission power of the antenna by changing the parallel number of Metal Oxide Semiconductor (MOS) transistors, increases the parallel number of power transistors when the transmission power needs to be increased, and decreases the parallel number of power transistors when the transmission power needs to be decreased.

In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:

it is common for communication devices that the number of power transistors in the power conditioning circuit has been fixed, making it difficult to perform power conditioning by changing the number of power transistors of the same communication device.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview nor is intended to identify key/critical elements or to delineate the scope of such embodiments but rather as a prelude to the more detailed description that is presented later.

The embodiment of the disclosure provides a method and a device for adjusting antenna transmission power, and communication equipment, so as to adjust the antenna transmission power.

In some embodiments, a method for adjusting antenna transmit power comprises:

acquiring a first clock signal; the first clock signal is used for triggering the antenna to transmit signals;

adjusting a voltage amplitude of the first clock signal;

and adjusting the transmitting power of the antenna according to the adjusted first clock signal.

In some embodiments, an apparatus for adjusting antenna transmit power includes a processor and a memory storing program instructions, the processor configured to, when executing the program instructions, perform the method for adjusting antenna transmit power described above.

In some embodiments, the communication device comprises the above-described means for adjusting the transmit power of the antenna.

The method, the device and the communication equipment for adjusting the transmitting power of the antenna provided by the embodiment of the disclosure can realize the following technical effects:

compared with the existing method for adjusting the transmitting power of the antenna, the method for adjusting the transmitting power of the antenna has the advantages that the power adjustment can be realized without changing the parallel connection quantity of the power tubes, and is more convenient.

The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the accompanying drawings and not in limitation thereof, in which elements having the same reference numeral designations are shown as like elements and not in limitation thereof, and wherein:

fig. 1 is a schematic diagram of a method for adjusting antenna transmission power according to an embodiment of the present disclosure;

FIG. 2 is a circuit diagram of a power conditioning circuit provided by embodiments of the present disclosure;

fig. 3 is a schematic diagram of an apparatus for adjusting antenna transmission power according to an embodiment of the present disclosure.

Detailed Description

So that the manner in which the features and elements of the disclosed embodiments can be understood in detail, a more particular description of the disclosed embodiments, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.

The terms "first," "second," and the like in the description and in the claims, and the above-described drawings of embodiments of the present disclosure, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the present disclosure described herein may be made. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.

The term "plurality" means two or more unless otherwise specified.

In the embodiment of the present disclosure, the character "/" indicates that the preceding and following objects are in an or relationship. For example, A/B represents: a or B.

The term "and/or" is an associative relationship that describes objects, meaning that three relationships may exist. For example, a and/or B, represents: a or B, or A and B.

As shown in fig. 1, an embodiment of the present disclosure provides a method for adjusting antenna transmission power, including:

step S1, acquiring a first clock signal; the first clock signal is used for triggering the antenna to transmit signals;

step S2, adjusting the voltage amplitude of the first clock signal;

and step S3, adjusting the antenna transmitting power according to the adjusted first clock signal.

Compared with the existing method for adjusting the transmitting power of the antenna, the method for adjusting the transmitting power of the antenna can adjust the power without changing the parallel connection quantity of the power tubes, and is more convenient.

Optionally, the obtaining the first clock signal voltage comprises: acquiring a clock signal which is output by a clock signal source and used for triggering an antenna to transmit a signal, and determining the clock signal which is used for triggering the antenna to transmit the signal as a first clock signal. In some embodiments, the frequency of the clock signal is 13.56 MHz.

Optionally, the antenna is connected to a power adjusting module, and adjusting the antenna transmission power according to the adjusted first clock signal includes: and adjusting the equivalent resistance of the power adjusting module according to the adjusted first clock signal.

Optionally, the power adjusting module includes a PMOS transistor and an NMOS transistor, a drain of the PMOS transistor is connected to a drain of the NMOS transistor, the voltage amplitude of the first clock signal is adjusted to obtain a second clock signal, and adjusting the equivalent resistance of the power adjusting module according to the adjusted first clock signal includes: and under the condition that the source voltage of the PMOS tube is not changed, the grid voltage of the PMOS tube is changed according to the second clock signal. Therefore, the PMOS tube and the NMOS tube form the power amplifier, the VGS of the PMOS tube is adjusted by adjusting the grid voltage of the PMOS tube, the equivalent resistance of the PMOS tube is changed, and the effect of adjusting the transmitting power of the antenna is achieved. VGS is the absolute value of the voltage difference of the grid and the source of the MOS tube.

Optionally, the power adjusting module includes a PMOS transistor and an NMOS transistor, a drain of the PMOS transistor is connected to a drain of the NMOS transistor, the voltage amplitude of the first clock signal is adjusted to obtain a third clock signal, and adjusting the equivalent resistance of the power adjusting module according to the adjusted first clock signal includes: and under the condition that the source voltage of the NMOS tube is not changed, changing the grid voltage of the NMOS tube according to a third clock signal. Therefore, the PMOS tube and the NMOS tube form the power amplifier, and the VGS of the NMOS tube is adjusted by adjusting the grid voltage of the NMOS tube, so that the equivalent resistance of the NMOS tube is changed, and the effect of adjusting the transmitting power of the antenna is achieved. VGS is the absolute value of the voltage difference of the grid and the source of the MOS tube.

Optionally, the power adjusting module includes a PMOS transistor and an NMOS transistor, a drain of the PMOS transistor is connected to a drain of the NMOS transistor, a voltage amplitude of the first clock signal is adjusted to obtain a second clock signal and a third clock signal, and adjusting an equivalent resistance of the power adjusting module according to the adjusted first clock signal includes: under the condition that the source voltage of the PMOS tube is not changed, the grid voltage of the PMOS tube is changed according to the second clock signal; and under the condition that the source voltage of the NMOS tube is not changed, changing the grid voltage of the NMOS tube according to a third clock signal. Therefore, the PMOS tube and the NMOS tube form the power amplifier, the VGS of the PMOS tube and the NMOS tube is adjusted by adjusting the grid voltage of the PMOS tube and the NMOS tube, the equivalent resistance of the PMOS tube and the NMOS tube is changed, and the effect of adjusting the transmitting power of the antenna is achieved. VGS is the absolute value of the voltage difference of the grid and the source of the MOS tube.

Optionally, the PMOS transistor is further connected in parallel with a plurality of PMOS transistors. Optionally, the NMOS transistor is further connected in parallel with a plurality of NMOS transistors. Therefore, the equivalent resistance of the power adjusting module can be further adjusted by changing the parallel connection quantity of the PMOS tubes or the NMOS tubes, and the effect of adjusting the transmitting power of the antenna is achieved.

Optionally, adjusting the voltage amplitude of the first clock signal to obtain the second clock signal comprises: setting the source voltage of the PMOS tube as a power supply voltage; acquiring a first regulating voltage; the voltage value of the first regulating voltage is less than 0; and converting the low-level voltage value of the first clock signal into the voltage value of the first regulating voltage to obtain a second clock signal. Optionally, the high level voltage value of the first clock signal is unchanged. Optionally, a value range of the first adjustment voltage satisfies a first preset range. Optionally, the first preset range is a safe operating voltage range of the PMOS transistor. Optionally, the supply voltage is greater than 0.

Optionally, adjusting the voltage amplitude of the first clock signal to obtain a third clock signal includes: setting the source voltage of the NMOS tube to be 0; acquiring a second regulating voltage; the voltage value of the second regulating voltage is greater than the power supply voltage; and converting the high-level voltage value of the first clock signal into the voltage value of the second regulating voltage to obtain a third clock signal. Optionally, the low level voltage value of the first clock signal is unchanged. Optionally, a value range of the second adjustment voltage satisfies a second preset range. Optionally, the second preset range is a safe operating voltage range of the NMOS transistor. Optionally, the supply voltage is greater than 0.

Optionally, a first clock signal is obtained according to a power adjusting circuit, and the voltage amplitude of the first clock signal is adjusted; and then adjusting the transmitting power of the antenna according to the adjusted first clock signal.

As shown in fig. 2, optionally, the power conditioning circuit comprises: the circuit comprises a first level conversion module 1, a first charge pump 2, a first amplifier 3, a PMOS (P-channel metal oxide semiconductor) tube 4, a second level conversion module 5, a second charge pump 6, a second amplifier 7, an NMOS (N-channel metal oxide semiconductor) tube 8, a capacitor 9 and an inductance coil 10. The input end of the first charge pump 2 is connected with a power supply voltage, the output end of the first charge pump 2 is connected with the power supply input end of the first level conversion module 1 and the power supply output end of the first amplifier 3, the power supply voltage is subjected to voltage conversion through the first charge pump to obtain a first regulation voltage, and the first regulation voltage is supplied to the first level conversion module; the signal input end of the first level conversion module 1 is connected with a clock signal source, the signal output end of the first level conversion module 1 is connected with the input end of the first amplifier 3, the first level conversion module acquires a first clock signal output by the clock signal source, and changes the signal amplitude of the first clock signal through a first adjusting voltage to acquire a second clock signal; the power supply input end of the first amplifier 3 is connected with a power supply voltage, the output end of the first amplifier 3 is connected with the grid electrode of the PMOS tube 4, the driving capability of the second clock signal is enhanced through the first amplifier, and the output signal is transmitted to the grid electrode of the PMOS tube; the source electrode of the PMOS tube 4 is connected with power supply voltage, and under the condition that the source electrode voltage of the PMOS tube is not changed, the absolute value VGS of the voltage difference between the grid electrode and the source electrode of the PMOS tube is changed, so that the equivalent resistance of the PMOS tube is changed; the input end of the second charge pump 6 is connected with a power supply voltage, the output end of the second charge pump 6 is connected with the power supply input end of the second level conversion module 5 and the power supply input end of the second amplifier 7, the power supply voltage is subjected to voltage conversion through the second charge pump to obtain a second regulated voltage, and the second regulated voltage is supplied to the second level conversion module; a signal input end of the second level conversion module 5 is connected with a clock signal source, a signal output end of the second level conversion module 5 is connected with an input end of the second amplifier 7, the second level conversion module acquires a first clock signal output by the clock signal source, and changes the signal amplitude of the first clock signal through a first adjusting voltage to acquire a third clock signal; the power supply output end of the second amplifier 7 is grounded, the output end of the second amplifier 7 is connected with the grid electrode of the NMOS tube 8, the driving capability of a third clock signal is enhanced through the first amplifier, and the output signal is transmitted to the grid electrode of the NMOS tube; the source electrode of the NMOS tube 8 is grounded, the driving capability of the third clock signal is enhanced through the first amplifier, the first amplifier transmits the output signal to the grid electrode of the NMOS tube, and under the condition that the source electrode voltage of the NMOS tube is not changed, the absolute value VGS of the voltage difference between the grid electrode and the source electrode of the MOS tube is changed, so that the equivalent resistance of the NMOS tube is changed. The capacitor 9 is connected with the inductance coil 10 in parallel, one end of the inductance coil 10 is connected with the drain electrode of the NMOS tube, the other end of the inductance coil 10 is connected with the source electrode of the NMOS tube, and the drain electrode of the PMOS tube 4 is connected with the drain electrode of the NMOS tube 8. Optionally, the capacitor 9 and the inductance coil 10 form an antenna matching network, the PMOS transistor 4, the NMOS transistor 8, the capacitor 9, and the inductance coil 10 together form a CLASS D power amplifier, and the equivalent resistance of the PMOS transistor and the NMOS transistor is changed by adjusting the voltage amplitude of a clock signal for triggering the antenna to transmit a signal, so that the equivalent resistance of the CLASS D power amplifier is changed, and the effect of adjusting the transmitting power of the antenna is achieved.

In some embodiments, the first charge pump obtains a power supply voltage VBAT, converts VBAT to a first regulation voltage VNEG, where VNEG is less than 0, and the first level conversion module converts a low-level voltage value of the first clock signal CLKP to VNEG to obtain a second clock signal, where a voltage value of the second clock signal is from VNEG to VBAT; the source voltage of the PMOS tube is VBAT; under the condition that the voltage value of the second clock signal is VNEG, VGS of the PMOS tube is | VBAT-VNEG |; the second charge pump obtains a power supply voltage VBAT, converts the VBAT into a second regulation voltage VPOS, the VPOS is larger than the VBAT, the second level conversion module converts a high-level voltage value of the first clock signal CLKP into the VPOS, a third clock signal is obtained, and the amplitude of the voltage value of the third clock signal is 0-VPOS; the source voltage of the NMOS tube is 0; when the voltage value of the third clock signal is VPOS, VGS of the NMOS transistor is | VPOS |. Therefore, compared with the situation that VGS of the PMOS tube and the NMOS tube are | VBAT | before adjustment, the VGS of the PMOS tube and the NMOS tube is adjusted by adjusting the voltage of the first clock signal, so that equivalent resistance of the PMOS tube and the NMOS tube is changed, and the effect of adjusting the transmitting power of the antenna is achieved. VGS is the absolute value of the voltage difference of the grid and the source of the MOS tube.

In some embodiments, the voltage gain of the first amplifier and the second amplifier is 1. The first amplifier and the second amplifier are used as driving units to increase the driving capability of the circuit.

In the prior art, a power amplifier of a wireless communication device can adjust a voltage of a source of an MOS transistor by adding a DC/DC (direct current/direct current converter) circuit and an LDO (low dropout regulator) circuit, so as to achieve an effect of adjusting an antenna transmission power. However, since the current output of the MOS transistor becomes the load of the DC/DC circuit and the LDO circuit, the circuit has high power and resistance, and a large number of electronic components need to be integrated to ensure sufficient driving capability. By adopting the method for adjusting the transmitting power of the antenna provided by the embodiment of the disclosure, the voltage of the grid electrode of the MOS tube is adjusted to adjust the transmitting power, and the circuit has no high-power resistive load, thereby reducing the use of electronic elements and saving the chip area.

As shown in fig. 3, an apparatus for adjusting antenna transmission power according to an embodiment of the present disclosure includes a processor (processor) 100 and a memory (memory) 101. Optionally, the apparatus may also include a Communication Interface (Communication Interface) 102 and a bus 103. The processor 100, the communication interface 102, and the memory 101 may communicate with each other via a bus 103. The communication interface 102 may be used for information transfer. The processor 100 may invoke logic instructions in the memory 101 to perform the method for adjusting antenna transmit power of the above-described embodiments.

In addition, the logic instructions in the memory 101 may be implemented in the form of software functional units and stored in a computer readable storage medium when the logic instructions are sold or used as independent products.

The memory 101, which is a computer-readable storage medium, may be used for storing software programs, computer-executable programs, such as program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 100 executes functional applications and data processing, i.e. implements the method for adjusting the antenna transmission power in the above embodiments, by executing program instructions/modules stored in the memory 101.

The memory 101 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal device, and the like. In addition, the memory 101 may include a high-speed random access memory, and may also include a nonvolatile memory.

By adopting the device for adjusting the transmitting power of the antenna, the effect of adjusting the wireless transmitting power is realized by adjusting the voltage amplitude of the clock signal for triggering the antenna to transmit signals.

The embodiment of the present disclosure provides a communication device, which includes the above-mentioned apparatus for adjusting the antenna transmission power.

Optionally, the communication device is a near field communication device.

Optionally, the communication device comprises: the mobile phone with the NFC function, the tablet personal computer with the NFC function, the notebook personal computer with the NFC function and the like.

By adopting the communication equipment provided by the embodiment of the disclosure, the effect of adjusting the wireless transmitting power is realized by adjusting the voltage amplitude of the clock signal for triggering the antenna to transmit signals.

The above description and drawings sufficiently illustrate embodiments of the disclosure to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. Furthermore, the words used in the specification are words of description only and are not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, the terms "comprises" and/or "comprising," when used in this application, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Without further limitation, an element defined by the phrase "comprising an …" does not exclude the presence of other like elements in a process, method or apparatus that comprises the element. In this document, each embodiment may be described with emphasis on differences from other embodiments, and the same and similar parts between the respective embodiments may be referred to each other. For methods, products, etc. of the embodiment disclosures, reference may be made to the description of the method section for relevance if it corresponds to the method section of the embodiment disclosure.

Those of skill in the art would appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software may depend upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments. It can be clearly understood by the skilled person that, for convenience and brevity of description, the specific working processes of the system, the apparatus and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the embodiments disclosed herein, the disclosed methods, products (including but not limited to devices, apparatuses, etc.) may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units may be merely a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form. The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to implement the present embodiment. In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than disclosed in the description, and sometimes there is no specific order between the different operations or steps. For example, two sequential operations or steps may in fact be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. Each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Claims

1. A method for adjusting antenna transmit power, the method comprising:

adjusting a voltage amplitude of the first clock signal;

adjusting the transmitting power of the antenna according to the adjusted first clock signal;

the antenna connection has power adjustment module, carries out the regulation of antenna transmission power according to the first clock signal after the regulation, includes:

and adjusting the equivalent resistance of the power adjusting module according to the adjusted first clock signal.

2. The method of claim 1, wherein obtaining the first clock signal voltage comprises:

acquiring a clock signal which is output by a clock signal source and used for triggering the antenna to transmit signals, and determining the clock signal which is used for triggering the antenna to transmit signals as a first clock signal.

3. The method of claim 1, wherein the power adjustment module comprises a PMOS transistor and an NMOS transistor, a drain of the PMOS transistor is connected to a drain of the NMOS transistor, the voltage amplitude of the first clock signal is adjusted to obtain a second clock signal, and an equivalent resistance of the power adjustment module is adjusted according to the adjusted first clock signal, and the method comprises:

and under the condition that the source voltage of the PMOS tube is not changed, changing the grid voltage of the PMOS tube according to the second clock signal.

4. The method of claim 1, wherein the power adjustment module comprises a PMOS transistor and an NMOS transistor, a drain of the PMOS transistor is connected to a drain of the NMOS transistor, the voltage amplitude of the first clock signal is adjusted to obtain a third clock signal, and an equivalent resistance of the power adjustment module is adjusted according to the adjusted first clock signal, and the method comprises:

and under the condition that the source voltage of the NMOS tube is not changed, changing the grid voltage of the NMOS tube according to the third clock signal.

5. The method of claim 1, wherein the power adjustment module comprises a PMOS transistor and an NMOS transistor, a drain of the PMOS transistor is connected to a drain of the NMOS transistor, the voltage amplitude of the first clock signal is adjusted to obtain a second clock signal and a third clock signal, and an equivalent resistance of the power adjustment module is adjusted according to the adjusted first clock signal, comprising:

under the condition that the source voltage of the PMOS tube is not changed, the grid voltage of the PMOS tube is changed according to the second clock signal;

6. The method of claim 3 or 5, wherein adjusting the voltage amplitude of the first clock signal to obtain a second clock signal comprises:

setting the source voltage of the PMOS tube as a power supply voltage;

acquiring a first regulating voltage; the voltage value of the first regulating voltage is less than 0;

and converting the low-level voltage value of the first clock signal into the voltage value of the first regulating voltage to obtain a second clock signal.

7. The method of claim 4 or 5, wherein adjusting the voltage amplitude of the first clock signal to obtain a third clock signal comprises:

setting the source voltage of the NMOS tube to be 0;

acquiring a second regulating voltage; the voltage value of the second regulating voltage is greater than the power supply voltage;

and converting the high-level voltage value of the first clock signal into the voltage value of the second regulating voltage to obtain a third clock signal.

8. An apparatus for adjusting antenna transmit power, comprising a processor and a memory storing program instructions, wherein the processor is configured to perform a method for adjusting antenna transmit power according to any one of claims 1 to 7 when executing the program instructions.

9. A communication device comprising the apparatus for adjusting antenna transmit power of claim 8.