CN112802760A - Multi-chip semiconductor package and forming method thereof - Google Patents
Multi-chip semiconductor package and forming method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
Abstract
The invention relates to a multi-chip semiconductor package and a forming method thereof, wherein in the process of curing a plastic packaging resin layer, silicon dangling bonds generated in the curing process of a silicon-based transistor can be effectively inhibited through segmented curing, the silicon dangling bonds are fully generated by the silicon-based transistor in the oxygen atmosphere, oxygen is completely discharged through the heat treatment process in the nitrogen atmosphere, and then the subsequent curing process is fully subjected to heat treatment through different hydrogen atmospheres, so that the silicon dangling bonds on the surface of the silicon-based transistor are fully converted into silicon hydrogen bonds, and the stability of the silicon-based transistor is further effectively improved.
Description
Technical Field
The present invention relates to the field of chip packaging, and more particularly to a multi-chip semiconductor package and a method of forming the same.
Background
Semiconductor packaging technology has been developed along with the present invention of integrated circuits, and has the main functions of completing power distribution, signal distribution, rapid heat dissipation, chip protection, and the like. With the development of semiconductor chip technology, the corresponding semiconductor packaging technology is also continuously being innovated. The packaging interconnection density is continuously improved, the packaging thickness is continuously reduced, and the three-dimensional packaging and system packaging means is continuously evolved. With the diversification of the application of integrated circuits, the rapid development of emerging fields such as intelligent portable equipment, the internet of things, automotive electronics, cloud computing, 5G technology, artificial intelligence and the like also puts higher requirements on advanced packaging. The multi-chip three-dimensional semiconductor packaging process relates to a plastic packaging process and a heat treatment process for post-curing a plastic packaging layer, a conventional curing process usually causes silicon dangling bonds on the surface of a silicon-based chip, so that the stability of the silicon-based chip is reduced.
Disclosure of Invention
The invention provides a multi-chip semiconductor package and a forming method thereof, aiming at solving the technical problem that in the prior art, a multi-chip package structure leads to the generation of silicon dangling bonds in the curing process of a plastic package layer, and further causes the stability of the multi-chip package structure to be reduced.
In one aspect, a method for forming a multi-chip semiconductor package structure includes the following steps.
Step (1), providing a first carrier substrate, and arranging a first semiconductor chip on the first carrier substrate.
And (2) bonding a second semiconductor chip on the first semiconductor chip, wherein the length and the width of the second semiconductor chip are respectively smaller than those of the first semiconductor chip, and the first semiconductor chip and/or the second semiconductor chip comprise silicon-based transistors.
And (3) next, arranging a patterned mask on the first carrier substrate, wherein the patterned mask comprises a first opening and a second opening, the first opening exposes a part of the upper surface of the first semiconductor chip, and the second opening exposes a part of the upper surface of the first carrier substrate.
And (4) forming a first metal column in the first opening and a second metal column in the second opening, wherein the first metal column is used for conducting heat generated by the first semiconductor chip, and the second metal column is used for electric connection, and removing the patterned mask.
And (5) arranging a plastic package resin layer on the first carrier substrate, wherein the plastic package resin layer wraps the first semiconductor chip, the second semiconductor chip, the first metal column and the second metal column.
And (6) curing the plastic package resin layer, wherein the curing specifically comprises the following steps: step a1 is performed first: heat treating in an oxygen-containing atmosphere for a first period of time; then, step a2 is performed: heat treating in a nitrogen atmosphere for a second period of time; then, step a3 is performed: heat treating in a first hydrogen atmosphere for a third period of time; then, step a4 is performed: heat treating in a second hydrogen atmosphere for a fourth time period; then, step a5 is performed: heat treating in a nitrogen atmosphere for a fifth period of time; then, step a6 is performed: heat treating in a third hydrogen atmosphere for a sixth period of time; then, step a7 is performed: heat-treating in a nitrogen atmosphere for a seventh period of time; wherein the first time period is greater than the second time period, the third time period is less than the fourth time period, and the third time period is greater than the sixth time period.
And (7) arranging a first mask on the plastic package resin layer, and etching a part of the second metal column by using the first mask so as to enable one end of the second metal column to be recessed into the plastic package resin layer.
And (8) forming a first redistribution layer on the plastic-sealed resin layer, wherein the second metal pillar is electrically connected with the first redistribution layer, the first metal pillar is not electrically connected with the first redistribution layer, and the first redistribution layer does not cover the first metal pillar.
And (9) arranging a second carrier substrate on the first rewiring layer, removing the first carrier substrate to expose the plastic package resin layer, arranging a second mask on the plastic package resin layer, and etching a part of the second metal column by using the second mask to enable the other end of the second metal column to be recessed into the plastic package resin layer.
And (10) forming a second re-wiring layer above the first semiconductor chip, the second metal column and the plastic-sealed resin layer, wherein the first semiconductor chip and the second metal column are electrically connected with the second re-wiring layer, forming a conductive solder ball on the second re-wiring layer, and removing the second carrier substrate.
According to one embodiment of the present invention, in the step (3), before the patterned mask is disposed on the first carrier substrate, a first metal seed layer is formed on the upper surface of the first carrier substrate, the upper surface and the side surfaces of the first semiconductor chip, and the upper surface and the side surfaces of the second semiconductor chip.
According to an embodiment of the present invention, a plurality of second metal seed protrusions are then formed on the first metal seed layer, the plurality of second metal seed protrusions being formed in advance at positions where the first openings and the second openings are to be formed.
According to an embodiment of the present invention, a width of the second metal seed protrusion is smaller than a width of the first opening or a width of the second opening, the second metal seed protrusion is located in a middle region of the first opening or a middle region of the second opening, and an included angle between a side surface of the second metal seed protrusion and a bottom surface of the second metal seed protrusion is 30 to 60 degrees.
According to one embodiment of the present invention, in the step (6), the temperature of each heat treatment is 200-300 ℃.
According to an embodiment of the present invention, in the step a1, the flow rate of the oxygen is 1000sccm to 2000sccm, and the first time period is 20 to 30 minutes; in the step a2, the flow rate of nitrogen is 2000 sccm-4000 sccm, and the second time period is 10-20 minutes; in the step a3, the flow rate of hydrogen in the first hydrogen atmosphere is 800sccm to 1500sccm, and the third time period is 30 to 50 minutes; in the step a4, the flow rate of hydrogen in the second hydrogen atmosphere is 2000sccm to 3000sccm, and the fourth time period is 60 to 100 minutes; in the step a5, the flow rate of nitrogen is 2000 sccm-4000 sccm, and the fifth time period is 10-20 minutes; in the step a6, the flow rate of hydrogen in the third hydrogen atmosphere is 4000sccm to 5000sccm, and the sixth time period is 10 to 20 minutes; in the step a7, the flow rate of the nitrogen gas is 2000sccm to 4000sccm, and the seventh time period is 10 to 20 minutes.
According to one embodiment of the present invention, each of the first and second redistribution layers includes a plurality of dielectric layers and a plurality of metallization pattern layers located between the plurality of dielectric layers, and the dielectric layers include one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and zirconium oxide.
On the other hand, the invention also provides a multi-chip semiconductor packaging structure which is formed by adopting the method.
The invention has the beneficial effects that:
the invention provides a novel multi-chip semiconductor package and a forming method thereof, wherein a first metal column and a second metal column are formed at the same time, the first metal column is used for conducting heat generated by a first semiconductor chip, and the second metal column is used for electric connection, so that the multi-chip semiconductor package has rich electric connection functions and is provided with an independent heat dissipation metal column, and further heat generated by the first semiconductor chip can be quickly transferred. Simultaneously, in the process of carrying out curing treatment on the plastic package resin layer, the curing treatment specifically comprises the following steps: step a1 is performed first: heat treating in an oxygen-containing atmosphere for a first period of time; then, step a2 is performed: heat treating in a nitrogen atmosphere for a second period of time; then, step a3 is performed: heat treating in a first hydrogen atmosphere for a third period of time; then, step a4 is performed: heat treating in a second hydrogen atmosphere for a fourth time period; then, step a5 is performed: heat treating in a nitrogen atmosphere for a fifth period of time; then, step a6 is performed: heat treating in a third hydrogen atmosphere for a sixth period of time; then, step a7 is performed: heat-treating in a nitrogen atmosphere for a seventh period of time; the first time period is greater than the second time period, the third time period is less than the fourth time period, the third time period is greater than the sixth time period, and the concrete process of optimizing curing treatment can effectively inhibit the silicon-based transistor from generating silicon dangling bonds in the curing process.
Drawings
FIG. 1 is a cross-sectional view of step (1) of the method of forming a multi-chip semiconductor package of the present invention.
FIG. 2 is a cross-sectional view of step (2) of the method of forming a multi-chip semiconductor package of the present invention.
FIG. 3 is a cross-sectional view of step (3) of the method of forming a multi-chip semiconductor package of the present invention.
Fig. 4 is a cross-sectional view of step (4) of the method of forming a multi-chip semiconductor package of the present invention.
Fig. 5 is a cross-sectional view illustrating step (5) and step (6) of the method of forming a multi-chip semiconductor package according to the present invention.
Fig. 6 is a cross-sectional view of step (7) of the method of forming a multi-chip semiconductor package of the present invention.
Fig. 7 is a cross-sectional view of step (8) of the method of forming a multi-chip semiconductor package of the present invention.
Fig. 8 is a cross-sectional view of step (9) of the method of forming a multi-chip semiconductor package of the present invention.
Fig. 9 is a cross-sectional view of step (10) of the method of forming a multi-chip semiconductor package of the present invention.
Detailed Description
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements thereof are described below to simplify the description of the disclosure. These are, of course, merely examples and are not intended to limit the disclosure. For example, the following disclosure describes forming a first feature over or on a second feature, including embodiments in which the first feature and the second feature are formed in direct contact, and also including embodiments in which additional features may be formed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact. In addition, various examples of the disclosure may use repeated reference characters and/or wording. The repeated symbols or words are for purposes of simplicity and clarity, and
and are not intended to limit the relationship between the various embodiments and/or the appearance structures.
Furthermore, spatially relative terms, such as "under", "below", "lower", "over", "upper" and the like, may be used herein for convenience in describing the relationship of one element or component to another element(s) or component(s) in the figures. Spatially relative terms may also encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
Please refer to fig. 1 to 9. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1 to 9, the present embodiment provides a multi-chip semiconductor package and a method of forming the same.
In a specific embodiment, as shown in fig. 1, step (1) is performed first, a first carrier substrate 100 is provided, and a first semiconductor chip 101 is disposed on the first carrier substrate 100.
In a specific embodiment, a semiconductor wafer may be provided, and then the semiconductor wafer is cut to form a plurality of first semiconductor chips 101, the specific cutting process is laser cutting, plasma cutting or mechanical saw cutting, the cut first semiconductor chips 101 are tested, the chips with normal electrical functions passing the test are used for subsequent packaging, the chips without passing the test are repaired and then applied to subsequent packaging, and the chips which cannot be repaired are discarded, so as to sufficiently save the packaging cost.
In a specific implementation, the first semiconductor chip 101 is attached to the first carrier substrate 100 in such a way that the front surface of the first semiconductor chip 101 faces the first carrier substrate 100, and in order to improve the packaging efficiency during the packaging process, a plurality of first semiconductor chips 101 arranged at intervals may be disposed on the first carrier substrate 100, so as to form a plurality of packages. Each first semiconductor chip 101 corresponds to a relatively large area of the first carrier substrate 100 for ease of packaging. The first carrier substrate 100 may be a glass carrier substrate, a ceramic carrier substrate, a semiconductor substrate, or a metal carrier substrate.
In a specific embodiment, the first semiconductor chip 101 may be attached to the first carrier substrate 100 by a temporary bonding layer, which may facilitate peeling of the first carrier substrate 100 in a subsequent process by losing adhesion.
As shown in fig. 2, step (2) is performed, and then a second semiconductor chip 102 is bonded on the first semiconductor chip 101, wherein the length and the width of the second semiconductor chip 102 are smaller than those of the first semiconductor chip 101, respectively, and the first semiconductor chip 101 and/or the second semiconductor chip 102 include silicon-based transistors.
In an exemplary embodiment, the second semiconductor chip 102 may have a similar structure to the first semiconductor chip 101, and similarly, the second semiconductor chip 102 is formed by a wafer dicing.
In a specific embodiment, the front surface of the second semiconductor chip 102 faces the back surface of the first semiconductor chip 101, the back surface of the first semiconductor chip 101 also has a conductive structure, and the first semiconductor chip 101 and the second semiconductor chip 102 are hybrid bonded, so that the first semiconductor chip 101 and the second semiconductor chip 102 are electrically connected.
As shown in fig. 3, next to step (3), before the patterned mask is disposed on the first carrier substrate 100, a first metal seed layer 103 is formed on the upper surface of the first carrier substrate 100, the upper surface and the side surfaces of the first semiconductor chip 101, and the upper surface and the side surfaces of the second semiconductor chip 102; next, a plurality of second metal seed protrusions 104 are formed on the first metal seed layer 103, and a plurality of the second metal seed protrusions 104 are formed in advance at positions where the first openings and the second openings are to be formed. Next, a patterned mask 105 is disposed on the first carrier substrate 100, the patterned mask 105 including a first opening 1051 and a second opening 1052, the first opening 1051 exposing a portion of the upper surface of the first semiconductor chip 101, the second opening 1052 exposing a portion of the upper surface of the first carrier substrate 100.
The width of the second metal seed protrusion 104 is smaller than the width of the first opening 1051 or the width of the second opening 1052, the second metal seed protrusion 104 is located in the middle area of the first opening 1051 or the middle area of the second opening 1052, and an included angle between the side surface of the second metal seed protrusion 104 and the bottom surface of the second metal seed protrusion 104 is 30-60 degrees.
In a specific embodiment, the first metal seed layer 103 and the second metal seed protrusion 104 may be a single layer structure or a plurality of layers formed by different metal materials, more specifically, the material of the first metal seed layer 103 and the second metal seed protrusion 104 is one or more of titanium, nickel, palladium, aluminum, cobalt, chromium, and copper, more specifically, the first metal seed layer 103 and the second metal seed protrusion 104 are a titanium/nickel/copper laminated structure, the total thickness of the first metal seed layer 103 is 80-200 nm, the ratio of the thickness of the second metal seed protrusion to the thickness of the first metal seed layer 103 is 1.5-3, the ratio of the width of the second metal seed protrusion to the widths of the first and second openings is 0.4-0.6, and the included angle between the side surface of the second metal seed protrusion 104 and the bottom surface of the second metal seed protrusion 104 is 30-60 degrees, more specifically, the total thickness of the first metal seed layer 103 is 150 nm, the ratio of the thickness of the second metal seed protrusion to the thickness of the first metal seed layer 103 is 2, the ratio of the width of the second metal seed protrusion to the widths of the first and second openings is 0.5, and the included angle between the side surface of the second metal seed protrusion 104 and the bottom surface of the second metal seed protrusion 104 is 45 degrees, the above-mentioned dimension setting can facilitate the formation of the subsequent first metal pillar and second metal pillar, due to the existence of the second metal seed protrusion 104, in the process of forming the first metal pillar and second metal pillar by subsequent electroplating, the electroplated metal material is more easily deposited in the middle area of the first and second openings, thereby avoiding the occurrence of voids in the first metal pillar and second metal pillar, and further improving the compactness of the first metal pillar and second metal pillar, so as to improve the heat conduction effect of the first metal column.
In a specific embodiment, the patterned mask 105 may be a photoresist layer.
As shown in fig. 4, step (4) is performed, and then a first metal pillar 1061 is formed in the first opening 1051 and a second metal pillar 1062 is formed in the second opening 1052, wherein the first metal pillar 1061 is used for conducting heat generated by the first semiconductor chip 101 and the second metal pillar 1062 is used for electrical connection.
In a specific embodiment, the first metal pillar 1061 and the second metal pillar 1062 are formed by an electroplating process, and the material of the first metal pillar 1061 and the second metal pillar 1062 is copper, aluminum, titanium, or other metal materials.
As shown in fig. 5, step (5) is performed, and then a molding resin layer 106 is disposed on the first carrier substrate 100, where the molding resin layer 106 wraps the first semiconductor chip 101, the second semiconductor chip 102, the first metal posts 1061, and the second metal posts 1062.
In a specific embodiment, the patterned mask 105 is removed first, and then the metal seed layer not covered by the first and second metal pillars 1061 and 1062 is removed. The molding resin layer 106 may be an epoxy resin, and may be specifically prepared by compression molding, transfer molding, or other processes. The mold resin layer 106 is injected into the mold in a liquid form, so that the first semiconductor chip 101, the second semiconductor chip 102, the first metal posts 1061, and the second metal posts 1062 are wrapped with the liquid resin.
And (6) curing the plastic-sealed resin layer 106, wherein the curing treatment specifically comprises the following steps: placing the package in a sealed chamber, and firstly performing step a 1: heat treating in an oxygen-containing atmosphere for a first period of time; then, step a2 is performed: heat treating in a nitrogen atmosphere for a second period of time; then, step a3 is performed: heat treating in a first hydrogen atmosphere for a third period of time; then, step a4 is performed: heat treating in a second hydrogen atmosphere for a fourth time period; then, step a5 is performed: heat treating in a nitrogen atmosphere for a fifth period of time; then, step a6 is performed: heat treating in a third hydrogen atmosphere for a sixth period of time; then, step a7 is performed: heat-treating in a nitrogen atmosphere for a seventh period of time; wherein the first time period is greater than the second time period, the third time period is less than the fourth time period, and the third time period is greater than the sixth time period.
In a specific embodiment, in the step (6), the temperature of each heat treatment is 200-300 ℃. In the step a1, the flow rate of oxygen is 1000sccm to 2000sccm, and the first time period is 20 to 30 minutes; in the step a2, the flow rate of nitrogen is 2000 sccm-4000 sccm, and the second time period is 10-20 minutes; in the step a3, the flow rate of hydrogen in the first hydrogen atmosphere is 800sccm to 1500sccm, and the third time period is 30 to 50 minutes; in the step a4, the flow rate of hydrogen in the second hydrogen atmosphere is 2000sccm to 3000sccm, and the fourth time period is 60 to 100 minutes; in the step a5, the flow rate of nitrogen is 2000 sccm-4000 sccm, and the fifth time period is 10-20 minutes; in the step a6, the flow rate of hydrogen in the third hydrogen atmosphere is 4000sccm to 5000sccm, and the sixth time period is 10 to 20 minutes; in the step a7, the flow rate of the nitrogen gas is 2000sccm to 4000sccm, and the seventh time period is 10 to 20 minutes.
In a specific embodiment, the curing treatment specifically includes: placing the package in a sealed chamber, and firstly performing step a 1: performing heat treatment in an oxygen-containing atmosphere for a first time period, wherein the sealed chamber is vacuumized, then oxygen is introduced, the flow rate of the oxygen is 1000 sccm-2000 sccm, then the first time period of the heat treatment is 20-30 minutes, the temperature of the heat treatment is 200-300 ℃, in a specific embodiment, the flow rate of the oxygen is 1500sccm, the first time period is 25 minutes, and the temperature of the heat treatment is 260 ℃.
Then, the oxygen in the chamber is exhausted, so as to vacuumize the chamber, and then the step a2 is performed: performing heat treatment in a nitrogen atmosphere for a second time period, vacuumizing, introducing nitrogen at a flow rate of 2000 sccm-4000 sccm, performing heat treatment for the second time period of 10-20 minutes at a temperature of 200-300 ℃, wherein in the specific embodiment, the flow rate of nitrogen is 3000sccm, the second time period is 15 minutes, and the heat treatment temperature is 260 ℃.
Then, the nitrogen gas in the chamber is exhausted, so that the chamber is vacuumized, and then the step a3 is carried out: heat treating in a first hydrogen atmosphere for a third period of time; and introducing hydrogen after vacuumizing, wherein the flow rate of the hydrogen in the first hydrogen atmosphere is 800 sccm-1500 sccm, the third time period is 30-50 minutes, the heat treatment temperature is 200-300 ℃, in a specific embodiment, the flow rate of the hydrogen in the first hydrogen atmosphere is 1200sccm, the third time period is 40 minutes, and the heat treatment temperature is 260 ℃.
Then, step a4 is performed: directly introducing second hydrogen into the sealed chamber, and performing heat treatment in a second hydrogen atmosphere for a fourth time period, wherein the flow rate of the hydrogen in the second hydrogen atmosphere is 2000sccm to 3000sccm, the fourth time period is 60 minutes to 100 minutes, the heat treatment temperature is 200-300 ℃, in a specific embodiment, the flow rate of the hydrogen in the second hydrogen atmosphere is 2500sccm, the fourth time period is 80 minutes, and the heat treatment temperature is 260 ℃.
Then, the hydrogen gas in the chamber is exhausted and vacuumized, and then the nitrogen gas is introduced, and then the step a5 is carried out: heat-treating in nitrogen atmosphere for a fifth time period of 2000 sccm-4000 sccm at a temperature of 200-300 deg.C for 10-20 min, wherein the nitrogen flow is 2500sccm, the fourth time period is 80 min, and the heat-treating temperature is 260 deg.C.
Then the chamber was evacuated and evacuated of nitrogen, then hydrogen was introduced, and then the process proceeded to step a 6: and performing heat treatment in a third hydrogen atmosphere for a sixth time period, wherein the flow rate of hydrogen in the third hydrogen atmosphere is 4000sccm to 5000sccm, the sixth time period is 10 to 20 minutes, the heat treatment temperature is 200-300 ℃, in a specific embodiment, the flow rate of hydrogen in the third hydrogen atmosphere is 4500sccm, the sixth time period is 15 minutes, and the heat treatment temperature is 260 ℃.
Then the hydrogen in the chamber is exhausted and vacuumized, then nitrogen is introduced, and then the step a7 is carried out: and (3) performing heat treatment in a nitrogen atmosphere for a seventh time period, wherein the flow rate of the nitrogen is 2000 sccm-4000 sccm, the seventh time period is 10-20 minutes, the heat treatment temperature is 200-300 ℃, in a specific embodiment, the flow rate of the nitrogen is 3000sccm, the seventh time period is 15 minutes, and the heat treatment temperature is 260 ℃.
By the curing process, the silicon dangling bonds on the surface of the silicon-based transistor can be fully converted into silicon-hydrogen bonds, so that the stability of the silicon-based transistor is effectively improved
As shown in fig. 6, step (7) is performed, a first mask 107 is then disposed on the molding resin layer 106, a portion of the second metal stud 1062 is etched by using the first mask 107, such that one end of the second metal stud 1062 is recessed into the molding resin layer 106, and then the first mask 107 (not shown) is removed.
In a specific embodiment, the plastic package resin layer 106 is thinned to expose the surfaces of the first metal posts 1061 and the second metal posts 1062, then a first mask 107 is disposed on the plastic package resin layer 106, the first mask 107 may be made of a suitable material, and then a part of the second metal posts 1062 is removed by wet etching or dry etching.
As shown in fig. 7, step (8) is performed, and then a first redistribution layer 108 is formed on the molding resin layer 106, the second metal pillars 1062 are electrically connected to the first redistribution layer 108, the first metal pillars 1061 are not electrically connected to the first redistribution layer 108, and the first redistribution layer 108 does not cover the first metal pillars 1061, so that heat can be directly transferred out.
The first redistribution layer 108 includes a plurality of dielectric layers and a plurality of metallization pattern layers located between the plurality of dielectric layers, where the dielectric layers include one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and zirconium oxide.
As shown in fig. 8, step (9) is performed, then a second carrier substrate 109 is disposed on the first redistribution layer 108, then the first carrier substrate 100 is removed to expose the molding resin layer 106, then a second mask 110 is disposed on the molding resin layer 106, a portion of the second metal stud 1062 is etched using the second mask 110, so that the other end of the second metal stud 1062 is also recessed into the molding resin layer 106, and then the second mask 110 is removed.
In a specific embodiment, the second carrier substrate 109 may be a glass carrier substrate, a ceramic carrier substrate, a semiconductor substrate, or a metal carrier substrate. The second mask 110 may be formed of a suitable material, and then a portion of the second metal pillar 1062 may be removed by wet etching or dry etching.
As shown in fig. 9, step (10) is performed, a second redistribution layer 111 is formed over the first semiconductor chip 101, the second metal pillar 1062, and the molding resin layer 106, the first semiconductor chip 101 and the second metal pillar 1062 are electrically connected to the second redistribution layer 111, a conductive solder ball 112 is formed on the second redistribution layer 111, and the second carrier substrate 109 is removed.
In a specific embodiment, the second redistribution layer 111 includes multiple dielectric layers and multiple metallization pattern layers located between the multiple dielectric layers, where the dielectric layers include one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and zirconium oxide.
As shown in fig. 9, the present invention further provides a multi-chip semiconductor package structure formed by the above method.
In another embodiment, the present invention provides a method for forming a multi-chip semiconductor package structure, which includes the following steps.
Step (1), providing a first carrier substrate, and arranging a first semiconductor chip on the first carrier substrate.
And (2) bonding a second semiconductor chip on the first semiconductor chip, wherein the length and the width of the second semiconductor chip are respectively smaller than those of the first semiconductor chip, and the first semiconductor chip and/or the second semiconductor chip comprise silicon-based transistors.
And (3) next, arranging a patterned mask on the first carrier substrate, wherein the patterned mask comprises a first opening and a second opening, the first opening exposes a part of the upper surface of the first semiconductor chip, and the second opening exposes a part of the upper surface of the first carrier substrate.
And (4) forming a first metal column in the first opening and a second metal column in the second opening, wherein the first metal column is used for conducting heat generated by the first semiconductor chip, and the second metal column is used for electric connection, and removing the patterned mask.
And (5) arranging a plastic package resin layer on the first carrier substrate, wherein the plastic package resin layer wraps the first semiconductor chip, the second semiconductor chip, the first metal column and the second metal column.
And (6) curing the plastic package resin layer, wherein the curing specifically comprises the following steps: step a1 is performed first: heat treating in an oxygen-containing atmosphere for a first period of time; then, step a2 is performed: heat treating in a nitrogen atmosphere for a second period of time; then, step a3 is performed: heat treating in a first hydrogen atmosphere for a third period of time; then, step a4 is performed: heat treating in a second hydrogen atmosphere for a fourth time period; then, step a5 is performed: heat treating in a nitrogen atmosphere for a fifth period of time; then, step a6 is performed: heat treating in a third hydrogen atmosphere for a sixth period of time; then, step a7 is performed: heat-treating in a nitrogen atmosphere for a seventh period of time; wherein the first time period is greater than the second time period, the third time period is less than the fourth time period, and the third time period is greater than the sixth time period.
And (7) arranging a first mask on the plastic package resin layer, and etching a part of the second metal column by using the first mask so as to enable one end of the second metal column to be recessed into the plastic package resin layer.
And (8) forming a first redistribution layer on the plastic-sealed resin layer, wherein the second metal pillar is electrically connected with the first redistribution layer, the first metal pillar is not electrically connected with the first redistribution layer, and the first redistribution layer does not cover the first metal pillar.
And (9) arranging a second carrier substrate on the first rewiring layer, removing the first carrier substrate to expose the plastic package resin layer, arranging a second mask on the plastic package resin layer, and etching a part of the second metal column by using the second mask to enable the other end of the second metal column to be recessed into the plastic package resin layer.
And (10) forming a second re-wiring layer above the first semiconductor chip, the second metal column and the plastic-sealed resin layer, wherein the first semiconductor chip and the second metal column are electrically connected with the second re-wiring layer, forming a conductive solder ball on the second re-wiring layer, and removing the second carrier substrate.
According to one embodiment of the present invention, in the step (3), before the patterned mask is disposed on the first carrier substrate, a first metal seed layer is formed on the upper surface of the first carrier substrate, the upper surface and the side surfaces of the first semiconductor chip, and the upper surface and the side surfaces of the second semiconductor chip.
According to an embodiment of the present invention, a plurality of second metal seed protrusions are then formed on the first metal seed layer, the plurality of second metal seed protrusions being formed in advance at positions where the first openings and the second openings are to be formed.
According to an embodiment of the present invention, a width of the second metal seed protrusion is smaller than a width of the first opening or a width of the second opening, the second metal seed protrusion is located in a middle region of the first opening or a middle region of the second opening, and an included angle between a side surface of the second metal seed protrusion and a bottom surface of the second metal seed protrusion is 30 to 60 degrees.
According to one embodiment of the present invention, in the step (6), the temperature of each heat treatment is 200-300 ℃.
According to an embodiment of the present invention, in the step a1, the flow rate of the oxygen is 1000sccm to 2000sccm, and the first time period is 20 to 30 minutes; in the step a2, the flow rate of nitrogen is 2000 sccm-4000 sccm, and the second time period is 10-20 minutes; in the step a3, the flow rate of hydrogen in the first hydrogen atmosphere is 800sccm to 1500sccm, and the third time period is 30 to 50 minutes; in the step a4, the flow rate of hydrogen in the second hydrogen atmosphere is 2000sccm to 3000sccm, and the fourth time period is 60 to 100 minutes; in the step a5, the flow rate of nitrogen is 2000 sccm-4000 sccm, and the fifth time period is 10-20 minutes; in the step a6, the flow rate of hydrogen in the third hydrogen atmosphere is 4000sccm to 5000sccm, and the sixth time period is 10 to 20 minutes; in the step a7, the flow rate of the nitrogen gas is 2000sccm to 4000sccm, and the seventh time period is 10 to 20 minutes.
According to one embodiment of the present invention, each of the first and second redistribution layers includes a plurality of dielectric layers and a plurality of metallization pattern layers located between the plurality of dielectric layers, and the dielectric layers include one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and zirconium oxide.
According to an embodiment of the present invention, the present invention further provides a multi-chip semiconductor package structure formed by the above method.
The invention has the beneficial effects that:
the invention provides a novel multi-chip semiconductor package and a forming method thereof, wherein a first metal column and a second metal column are formed at the same time, the first metal column is used for conducting heat generated by a first semiconductor chip, and the second metal column is used for electric connection, so that the multi-chip semiconductor package has rich electric connection functions and is provided with an independent heat dissipation metal column, and further heat generated by the first semiconductor chip can be quickly transferred. Simultaneously, in the process of carrying out curing treatment on the plastic package resin layer, the curing treatment specifically comprises the following steps: step a1 is performed first: heat treating in an oxygen-containing atmosphere for a first period of time; then, step a2 is performed: heat treating in a nitrogen atmosphere for a second period of time; then, step a3 is performed: heat treating in a first hydrogen atmosphere for a third period of time; then, step a4 is performed: heat treating in a second hydrogen atmosphere for a fourth time period; then, step a5 is performed: heat treating in a nitrogen atmosphere for a fifth period of time; then, step a6 is performed: heat treating in a third hydrogen atmosphere for a sixth period of time; then, step a7 is performed: heat-treating in a nitrogen atmosphere for a seventh period of time; the first time period is greater than the second time period, the third time period is less than the fourth time period, the third time period is greater than the sixth time period, and the concrete process of optimizing curing treatment can effectively inhibit the silicon-based transistor from generating silicon dangling bonds in the curing process.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A method for forming a multi-chip semiconductor packaging structure is characterized in that: the method comprises the following steps:
(1) providing a first carrier substrate, and arranging a first semiconductor chip on the first carrier substrate;
(2) then bonding a second semiconductor chip on the first semiconductor chip, wherein the length and the width of the second semiconductor chip are respectively smaller than those of the first semiconductor chip, and the first semiconductor chip and/or the second semiconductor chip comprise silicon-based transistors;
(3) then, a patterned mask is arranged on the first carrier substrate, wherein the patterned mask comprises a first opening and a second opening, the first opening exposes a part of the upper surface of the first semiconductor chip, and the second opening exposes a part of the upper surface of the first carrier substrate;
(4) then forming a first metal pillar in the first opening, forming a second metal pillar in the second opening, wherein the first metal pillar is used for conducting heat generated by the first semiconductor chip, the second metal pillar is used for electric connection, and then removing the patterned mask;
(5) then arranging a plastic packaging resin layer on the first carrier substrate, wherein the plastic packaging resin layer wraps the first semiconductor chip, the second semiconductor chip, the first metal column and the second metal column;
(6) and then, carrying out curing treatment on the plastic packaging resin layer, wherein the curing treatment specifically comprises the following steps: step a1 is performed first: heat treating in an oxygen-containing atmosphere for a first period of time; then, step a2 is performed: heat treating in a nitrogen atmosphere for a second period of time; then, step a3 is performed: heat treating in a first hydrogen atmosphere for a third period of time; then, step a4 is performed: heat treating in a second hydrogen atmosphere for a fourth time period; then, step a5 is performed: heat treating in a nitrogen atmosphere for a fifth period of time; then, step a6 is performed: heat treating in a third hydrogen atmosphere for a sixth period of time; then, step a7 is performed: heat-treating in a nitrogen atmosphere for a seventh period of time; wherein the first time period is greater than the second time period, the third time period is less than the fourth time period, and the third time period is greater than the sixth time period;
(7) then arranging a first mask on the plastic package resin layer, and etching a part of the second metal column by using the first mask so as to enable one end of the second metal column to be recessed into the plastic package resin layer;
(8) forming a first redistribution layer on the plastic package resin layer, wherein the second metal pillar is electrically connected with the first redistribution layer, the first metal pillar is not electrically connected with the first redistribution layer, and the first redistribution layer does not cover the first metal pillar;
(9) then, arranging a second carrier substrate on the first rewiring layer, removing the first carrier substrate to expose the plastic package resin layer, arranging a second mask on the plastic package resin layer, and etching a part of the second metal column by using the second mask to enable the other end of the second metal column to be recessed into the plastic package resin layer;
(10) and then forming a second re-wiring layer above the first semiconductor chip, the second metal column and the plastic-sealed resin layer, wherein the first semiconductor chip and the second metal column are electrically connected with the second re-wiring layer, then forming a conductive solder ball on the second re-wiring layer, and then removing the second carrier substrate.
2. The method of forming a multi-chip semiconductor package structure of claim 1, wherein: in the step (3), before the patterned mask is disposed on the first carrier substrate, a first metal seed layer is formed on an upper surface of the first carrier substrate, upper surfaces and side surfaces of the first semiconductor chip, and upper surfaces and side surfaces of the second semiconductor chip.
3. The method of forming a multi-chip semiconductor package structure of claim 2, wherein: then, a plurality of second metal seed protrusions are formed on the first metal seed layer, the plurality of second metal seed protrusions being formed in advance at positions where the first openings and the second openings are to be formed.
4. The method of forming a multi-chip semiconductor package structure of claim 3, wherein: the width of the second metal seed protrusion is smaller than that of the first opening or that of the second opening, the second metal seed protrusion is located in the middle area of the first opening or in the middle area of the second opening, and an included angle between the side surface of the second metal seed protrusion and the bottom surface of the second metal seed protrusion is 30-60 degrees.
5. The method of forming a multi-chip semiconductor package structure of claim 1, wherein: in the step (6), the temperature of each heat treatment is 200-300 ℃.
6. The method of forming a multi-chip semiconductor package structure of claim 5, wherein: in the step a1, the flow rate of oxygen is 1000sccm to 2000sccm, and the first time period is 20 to 30 minutes; in the step a2, the flow rate of nitrogen is 2000 sccm-4000 sccm, and the second time period is 10-20 minutes; in the step a3, the flow rate of hydrogen in the first hydrogen atmosphere is 800sccm to 1500sccm, and the third time period is 30 to 50 minutes; in the step a4, the flow rate of hydrogen in the second hydrogen atmosphere is 2000sccm to 3000sccm, and the fourth time period is 60 to 100 minutes; in the step a5, the flow rate of nitrogen is 2000 sccm-4000 sccm, and the fifth time period is 10-20 minutes; in the step a6, the flow rate of hydrogen in the third hydrogen atmosphere is 4000sccm to 5000sccm, and the sixth time period is 10 to 20 minutes; in the step a7, the flow rate of the nitrogen gas is 2000sccm to 4000sccm, and the seventh time period is 10 to 20 minutes.
7. The method of forming a multi-chip semiconductor package structure of claim 1, wherein: the first and second rewiring layers respectively comprise a plurality of dielectric layers and a plurality of metallized pattern layers positioned in the middle of the plurality of dielectric layers, and the dielectric layers comprise one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and zirconium oxide.
8. A multi-chip semiconductor package structure formed by the method of any of claims 1-7.
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| CN1866485A (en) * | 2005-05-16 | 2006-11-22 | 沛扬科技股份有限公司 | Method for decreasing adhesion of resin on semiconductor packaging mould surface |
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