CN112802525A - Three-dimensional memory and control method thereof - Google Patents
Three-dimensional memory and control method thereof Download PDFInfo
- Publication number
- CN112802525A CN112802525A CN202110118819.8A CN202110118819A CN112802525A CN 112802525 A CN112802525 A CN 112802525A CN 202110118819 A CN202110118819 A CN 202110118819A CN 112802525 A CN112802525 A CN 112802525A
- Authority
- CN
- China
- Prior art keywords
- word line
- voltage
- turn
- memory
- word lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
Landscapes
- Read Only Memory (AREA)
Abstract
The invention relates to a control method of a three-dimensional memory, the three-dimensional memory comprises a plurality of memory strings and a plurality of word lines, each memory string comprises a plurality of memory units which are sequentially connected in series from top to bottom, each word line is connected with the memory units which are positioned at the same height in each memory string, and the method comprises the following steps: determining a selected word line for a program verify operation; applying a first turn-on voltage to a first word line region located at one side of the selected word line and applying a second turn-on voltage to a second word line region located at the other side of the selected word line during a program verify operation; the memory cells connected with the word lines in the first word line region are in a programmed state, the memory cells connected with the word lines in the second word line region are in an unprogrammed state, and the magnitude of the second turn-on voltage is adjustable.
Description
Technical Field
The invention relates to a control method of a three-dimensional memory, which can effectively improve the back model effect of the three-dimensional memory without an additional voltage source.
Background
As technology develops, the semiconductor industry continues to seek new ways to produce such that each memory die in a memory device has a greater number of memory cells. In non-volatile memories, such as NAND memories, one way to increase memory density is through the use of vertical memory arrays, i.e., 3D NAND (three-dimensional NAND) memories; with higher and higher integration, 3D NAND memories have evolved from 32 layers to 64 layers, and even higher.
As market demands for memory density continue to increase, programming methods with more programming states are being developed so that each physical memory cell (cell) can represent more bits (bit) of information. However, the implementation of more programmed states has higher requirements on the formation process of a single memory cell and the distribution uniformity among multiple memory cells. Therefore, how to increase the storage density of the memory cells and improve the performance of the three-dimensional memory is a technical problem to be solved.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a control method for a three-dimensional memory, which can effectively improve the back model effect of the three-dimensional memory without an additional voltage source.
The present invention provides a method for controlling a three-dimensional memory to solve the above technical problem, where the three-dimensional memory includes a plurality of memory strings and a plurality of word lines, each memory string includes a plurality of memory cells connected in series from top to bottom, and each word line is connected to a memory cell in the same height in each memory string, and the method includes: determining a selected word line for a program verify operation; and applying a first turn-on voltage to a first word line region located at one side of the selected word line and applying a second turn-on voltage to a second word line region located at the other side of the selected word line in the program verify operation; the memory cells connected with the word lines in the first word line region are in a programmed state, the memory cells connected with the word lines in the second word line region are in an unprogrammed state, and the second conduction voltage is adjustable.
In an embodiment of the invention, the second turn-on voltage is gradually increased in magnitude during the program verify operations performed on the word lines.
In an embodiment of the invention, the word lines are divided into a plurality of continuous word line groups, wherein when the program verification operation is performed on the word lines in each of the word line groups, the second turn-on voltages have the same magnitude; wherein the magnitude of the second turn-on voltage is gradually increased during the program verify operation on the plurality of word line groups.
In an embodiment of the invention, each of the word line groups includes word lines of 1 to 20.
In an embodiment of the present invention, the method further includes: applying a third turn-on voltage to at least one word line between the selected word line and the first word line region and at least one word line between the selected word line and the second word line region, respectively.
In an embodiment of the present invention, the method further includes: applying a program verify voltage to the selected word line at the program verify operation.
In an embodiment of the invention, the second turn-on voltage is 1V to 3V.
In an embodiment of the invention, the first turn-on voltage and/or the third turn-on voltage has a magnitude of 6V to 8V.
In an embodiment of the invention, a magnitude of the first turn-on voltage and/or the third turn-on voltage is fixed.
In one embodiment of the present invention, the programming is either forward programming or reverse programming.
Another aspect of the present invention provides a three-dimensional memory, including a plurality of memory strings and a plurality of word lines, each of the memory strings including a plurality of memory cells connected in series from top to bottom, each of the word lines being connected to the memory cells in each of the memory strings at the same height, the three-dimensional memory further including: a control circuit configured to determine a selected word line for a program verify operation; and applying a first turn-on voltage to a first word line region located at one side of the selected word line and applying a second turn-on voltage to a second word line region located at the other side of the selected word line in the program verify operation; the memory cells connected with the word lines in the first word line region are in a programmed state, the memory cells connected with the word lines in the second word line region are in an unprogrammed state, and the second conduction voltage is adjustable.
In an embodiment of the invention, the second turn-on voltage is gradually increased in magnitude during the program verify operations performed on the word lines.
In an embodiment of the invention, the word lines are divided into a plurality of continuous word line groups, wherein when the program verification operation is performed on the word lines in each of the word line groups, the second turn-on voltages have the same magnitude; wherein the magnitude of the second turn-on voltage is gradually increased during the program verify operation on the plurality of word line groups.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following remarkable advantages:
the control method of the three-dimensional memory can effectively improve the back model effect of the three-dimensional memory without an additional voltage source by applying the first conduction voltage to the programmed first word line region at one side of the selected word line and applying the second conduction voltage to the unprogrammed second word line region at the other side of the selected word line during the programming verification operation, and the size of the second conduction voltage is adjustable.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
fig. 1 is a flowchart of a method for controlling a three-dimensional memory according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a method for controlling a three-dimensional memory according to an embodiment of the invention;
FIG. 3 is a diagram illustrating another method for controlling a three-dimensional memory according to an embodiment of the invention;
FIG. 4 is a voltage diagram illustrating a control method for a three-dimensional memory according to an embodiment of the invention;
fig. 5 is a diagram of a three-dimensional memory according to an embodiment of the invention.
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only examples or embodiments of the application, from which the application can also be applied to other similar scenarios without inventive effort for a person skilled in the art. Unless otherwise apparent from the context, or otherwise indicated, like reference numbers in the figures refer to the same structure or operation.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
The relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
In the description of the present application, it is to be understood that the orientation or positional relationship indicated by the directional terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc., are generally based on the orientation or positional relationship shown in the drawings, and are used for convenience of description and simplicity of description only, and in the case of not making a reverse description, these directional terms do not indicate and imply that the device or element being referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be considered as limiting the scope of the present application; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present.
It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited. Further, although the terms used in the present application are selected from publicly known and used terms, some of the terms mentioned in the specification of the present application may be selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Further, it is required that the present application is understood not only by the actual terms used but also by the meaning of each term lying within.
In a three-dimensional memory (e.g., 3D NAND), the back-pattern effect (BPD) is mainly caused by the fact that the programming states of the memory cells above the memory cell corresponding to the selected word line are different during the program verify operation and the read operation.
For example, when a program verify operation is performed on a selected word line WLn, memory cells corresponding to word lines WLn +1 and above are in an erased state, and when a read operation is performed on the selected word line WLn, memory cells corresponding to word lines WLn +1 and above are already in a random data (random pattern) programmed state, which results in a significant increase in string resistance of the memory cells corresponding to the word lines WLn +1 and above during reading, thereby increasing a threshold voltage during reading and widening a threshold voltage distribution.
In view of the above problems, the following embodiments of the present invention provide a control method for a three-dimensional memory, which can effectively improve the back-mode effect of the three-dimensional memory without an additional voltage source.
The three-dimensional memory comprises a plurality of memory strings and a plurality of word lines, wherein each memory string comprises a plurality of memory cells which are sequentially connected in series from top to bottom, and each word line is connected with the memory cells which are positioned at the same height in each memory string.
The control method of the three-dimensional memory comprises the following steps: determining a selected word line for a program verify operation; applying a first turn-on voltage to a first word line region located at one side of the selected word line and applying a second turn-on voltage to a second word line region located at the other side of the selected word line during a program verify operation; the memory cells connected with the word lines in the first word line region are in a programmed state, the memory cells connected with the word lines in the second word line region are in an unprogrammed state, and the magnitude of the second turn-on voltage is adjustable.
Fig. 1 is a flowchart of a method for controlling a three-dimensional memory according to an embodiment of the invention. This control method will be described below with reference to fig. 1. It is to be understood that the following description is merely exemplary, and that variations may be made by those skilled in the art without departing from the spirit of the invention.
Referring to fig. 1, the method comprises the steps of:
in step S10, the selected word line for the program verify operation is determined.
Fig. 2 is a schematic diagram of a control method of a three-dimensional memory according to an embodiment of the invention. Fig. 3 is a schematic diagram of another control method of a three-dimensional memory according to an embodiment of the invention.
Referring to fig. 2 and 3, first, a selected word line WL for a program verify operation is determinedm。
In some examples, the three-dimensional memory includes a plurality of memory strings each including a plurality of memory cells connected in series from top to bottom, and a plurality of word lines each connected to the memory cells located at the same height in each of the memory strings.
For example, each memory string may include a plurality of top select pipes, a plurality of dummy memory cells located at the top, a plurality of memory cells, a plurality of dummy memory cells located at the bottom, and a plurality of bottom select pipes (not shown) connected in series from top to bottom.
Wherein, a plurality of Top Select gates may be connected to the Top Select Gates (TSG), a plurality of Top dummy memory cells may be respectively connected to dummy word lines with corresponding heights (e.g. a plurality of Top dummy word lines Top DMY), and a plurality of Top dummy memory cells may be respectively connected to word lines with corresponding heights (e.g. word lines WL shown in fig. 2 or 3)m-1Word line WLmAnd word line WLm+1) The dummy memory cells at the Bottom are connected to dummy word lines (e.g., Bottom dummy word lines Btm DMY) with corresponding heights, and the Bottom Select Gates (BSG) are connected to Bottom Select gates.
Preferably, the three-dimensional memory may be a 3D NAND.
In one embodiment of the present invention, the programming may be forward programming or reverse programming. For example, forward programming may refer to a bottom-up programming order and reverse programming may refer to a top-down programming order, but the invention is not limited thereto.
For example, in one example shown in FIG. 2, the programming order for this programming is forward programming. In one example shown in fig. 3, the programming order of this programming is reverse programming.
In step S20, a first turn-on voltage is applied to a first word line region on one side of the selected word line and a second turn-on voltage is applied to a second word line region on the other side of the selected word line during the program verify operation.
The memory cells connected with the word lines in the first word line region are in a programmed state, the memory cells connected with the word lines in the second word line region are in an unprogrammed state, and the magnitude of the second turn-on voltage is adjustable.
Referring to FIG. 2, in one embodiment of the present invention, when programming is forward programming, the word line WL selected in the program verify operation can be verifiedmThe first word line region on one side, i.e. word line WLm-2And the following word lines apply a first turn-on voltage Vpass1And is aligned to the selected word line WLmThe second word line region on the other side, i.e. word line WLm+2And applying a second turn-on voltage V to the word linespass2。
Wherein the first word line region (e.g. word line WL)0To word line WLm-2) The memory cell connected with the word line in the memory cell is in a programmed state and is connected with a second word line region (such as word line WL)m+2To word line WLn) The memory cell connected with the word line is in an un-programmed state, and the second conduction voltage Vpass2Is adjustable in size.
Referring to FIG. 3, in another embodiment of the present invention, when programming is reverse programming, the word line WL selected in the program verify operation can be verifiedmThe first word line region on one side, i.e. word line WLm-2And applying the first turn-on voltage V to the word linespass1And is aligned to the selected word line WLmThe second word line region on the other side, i.e. word line WLm+2And applying a second turn-on voltage V to the word linespass2。
Wherein the first word line region (e.g. word line WL)0To word line WLm-2) The memory cell connected with the word line in the memory cell is in a programmed state and is connected with a second word line region (such as word line WL)m+2To word line WLn) The memory cell connected with the word line is in an un-programmed state, and the second conduction voltage Vpass2Is adjustable in size.
For example, a programmed memory cell may be in a programmed State (Program State); the un-programmed memory cells may be in an erased State (Erase State).
In an embodiment of the invention, the second turn-on voltage Vpass2Is gradually increased during the program verify operation on the plurality of word lines.
For example, in the embodiment of forward programming as shown in FIG. 2 or reverse programming as shown in FIG. 3, multiple word lines (e.g., word lines WL) are programmed0To word line WLn) During the program verification operation, the second turn-on voltage Vpass2May gradually increase in size.
Referring to FIG. 2, as a non-limiting example, in the forward programming order, when the selected word lines are respectively word lines WLm-1Word line WLmAnd word line WLm+1Then, the corresponding second word line regions are word lines WLm+1And the above word lines, word lines WLm+2And the above word lines, and word line WLm+3And the second conduction voltage V corresponding to the above word linespass2Are respectively V1, V2 and V3.
A second turn-on voltage V applied to the second word line region during a program verify operationpass2Gradually increase in size, so there are: v1 is not less than V2 is not less than V3.
Similarly, referring to FIG. 3, as a non-limiting example, in reverse programming order, when the selected word lines are respectively word lines WLm-1Word line WLmAnd word line WLm+1Then, the corresponding second word line regions are word lines WLm+1And the following word lines, word lines WLm+2And the following word lines, and word line WLm+3And the following word lines, corresponding to the second turn-on voltage Vpass2Are respectively V1, V2 and V3.
A second turn-on voltage V applied to the second word line region during a program verify operationpass2Gradually increase in size, so there are: v1 is not less than V2 is not less than V3.
In an embodiment of the present invention, the plurality of word lines may be further divided into a plurality of continuous word line groups. When the programming verification operation is performed on the word lines in each word line group, the second turn-on voltages are the same. The magnitude of the second turn-on voltage is gradually increased during the program verify operation on the plurality of word line groups.
In some examples, each word line group includes a number of word lines from 1 to 20. Wherein, the number of the word lines included in each word line group can be the same or different.
Illustratively, referring to fig. 2, when programming in the forward direction, each word line group includes the same number of word lines, which are 10. Multiple word lines (e.g. word line WL)0To word line WLn) Can be divided into (n +1)/10 word line groups from bottom to top. I.e. word line WL0To word line WL9The first word line group of (1), word line WL10To word line WL19The second word line group, and so on.
Wherein, when the word line in each sub-line group (for example, the first word line group, etc.) is subjected to the program verification operation, the second turn-on voltage Vpass2Are the same size. Second on voltage Vpass2Is gradually increased during the program verify operation on a plurality of word line groups (e.g., the first word line group, the second word line group, the third word line group, etc.).
For example, when the program verification operation is performed on the word lines in the first word line group, the second word line group and the third word line group, the corresponding second turn-on voltages V are appliedpass2Are Vg1, Vg2, and Vg3, respectively.
A second turn-on voltage V applied to the second word line region during a program verify operationpass2Is gradually increased according to the word line group, and thus there are: vg1 is less than or equal to Vg2 is less than or equal to Vg 3.
Illustratively, referring to fig. 3, when reverse programming is performed, each word line group includes the same number of word lines, which are 10. Multiple word lines (e.g. word line WL)0To word line WLn) Can be divided into (n +1)/10 word line groups from top to bottom. I.e. word line WL0To word line WL9The first word line group of (1), word line WL10To word line WL19The second word line group, and so on.
Wherein, when the word line in each sub-line group (for example, the first word line group, etc.) is subjected to the program verification operation, the second turn-on voltage Vpass2Are the same size. Second on voltage Vpass2Is gradually increased during the program verify operation on a plurality of word line groups (e.g., the first word line group, the second word line group, the third word line group, etc.).
For example, when the program verification operation is performed on the word lines in the first word line group, the second word line group and the third word line group, the corresponding second turn-on voltages V are appliedpass2Are Vg1, Vg2, and Vg3, respectively.
A second turn-on voltage V applied to the second word line region during a program verify operationpass2Is gradually increased according to the word line group, and thus there are: vg1 is less than or equal to Vg2 is less than or equal to Vg 3.
In an embodiment of the present invention, the control method further includes: a third turn-on voltage is applied to at least one word line between the selected word line and the first word line region and at least one word line between the selected word line and the second word line region, respectively.
For example, referring to FIG. 2, when programming in the forward direction, the word line WL selected can be alignedmAnd the first word line region (i.e., word line WL)m-2And below) word lines WL between the word lines WLm-1And at the selected word line WLmAnd a second word line region (i.e., word line WL)m+2And above) word lines WL between the word lines WLm+1Respectively applying a third on-voltage Vpass3。
Referring to FIG. 3, when programming in reverse, the word line WL selected can be alignedmAnd the first word line region (i.e., word line WL)m-2And above) word lines WL between the word lines WLm-1And at the selected word line WLmAnd a second word line region (i.e., word line WL)m+2And below) word lines WL between the word lines WLm+1Respectively applying a third on-voltage Vpass3。
In some embodiments, the method for controlling a three-dimensional memory of the present invention further includes: a program verify voltage is applied to a selected word line at the time of a program verify operation.
Fig. 4 is a voltage diagram illustrating a control method of a three-dimensional memory according to an embodiment of the invention. Referring to FIG. 4, the word line WL selected in FIG. 2 or FIG. 3 may be selectedmApplying a program verify voltage Vverify。
In some embodiments, the second turn-on voltage Vpass2May be 1V to 3V. Preferably, the second turn-on voltage Vpass2The size of (2) is 2V, but the invention is not limited thereto.
In some embodiments, the first turn-on voltage Vpass1May be 6V to 8V. Preferably, the first turn-on voltage Vpass1Is 6.6V, but the invention is not limited thereto.
In an embodiment of the invention, the third turn-on voltage Vpass3Is 6V to 8V.
Preferably, in the above embodiment of the present invention, the second turn-on voltage Vpass2Is less than the first on-voltage Vpass1And the first on-voltage Vpass1And the third on-state voltage Vpass3Are different in size.
In some embodiments, the first turn-on voltage Vpass1And/or a third on-voltage Vpass3Is fixed.
It should be understood that the first conducting voltage V can be adjusted by one skilled in the art according to actual requirementspass1A second on-state voltage Vpass2And a third on-voltage Vpass3The size of the present invention is not limited thereto.
The control method of the three-dimensional memory of the invention is realized by aiming at the selected word line WL in the programming verification operationmA first conduction voltage V is applied to the programmed first word line region on one sidepass1And is aligned to the selected word line WLmThe second word line region on the other side without programming applies a second conduction voltage Vpass2And make the second on-voltage Vpass2Is adjustable, so that the back model (BPD) effect of the three-dimensional memory can be effectively improved without the need ofAn additional voltage source.
The flowchart shown in fig. 1 is used herein to illustrate the steps/operations performed by the control method according to an embodiment of the present application. It should be understood that these steps/operations are not necessarily performed in the exact order in which they are performed. Rather, various steps/operations may be processed in reverse order or concurrently. Meanwhile, other steps/operations may be added to or removed from these processes.
The above embodiments of the present invention provide a control method of a three-dimensional memory, which can effectively improve the back-mode effect of the three-dimensional memory without an additional voltage source.
Another aspect of the present invention is to provide a three-dimensional memory, which can effectively improve a back-mode effect of the three-dimensional memory through its control circuit without an additional voltage source.
Fig. 5 is a diagram of a three-dimensional memory according to an embodiment of the invention. The three-dimensional memory will be described with reference to fig. 5. It is to be understood that the following description is merely exemplary, and that variations may be made by those skilled in the art without departing from the spirit of the invention.
It should be noted that the above control method of the present invention can be implemented in, for example, the three-dimensional memory 500 shown in fig. 5 or a variation thereof, but the present invention is not limited thereto.
Referring to fig. 5, a three-dimensional memory 500 of the present invention includes a plurality of memory strings each including a plurality of memory cells connected in series from top to bottom, and a plurality of word lines each connected to the memory cells located at the same height in each of the memory strings. The three-dimensional memory also includes control circuitry 510. Control circuitry 510 is configured to determine the selected word line for the program verify operation; and applying a first turn-on voltage to a first word line region located at one side of the selected word line and applying a second turn-on voltage to a second word line region located at the other side of the selected word line in a program verify operation. The memory cells connected with the word lines in the first word line region are in a programmed state, the memory cells connected with the word lines in the second word line region are in an unprogrammed state, and the magnitude of the second turn-on voltage is adjustable.
Preferably, the three-dimensional memory may be a 3D NAND.
In one embodiment of the present invention, the programming may be forward programming or reverse programming. For example, forward programming may refer to a bottom-up programming order and reverse programming may refer to a top-down programming order, but the invention is not limited thereto.
Referring to FIG. 2, in one embodiment of the present invention, when programming is forward programming, the control circuit 510 can perform a program verify operation on the selected word line WLmThe first word line region on one side, i.e. word line WLm-2And the following word lines apply a first turn-on voltage Vpass1And is aligned to the selected word line WLmThe second word line region on the other side, i.e. word line WLm+2And applying a second turn-on voltage V to the word linespass2。
Wherein the first word line region (e.g. word line WL)0To word line WLm-2) The memory cell connected with the word line in the memory cell is in a programmed state and is connected with a second word line region (such as word line WL)m+2To word line WLn) The memory cell connected with the word line is in an un-programmed state, and the second conduction voltage Vpass2Is adjustable in size.
Referring to FIG. 3, in another embodiment of the present invention, when programming is reverse programming, the control circuit 510 can be used for programming the selected word line WL during the program verify operationmThe first word line region on one side, i.e. word line WLm-2And applying the first turn-on voltage V to the word linespass1And is aligned to the selected word line WLmThe second word line region on the other side, i.e. word line WLm+2And applying a second turn-on voltage V to the word linespass2。
Wherein the first word line region (e.g. word line WL)0To word line WLm-2) The memory cell connected with the word line in the memory cell is in a programmed state and is connected with a second word line region (such as word line WL)m+2To word line WLn) The memory cells connected by the word lines in the memory cell array are not programmedState of stroke, second on voltage Vpass2Is adjustable in size.
In an embodiment of the invention, the second turn-on voltage Vpass2Is gradually increased during the program verify operation on the plurality of word lines.
For example, in the embodiment of forward programming as shown in FIG. 2 or reverse programming as shown in FIG. 3, multiple word lines (e.g., word lines WL) are programmed0To word line WLn) During the program verification operation, the second turn-on voltage Vpass2May gradually increase in size.
Referring to FIG. 2, as a non-limiting example, in the forward programming order, when the selected word lines are respectively word lines WLm-1Word line WLmAnd word line WLm+1Then, the corresponding second word line regions are word lines WLm+1And the above word lines, word lines WLm+2And the above word lines, and word line WLm+3And the second conduction voltage V corresponding to the above word linespass2Are respectively V1, V2 and V3.
During a program verify operation, the second turn-on voltage V applied by the control circuit 510 to the second word line regionpass2Gradually increase in size, so there are: v1 is not less than V2 is not less than V3.
Similarly, referring to FIG. 3, as a non-limiting example, in reverse programming order, when the selected word lines are respectively word lines WLm-1Word line WLmAnd word line WLm+1Then, the corresponding second word line regions are word lines WLm+1And the following word lines, word lines WLm+2And the following word lines, and word line WLm+3And the following word lines, corresponding to the second turn-on voltage Vpass2Are respectively V1, V2 and V3.
During a program verify operation, the second turn-on voltage V applied by the control circuit 510 to the second word line regionpass2Gradually increase in size, so there are: v1 is not less than V2 is not less than V3.
In an embodiment of the present invention, the plurality of word lines may be further divided into a plurality of continuous word line groups. When the programming verification operation is performed on the word lines in each word line group, the second turn-on voltages are the same. The magnitude of the second turn-on voltage is gradually increased during the program verify operation on the plurality of word line groups.
In some examples, each word line group includes a number of word lines from 1 to 20. Wherein, the number of the word lines included in each word line group can be the same or different.
Illustratively, referring to fig. 2, when programming in the forward direction, each word line group includes the same number of word lines, which are 10. Multiple word lines (e.g. word line WL)0To word line WLn) Can be divided into (n +1)/10 word line groups from bottom to top. I.e. word line WL0To word line WL9The first word line group of (1), word line WL10To word line WL19The second word line group, and so on.
Wherein, when the word line in each sub-line group (for example, the first word line group, etc.) is subjected to the program verification operation, the second turn-on voltage Vpass2Are the same size. Second on voltage Vpass2Is gradually increased during the program verify operation on a plurality of word line groups (e.g., the first word line group, the second word line group, the third word line group, etc.).
For example, when the program verification operation is performed on the word lines in the first word line group, the second word line group and the third word line group, the corresponding second turn-on voltages V are appliedpass2Are Vg1, Vg2, and Vg3, respectively.
A second turn-on voltage V applied to the second word line region during a program verify operationpass2Is gradually increased according to the word line group, and thus there are: vg1 is less than or equal to Vg2 is less than or equal to Vg 3.
Illustratively, referring to fig. 3, when reverse programming is performed, each word line group includes the same number of word lines, which are 10. Multiple word lines (e.g. word line WL)0To word line WLn) Can be divided into (n +1)/10 word line groups from top to bottom. I.e. word line WL0To word line WL9The first word line group of (1), word line WL10To word line WL19The second word line group, and so on.
Wherein, when the word line in each sub-line group (for example, the first word line group, etc.) is subjected to the program verification operation, the second turn-on voltage Vpass2Are the same size. Second on voltage Vpass2Is gradually increased during the program verify operation on a plurality of word line groups (e.g., the first word line group, the second word line group, the third word line group, etc.).
For example, when the program verification operation is performed on the word lines in the first word line group, the second word line group and the third word line group, the corresponding second turn-on voltages V are appliedpass2Are Vg1, Vg2, and Vg3, respectively.
A second turn-on voltage V applied to the second word line region during a program verify operationpass2Is gradually increased according to the word line group, and thus there are: vg1 is less than or equal to Vg2 is less than or equal to Vg 3.
Other implementation details of the three-dimensional memory 500 of the present embodiment can refer to the embodiments described in fig. 1 to 4, and are not expanded herein. Those skilled in the art can make appropriate adjustments to the internal structure of the three-dimensional memory 500 according to actual needs, and the invention is not limited thereto.
The three-dimensional memory 500 of the present invention is manufactured by configuring the control circuit 510 to be aligned to the selected word line WL during the program verify operationmA first conduction voltage V is applied to the programmed first word line region on one sidepass1And is aligned to the selected word line WLmThe second word line region on the other side without programming applies a second conduction voltage Vpass2And make the second on-voltage Vpass2Is adjustable, so that the back model (BPD) effect of the three-dimensional memory can be effectively improved without an additional voltage source.
The above embodiments of the present invention propose a three-dimensional memory which can effectively improve the back-mode effect of the three-dimensional memory through its control circuit without an additional voltage source.
It is to be understood that while certain presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of illustration, and not by way of limitation, such details are provided for purposes of illustration only and the appended claims are intended to cover all such modifications and equivalent arrangements as fall within the true spirit and scope of the embodiments of the disclosure.
The computer-readable storage media referred to in this application may include, but are not limited to, magnetic storage devices (e.g., hard disk, floppy disk, magnetic strips), optical disks (e.g., Compact Disk (CD), Digital Versatile Disk (DVD)), smart cards, and flash memory devices (e.g., electrically erasable programmable read-only memory (EPROM), card, stick, key drive). In addition, various storage media described herein can represent one or more devices and/or other machine-readable media for storing information. The term "machine-readable medium" can include, without being limited to, wireless channels and various other media (and/or storage media) capable of storing, containing, and/or carrying code and/or instructions and/or data.
It should be understood that the above-described embodiments are illustrative only. The embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or any combination thereof. For a hardware implementation, the processing units may be implemented within one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, and/or other electronic units designed to perform the functions described herein, or a combination thereof.
Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing disclosure is by way of example only, and is not intended to limit the present application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the exemplary embodiments of the present application.
Also, this application uses specific language to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.
Computer program code required for the operation of various portions of the present application may be written in any one or more programming languages, including an object oriented programming language such as Java, Scala, Smalltalk, Eiffel, JADE, Emerald, C + +, C #, VB.NET, Python, and the like, a conventional programming language such as C, Visual Basic, Fortran 2003, Perl, COBOL 2002, PHP, ABAP, a dynamic programming language such as Python, Ruby, and Groovy, or other programming languages, and the like. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any network format, such as a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet), or in a cloud computing environment, or as a service, such as a software as a service (SaaS).
Additionally, the order in which elements and sequences of the processes described herein are processed, the use of alphanumeric characters, or the use of other designations, is not intended to limit the order of the processes and methods described herein, unless explicitly claimed. While various presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of example, it is to be understood that such detail is solely for that purpose and that the appended claims are not limited to the disclosed embodiments, but, on the contrary, are intended to cover all modifications and equivalent arrangements that are within the spirit and scope of the embodiments herein. For example, although the system components described above may be implemented by hardware devices, they may also be implemented by software-only solutions, such as installing the described system on an existing server or mobile device.
Similarly, it should be noted that in the preceding description of embodiments of the application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.
Numerals describing the number of components, attributes, etc. are used in some embodiments, it being understood that such numerals used in the description of the embodiments are modified in some instances by the use of the modifier "about", "approximately" or "substantially". Unless otherwise indicated, "about", "approximately" or "substantially" indicates that the number allows a variation of ± 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that may vary depending upon the desired properties of the individual embodiments. In some embodiments, the numerical parameter should take into account the specified significant digits and employ a general digit preserving approach. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the range are approximations, in the specific examples, such numerical values are set forth as precisely as possible within the scope of the application.
Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.
Claims (13)
1. A control method of a three-dimensional memory, wherein the three-dimensional memory comprises a plurality of memory strings and a plurality of word lines, each memory string comprises a plurality of memory cells which are sequentially connected in series from top to bottom, each word line is connected with the memory cells which are positioned at the same height in each memory string, and the method comprises the following steps:
determining a selected word line for a program verify operation; and
applying a first turn-on voltage to a first word line region located at one side of the selected word line and applying a second turn-on voltage to a second word line region located at the other side of the selected word line in the program verify operation;
the memory cells connected with the word lines in the first word line region are in a programmed state, the memory cells connected with the word lines in the second word line region are in an unprogrammed state, and the second conduction voltage is adjustable.
2. The method according to claim 1, wherein the second turn-on voltage is gradually increased in magnitude during the program verify operation on the plurality of word lines.
3. The control method according to claim 1, wherein the word lines are divided into a plurality of continuous word line groups, and the second turn-on voltages are the same when the program verify operations are performed on the word lines in each of the word line groups; wherein the magnitude of the second turn-on voltage is gradually increased during the program verify operation on the plurality of word line groups.
4. The control method according to claim 3, wherein each of the word line groups includes word lines in a number of 1 to 20.
5. The control method according to claim 1, characterized in that the method further comprises: applying a third turn-on voltage to at least one word line between the selected word line and the first word line region and at least one word line between the selected word line and the second word line region, respectively.
6. The control method according to claim 1, characterized in that the method further comprises: applying a program verify voltage to the selected word line at the program verify operation.
7. The control method according to claim 1, wherein the second turn-on voltage has a magnitude of 1V to 3V.
8. The control method according to claim 5, characterized in that the magnitude of the first and/or third turn-on voltage is 6V to 8V.
9. The control method according to claim 5, characterized in that the magnitude of the first turn-on voltage and/or the third turn-on voltage is fixed.
10. Control method according to claim 1, characterized in that the programming is a forward programming or a reverse programming.
11. A three-dimensional memory, comprising a plurality of memory strings and a plurality of word lines, wherein each memory string comprises a plurality of memory cells connected in series from top to bottom, each word line is connected to a memory cell at the same height in each memory string, and the three-dimensional memory further comprises:
a control circuit configured to determine a selected word line for a program verify operation; and applying a first turn-on voltage to a first word line region located at one side of the selected word line and applying a second turn-on voltage to a second word line region located at the other side of the selected word line in the program verify operation;
the memory cells connected with the word lines in the first word line region are in a programmed state, the memory cells connected with the word lines in the second word line region are in an unprogrammed state, and the second conduction voltage is adjustable.
12. The three-dimensional memory according to claim 11, wherein the second turn-on voltage is gradually increased in magnitude during the program verify operation on the plurality of word lines.
13. The three-dimensional memory according to claim 11, wherein the word lines are divided into a plurality of continuous word line groups, and the second turn-on voltages are the same when the program verification operation is performed on the word lines in each of the word line groups; wherein the magnitude of the second turn-on voltage is gradually increased during the program verify operation on the plurality of word line groups.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211236030.3A CN115579039A (en) | 2021-01-28 | 2021-01-28 | Three-dimensional memory and control method thereof |
| CN202110118819.8A CN112802525B (en) | 2021-01-28 | 2021-01-28 | Three-dimensional memory and control method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110118819.8A CN112802525B (en) | 2021-01-28 | 2021-01-28 | Three-dimensional memory and control method thereof |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211236030.3A Division CN115579039A (en) | 2021-01-28 | 2021-01-28 | Three-dimensional memory and control method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112802525A true CN112802525A (en) | 2021-05-14 |
| CN112802525B CN112802525B (en) | 2022-10-28 |
Family
ID=75812482
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110118819.8A Active CN112802525B (en) | 2021-01-28 | 2021-01-28 | Three-dimensional memory and control method thereof |
| CN202211236030.3A Pending CN115579039A (en) | 2021-01-28 | 2021-01-28 | Three-dimensional memory and control method thereof |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211236030.3A Pending CN115579039A (en) | 2021-01-28 | 2021-01-28 | Three-dimensional memory and control method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN112802525B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090073763A1 (en) * | 2007-09-14 | 2009-03-19 | Kabushiki Kaisha Toshiba | Method for controlling a non-volatile semiconductor memory device |
| US20180033492A1 (en) * | 2016-07-28 | 2018-02-01 | SK Hynix Inc. | Memory device and method of operating the same |
| KR20190122061A (en) * | 2018-04-19 | 2019-10-29 | 에스케이하이닉스 주식회사 | Memory device and operating method thereof |
| CN110678926A (en) * | 2019-08-28 | 2020-01-10 | 长江存储科技有限责任公司 | Programming method in flash memory device |
| CN111630600A (en) * | 2020-04-15 | 2020-09-04 | 长江存储科技有限责任公司 | 3D NAND flash memory and operation method thereof |
| US20200357469A1 (en) * | 2018-02-26 | 2020-11-12 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of operating the same |
-
2021
- 2021-01-28 CN CN202110118819.8A patent/CN112802525B/en active Active
- 2021-01-28 CN CN202211236030.3A patent/CN115579039A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090073763A1 (en) * | 2007-09-14 | 2009-03-19 | Kabushiki Kaisha Toshiba | Method for controlling a non-volatile semiconductor memory device |
| US20180033492A1 (en) * | 2016-07-28 | 2018-02-01 | SK Hynix Inc. | Memory device and method of operating the same |
| US20200357469A1 (en) * | 2018-02-26 | 2020-11-12 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of operating the same |
| KR20190122061A (en) * | 2018-04-19 | 2019-10-29 | 에스케이하이닉스 주식회사 | Memory device and operating method thereof |
| CN110678926A (en) * | 2019-08-28 | 2020-01-10 | 长江存储科技有限责任公司 | Programming method in flash memory device |
| CN111630600A (en) * | 2020-04-15 | 2020-09-04 | 长江存储科技有限责任公司 | 3D NAND flash memory and operation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115579039A (en) | 2023-01-06 |
| CN112802525B (en) | 2022-10-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9129698B2 (en) | Solid state storage device and sensing voltage setting method thereof | |
| US9858993B2 (en) | Non-volatile memory device and method of programming the same | |
| US10304551B2 (en) | Erase speed based word line control | |
| US9703698B2 (en) | Data writing method, memory controller and memory storage apparatus | |
| CN109817265B (en) | Semiconductor memory device and method of operating the same | |
| CN107039072B (en) | Nonvolatile memory device and method of operating nonvolatile memory device | |
| KR20060115996A (en) | Programming method based on the behaviour of non-volatile memory cells | |
| CN109754840B (en) | Semiconductor memory device and method of operating the same | |
| WO2020006060A1 (en) | Nand temperature-aware operations | |
| CN110851375A (en) | Memory controller and method of operating the same | |
| US20150357040A1 (en) | Nonvolatile memory and data writing method | |
| CN112634961B (en) | Three-dimensional memory and control method thereof | |
| CN113126905A (en) | Secure key update for replaying protected memory blocks | |
| US10340017B2 (en) | Erase-verify method for three-dimensional memories and memory system | |
| CN114078538A (en) | Hybrid routines for memory devices | |
| US10504587B2 (en) | Method and system for compensating for floating gate-to-floating gate (fg-fg) interference in flash memory cell read operations | |
| CN112802525B (en) | Three-dimensional memory and control method thereof | |
| US20230120129A1 (en) | Three-dimensional memory device and method for reading the same | |
| CN112614530B (en) | Three-dimensional memory and control method thereof | |
| US11923022B2 (en) | Storage device and operating method for controller | |
| CN109243516B (en) | Erasing method and device and computer readable storage medium | |
| CN112863564B (en) | Three-dimensional memory and control method thereof | |
| TW202119421A (en) | Semiconductor memory device and method of operating the same | |
| US11941271B2 (en) | Storage devices performing secure erase and operating methods thereof | |
| KR102649347B1 (en) | Method for programming non-volatile memory device and method for operating system having the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |