CN112801196A - Method for identifying storage unit in memory circuit - Google Patents
Method for identifying storage unit in memory circuit Download PDFInfo
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- CN112801196A CN112801196A CN202110155309.8A CN202110155309A CN112801196A CN 112801196 A CN112801196 A CN 112801196A CN 202110155309 A CN202110155309 A CN 202110155309A CN 112801196 A CN112801196 A CN 112801196A
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Abstract
A method of identifying a memory cell in a memory circuit, comprising the steps of: analyzing the circuit netlist, and modeling the input circuit into a bipartite graph; according to the bipartite graph, identifying the resistance network; identifying the resistor network as a word line or a bit line; extracting a connected component from the word line or the bit line; and gathering the connected components, identifying the storage unit and outputting the storage unit. The method for identifying the storage unit in the memory circuit can output correct identification results for the input front imitation memory circuit and the input rear imitation memory circuit, can automatically identify the storage unit for the input memory circuit netlist, and outputs the identification results for subsequent simulation, thereby reducing the calculation amount and shortening the simulation time.
Description
Technical Field
The invention relates to the technical field of integrated circuit design automation, in particular to a method for identifying a storage unit.
Background
In the design of an integrated circuit, a design engineer performs functional simulation on the designed circuit, observes a simulation result to confirm whether the simulation result reaches an expectation or not, and accordingly modifies the design or enters the next stage of verification, so that the time overhead of the simulation on a large-scale circuit, particularly a post-simulation circuit, is very large. For some special circuit types, such as memory circuits, the structure of which comprises a large number of repeated storage units, if the units can be identified in advance, the information can be used for assisting the circuit division so as to reuse matrix data by using isomorphic, homomorphic and other techniques in subsequent simulation, thereby reducing the calculation amount and shortening the simulation time.
The identification of the existing circuit unit can be summarized to the problem of searching isomorphic subgraphs mathematically, the existing circuit unit belongs to NP-Hard class in the calculation theory, the traditional algorithm based on graph search has universality but does not consider the special structure of the graph in specific application, and for a large-scale post-simulation circuit, the algorithm has high time complexity and cannot be efficiently applied to the simulation of special types of circuits such as a memory circuit and the like.
Disclosure of Invention
In order to solve the defects in the prior art, the invention aims to provide a method for identifying a storage unit in a memory circuit, which can automatically identify the storage unit for an input memory circuit netlist and output the identification result for subsequent simulation.
In order to achieve the above object, the present invention provides a method for identifying a memory cell in a memory circuit, comprising the steps of:
analyzing the circuit netlist, and modeling the input circuit into a bipartite graph;
according to the bipartite graph, identifying the resistance network;
identifying the resistor network as a word line or a bit line;
extracting a connected component from the word line or the bit line;
and gathering the connected components, identifying the storage unit and outputting the storage unit.
Further, the step of modeling the input circuit as a bipartite graph further includes dividing vertices of the bipartite graph into device vertices and node vertices, each edge corresponding to a connection of a device port and a node.
Further, the step of identifying the resistor network according to the bipartite graph further includes merging device vertices and node vertices of each resistor into the same class of a parallel search set by using the parallel search set, and forming different resistor networks by disjoint sets of the search set.
Further, the step of identifying the resistor networks as word lines or bit lines further includes, for each resistor network, searching the field effect transistors connected thereto, and counting the number of the types of the ports of the field effect transistors; and identifying the resistance network as a word line or a bit line according to the counted number of the types of the field effect tube ports and a preset threshold value.
Further, the step of extracting the connected component from the word line or the bit line further includes,
marking device vertexes and node vertexes in all word lines and bit lines;
establishing a set for each device vertex and node vertex in the bipartite graph that is not in a word line and a bit line;
and combining the sets with the connection relation, wherein the disjoint sets form different connected components.
Further, the step of merging sets with connection relations, where disjoint sets form different connected components, further includes merging device vertices and node vertices connected by each edge into the same class by using a parallel-search set; and the disjoint sets in the lookup set constitute different connected components.
Further, the step of gathering the connected components, identifying the storage unit and outputting the storage unit further comprises,
clustering the connected components, wherein the connected components have the same characteristics and are of the same type, and identifying the type with the largest quantity as a storage unit;
and outputting according to the set output format, and entering the next simulation stage.
Further, the step of clustering the connected components, wherein the connected components have the same characteristics and are in the same class, and identifying the class with the largest number as the storage unit, further comprises,
and clustering by taking the number of field effect tubes, the number of resistors, the number of capacitors and the number of nodes contained in each connected component as characteristics, wherein the same characteristics are used for identifying the type with the most number as a storage unit.
In order to achieve the above object, the present invention further provides an electronic device, which includes a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the steps of the method for identifying the memory cells in the memory circuit when executing the computer program.
To achieve the above object, the present invention further provides a computer readable storage medium having stored thereon computer instructions which, when executed, perform the steps of the method for identifying memory cells in the memory circuit.
The technical scheme of the invention has the following advantages:
the invention utilizes the characteristics of the circuit structure of the memory, adopts the heuristic method to efficiently identify all the memory cells in the large-scale back-imitation memory circuit, can automatically identify the memory cells for the input circuit netlist of the memory, and outputs the identification result for subsequent simulation.
The method can quickly identify the memory cells in the memory circuit, and the algorithm time complexity is O (N x D), N is the number of the vertexes of the graph, and D is the average degree of the vertexes. The method can output correct recognition results to the input front imitation memory circuit and the input rear imitation memory circuit, thereby reducing the calculation amount and shortening the simulation time.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart of a method for identifying memory cells in a memory circuit according to the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Fig. 1 is a flow chart of a method for identifying a memory cell in a memory circuit according to the present invention, and the method for identifying a memory cell in a memory circuit according to the present invention will be described in detail with reference to fig. 1.
First, in step 101, a circuit netlist and option settings input by a user are received.
In the embodiment of the present invention, the setting of the option input by the user specifically includes setting a resistance threshold, a word line threshold, a bit line threshold and an output format in the resistance network.
At step 102, the circuit netlist is parsed to construct a bipartite graph model of the input circuit.
Circuits in computers are typically stored in the data structure of a graph in which vertices are divided into two categories: device vertices (device vertices) and node vertices (node vertices), each edge of the graph corresponds to a connection of a device port to a node. Each device in the circuit corresponds to one device vertex in the graph during modeling; each node in the circuit corresponds to a node vertex in the graph. The edges in the graph are constructed according to the connection situation in the circuit. The circuit is constructed into a bipartite graph, so that the storage scale of the circuit can be reduced, if the circuit is modeled into a common graph model, the scale of the number of connecting edges is N x N, and N is the number of devices in the circuit; modeling as a bipartite graph means that the number of edges in the circuit is k N, k being the average number of ports per device, and N being the number of devices in the circuit.
In the embodiment of the invention, an input circuit is modeled into a bipartite graph, the vertexes of the graph are divided into two types, the two types of vertexes correspond to a device and a node in the circuit respectively, and each edge of the graph corresponds to the connection between a certain device port and a certain node.
In step 103, a resistor network (R network) in the input circuit is identified.
In the embodiment of the invention, according to the set resistance threshold, device vertexes and node vertexes of each resistance with the resistance value smaller than the threshold are combined into the same type of parallel search set by utilizing the parallel search set, and the non-intersecting sets of the parallel search set form different R networks.
At step 104, the resistance network is identified as a word line or a bit line.
The R network is composed of a series of connected device vertices (corresponding to resistors in the circuit) and node vertices, and the node vertices in the R network may be connected to other device vertices, such as device vertices of mosfet (metal-oxide semiconductor field effect transistor) in the corresponding circuit. Traversing adjacent vertexes of node vertexes in the R network, counting the device vertex number of mosfets in a circuit connected with the nodes, recording the ports connected with the corresponding mosfets, and identifying the R network as a word line or a bit line if the number is larger than a threshold set by a user in options.
In the embodiment of the invention, each R network is searched for the mosfets connected with the R network, the number of the mosfet port types (gates, sources and drains) is counted, and whether the R network is a word line or a bit line is identified according to the number and the preset word line threshold and bit line threshold.
For example:
setting the word line threshold to 20 in the option, then identifying each R network connecting more than 20 different mosfet gates as a word line;
setting the bit line threshold to 20 in the option, then each R-network connecting more than 20 different mosfet sources or drains is identified as a bit line.
At step 105, connected components are extracted using the union set.
In the embodiment of the invention, all edges on the word line and the bit line are removed, other edges are reserved, device vertexes and node vertexes connected with each edge are combined into the same class by utilizing a parallel search set, and finally, different connected components are formed by the disjoint sets of the parallel search set.
In the embodiment of the invention, the process of extracting the connected components is realized by adopting a parallel search set, and the specific steps are as follows:
marking device vertexes and node vertexes in all the word lines and bit lines obtained in the step 104;
establishing a set of device vertices and node vertices in the bipartite graph that are not in the word lines and bit lines;
merging the sets with the connection relation, namely merging the device vertex and the node vertex connected with each edge into the same class by using a parallel search set;
and the disjoint sets of the lookup sets constitute different connected components.
At step 106, the connected components are clustered to identify a storage unit.
In the embodiment of the invention, connected components are clustered, the number of field effect transistors, the number of resistors, the number of capacitors and the number of nodes contained in each connected component are used as characteristics for clustering, the characteristics are the same, the type with the largest number is identified as a storage unit, and identification information is output according to a set output format.
The invention provides a heuristic method for efficiently identifying all storage units in a large-scale back-imitation storage circuit by utilizing the characteristics of a storage circuit structure, which can automatically identify the storage units for an input storage circuit netlist and output an identification result for subsequent simulation.
In an embodiment of the present invention, an electronic device is further provided, including a memory and a processor, where the memory stores a computer program running on the processor, and the processor executes the steps of the method for identifying a storage unit in a memory circuit when running the computer program, where the method for identifying a storage unit in a memory circuit is described in the foregoing description and is not described again.
In an embodiment of the present invention, a computer-readable storage medium is further provided, on which computer instructions are stored, and when the computer instructions are executed, the steps of the method for identifying a storage unit in a memory circuit are performed, where the method for identifying a storage unit in a memory circuit is described in the foregoing description, and details are not repeated.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method of identifying a memory cell in a memory circuit, comprising the steps of:
analyzing the circuit netlist, and modeling the input circuit into a bipartite graph;
according to the bipartite graph, identifying the resistance network;
identifying the resistor network as a word line or a bit line;
extracting a connected component from the word line or the bit line;
and gathering the connected components, identifying the storage unit and outputting the storage unit.
2. The method of claim 1, wherein the step of modeling the input circuit as a bipartite graph further comprises dividing vertices of the bipartite graph into device vertices and node vertices, each edge corresponding to a connection of a device port to a node.
3. The method of claim 1, wherein the identifying the resistor network according to the bipartite graph further comprises merging device vertices and node vertices of each resistor into a same class of a merged set using the merged set, wherein disjoint sets of the merged set form different resistor networks.
4. The method of claim 1, wherein the step of identifying the resistor networks as word lines or bit lines further comprises, for each resistor network, searching for fets connected to it, counting the number of fet port types; and identifying the resistance network as a word line or a bit line according to the counted number of the types of the field effect tube ports and a preset threshold value.
5. The method of claim 1, wherein the step of extracting the connected component from the word line or the bit line further comprises,
marking device vertexes and node vertexes in all word lines and bit lines;
establishing a set for each device vertex and node vertex in the bipartite graph that is not in a word line and a bit line;
and combining the sets with the connection relation, wherein the disjoint sets form different connected components.
6. The method of claim 5, wherein said step of merging sets having a connection relationship, disjoint sets forming different connected components, further comprises merging device vertices and node vertices connected by each edge into the same class using a parallel-search set; and the disjoint sets in the lookup set constitute different connected components.
7. The method of claim 1, wherein the step of aggregating connected components, identifying and outputting memory cells further comprises,
clustering the connected components, wherein the connected components have the same characteristics and are of the same type, and identifying the type with the largest quantity as a storage unit;
and outputting according to the set output format, and entering the next simulation stage.
8. The method of claim 7, wherein said step of clustering said connected components, identical in character, into a same class, identifying a class with a largest number as a memory cell, further comprises,
and clustering by taking the number of field effect tubes, the number of resistors, the number of capacitors and the number of nodes contained in each connected component as characteristics, wherein the same characteristics are used for identifying the type with the most number as a storage unit.
9. An electronic device, comprising a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the computer program to perform the steps of the method for identifying memory cells in a memory circuit according to any one of claims 1 to 8.
10. A computer-readable storage medium having stored thereon computer instructions, wherein said computer instructions when executed perform the steps of the method for identifying memory cells in a memory circuit according to any one of claims 1 to 8.
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| CN111553120A (en) * | 2020-05-12 | 2020-08-18 | 北京华大九天软件有限公司 | Method for generating SPICE netlist of digital circuit local clock network |
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| CN112597733A (en) * | 2020-12-30 | 2021-04-02 | 北京华大九天科技股份有限公司 | Storage unit identification method and device and computer readable storage medium |
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2021
- 2021-02-04 CN CN202110155309.8A patent/CN112801196A/en active Pending
Patent Citations (6)
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| CN1763928A (en) * | 2004-10-18 | 2006-04-26 | 中国科学院微电子研究所 | Rapid comprehensive design method based on static random access memory |
| CN102646143A (en) * | 2011-11-30 | 2012-08-22 | 清华大学 | Conductance matrix construction method and system in simulation of on-chip power supply network |
| CN109376471A (en) * | 2018-11-22 | 2019-02-22 | 北京华大九天软件有限公司 | A method of equivalent output after rear imitative circuit optimization |
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