CN112800710A - Multi-medium Green function pre-drawing method for extracting interconnection capacitance of integrated circuit - Google Patents
Multi-medium Green function pre-drawing method for extracting interconnection capacitance of integrated circuit Download PDFInfo
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Abstract
The application provides a multi-medium Green function pre-drawing method for integrated circuit interconnection capacitance extraction. The method comprises the following steps: according to given integrated circuit interconnection process information, utilizing the geometric symmetry of a cube transfer region Green function table to perform compressed pre-drawing on a plurality of transfer cubes containing multiple dielectric layers to obtain compressed pre-drawing data; wherein the pre-drawing data comprises: transition probability distribution GFT of a transition region containing two dielectric layers and corresponding weight distribution data WVT; and extracting random walking capacitance parameters of the multilayer dielectric interconnection structure based on the compressed pre-drawing data. According to the method, the geometrical symmetry of the Green function table of the cube transfer region is utilized, the storage quantity of GFT (global context transfer) and WVT (global context transfer) data of the original transfer region is compressed, the compressed GFT and WVT are directly used for carrying out normal random walking capacitance extraction, and the memory overhead during program operation is saved.
Description
Technical Field
The application relates to the field of VLSI (Very Large Scale Integrated circuits) physical design and verification, in particular to a multi-medium green function pre-drawing method for extracting interconnection capacitance of an Integrated circuit.
Background
In the design flow of the integrated circuit, functional description is firstly provided, and then a layout for describing the process size and the structure of the semiconductor is obtained through logic design and layout design. At this time, the layout verification is needed, that is, whether the design can meet the initially set requirements is verified through computer software simulation and the like. If the requirements are met, the next production and manufacturing can be carried out; otherwise, the necessary modifications are made to return to the logic design and the like. This iterative process is repeated until layout verification indicates that the design can indeed meet the requirements. In layout verification, an important link is called as 'interconnection parasitic parameter extraction'.
With the development of integrated circuit manufacturing technology, circuit scale is increasing and feature size is shrinking, and nowadays many chips already contain several millions or even hundreds of millions of devices. However, parasitic effects of interconnect lines in integrated circuits cause the effect of the interconnect lines on circuit delay to exceed the effect of the device on delay. Therefore, accurate extraction and calculation of parameters such as capacitance and resistance of the interconnection line are required, and the correctness and the validity of circuit simulation and verification can be guaranteed only in this way. With the increasing requirement on the calculation accuracy in practical application, a three-dimensional extraction method, namely a three-dimensional field solver, is required to be used for extracting the capacitance parameters between the interconnection lines for accurate solution. The calculation of the field solver is time-consuming, and the optimization and accelerated research significance of the algorithm is great. However, the related art pre-scribing method usually involves excessively large memory overhead.
Disclosure of Invention
The object of the present application is to solve at least to some extent one of the above mentioned technical problems.
To this end, an object of the present application is to provide a method for pre-patterning a multi-dielectric green function oriented to integrated circuit interconnection capacitance extraction. The method utilizes the geometric symmetry of the Green function table of the cube transfer region to compress the storage quantity of the pre-drawing data GFT and WVT of the original transfer region, and directly uses the compressed GFT and WVT to extract the normal random walking capacitance, thereby saving the memory overhead when the program runs.
In order to achieve the above object, an embodiment of a first aspect of the present application provides a method for pre-patterning a multi-dielectric green function oriented to integrated circuit interconnection capacitance extraction, including:
according to given integrated circuit interconnection process information, utilizing the geometric symmetry of a cube transfer region Green function table to perform compressed pre-drawing on a plurality of transfer cubes containing multiple dielectric layers to obtain compressed pre-drawing data; wherein the pre-characterization data comprises: transition probability distribution GFT of a transition region containing two dielectric layers and corresponding weight distribution data WVT;
and extracting random walking capacitance parameters of the multilayer dielectric interconnection structure based on the compressed pre-drawing data.
Optionally, in some embodiments of the present application, the pre-scribing in a compressed form on several transfer cubes including multiple dielectric layers according to given integrated circuit interconnection process information by using geometric symmetry of a cube transfer region green function table to obtain compressed pre-scribing data includes:
s11, obtaining the integrated circuit dielectric layer information in the given integrated circuit interconnection process information, and assuming that different dielectric interfaces are all horizontal;
s12, constructing a transfer cube region with a unit length, and assuming that the boundary of the transfer cube region is divided into n parts, wherein n is an even number;
s13, calculating GFT and z-direction WVT using finite difference method for triangular prism sub-regions using symmetric potential conditions at the vertical plane P1 and the vertical plane P3 inside the transfer cube region; wherein the triangular prism sub-region is defined by a front side surface, a bottom surface, a top surface and a surface M of the transfer cube3Enclosed, the surface M3Is a diagonal plane within the transfer cube perpendicular to the bottom surface;
s14, calculating the remaining WVT in the x-direction by applying finite difference method to the cuboid sub-region using antisymmetric difference formula at the vertical plane P1 inside the transition cuboid region and symmetric difference formula at the vertical plane P2,determining the WVT in the y direction according to the WVT in the x direction; wherein the cuboid subregion is formed by a front side surface, a left side surface, the bottom surface, the top surface and a surface M of the transfer cube1Flour M2Enclosed, the surface M1The face M is a face passing through the center of the transfer cube and parallel to the front side of the transfer cube2Is a face passing through the center of the transfer cube and parallel to the left side of the transfer cube;
and S15, storing the calculated GFT and WVT into a database to realize the compression of the storage amount of the pre-drawing data.
Optionally, in an embodiment of the present application, the triangular prism sub-region occupies one eighth of the total volume of the transfer cube region; the cuboid subregion accounts for one fourth of the total volume of the transfer cuboid region.
In the embodiment of the present application, the finite difference method calculation process used in step S13 and step S14 is represented as follows:
1) establishing a relation matrix for solving the potential of the surface grid of the target cube area and the central point and the potential of the target cube area in a finite difference mode according to the Laplace equation of the electrostatic field and the interface potential shift continuity condition:
wherein E is11Is the potential relationship coefficient between any two cubic units in the target cubic region satisfying the Laplace equation, E12Is the potential relationship coefficient between any cubic unit and any surface grid in the target cubic region satisfying the Laplace equation, E13Is the potential relationship coefficient between the medium interface and any one cube cell in the target cube region satisfying the Laplace equation, E31And D33Respectively, the medium interface and any one of the target cubic region simultaneously satisfying the interface potential continuous condition and the electric displacement continuous conditionCoefficient of potential relationship between individual cubic cells, I2Is a unit diagonal matrix for aligning the potentials φ on the surface mesh of the region of the object cubeBIs equal to an intermediate variable fB,φFIs the potential on the target cube region medium interface, phiIIs the potential of a cube cell in the target cube region;
let k be the number of the cube cell in the target cube region where the center point of the transition region is located, ekIs a vector for extracting the electric potential of the center point of the target cube region, the value of the k position of the vector is 1, and the other values are 0, then phiIExpressed as follows:
elimination of boundary condition fBObtaining a Green function numerical solution P of the relation between the electric potential of the surface grid of the target cube area and the electric potential of the central pointkAnd solving the Green function numerical value by PkAs an initial transition probability density vector for a target cube region in the integrated circuit:
2) applying a gradient operator to the initial transition probability density vector PkObtaining an initial weight numerical value vector of a target cube region in the integrated circuit as follows:
Wherein i is 1, n2K is the number of the cubic unit in the target cubic body area where the central point of the transfer area is located, and h is the center distance between two adjacent cubic units in the target cubic body area.
In the embodiment of the present application, when the target cube region is the triangular prism sub-region, the surface mesh includes the front side surface, the top surface, and the bottom surface, excluding the surface M3(ii) a When the target cube region is the cuboid subregion, the surface mesh includes the front side, left side, top surface, and bottom surface, excluding the surface M1Flour M2。
Optionally, in some embodiments of the present application, the performing random walk capacitance parameter extraction on the multilayer dielectric interconnect structure based on the compressed pre-drawing data includes:
s21, reading the compressed pre-drawing data GFT and WVT from the database;
s22, reading a file describing an interconnection layout of the integrated circuit, and generating space management data according to the distribution condition of the conductors;
s23, selecting a main conductor i and constructing a Gaussian surface surrounding the main conductor;
s24, setting the initial value of the capacitanceSetting an initial value npath of the random walking times as 0, and setting a program termination condition;
s25, randomly taking a point r on the Gaussian surface of the main conductor i(0)At the point r(0)Generating a layered transfer cube region for the center point;if the Gaussian face is at the point r(0)The normal vector of the transfer cube is along the z-axis, one of 8 symmetrical triangular prism sub-regions of the transfer cube is randomly selected, and then the point r is selected according to the compressed z-direction WVT(1)And calculating corresponding weight omega; if the Gaussian face is at the point r(0)Selecting one of 4 symmetrical cuboid sub-regions of the transfer cube randomly along the x or y axis of the normal vector, and selecting a point r according to the compressed xy direction WVT(1)And calculating corresponding weight omega;
s26, if the current point is not on the surface of the conductor, a layered transfer cube area is constructed by taking the current point as the center, one of 8 symmetrical triangular prism sub-areas of the transfer cube is randomly selected, and then a random transfer point is selected on the surface of the cube according to the compressed GFT matched with the random transfer point;
s27, repeating the step S26 until the current point is on the surface of the conductor j, then Cij:=Cij+ω,npath:=npath+1;
According to the technical scheme of the embodiment of the application, according to given integrated circuit interconnection process information, a plurality of transfer cubes containing multiple dielectric layers are subjected to compressed-form pre-drawing by utilizing the geometric symmetry of a cube transfer region Green function table, and compressed pre-drawing data are obtained; wherein the pre-drawing data comprises: transition probability distribution GFT of a transition region containing two dielectric layers and corresponding weight distribution data WVT; and extracting random walking capacitance parameters of the multilayer dielectric interconnection structure based on the compressed pre-drawing data. Therefore, according to the method, the geometrical symmetry of the Green function table of the cubic transfer region is utilized, the storage quantity of GFT and WVT of the original pre-drawing data of the transfer region is compressed to one eighth, the compressed GFT and WVT are directly used for carrying out normal random walking capacitance extraction, and the memory overhead during program operation is saved.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
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The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic flowchart of a method for pre-patterning a multi-dielectric green's function oriented to integrated circuit interconnection capacitance extraction according to an embodiment of the present disclosure;
FIG. 2 is a diagram illustrating an exemplary method for pre-patterning a multi-dielectric green's function oriented to integrated circuit interconnection capacitance extraction according to an embodiment of the present application;
FIG. 3(a) is an exemplary diagram of a transition cube region in an embodiment of the present application;
FIG. 3(b) is an exemplary diagram of a triangular prism subregion within the transfer cube region of FIG. 3 (a);
fig. 3(c) is an exemplary diagram of a rectangular parallelepiped sub-region among the transfer cube regions in fig. 3 (a).
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.
The method for pre-drawing the multi-medium green function oriented to the extraction of the interconnection capacitance of the integrated circuit is described below with reference to the accompanying drawings.
Fig. 1 is a schematic flowchart of a method for pre-patterning a multi-dielectric green function oriented to integrated circuit interconnection capacitance extraction according to an embodiment of the present disclosure. As shown in fig. 1, the method of the present embodiment may include the following steps.
In step 101, according to given integrated circuit interconnection process information, a plurality of transfer cubes including multiple dielectric layers are pre-engraved in a compressed form by utilizing the geometric symmetry of a cube transfer region green function table, and compressed pre-engraved data are obtained. In this embodiment, the pre-drawing data may include: transition probability distribution GFT of a transition region containing two dielectric layers and corresponding weight distribution data WVT.
It should be noted that the present application makes some conventions about the faces associated with the transition cube. The six surfaces of the transfer cube are referred to in order as the bottom surface, front side surface, left side surface, back side surface, right side surface, and top surface. The face through the center of the transfer cube and parallel to the front side of the transfer cube, called face M1It divides the cube into two parts, front and back. The face passing through the center of the transfer cube and parallel to the left side of the transfer cube, called face M2It divides the cube into two parts, left and right. The diagonal plane perpendicular to the base plane within the cube is called plane M3It divides the cube equally into a left rear and a right front.
Optionally, in this embodiment of the application, as shown in fig. 2, the step 101 specifically includes:
in step 201, the integrated circuit dielectric layer information in the given integrated circuit interconnection process information is obtained, assuming that the interfaces of different dielectrics are all horizontal.
At step 202, a branch cube region of a unit length is constructed, and the boundary of the branch cube region is assumed to be divided into n parts, where n is an even number.
For example, using symmetric potential conditions (i.e., the same electrical potential for the homeotropic bilateral symmetry points) at vertical plane P1 and vertical plane P3 within the transfer cube region as shown in FIG. 3(a), for the front side, bottom, top and face M of the transfer cube as shown in FIG. 3(b)3The enclosed area occupies one eighth of the total volume of the transfer cubic areaThe GFT and the z-direction WVT are calculated using finite difference method.
204, using an anti-symmetric difference formula at a vertical plane P1 in the transfer cubic region and a symmetric difference formula at a vertical plane P2, calculating the rest WVT in the x direction by applying a finite difference method to the cuboid sub-region, and determining the WVT in the y direction according to the WVT in the x direction; wherein the cuboid subregion is composed of a front side surface, a left side surface, a bottom surface, a top surface and a surface M of the transfer cube1Flour M2Enclosed into a surface M1For a face passing through the center of the transfer cube and parallel to the front side of the transfer cube, face M2Is a face that passes through the center of the transfer cube and is parallel to the left side of the transfer cube.
For example, using an antisymmetric differential formula (i.e., the potentials of the homeotropic point symmetries are opposite to each other) at the transfer cube region interior vertical plane P1 as shown in fig. 3(a), using a symmetric differential formula (i.e., the potentials of the homeotropic point symmetries are the same) at the transfer cube region interior vertical plane P2 as shown in fig. 3(a), versus a difference between the potentials of the transfer cube front side, left side, bottom, top and face planes M as shown in fig. 3(c) of the transfer cube1Flour M2And the enclosed cuboid subarea which occupies one fourth of the total volume of the transfer cuboid area is used for calculating the rest WVT in the x direction by using a finite difference method, and the WVT table in the y direction can be directly multiplexed with the WVT in the x direction without repeated calculation.
It should be noted that, in the embodiment of the present application, the transition probabilities and corresponding weight value vectors of the transition cube are calculated by using the electrostatic field equation and the finite difference method mentioned in step 203 and step 204, and the calculation process can be as follows (assuming that the discrete number of finite difference parts on each side of the transition cube is n):
1) according to (a) laplace equation of electrostatic field:
(b) interface electrical displacement continuity condition:
establishing a relation matrix for solving the potential of the surface grid of the target cube region and the central point and the potential of the target cube region in a finite difference mode:
wherein E is11Is the potential relationship coefficient between any two cubic units in the target cubic region satisfying the Laplace's equation, E12Is the potential relationship coefficient between any cubic unit and any surface grid in the target cubic region satisfying the Laplace equation, E13Is the potential relationship coefficient between the medium interface and any one cube cell in the target cube region satisfying the Laplace equation, E31And D33The potential relation coefficients between the medium interface and any cubic unit in the target cubic area satisfying the interface potential continuous condition and the electric displacement continuous condition simultaneously, I2Is a unit diagonal matrix for aligning the potentials φ on the surface mesh of the target cubic regionBIs equal to an intermediate variable fB,φFIs the potential, phi, at the interface of the target cubic regional mediumIIs the potential of the cube cell in the target cube region;
let k be the number of the cube cell in the target cube region where the center point of the transition region is located, ekIs a vector for extracting the potential of the center point of the target cubic region, at the k position of the vectorThe value is 1, and the other values are all 0, then phiIExpressed as follows:
elimination of boundary condition fBObtaining a Green function numerical solution P of the relation between the electric potential of the surface grid of the target cube area and the electric potential of the central pointkAnd solving the Green function value by PkAs initial transition probability density vector for the target cube region in the integrated circuit:
2) acting gradient operators on the initial transition probability density vector PkObtaining an initial weight value vector of a target cube region in the integrated circuit as follows:
Wherein i is 1, n2K is the number of the cubic unit in the target cubic body area where the central point of the transfer area is located, and h is the target cubicThe center-to-center spacing of two adjacent cubic elements in a region.
It should be noted that, when the above method is applied, it is necessary to define an internal mesh, a surface mesh, and an interface mesh. When the object cube region is a triangular prism subregion, the surface mesh includes a front side surface, a top surface, and a bottom surface, excluding the surface M3(ii) a When the target cubic region is a cuboid subregion, the surface mesh includes a front side, a left side, a top surface and a bottom surface, excluding the surface M1Flour M2。
As shown in fig. 3(a) to 3(c), a finite difference region reduction scheme is used. In which fig. 3(a) sets vertical virtual interfaces P1, P2, and P3 in the primitive finite difference region. P1 is over center C and parallel to the yz plane; p2 is over center C and parallel to the xz plane; p3 is centered over C and makes a 45 degree angle with the xz plane. P1 and P3 in fig. 3(b) cut the original region into one-eighth for speeding up the computation of GFT and z-direction WVT. P1 and P2 in fig. 3(c) cut the original region into quarters to speed up the calculation of the xy direction WVT.
It should be noted that each of the uncompressed GFT and WVT tables contains six faces of data for a cube, and the four tables contain a total of 24 faces of data. As shown in fig. 3(b), the amount of GFT and z-direction WVT data pre-written in compressed form contains only one-eighth of the amount of data for the top and bottom surfaces, one-half of the front surface, and one-eighth of the total amount of data for the original six surfaces. As shown in fig. 3(c), the xy-direction WVT data amount pre-drawn in compressed form only contains one fourth of the top and bottom surfaces, one half of the front and left surfaces, and the total storage amount is one eighth of the data amount of the twelve surfaces of the original two tables. The overall pre-embossed data would be reduced by 87.5%. At the same time, the computational resource overhead for generating the data is significantly reduced because the finite difference region for generating the data is reduced.
In step 102, random walk capacitance parameter extraction is performed on the multilayer dielectric interconnect structure based on the compressed pre-drawing data.
Optionally, the method performs equiprobable random selection in the transfer cube sub-region by using symmetry, and then performs random sampling according to the matched compressed GFT and WVT. As an example, the step 102 specifically includes:
1) the compressed pre-engraving data GFT and WVT are read from the database.
2) And reading a file describing the layout of the interconnection line of the integrated circuit, and generating space management data according to the distribution condition of the conductors.
3) A main conductor i is selected and a gaussian surface surrounding the main conductor is constructed.
4) Setting initial value of capacitanceAnd setting the initial value npath of the random walking times as 0, and setting a program termination condition (the termination condition is not set as the precision q).
5) Randomly picking points r on the Gaussian surface of the main conductor i(0)At a point r(0)Generating a layered transfer cube region for the center point; if the Gaussian surface is at point r(0)The normal vector of the transfer cube is along the z-axis, one of 8 symmetrical triangular prism sub-regions of the transfer cube is randomly selected, and then the point r is selected according to the compressed z-direction WVT(1)And calculating corresponding weight omega; if the Gaussian surface is at point r(0)Selecting one of 4 symmetrical cuboid sub-regions of the transfer cube randomly along the x or y axis of the normal vector, and selecting a point r according to the compressed xy direction WVT(1)And calculating the corresponding weight omega.
6) If the current point is not on the surface of the conductor, a layered transfer cube region is constructed by taking the current point as the center, one of 8 symmetrical triangular prism sub-regions of the transfer cube is randomly selected, and then a random transfer point is selected on the surface of the cube according to the compressed GFT matched with the random transfer point.
7) Repeating the step 6) until the current point is on the surface of the conductor j, and Cij:=Cij+ω,npath:=npath+1。
Therefore, the steps of sampling the original GFT and the WVT are modified into the steps of firstly utilizing symmetry to carry out equal probability random selection in the sub-area of the transfer cube, and then carrying out random sampling according to the matched compressed GFT and WVT. In this way, the storage space of the compressed data on the disk is reduced by one eighth, and the memory overhead in the running process corresponding to the random walk program is reduced by one eighth.
According to the method for pre-engraving the multi-medium Green's function extracted for the interconnection capacitance of the integrated circuit, according to given interconnection process information of the integrated circuit, the geometric symmetry of a cubic transfer region Green's function table is utilized to pre-engrave a plurality of transfer cubes containing multi-medium layers in a compression mode, and compressed pre-engraving data are obtained; wherein the pre-drawing data comprises: transition probability distribution GFT of a transition region containing two dielectric layers and corresponding weight distribution data WVT; and extracting random walking capacitance parameters of the multilayer dielectric interconnection structure based on the compressed pre-drawing data. Therefore, according to the method, the geometrical symmetry of the Green function table of the cubic transfer region is utilized, the storage quantity of GFT and WVT of the original pre-drawing data of the transfer region is compressed to one eighth, the compressed GFT and WVT are directly used for carrying out normal random walking capacitance extraction, and the memory overhead during program operation is saved.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.
The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.
Claims (6)
1. A multi-medium Green function pre-drawing method for integrated circuit interconnection capacitance extraction is characterized by comprising the following steps:
according to given integrated circuit interconnection process information, utilizing the geometric symmetry of a cube transfer region Green function table to perform compressed pre-drawing on a plurality of transfer cubes containing multiple dielectric layers to obtain compressed pre-drawing data; wherein the pre-characterization data comprises: transition probability distribution GFT of a transition region containing two dielectric layers and corresponding weight distribution data WVT;
and extracting random walking capacitance parameters of the multilayer dielectric interconnection structure based on the compressed pre-drawing data.
2. The method of claim 1, wherein said pre-scribing several transfer cubes with multiple dielectric layers in a compressed form using the geometric symmetry of the cube transfer region green function table according to given ic interconnect process information to obtain compressed pre-scribing data comprises:
s11, obtaining the integrated circuit dielectric layer information in the given integrated circuit interconnection process information, and assuming that different dielectric interfaces are all horizontal;
s12, constructing a transfer cube region with a unit length, and assuming that the boundary of the transfer cube region is divided into n parts, wherein n is an even number;
s13, calculating GFT and z-direction WVT using finite difference method for triangular prism sub-regions using symmetric potential conditions at the vertical plane P1 and the vertical plane P3 inside the transfer cube region; wherein the triangular prism sub-region is defined by the face of a transfer cubeSide, bottom, top and face M3Enclosed, the surface M3Is a diagonal plane within the transfer cube perpendicular to the bottom surface;
s14, using an anti-symmetric difference formula at a vertical plane P1 in the transfer cubic region and a symmetric difference formula at a vertical plane P2, applying a finite difference method to the cuboid sub-region to calculate the rest of the WVT in the x direction, and determining the WVT in the y direction according to the WVT in the x direction; wherein the cuboid subregion is formed by a front side surface, a left side surface, the bottom surface, the top surface and a surface M of the transfer cube1Flour M2Enclosed, the surface M1The face M is a face passing through the center of the transfer cube and parallel to the front side of the transfer cube2Is a face passing through the center of the transfer cube and parallel to the left side of the transfer cube;
and S15, storing the calculated GFT and WVT into a database to realize the compression of the storage amount of the pre-drawing data.
3. The method of claim 2, wherein the triangular prism sub-region occupies one-eighth of the total volume of the transfer cube region; the cuboid subregion accounts for one fourth of the total volume of the transfer cuboid region.
4. The method of claim 2, wherein the finite difference method calculation procedure used in the steps S13 and S14 is expressed as follows:
1) establishing a relation matrix for solving the potential of the surface grid of the target cube area and the central point and the potential of the target cube area in a finite difference mode according to the Laplace equation of the electrostatic field and the interface potential shift continuity condition:
wherein E is11Is to satisfy the target of the Laplace equationCoefficient of the potential relationship between any two cubic units in the cubic region, E12Is the potential relationship coefficient between any cubic unit and any surface grid in the target cubic region satisfying the Laplace equation, E13Is the potential relationship coefficient between the medium interface and any one cube cell in the target cube region satisfying the Laplace equation, E31And D33Respectively is the potential relation coefficient between the medium interface and any cubic unit in the target cubic area which simultaneously satisfies the interface potential continuous condition and the electric displacement continuous condition, I2Is a unit diagonal matrix for aligning the potentials φ on the surface mesh of the region of the object cubeBIs equal to an intermediate variable fB,φFIs the potential on the target cube region medium interface, phiIIs the potential of a cube cell in the target cube region;
let k be the number of the cube cell in the target cube region where the center point of the transition region is located, ekIs a vector for extracting the electric potential of the center point of the target cube region, the value of the k position of the vector is 1, and the other values are 0, then phiIExpressed as follows:
elimination of boundary condition fBObtaining a Green function numerical solution P of the relation between the electric potential of the surface grid of the target cube area and the electric potential of the central pointkAnd solving the Green function numerical value by PkAs an initial transition probability density vector for a target cube region in the integrated circuit:
2) applying a gradient operator to the initial transition probability density vector PkObtaining the objects in the integrated circuitThe initial weight value vector for the cube region is as follows:
Wherein i is 1, n2K is the number of the cubic unit in the target cubic body area where the central point of the transfer area is located, and h is the center distance between two adjacent cubic units in the target cubic body area.
5. The method of claim 4, wherein when the target cube region is the triangular prism subregion, the surface mesh includes the front side, top, and bottom surfaces, excluding the face M3(ii) a When the target cube region is the cuboid subregion, the surface mesh includes the front side, left side, top surface, and bottom surface, excluding the surface M1Flour M2。
6. The method of claim 1, wherein the performing random walk capacitance parameter extraction on the multilayer dielectric interconnect structure based on the compressed pre-scribing data comprises:
s21, reading the compressed pre-drawing data GFT and WVT from the database;
s22, reading a file describing an interconnection layout of the integrated circuit, and generating space management data according to the distribution condition of the conductors;
s23, selecting a main conductor i and constructing a Gaussian surface surrounding the main conductor;
s24, setting the initial value of the capacitanceSetting an initial value npath of the random walking times as 0, and setting a program termination condition;
s25, randomly taking a point r on the Gaussian surface of the main conductor i(0)At the point r(0)Generating a layered transfer cube region for the center point; if the Gaussian face is at the point r(0)The normal vector of the transfer cube is along the z-axis, one of 8 symmetrical triangular prism sub-regions of the transfer cube is randomly selected, and then the point r is selected according to the compressed z-direction WVT(1)And calculating corresponding weight omega; if the Gaussian face is at the point r(0)Selecting one of 4 symmetrical cuboid sub-regions of the transfer cube randomly along the x or y axis of the normal vector, and selecting a point r according to the compressed xy direction WVT(1)And calculating corresponding weight omega;
s26, if the current point is not on the surface of the conductor, a layered transfer cube area is constructed by taking the current point as the center, one of 8 symmetrical triangular prism sub-areas of the transfer cube is randomly selected, and then a random transfer point is selected on the surface of the cube according to the compressed GFT matched with the random transfer point;
s27, repeating the step S26 until the current point is on the surface of the conductor j, then Cij:=Cij+ω,npath:=npath+1;
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN116266209A (en) * | 2022-11-28 | 2023-06-20 | 湘潭大学 | Calculation method for double-sided medium loaded parallel plate waveguide electrostatic field |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102651047A (en) * | 2012-04-11 | 2012-08-29 | 清华大学 | Method for extracting and calculating capacitance parameter based on random walk in integrated circuit design |
CN104008255A (en) * | 2014-06-13 | 2014-08-27 | 清华大学 | Multimedium random walk calculating method and system oriented to integrated circuit capacitance extraction |
CN105930572A (en) * | 2016-04-15 | 2016-09-07 | 清华大学 | Touch screen capacitance simulation-oriented multi-medium pre-description method |
CN111767669A (en) * | 2020-07-08 | 2020-10-13 | 湖南省有色地质勘查研究院 | Novel pseudo-random induced polarization finite element numerical simulation method and system |
-
2021
- 2021-02-19 CN CN202110191939.0A patent/CN112800710B/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102651047A (en) * | 2012-04-11 | 2012-08-29 | 清华大学 | Method for extracting and calculating capacitance parameter based on random walk in integrated circuit design |
CN104008255A (en) * | 2014-06-13 | 2014-08-27 | 清华大学 | Multimedium random walk calculating method and system oriented to integrated circuit capacitance extraction |
CN105930572A (en) * | 2016-04-15 | 2016-09-07 | 清华大学 | Touch screen capacitance simulation-oriented multi-medium pre-description method |
CN111767669A (en) * | 2020-07-08 | 2020-10-13 | 湖南省有色地质勘查研究院 | Novel pseudo-random induced polarization finite element numerical simulation method and system |
Non-Patent Citations (2)
Title |
---|
YU, WJ 等: "《Advancements and Challenges on Parasitic Extraction for Advanced Process Technologies》", 《ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE PROCEEDINGS》 * |
齐明 等: "《面向高精度寄生参数提取与时延分析的集成电路版图数据转换方法》", 《计算机辅助设计与图形学学报》 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN116266209A (en) * | 2022-11-28 | 2023-06-20 | 湘潭大学 | Calculation method for double-sided medium loaded parallel plate waveguide electrostatic field |
CN116266209B (en) * | 2022-11-28 | 2024-03-01 | 湘潭大学 | Calculation method for double-sided medium loaded parallel plate waveguide electrostatic field |
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