CN112800710A - Multi-medium Green function pre-drawing method for extracting interconnection capacitance of integrated circuit - Google Patents

Multi-medium Green function pre-drawing method for extracting interconnection capacitance of integrated circuit Download PDF

Info

Publication number
CN112800710A
CN112800710A CN202110191939.0A CN202110191939A CN112800710A CN 112800710 A CN112800710 A CN 112800710A CN 202110191939 A CN202110191939 A CN 202110191939A CN 112800710 A CN112800710 A CN 112800710A
Authority
CN
China
Prior art keywords
cube
transfer
region
area
wvt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110191939.0A
Other languages
Chinese (zh)
Other versions
CN112800710B (en
Inventor
喻文健
杨明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tsinghua University
Original Assignee
Tsinghua University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tsinghua University filed Critical Tsinghua University
Priority to CN202110191939.0A priority Critical patent/CN112800710B/en
Publication of CN112800710A publication Critical patent/CN112800710A/en
Application granted granted Critical
Publication of CN112800710B publication Critical patent/CN112800710B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F18/00—Pattern recognition
    • G06F18/20—Analysing
    • G06F18/23—Clustering techniques
    • G06F18/232—Non-hierarchical techniques
    • G06F18/2321—Non-hierarchical techniques using statistics or function optimisation, e.g. modelling of probability density functions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G06F30/23—Design optimisation, verification or simulation using finite element methods [FEM] or finite difference methods [FDM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/08—Probabilistic or stochastic CAD
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Data Mining & Analysis (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Evolutionary Biology (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Bioinformatics & Computational Biology (AREA)
  • Bioinformatics & Cheminformatics (AREA)
  • Artificial Intelligence (AREA)
  • Probability & Statistics with Applications (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

本申请提出一种面向集成电路互连电容提取的多介质格林函数预刻画方法。该方法包括：根据给定的集成电路互连工艺信息，利用立方体转移区域格林函数表的几何对称性，对若干种含多介质层的转移立方体进行压缩形式的预刻画，获得压缩的预刻画数据；其中，预刻画数据包括：含两层介质层转移区域的转移概率分布GFT、以及相应权值分布数据WVT；基于压缩的预刻画数据对多层介质互连结构进行随机行走电容参数提取。本申请利用立方体转移区域格林函数表的几何对称性，将原有的转移区域预刻画数据GFT和WVT的存储量进行压缩，并直接使用压缩后的GFT和WVT进行正常随机行走电容提取，节省了程序运行时内存开销。

Figure 202110191939

The present application proposes a multi-medium Green's function pre-characterization method for the extraction of interconnect capacitance of integrated circuits. The method includes: according to given integrated circuit interconnection process information, using the geometric symmetry of the Green's function table of the cube transfer area, pre-characterizing several transfer cubes containing multiple dielectric layers in a compressed form to obtain compressed pre-characterizing data ; wherein, the pre-characterized data includes: transition probability distribution GFT containing two-layer dielectric layer transition regions, and corresponding weight distribution data WVT; based on the compressed pre-characterized data, random walk capacitance parameter extraction is performed on the multi-layer dielectric interconnect structure. The present application utilizes the geometric symmetry of the Green's function table of the cube transfer area to compress the storage capacity of the original transfer area pre-characterized data GFT and WVT, and directly uses the compressed GFT and WVT for normal random walk capacitance extraction, which saves money. Program runtime memory overhead.

Figure 202110191939

Description

Multi-medium Green function pre-drawing method for extracting interconnection capacitance of integrated circuit
Technical Field
The application relates to the field of VLSI (Very Large Scale Integrated circuits) physical design and verification, in particular to a multi-medium green function pre-drawing method for extracting interconnection capacitance of an Integrated circuit.
Background
In the design flow of the integrated circuit, functional description is firstly provided, and then a layout for describing the process size and the structure of the semiconductor is obtained through logic design and layout design. At this time, the layout verification is needed, that is, whether the design can meet the initially set requirements is verified through computer software simulation and the like. If the requirements are met, the next production and manufacturing can be carried out; otherwise, the necessary modifications are made to return to the logic design and the like. This iterative process is repeated until layout verification indicates that the design can indeed meet the requirements. In layout verification, an important link is called as 'interconnection parasitic parameter extraction'.
With the development of integrated circuit manufacturing technology, circuit scale is increasing and feature size is shrinking, and nowadays many chips already contain several millions or even hundreds of millions of devices. However, parasitic effects of interconnect lines in integrated circuits cause the effect of the interconnect lines on circuit delay to exceed the effect of the device on delay. Therefore, accurate extraction and calculation of parameters such as capacitance and resistance of the interconnection line are required, and the correctness and the validity of circuit simulation and verification can be guaranteed only in this way. With the increasing requirement on the calculation accuracy in practical application, a three-dimensional extraction method, namely a three-dimensional field solver, is required to be used for extracting the capacitance parameters between the interconnection lines for accurate solution. The calculation of the field solver is time-consuming, and the optimization and accelerated research significance of the algorithm is great. However, the related art pre-scribing method usually involves excessively large memory overhead.
Disclosure of Invention
The object of the present application is to solve at least to some extent one of the above mentioned technical problems.
To this end, an object of the present application is to provide a method for pre-patterning a multi-dielectric green function oriented to integrated circuit interconnection capacitance extraction. The method utilizes the geometric symmetry of the Green function table of the cube transfer region to compress the storage quantity of the pre-drawing data GFT and WVT of the original transfer region, and directly uses the compressed GFT and WVT to extract the normal random walking capacitance, thereby saving the memory overhead when the program runs.
In order to achieve the above object, an embodiment of a first aspect of the present application provides a method for pre-patterning a multi-dielectric green function oriented to integrated circuit interconnection capacitance extraction, including:
according to given integrated circuit interconnection process information, utilizing the geometric symmetry of a cube transfer region Green function table to perform compressed pre-drawing on a plurality of transfer cubes containing multiple dielectric layers to obtain compressed pre-drawing data; wherein the pre-characterization data comprises: transition probability distribution GFT of a transition region containing two dielectric layers and corresponding weight distribution data WVT;
and extracting random walking capacitance parameters of the multilayer dielectric interconnection structure based on the compressed pre-drawing data.
Optionally, in some embodiments of the present application, the pre-scribing in a compressed form on several transfer cubes including multiple dielectric layers according to given integrated circuit interconnection process information by using geometric symmetry of a cube transfer region green function table to obtain compressed pre-scribing data includes:
s11, obtaining the integrated circuit dielectric layer information in the given integrated circuit interconnection process information, and assuming that different dielectric interfaces are all horizontal;
s12, constructing a transfer cube region with a unit length, and assuming that the boundary of the transfer cube region is divided into n parts, wherein n is an even number;
s13, calculating GFT and z-direction WVT using finite difference method for triangular prism sub-regions using symmetric potential conditions at the vertical plane P1 and the vertical plane P3 inside the transfer cube region; wherein the triangular prism sub-region is defined by a front side surface, a bottom surface, a top surface and a surface M of the transfer cube3Enclosed, the surface M3Is a diagonal plane within the transfer cube perpendicular to the bottom surface;
s14, calculating the remaining WVT in the x-direction by applying finite difference method to the cuboid sub-region using antisymmetric difference formula at the vertical plane P1 inside the transition cuboid region and symmetric difference formula at the vertical plane P2,determining the WVT in the y direction according to the WVT in the x direction; wherein the cuboid subregion is formed by a front side surface, a left side surface, the bottom surface, the top surface and a surface M of the transfer cube1Flour M2Enclosed, the surface M1The face M is a face passing through the center of the transfer cube and parallel to the front side of the transfer cube2Is a face passing through the center of the transfer cube and parallel to the left side of the transfer cube;
and S15, storing the calculated GFT and WVT into a database to realize the compression of the storage amount of the pre-drawing data.
Optionally, in an embodiment of the present application, the triangular prism sub-region occupies one eighth of the total volume of the transfer cube region; the cuboid subregion accounts for one fourth of the total volume of the transfer cuboid region.
In the embodiment of the present application, the finite difference method calculation process used in step S13 and step S14 is represented as follows:
1) establishing a relation matrix for solving the potential of the surface grid of the target cube area and the central point and the potential of the target cube area in a finite difference mode according to the Laplace equation of the electrostatic field and the interface potential shift continuity condition:
Figure BDA0002944779100000031
wherein E is11Is the potential relationship coefficient between any two cubic units in the target cubic region satisfying the Laplace equation, E12Is the potential relationship coefficient between any cubic unit and any surface grid in the target cubic region satisfying the Laplace equation, E13Is the potential relationship coefficient between the medium interface and any one cube cell in the target cube region satisfying the Laplace equation, E31And D33Respectively, the medium interface and any one of the target cubic region simultaneously satisfying the interface potential continuous condition and the electric displacement continuous conditionCoefficient of potential relationship between individual cubic cells, I2Is a unit diagonal matrix for aligning the potentials φ on the surface mesh of the region of the object cubeBIs equal to an intermediate variable fB，φFIs the potential on the target cube region medium interface, phiIIs the potential of a cube cell in the target cube region;
let k be the number of the cube cell in the target cube region where the center point of the transition region is located, ekIs a vector for extracting the electric potential of the center point of the target cube region, the value of the k position of the vector is 1, and the other values are 0, then phiIExpressed as follows:
Figure BDA0002944779100000032
elimination of boundary condition fBObtaining a Green function numerical solution P of the relation between the electric potential of the surface grid of the target cube area and the electric potential of the central pointkAnd solving the Green function numerical value by PkAs an initial transition probability density vector for a target cube region in the integrated circuit:
Figure BDA0002944779100000033
2) applying a gradient operator to the initial transition probability density vector PkObtaining an initial weight numerical value vector of a target cube region in the integrated circuit as follows:
Figure BDA0002944779100000034
Figure BDA0002944779100000035
Figure BDA0002944779100000036
wherein
Figure BDA0002944779100000037
Is a vector in which the elements
Figure BDA0002944779100000041
Wherein i is 1, n2K is the number of the cubic unit in the target cubic body area where the central point of the transfer area is located, and h is the center distance between two adjacent cubic units in the target cubic body area.
In the embodiment of the present application, when the target cube region is the triangular prism sub-region, the surface mesh includes the front side surface, the top surface, and the bottom surface, excluding the surface M3(ii) a When the target cube region is the cuboid subregion, the surface mesh includes the front side, left side, top surface, and bottom surface, excluding the surface M1Flour M2。
Optionally, in some embodiments of the present application, the performing random walk capacitance parameter extraction on the multilayer dielectric interconnect structure based on the compressed pre-drawing data includes:
s21, reading the compressed pre-drawing data GFT and WVT from the database;
s22, reading a file describing an interconnection layout of the integrated circuit, and generating space management data according to the distribution condition of the conductors;
s23, selecting a main conductor i and constructing a Gaussian surface surrounding the main conductor;
s24, setting the initial value of the capacitance
Figure BDA0002944779100000042
Setting an initial value npath of the random walking times as 0, and setting a program termination condition;
s25, randomly taking a point r on the Gaussian surface of the main conductor i(0)At the point r(0)Generating a layered transfer cube region for the center point;if the Gaussian face is at the point r(0)The normal vector of the transfer cube is along the z-axis, one of 8 symmetrical triangular prism sub-regions of the transfer cube is randomly selected, and then the point r is selected according to the compressed z-direction WVT(1)And calculating corresponding weight omega; if the Gaussian face is at the point r(0)Selecting one of 4 symmetrical cuboid sub-regions of the transfer cube randomly along the x or y axis of the normal vector, and selecting a point r according to the compressed xy direction WVT(1)And calculating corresponding weight omega;
s26, if the current point is not on the surface of the conductor, a layered transfer cube area is constructed by taking the current point as the center, one of 8 symmetrical triangular prism sub-areas of the transfer cube is randomly selected, and then a random transfer point is selected on the surface of the cube according to the compressed GFT matched with the random transfer point;
s27, repeating the step S26 until the current point is on the surface of the conductor j, then Cij:＝Cij+ω,npath:＝npath+1；
S28, repeating the steps S25-S27 until the termination condition is satisfied, at which time
Figure BDA0002944779100000043
According to the technical scheme of the embodiment of the application, according to given integrated circuit interconnection process information, a plurality of transfer cubes containing multiple dielectric layers are subjected to compressed-form pre-drawing by utilizing the geometric symmetry of a cube transfer region Green function table, and compressed pre-drawing data are obtained; wherein the pre-drawing data comprises: transition probability distribution GFT of a transition region containing two dielectric layers and corresponding weight distribution data WVT; and extracting random walking capacitance parameters of the multilayer dielectric interconnection structure based on the compressed pre-drawing data. Therefore, according to the method, the geometrical symmetry of the Green function table of the cubic transfer region is utilized, the storage quantity of GFT and WVT of the original pre-drawing data of the transfer region is compressed to one eighth, the compressed GFT and WVT are directly used for carrying out normal random walking capacitance extraction, and the memory overhead during program operation is saved.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic flowchart of a method for pre-patterning a multi-dielectric green's function oriented to integrated circuit interconnection capacitance extraction according to an embodiment of the present disclosure;
FIG. 2 is a diagram illustrating an exemplary method for pre-patterning a multi-dielectric green's function oriented to integrated circuit interconnection capacitance extraction according to an embodiment of the present application;
FIG. 3(a) is an exemplary diagram of a transition cube region in an embodiment of the present application;
FIG. 3(b) is an exemplary diagram of a triangular prism subregion within the transfer cube region of FIG. 3 (a);
fig. 3(c) is an exemplary diagram of a rectangular parallelepiped sub-region among the transfer cube regions in fig. 3 (a).
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.
The method for pre-drawing the multi-medium green function oriented to the extraction of the interconnection capacitance of the integrated circuit is described below with reference to the accompanying drawings.
Fig. 1 is a schematic flowchart of a method for pre-patterning a multi-dielectric green function oriented to integrated circuit interconnection capacitance extraction according to an embodiment of the present disclosure. As shown in fig. 1, the method of the present embodiment may include the following steps.
In step 101, according to given integrated circuit interconnection process information, a plurality of transfer cubes including multiple dielectric layers are pre-engraved in a compressed form by utilizing the geometric symmetry of a cube transfer region green function table, and compressed pre-engraved data are obtained. In this embodiment, the pre-drawing data may include: transition probability distribution GFT of a transition region containing two dielectric layers and corresponding weight distribution data WVT.
It should be noted that the present application makes some conventions about the faces associated with the transition cube. The six surfaces of the transfer cube are referred to in order as the bottom surface, front side surface, left side surface, back side surface, right side surface, and top surface. The face through the center of the transfer cube and parallel to the front side of the transfer cube, called face M1It divides the cube into two parts, front and back. The face passing through the center of the transfer cube and parallel to the left side of the transfer cube, called face M2It divides the cube into two parts, left and right. The diagonal plane perpendicular to the base plane within the cube is called plane M3It divides the cube equally into a left rear and a right front.
Optionally, in this embodiment of the application, as shown in fig. 2, the step 101 specifically includes:
in step 201, the integrated circuit dielectric layer information in the given integrated circuit interconnection process information is obtained, assuming that the interfaces of different dielectrics are all horizontal.
At step 202, a branch cube region of a unit length is constructed, and the boundary of the branch cube region is assumed to be divided into n parts, where n is an even number.
Step 203, calculating the GFT and the WVT in the z direction by applying a finite difference method to the triangular prism subarea by using a symmetrical potential condition at a vertical plane P1 and a vertical plane P3 in the transfer cube area; wherein the triangular prism sub-region consists of the front side surface, the bottom surface, the top surface and the surface M of the transfer cube3Enclosed into a surface M3Is a diagonal plane perpendicular to the bottom plane within the transfer cube.
For example, using symmetric potential conditions (i.e., the same electrical potential for the homeotropic bilateral symmetry points) at vertical plane P1 and vertical plane P3 within the transfer cube region as shown in FIG. 3(a), for the front side, bottom, top and face M of the transfer cube as shown in FIG. 3(b)3The enclosed area occupies one eighth of the total volume of the transfer cubic areaThe GFT and the z-direction WVT are calculated using finite difference method.
204, using an anti-symmetric difference formula at a vertical plane P1 in the transfer cubic region and a symmetric difference formula at a vertical plane P2, calculating the rest WVT in the x direction by applying a finite difference method to the cuboid sub-region, and determining the WVT in the y direction according to the WVT in the x direction; wherein the cuboid subregion is composed of a front side surface, a left side surface, a bottom surface, a top surface and a surface M of the transfer cube1Flour M2Enclosed into a surface M1For a face passing through the center of the transfer cube and parallel to the front side of the transfer cube, face M2Is a face that passes through the center of the transfer cube and is parallel to the left side of the transfer cube.
For example, using an antisymmetric differential formula (i.e., the potentials of the homeotropic point symmetries are opposite to each other) at the transfer cube region interior vertical plane P1 as shown in fig. 3(a), using a symmetric differential formula (i.e., the potentials of the homeotropic point symmetries are the same) at the transfer cube region interior vertical plane P2 as shown in fig. 3(a), versus a difference between the potentials of the transfer cube front side, left side, bottom, top and face planes M as shown in fig. 3(c) of the transfer cube1Flour M2And the enclosed cuboid subarea which occupies one fourth of the total volume of the transfer cuboid area is used for calculating the rest WVT in the x direction by using a finite difference method, and the WVT table in the y direction can be directly multiplexed with the WVT in the x direction without repeated calculation.
It should be noted that, in the embodiment of the present application, the transition probabilities and corresponding weight value vectors of the transition cube are calculated by using the electrostatic field equation and the finite difference method mentioned in step 203 and step 204, and the calculation process can be as follows (assuming that the discrete number of finite difference parts on each side of the transition cube is n):
1) according to (a) laplace equation of electrostatic field:
Figure BDA0002944779100000071
(b) interface electrical displacement continuity condition:
Figure BDA0002944779100000072
Figure BDA0002944779100000073
Figure BDA0002944779100000074
establishing a relation matrix for solving the potential of the surface grid of the target cube region and the central point and the potential of the target cube region in a finite difference mode:
Figure BDA0002944779100000075
wherein E is11Is the potential relationship coefficient between any two cubic units in the target cubic region satisfying the Laplace's equation, E12Is the potential relationship coefficient between any cubic unit and any surface grid in the target cubic region satisfying the Laplace equation, E13Is the potential relationship coefficient between the medium interface and any one cube cell in the target cube region satisfying the Laplace equation, E31And D33The potential relation coefficients between the medium interface and any cubic unit in the target cubic area satisfying the interface potential continuous condition and the electric displacement continuous condition simultaneously, I2Is a unit diagonal matrix for aligning the potentials φ on the surface mesh of the target cubic regionBIs equal to an intermediate variable fB，φFIs the potential, phi, at the interface of the target cubic regional mediumIIs the potential of the cube cell in the target cube region;
let k be the number of the cube cell in the target cube region where the center point of the transition region is located, ekIs a vector for extracting the potential of the center point of the target cubic region, at the k position of the vectorThe value is 1, and the other values are all 0, then phiIExpressed as follows:
Figure BDA0002944779100000076
elimination of boundary condition fBObtaining a Green function numerical solution P of the relation between the electric potential of the surface grid of the target cube area and the electric potential of the central pointkAnd solving the Green function value by PkAs initial transition probability density vector for the target cube region in the integrated circuit:
Figure BDA0002944779100000081
2) acting gradient operators on the initial transition probability density vector PkObtaining an initial weight value vector of a target cube region in the integrated circuit as follows:
Figure BDA0002944779100000082
Figure BDA0002944779100000083
Figure BDA0002944779100000084
wherein
Figure BDA0002944779100000085
Is a vector in which the elements
Figure BDA0002944779100000086
Wherein i is 1, n2K is the number of the cubic unit in the target cubic body area where the central point of the transfer area is located, and h is the target cubicThe center-to-center spacing of two adjacent cubic elements in a region.
It should be noted that, when the above method is applied, it is necessary to define an internal mesh, a surface mesh, and an interface mesh. When the object cube region is a triangular prism subregion, the surface mesh includes a front side surface, a top surface, and a bottom surface, excluding the surface M3(ii) a When the target cubic region is a cuboid subregion, the surface mesh includes a front side, a left side, a top surface and a bottom surface, excluding the surface M1Flour M2。
Step 205, storing the calculated GFT and WVT into a database to compress the storage amount of the pre-drawing data.
As shown in fig. 3(a) to 3(c), a finite difference region reduction scheme is used. In which fig. 3(a) sets vertical virtual interfaces P1, P2, and P3 in the primitive finite difference region. P1 is over center C and parallel to the yz plane; p2 is over center C and parallel to the xz plane; p3 is centered over C and makes a 45 degree angle with the xz plane. P1 and P3 in fig. 3(b) cut the original region into one-eighth for speeding up the computation of GFT and z-direction WVT. P1 and P2 in fig. 3(c) cut the original region into quarters to speed up the calculation of the xy direction WVT.
It should be noted that each of the uncompressed GFT and WVT tables contains six faces of data for a cube, and the four tables contain a total of 24 faces of data. As shown in fig. 3(b), the amount of GFT and z-direction WVT data pre-written in compressed form contains only one-eighth of the amount of data for the top and bottom surfaces, one-half of the front surface, and one-eighth of the total amount of data for the original six surfaces. As shown in fig. 3(c), the xy-direction WVT data amount pre-drawn in compressed form only contains one fourth of the top and bottom surfaces, one half of the front and left surfaces, and the total storage amount is one eighth of the data amount of the twelve surfaces of the original two tables. The overall pre-embossed data would be reduced by 87.5%. At the same time, the computational resource overhead for generating the data is significantly reduced because the finite difference region for generating the data is reduced.
In step 102, random walk capacitance parameter extraction is performed on the multilayer dielectric interconnect structure based on the compressed pre-drawing data.
Optionally, the method performs equiprobable random selection in the transfer cube sub-region by using symmetry, and then performs random sampling according to the matched compressed GFT and WVT. As an example, the step 102 specifically includes:
1) the compressed pre-engraving data GFT and WVT are read from the database.
2) And reading a file describing the layout of the interconnection line of the integrated circuit, and generating space management data according to the distribution condition of the conductors.
3) A main conductor i is selected and a gaussian surface surrounding the main conductor is constructed.
4) Setting initial value of capacitance
Figure BDA0002944779100000091
And setting the initial value npath of the random walking times as 0, and setting a program termination condition (the termination condition is not set as the precision q).
5) Randomly picking points r on the Gaussian surface of the main conductor i(0)At a point r(0)Generating a layered transfer cube region for the center point; if the Gaussian surface is at point r(0)The normal vector of the transfer cube is along the z-axis, one of 8 symmetrical triangular prism sub-regions of the transfer cube is randomly selected, and then the point r is selected according to the compressed z-direction WVT(1)And calculating corresponding weight omega; if the Gaussian surface is at point r(0)Selecting one of 4 symmetrical cuboid sub-regions of the transfer cube randomly along the x or y axis of the normal vector, and selecting a point r according to the compressed xy direction WVT(1)And calculating the corresponding weight omega.
6) If the current point is not on the surface of the conductor, a layered transfer cube region is constructed by taking the current point as the center, one of 8 symmetrical triangular prism sub-regions of the transfer cube is randomly selected, and then a random transfer point is selected on the surface of the cube according to the compressed GFT matched with the random transfer point.
7) Repeating the step 6) until the current point is on the surface of the conductor j, and Cij:＝Cij+ω,npath:＝npath+1。
8) Repeating the steps 5) to 7) until the termination condition is satisfied, at which time
Figure BDA0002944779100000092
Therefore, the steps of sampling the original GFT and the WVT are modified into the steps of firstly utilizing symmetry to carry out equal probability random selection in the sub-area of the transfer cube, and then carrying out random sampling according to the matched compressed GFT and WVT. In this way, the storage space of the compressed data on the disk is reduced by one eighth, and the memory overhead in the running process corresponding to the random walk program is reduced by one eighth.
According to the method for pre-engraving the multi-medium Green's function extracted for the interconnection capacitance of the integrated circuit, according to given interconnection process information of the integrated circuit, the geometric symmetry of a cubic transfer region Green's function table is utilized to pre-engrave a plurality of transfer cubes containing multi-medium layers in a compression mode, and compressed pre-engraving data are obtained; wherein the pre-drawing data comprises: transition probability distribution GFT of a transition region containing two dielectric layers and corresponding weight distribution data WVT; and extracting random walking capacitance parameters of the multilayer dielectric interconnection structure based on the compressed pre-drawing data. Therefore, according to the method, the geometrical symmetry of the Green function table of the cubic transfer region is utilized, the storage quantity of GFT and WVT of the original pre-drawing data of the transfer region is compressed to one eighth, the compressed GFT and WVT are directly used for carrying out normal random walking capacitance extraction, and the memory overhead during program operation is saved.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.
The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.

Claims (6)

1.一种面向集成电路互连电容提取的多介质格林函数预刻画方法，其特征在于，包括：1. a kind of multi-medium Green's function pre-characterization method for the extraction of integrated circuit interconnection capacitance, is characterized in that, comprises: 根据给定的集成电路互连工艺信息，利用立方体转移区域格林函数表的几何对称性，对若干种含多介质层的转移立方体进行压缩形式的预刻画，获得压缩的预刻画数据；其中，所述预刻画数据包括：含两层介质层转移区域的转移概率分布GFT、以及相应权值分布数据WVT；According to the given integrated circuit interconnection process information, using the geometric symmetry of the Green's function table of the cube transfer area, several kinds of transfer cubes containing multiple dielectric layers are pre-characterized in a compressed form to obtain compressed pre-characterized data; The pre-characterized data includes: transition probability distribution GFT containing two-layer dielectric layer transition regions, and corresponding weight distribution data WVT; 基于所述压缩的预刻画数据对多层介质互连结构进行随机行走电容参数提取。Random walk capacitance parameter extraction is performed on the multilayer dielectric interconnect structure based on the compressed pre-characterized data. 2.根据权利要求1所述的方法，其特征在于，所述根据给定的集成电路互连工艺信息，利用立方体转移区域格林函数表的几何对称性，对若干种含多介质层的转移立方体进行压缩形式的预刻画，获得压缩的预刻画数据，包括：2. The method according to claim 1, wherein, according to the given integrated circuit interconnection process information, the geometric symmetry of the Green's function table of the cube transfer area is used to perform the transfer cubes containing multiple dielectric layers for several kinds of transfer cubes. Pre-profile in compressed form to obtain compressed pre-profile data, including: S11，获取给定的集成电路互连工艺信息之中的集成电路介质层信息，假设不同介质交界面都是水平的；S11, obtain the integrated circuit dielectric layer information in the given integrated circuit interconnection process information, assuming that the interfaces of different media are horizontal; S12，构建一个单位长度的转移立方体区域，且假定所述转移立方体区域的边界被分割成n份，其中所述n为偶数；S12, constructing a transfer cube region of unit length, and it is assumed that the boundary of the transfer cube region is divided into n parts, wherein the n is an even number; S13，在所述转移立方体区域内部垂直平面P1和垂直平面P3处使用对称电势条件，对三棱柱子区域应用有限差分法计算GFT和z方向的WVT；其中，所述三棱柱子区域由转移立方体的正侧面、底面、顶面和面M3围成的，所述面M3为所述转移立方体内垂直于所述底面的对角面；S13, using symmetrical potential conditions at the vertical plane P1 and the vertical plane P3 inside the transfer cube region, applying the finite difference method to the triangular prism sub-region to calculate the GFT and the WVT in the z direction; wherein, the triangular prism sub-region is composed of the transfer cube The front side surface, bottom surface, top surface and surface M 3 are surrounded by, and the surface M 3 is the diagonal surface perpendicular to the bottom surface in the transfer cube; S14，在所述转移立方体区域内部垂直平面P1处使用反对称差分公式，在所述垂直平面P2处使用对称差分公式，对长方体子区域应用有限差分法计算余下x方向的WVT，并根据所述x方向的WVT确定y方向的WVT；其中，所述长方体子区域由所述转移立方体的正侧面、左侧面、所述底面、所述顶面和面M1、面M2围成的，所述面M1为通过所述转移立方体的中心且平行于所述转移立方体前侧面的面，所述面M2为通过所述转移立方体的中心且平行于所述转移立方体左侧面的面；S14, using the antisymmetric difference formula at the vertical plane P1 inside the transfer cube region, using the symmetric difference formula at the vertical plane P2, applying the finite difference method to the cuboid sub-region to calculate the WVT in the remaining x direction, and according to the The WVT in the x-direction determines the WVT in the y-direction; wherein, the cuboid sub-region is surrounded by the front side, left side, bottom, top, and M 1 and M 2 of the transfer cube, The face M 1 is the face passing through the center of the transfer cube and parallel to the front side of the transfer cube, and the face M 2 is the face passing through the center of the transfer cube and parallel to the left side of the transfer cube ; S15，将算得的GFT和WVT存入数据库，以实现将所述预刻画数据的存储量进行压缩。S15: Store the calculated GFT and WVT in a database, so as to compress the storage amount of the pre-characterized data. 3.根据权利要求2所述的方法，其特征在于，所述三棱柱子区域占所述转移立方体区域总体积的八分之一；所述长方体子区域占所述转移立方体区域总体积的四分之一。3 . The method according to claim 2 , wherein the triangular prism sub-region accounts for one-eighth of the total volume of the transfer cube region; the rectangular parallelepiped sub-region accounts for four-fourth of the total volume of the transfer cube region. one part. 4.根据权利要求2所述的方法，其特征在于，所述步骤S13和步骤S14中所使用的有限差分法计算过程如下表示：4. The method according to claim 2, wherein the finite difference method calculation process used in the step S13 and the step S14 is expressed as follows: 1)根据静电场的拉普拉斯方程和交界面电位移连续性条件，以有限差分形式建立一个求解目标立方体区域表面网格的电势与目标立方体区域中心点与电势的关系矩阵：1) According to the Laplace equation of the electrostatic field and the continuity condition of the electric displacement at the interface, a relationship matrix between the electric potential for solving the surface mesh of the target cube area and the center point of the target cube area and the electric potential is established in the form of finite difference:
Figure FDA0002944779090000021
Figure FDA0002944779090000021
 其中，E11是满足所述拉普拉斯方程的目标立方体区域内任意两个立方体单元之间的电势关系系数，E12是满足所述拉普拉斯方程的目标立方体区域内任意一个立方体单元与任意一个表面网格之间的电势关系系数，E13是满足所述拉普拉斯方程的目标立方体区域中介质交界面与任意一个立方体单元之间的电势关系系数，E31和D33分别是同时满足所述交界面电势连续条件和电位移连续条件的目标立方体区域中介质交界面与任意一个立方体单元之间的电势关系系数，I2是单位对角矩阵，用于使所述目标立方体区域表面网格上的电势φB等于一个中间变量fB，φF是所述目标立方体区域介质交界面上的电势，φI是所述目标立方体区域中立方体单元的电势；Wherein, E 11 is the potential relationship coefficient between any two cube elements in the target cube region that satisfies the Laplace equation, and E 12 is any cube element in the target cube region that satisfies the Laplace equation and the potential relationship coefficient between any one of the surface meshes, E 13 is the potential relationship coefficient between the dielectric interface and any one of the cubic elements in the target cube region that satisfies the Laplace equation, E 31 and D 33 , respectively is the potential relationship coefficient between the medium interface and any cube unit in the target cube region that simultaneously satisfies the potential continuity condition and the electrical displacement continuity condition of the interface, I 2 is the unit diagonal matrix, used to make the target cube The electric potential φ B on the area surface mesh is equal to an intermediate variable f B , φ F is the electric potential on the medium interface of the target cube area, and φ I is the electric potential of the cube element in the target cube area; 设k是转移区域中心点所在目标立方体区域中立方体单元的编号，ek是用于提取目标立方体区域中心点电势的向量，在所述向量的k位置的数值为1，其余数值均是0，则φI表达成：Let k be the number of the cube unit in the target cube area where the center point of the transfer area is located, e k is the vector used to extract the electric potential of the center point of the target cube area, the value at the k position of the vector is 1, and the other values are 0, Then φI is expressed as:
Figure FDA0002944779090000022
Figure FDA0002944779090000022
 消去边界条件fB，得到所述目标立方体区域表面网格的电势与中心点电势关系的格林函数数值解Pk，并将所述格林函数数值解Pk作为所述集成电路中目标立方体区域的初始转移概率密度向量：Eliminate the boundary condition f B , obtain the Green's function numerical solution P k of the relationship between the potential of the surface mesh of the target cube area and the potential of the center point, and use the Green's function numerical solution P k as the target cube area in the integrated circuit. Initial transition probability density vector:
Figure FDA0002944779090000023
Figure FDA0002944779090000023
 2)使梯度算子作用于所述初始转移概率密度向量Pk，得到所述集成电路中目标立方体区域的初始权重数值向量如下:2) Make the gradient operator act on the initial transition probability density vector P k , and obtain the initial weight numerical vector of the target cube region in the integrated circuit as follows:
Figure FDA0002944779090000031
Figure FDA0002944779090000031
Figure FDA0002944779090000032
Figure FDA0002944779090000032
Figure FDA0002944779090000033
Figure FDA0002944779090000033
 其中
Figure FDA0002944779090000034
是向量，其中元素in
Figure FDA0002944779090000034
is a vector where the elements
Figure FDA0002944779090000035
Figure FDA0002944779090000035
 其中i＝1,n,n2，k是转移区域中心点所在目标立方体区域中立方体单元的编号，h为目标立方体区域中相邻两个立方体单元的中心间距。where i=1,n,n 2 , k is the number of the cube unit in the target cube area where the center point of the transfer area is located, and h is the center distance between two adjacent cube units in the target cube area. 5.根据权利要求4所述的方法，其特征在于，当所述目标立方体区域为所述三棱柱子区域时，所述表面网格包括所述前侧面、顶面和底面，不包括所述面M3；当所述目标立方体区域为所述长方体子区域时，所述表面网格包括所述前侧面、左侧面、顶面和底面，不包括所述面M1、面M2。5 . The method according to claim 4 , wherein when the target cube area is the triangular prism sub-area, the surface grid includes the front side, the top surface and the bottom surface, and does not include the face M 3 ; when the target cube area is the cuboid sub-area, the surface grid includes the front side, left side, top and bottom, excluding the faces M 1 and M 2 . 6.根据权利要求1所述的方法，其特征在于，所述基于所述压缩的预刻画数据对多层介质互连结构进行随机行走电容参数提取，包括：6 . The method according to claim 1 , wherein the performing random walk capacitance parameter extraction on the multilayer dielectric interconnect structure based on the compressed pre-characterized data comprises: 6 . S21，从数据库读取压缩的预刻画数据GFT和WVT；S21, read the compressed pre-characterized data GFT and WVT from the database; S22，读取描述集成电路互连线版图的文件，根据导体分布情况生成空间管理数据；S22, read the file describing the layout of the interconnection lines of the integrated circuit, and generate space management data according to the conductor distribution; S23，选取主导体i并构造包围主导体的高斯面；S23, select the main conductor i and construct a Gaussian surface surrounding the main conductor; S24，设置电容初始值
Figure FDA0002944779090000036
设置随机行走次数初值npath:＝0，设置程序终止条件；S24, set the initial value of the capacitor
Figure FDA0002944779090000036
Set the initial value of the number of random walks npath:=0, and set the program termination condition; S25，在所述主导体i的高斯面上随机取点r(0)，以所述点r(0)为中心点生成一分层转移立方体区域；如果所述高斯面在所述点r(0)处的法向量沿z轴，则从转移立方体8个对称的三棱柱子区域中，随机选取一个，再根据压缩的z方向WVT选点r(1)，并计算相应的权值ω；如果所述高斯面在所述点r(0)处的法向量沿x或y轴，则从转移立方体4个对称的长方体子区域中，随机选取一个，再根据压缩的xy方向WVT选点r(1)，并计算相应的权值ω；S25, randomly select point r (0) on the Gaussian surface of the main conductor i, and use the point r (0) as the center point to generate a layered transition cube area; if the Gaussian surface is at the point r ( The normal vector at 0) is along the z-axis, then randomly select one from the 8 symmetrical triangular prism sub-regions of the transfer cube, and then select the point r (1) according to the compressed z-direction WVT, and calculate the corresponding weight ω; If the normal vector of the Gaussian surface at the point r (0) is along the x or y axis, select one randomly from the four symmetrical cuboid sub-regions of the transfer cube, and then select the point r according to the compressed xy direction WVT (1) , and calculate the corresponding weight ω; S26，若当前点不在导体表面，则以当前点为中心构造分层转移立方体区域，从转移立方体8个对称的三棱柱子区域中，随机选取一个，再按照与之匹配的压缩的GFT在立方体表面选取随机转移点；S26, if the current point is not on the conductor surface, construct a layered transfer cube area with the current point as the center, randomly select one from the 8 symmetrical triangular prism sub-areas of the transfer cube, and then use the matched compressed GFT in the cube Random transfer points are selected on the surface; S27，重复执行所述步骤S26,直到当前点在导体j表面，则Cij:＝Cij+ω,npath:＝npath+1；S27, repeating the step S26, until the current point is on the surface of the conductor j, then C ij :=C ij +ω, npath :=npath+1; S28，重复所述步骤S25～步骤S27，直到满足终止条件为止，此时
Figure FDA0002944779090000041
S28, repeating the steps S25 to S27 until the termination condition is satisfied, at this time
Figure FDA0002944779090000041
CN202110191939.0A 2021-02-19 2021-02-19 Multi-medium Green function pre-drawing method for extracting interconnection capacitance of integrated circuit Active CN112800710B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110191939.0A CN112800710B (en) 2021-02-19 2021-02-19 Multi-medium Green function pre-drawing method for extracting interconnection capacitance of integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110191939.0A CN112800710B (en) 2021-02-19 2021-02-19 Multi-medium Green function pre-drawing method for extracting interconnection capacitance of integrated circuit

Publications (2)

Publication Number Publication Date
CN112800710A true CN112800710A (en) 2021-05-14
CN112800710B CN112800710B (en) 2022-09-02

Family

ID=75815249

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110191939.0A Active CN112800710B (en) 2021-02-19 2021-02-19 Multi-medium Green function pre-drawing method for extracting interconnection capacitance of integrated circuit

Country Status (1)

Country Link
CN (1) CN112800710B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113609811A (en) * 2021-08-18 2021-11-05 北京超逸达科技有限公司 Multi-medium pre-description data processing method and device, electronic equipment and storage medium
CN114580334A (en) * 2022-01-20 2022-06-03 清华大学 A Gaussian Surface Establishment Method for Interconnect Capacitance Extraction of Integrated Circuits
CN116266209A (en) * 2022-11-28 2023-06-20 湘潭大学 A Calculation Method of Electrostatic Field of Parallel Plate Waveguide Loaded by Double-sided Dielectric

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102651047A (en) * 2012-04-11 2012-08-29 清华大学 Method for extracting and calculating capacitance parameter based on random walk in integrated circuit design
CN104008255A (en) * 2014-06-13 2014-08-27 清华大学 Multimedia Random Walk Calculation Method and System for Integrated Circuit Capacitance Extraction
CN105930572A (en) * 2016-04-15 2016-09-07 清华大学 Touch screen capacitance simulation-oriented multi-medium pre-description method
CN111767669A (en) * 2020-07-08 2020-10-13 湖南省有色地质勘查研究院 Novel pseudo-random induced polarization finite element numerical simulation method and system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102651047A (en) * 2012-04-11 2012-08-29 清华大学 Method for extracting and calculating capacitance parameter based on random walk in integrated circuit design
CN104008255A (en) * 2014-06-13 2014-08-27 清华大学 Multimedia Random Walk Calculation Method and System for Integrated Circuit Capacitance Extraction
CN105930572A (en) * 2016-04-15 2016-09-07 清华大学 Touch screen capacitance simulation-oriented multi-medium pre-description method
CN111767669A (en) * 2020-07-08 2020-10-13 湖南省有色地质勘查研究院 Novel pseudo-random induced polarization finite element numerical simulation method and system

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
YU, WJ 等: "《Advancements and Challenges on Parasitic Extraction for Advanced Process Technologies》", 《ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE PROCEEDINGS》 *
齐明 等: "《面向高精度寄生参数提取与时延分析的集成电路版图数据转换方法》", 《计算机辅助设计与图形学学报》 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113609811A (en) * 2021-08-18 2021-11-05 北京超逸达科技有限公司 Multi-medium pre-description data processing method and device, electronic equipment and storage medium
CN114580334A (en) * 2022-01-20 2022-06-03 清华大学 A Gaussian Surface Establishment Method for Interconnect Capacitance Extraction of Integrated Circuits
CN116266209A (en) * 2022-11-28 2023-06-20 湘潭大学 A Calculation Method of Electrostatic Field of Parallel Plate Waveguide Loaded by Double-sided Dielectric
CN116266209B (en) * 2022-11-28 2024-03-01 湘潭大学 Calculation method for double-sided medium loaded parallel plate waveguide electrostatic field

Also Published As

Publication number Publication date
CN112800710B (en) 2022-09-02

Similar Documents

Publication Publication Date Title
CN112800710B (en) Multi-medium Green function pre-drawing method for extracting interconnection capacitance of integrated circuit
Yu et al. RWCap: A floating random walk solver for 3-D capacitance extraction of very-large-scale integration interconnects
CN111898330A (en) Integrated circuit electromagnetic response calculation method and device based on multilevel parallel strategy
US8165861B2 (en) Printed circuit analysis method and device
US6061508A (en) Modeling and processing of on-chip interconnect capacitance
CN104008255B (en) Multi-medium random walking method and system for integrated circuit capacitance extraction
CN102651047B (en) Method for extracting and calculating capacitance parameter based on random walk in integrated circuit design
US8219377B2 (en) Multi-layer finite element method for modeling of package power and ground planes
US6963122B1 (en) Capacitor structure and automated design flow for incorporating same
CN111898332B (en) Frequency domain simulation adaptive frequency point extraction and calculation method for very large scale integrated circuit
US8954308B2 (en) Modeling of multi-layered power/ground planes using triangle elements
CN103473402B (en) Spatial management data generation method for IC interconnect capacitance parameter extraction
CN111814422A (en) Interpolation matrix construction method and device of integrated circuit electromagnetic simulation multiple grid method
CN118709618B (en) Pressure drop analysis method for three-dimensional integrated circuit, computer device and storage medium
Nowacka A Hybrid Element Method For Capacitance Extraction In VLSI Layout Verification System
Ding et al. System level PDN impedance optimization utilizing the zeros of the decoupling capacitors
CN105930572B (en) A kind of pre- depicting method of multimedium towards the emulation of touch screen capacitance
JP2002535752A (en) Method and apparatus for verifying the layout of an integrated circuit by computer and use of the method for manufacturing an integrated circuit
JP3664934B2 (en) Semiconductor integrated circuit analysis apparatus, analysis method thereof, and recording medium recording the analysis method
US20130138417A1 (en) Methods, systems, and computer-readable media for model order reduction in electromagnetic simulation and modeling
KR100331567B1 (en) Caculation method of parastic capacitance between interconnections of integrated circuit considering floating conductive patterns and recoding medium inwhich the calculation program recorded
US8959009B1 (en) Modeling dielectric coating of conductor
CN113609811A (en) Multi-medium pre-description data processing method and device, electronic equipment and storage medium
Nowacka et al. A hybrid element method for calculation of capacitances from the layout of integrated circuits
CN117390945A (en) Super-multilayer parallel dielectric parasitic capacitance parameter extraction method based on random walk

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant