CN112788082A

CN112788082A - High-availability memory caching system

Info

Publication number: CN112788082A
Application number: CN201911084878.7A
Authority: CN
Inventors: 戴元顺
Original assignee: Neijiang Xiayidai Internet Data Processing Technology Research Institute
Current assignee: Neijiang Xiayidai Internet Data Processing Technology Research Institute
Priority date: 2019-11-08
Filing date: 2019-11-08
Publication date: 2021-05-11

Abstract

The invention discloses a high-availability memory cache system, which comprises a system control layer and a data processing layer; the system control layer includes: the system comprises a load balancing module, a heartbeat detection module, a fault processing module and a node coordination module; the data processing layer comprises: the device comprises a data synchronization module, a memory storage module and a data persistence module. Compared with the prior art, the system can well handle the problem of single-point failure, can ensure better hit rate, can store data in the memory into the hard disk, and has the characteristics of high availability, high-efficiency data access, good disaster tolerance and the like.

Description

High-availability memory caching system

Technical Field

The invention relates to the technical field of distributed computing, in particular to a high-availability memory cache system.

Background

1. With the development of cloud computing, more and more enterprises are used to host web applications to a cloud platform, and large-scale access of users to the web applications on the cloud platform brings huge pressure to the platform, while the traditional database has low efficiency in reading data on a hard disk.

Therefore, in order to increase the access speed, a layer of memory cache system is urgently needed to be used among users, applications and databases. The hot data are stored in the memory, the data are read from the cache system during access, and if the data are not read, the data are accessed from the traditional database, so that the access efficiency is greatly accelerated, and the user friendliness is improved.

2. At present, memcached memory object caching software is target popular caching software, and stores data in a memory in a key value mode. The caching efficiency is effectively improved by using a caching mechanism to pre-allocate memory blocks with different sizes, and meanwhile, the cache hit rate is ensured by adopting an lru memory replacement strategy. memcached is very efficient in memory storage, but has several disadvantages:

a. the server side is single, which is easy to cause single point failure.

b. lru strategy can keep better hit rate, but it is easy to cause cache pollution phenomenon when facing accidental data operation, thereby resulting in reduced hit rate.

c. The data is put into the memory and not put into the hard disk, so that the data is completely lost after the server is down due to extreme conditions.

3. Chinese patent application No. CN201410836092.7 discloses a distributed memory cache system. The system carries out clustering processing on memcached caching software, provides n master-slave memcached server clusters, each cluster adopts one master memcached server and a plurality of slave memcached servers, provides 2 fragment servers, one master fragment server and one slave fragment server, is used for recording index information of data, and provides a scheduler for receiving a read-write cache data request of a client, inquiring an index from the fragment servers, finding a specific memcached server where the data is located and reading and writing the cache data.

However, in the system, the scheduler needs to query the fragment server through a network line to obtain the index information of the cached data, and then finds a specific memcached server through the network. Thus, after two network accesses, the query efficiency of the cache can be greatly reduced. Meanwhile, only one scheduler is needed, and the requests of the clients all need to pass through the scheduler, so that great pressure is brought to the scheduler, and when the scheduler breaks down, the whole system cannot run. On the other hand, the whole system cache data is in the memory, and once an extreme condition is met, the whole data is lost, and the system cache data does not have good disaster tolerance.

Disclosure of Invention

In view of the technical deficiencies, the present invention provides a highly available memory caching system, which solves the following problems:

1. the single-point failure problem of memcached memory object caching software faces the problems of low hit rate and permanent loss of data due to power failure during accidental data operation;

2. the problem of low efficiency is caused by that a distributed memory cache system scheduler disclosed in the chinese patent application No. CN201410836092.7 accesses data through multiple network communications, and the problem of system bottleneck and single point failure and the problem of non-persistent storage of data are easily caused by using a single scheduler.

In order to solve the technical problems, the invention adopts the following technical scheme:

a high-availability memory cache system comprises a system control layer and a data processing layer;

wherein the system control layer comprises:

the load balancing module is used for uniformly distributing the cache data and the requests to each group of data nodes, and when the client requests come, the cache data and the requests are dispersed to each group of data nodes by adopting a consistency hash algorithm based on the virtual nodes;

the heartbeat detection module is used for detecting the state of each cluster in the whole cache system;

the fault processing module can select a new main data node to store data after the main data node of each group of data nodes breaks down;

the node coordination module is used for ensuring the cognition consistency of the main control node in each group of control nodes to the whole cluster by adopting a raft protocol, and coordinating a new main control node to continue providing service when the main control node is crashed;

the data processing layer comprises:

the data synchronization module is used for ensuring that the data stored in the master data node and the slave data node in each group of data nodes are consistent;

the data are stored in the memory storage module in a key value mode, are stored through a huge hash table, and are resolved by using an open chain method, and meanwhile, a 2q replacement strategy is adopted by a replacement strategy of the data in the memory storage module;

and the data persistence module is used for writing the data in the memory storage module into a persistence file in a certain format so as to ensure that the original data can still be recovered after the system is down.

Preferably, each group of data nodes comprises a master data node and a plurality of slave data nodes; each group of control nodes comprises a master control node and a plurality of slave control nodes.

The invention has the beneficial effects that: compared with the prior art, the invention can well process the single-point failure problem, can ensure better hit rate, can store the data in the memory into the hard disk, and has the characteristics of high availability, high-efficiency data access, good disaster tolerance and the like.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a high-availability memory cache system according to the present invention;

FIG. 2 is a flow chart of an insert cache according to an embodiment of the present invention;

FIG. 3 is a flow chart of inserting data synchronization according to an embodiment of the present invention;

FIG. 4 is a flow chart of persistence in an embodiment of the invention;

FIG. 5 is a flow chart of node coordination according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 1, a highly available memory cache system includes a system control layer and a data processing layer;

wherein the system control layer includes:

the data processing layer comprises:

Furthermore, each group of data nodes comprises a master data node and a plurality of slave data nodes; each group of control nodes comprises a master control node and a plurality of slave control nodes.

The caching process of the invention is as follows:

the method comprises the following steps: as shown in fig. 2, when the master control node receives a request from a user (for example, inserting cache data), the master control node first analyzes a key of the cache data through the load balancing module, obtains a location of the key on a hash ring through hash calculation, finds out which set of data nodes the key should be placed in according to a mapping list, and forwards the key to the master data node of the set of data nodes;

step two: as shown in fig. 4, when receiving a write command from the master control node, the master data node first calculates the size of the memory needed by the cache data, then finds a memory block with a suitable size, fills the cache data into the memory block, checks whether the key is already in the memory before, replaces the original memory block with a new memory block if the key exists, and puts the key into the head of the lru queue in 2q according to the 2q replacement policy. If the key does not exist in the memory, the key is put into a hash table in the memory, and the key is put into the tail of a fifo queue in 2q according to a 2q replacement strategy;

step three: as shown in fig. 3, when the master data node processes data and writes the data into the memory, data synchronization needs to be performed, the master node numbers a command first, and then sends the numbered command to the slave node, and the slave node checks whether the command carries a next command that needs to be executed, and if so, executes the command and writes the command into the memory; if not, the master node is informed to carry out synchronization, the master node sends the persistent file to the slave node, and then the slave node receives file synchronization data;

step four: and after the data is processed and written into the memory, writing the index information of the command into an index file, and simultaneously adding the command into a log file in a certain format. Checking whether a reconstruction condition is met, if so, regenerating a new write command from the cache data in the current memory by the sub-thread, storing the new write command into a new log file, and replacing the old log file;

step five: as shown in fig. 5, the master control node periodically sends a heartbeat packet to each group of control nodes through the heartbeat detection module, each group of control nodes responds, and when there is no response for four times continuously, the master control node marks the master control node as an off-line state; if the offline node is a main data node, the fault processing module carries out fault processing, and a new main control node is selected from each group of control nodes to replace the main control node;

step six: when the master control node is down, other slave control nodes cannot receive heartbeat packets, the timer of each slave control node is overtime, the node coordination module performs node coordination at the moment, a certain slave control node initiates election requests to other control nodes, the other nodes determine whether to vote or not according to the conditions of the other nodes after receiving the heartbeat packets, the slave control nodes receive more than half votes in a certain period, represent that most control nodes support the slave control nodes to serve as new master control nodes, and otherwise, perform the next round of election.

The invention provides a high-availability memory caching system and method, which effectively solve the problems of single-point failure, low hit rate, power failure data loss and the like, can realize high-efficiency storage of cached data, and has the characteristics of durability and the like.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A high-availability memory cache system is characterized by comprising a system control layer and a data processing layer;

wherein the system control layer comprises:

the data processing layer comprises:

2. The system of claim 1, wherein the plurality of data nodes each comprise a master data node and a plurality of slave data nodes; each group of control nodes comprises a master control node and a plurality of slave control nodes.