CN112787665A

CN112787665A - Phase-adjustable clock signal generation method and device

Info

Publication number: CN112787665A
Application number: CN202011579269.1A
Authority: CN
Inventors: 刘烨; 丁然
Original assignee: Allwinner Technology Co Ltd
Current assignee: Allwinner Technology Co Ltd
Priority date: 2020-12-28
Filing date: 2020-12-28
Publication date: 2021-05-11
Anticipated expiration: 2040-12-28
Also published as: CN112787665B

Abstract

The invention discloses a phase-adjustable clock signal generation method and a phase-adjustable clock signal generation device, wherein the method determines a first target clock signal input into a second multi-stage signal delay unit from a plurality of first clock signals output by a first multi-stage signal delay unit and having phase delay precision of 1/N reference clock cycles, further determines a second target clock signal from a plurality of second clock signals output by the second multi-stage signal delay unit and having phase delay precision of 1/M reference clock cycles, and determines the second target clock signal as a target output clock signal having phase delay precision of 1/(N M) reference clock cycles. Therefore, the embodiment of the invention realizes the effect of delaying the phase of the signal with higher precision by cascading and selecting the delayed clock signals which are output by the two multi-stage signal delay units and have specific mathematical relations, and can meet the same precision requirement under the conditions that the number of stages of the delay units is less and the circuit area and the power consumption are both effectively reduced compared with the prior art.

Description

Phase-adjustable clock signal generation method and device

Technical Field

The present invention relates to the field of signal processing technologies, and in particular, to a phase-adjustable clock signal generating method and apparatus.

Background

In the existing circuit application, for example, circuits such as a fractional pll circuit, a clock/data recovery circuit, and a DDR-DRAM data receiving circuit, there is a need for controlling the phase of an output clock with high precision. In these applications, the phase of the output clock needs to be delayed or advanced with precise control accuracy (e.g., 1/30 clock cycles) to meet system requirements. In response to the above requirement, the conventional methods generally include the following two methods:

1. a high-precision multi-stage signal delay unit is adopted, and the output of each stage is utilized to provide accurate phase delay. For example, when the control requirement that the phase delay precision is 1/30 clock cycles is met, a 30-stage multi-stage signal delay unit is required, and the phase adjustment precision in 1/30 clock cycles can be obtained by selecting 30 clocks. The phase delay precision of the method is determined by the multi-stage signal delay units, the relatively accurate phase precision can be ensured under the condition of locking, and under the condition that the frequency of the oscillator is stable, the phase precision is irrelevant to the process, the voltage and the temperature, and the stability is relatively high.

2. And a multi-phase clock with lower precision is used as input to interpolate the clocks of adjacent phases to obtain higher-precision phase precision. For example, two clocks with a phase difference of 1/5 clock cycles are taken as input, and the weights of the two input clocks are matched according to the accuracy of 1/6 by a phase interpolation circuit, so that the phase difference of 1/5 can be interpolated to 1/30 to meet the system requirement. Compared with the previous method, the method can obviously reduce power consumption and area, but has the defects that the output phase precision is limited by the phase interpolation circuit and cannot be too high, and the phase interpolation circuit is usually obviously influenced by the process, voltage and temperature, so that the output phase precision is greatly changed along with external factors.

Therefore, in the method for realizing high-precision phase delay control in the prior art, high output phase precision and low circuit area power consumption are difficult to be considered, the problems of complex circuit and high circuit area and power consumption are required to be solved when a high-precision application scene is realized, and the problem that the output phase precision is greatly changed along with external factors due to obvious influences of process, voltage and temperature is required to be solved when high precision is realized through a phase interpolation circuit.

Disclosure of Invention

The present invention provides a method and a device for generating a phase-adjustable clock signal, which can achieve the same accuracy requirement under the conditions of fewer stages of delay units and effectively reduced circuit area and power consumption, and avoid the problem that the output phase accuracy varies greatly with external factors due to the signal delay realized by a phase interpolation circuit in the prior art, compared with the prior method of directly performing signal delay through a multi-stage signal delay unit.

In order to solve the above technical problem, a first aspect of the embodiments of the present invention discloses a phase-adjustable clock signal generating method, where the method includes:

acquiring a plurality of first clock signals output by a first multi-stage signal delay unit, and determining a first target clock signal from the plurality of first clock signals; the first target clock signal is used for being input to a second multi-stage signal delay unit; the phase delay precision of the first clock signal and the reference clock signal input into the first multi-stage signal delay unit is 1/N reference clock cycles; the reference clock period is a clock period of the reference clock signal;

acquiring a plurality of second clock signals output by the second multi-stage signal delay unit, determining a second target clock signal from the plurality of second clock signals according to the phase delay between the target output clock signal and the reference clock signal and the phase delay between the first target clock signal and the reference clock signal, and determining the second target clock signal as the target output clock signal; the phase delay precision of the second clock signal and the reference clock signal is 1/M of the reference clock period; the phase delay precision of the target output clock signal and the reference clock signal is 1/(N × M) reference clock cycles, where M ═ N ± 1, and M and N are positive integers.

The second aspect of the embodiment of the invention discloses a phase-adjustable clock signal generating device, which comprises a first multi-stage signal delay unit, a first signal selection unit, a second multi-stage signal delay unit and a second signal selection unit; the output end of the first multi-stage signal delay unit is connected to the input end of the first signal selection unit; the output end of the first signal selection unit is connected to the input end of the second multi-stage signal delay unit; the output end of the second multi-stage signal delay unit is connected to the input end of the second signal selection unit;

the first signal selection unit is used for acquiring a plurality of first clock signals output by the first multi-stage signal delay unit, determining a first target clock signal from the plurality of first clock signals, and inputting the first target clock signal to the second multi-stage signal delay unit; the phase delay precision of the first clock signal and the reference clock signal input into the first multi-stage signal delay unit is 1/N reference clock cycles; the reference clock period is a clock period of the reference clock signal;

the second signal selection unit is configured to acquire a plurality of second clock signals output by the second multi-stage signal delay unit, determine a second target clock signal from the plurality of second clock signals according to a phase delay between the target output clock signal and the reference clock signal and a phase delay between the first target clock signal and the reference clock signal, and determine the second target clock signal as the target output clock signal; the phase delay precision of the second clock signal and the reference clock signal is 1/M of the reference clock period; the phase delay precision of the target output clock signal and the reference clock signal is 1/(N × M) reference clock cycles, where M ═ N ± 1, and M and N are positive integers.

In a third aspect, the present invention discloses another phase-adjustable clock signal generating apparatus, including:

the first determining module is used for acquiring a plurality of first clock signals output by the first multi-stage signal delay unit and determining a first target clock signal from the plurality of first clock signals; the first target clock signal is used for being input to a second multi-stage signal delay unit; the phase delay precision of the first clock signal and the reference clock signal input into the first multi-stage signal delay unit is 1/N reference clock cycles; the reference clock period is a clock period of the reference clock signal;

a second determining module, configured to obtain a plurality of second clock signals output by the second multi-stage signal delay unit, determine a second target clock signal from the plurality of second clock signals according to a phase delay between a target output clock signal and the reference clock signal and a phase delay between the first target clock signal and the reference clock signal, and determine the second target clock signal as the target output clock signal; the phase delay precision of the second clock signal and the reference clock signal is 1/M of the reference clock period; the phase delay precision of the target output clock signal and the reference clock signal is 1/(N × M) reference clock cycles, where M ═ N ± 1, and M and N are positive integers.

The fourth aspect of the present invention discloses a clock signal generating apparatus with adjustable phase, the apparatus comprising:

a memory storing executable program code;

a processor coupled with the memory;

the processor calls the executable program code stored in the memory to execute the method for generating the clock signal with adjustable phase disclosed by the first aspect of the invention.

In a fifth aspect, the present invention discloses a computer storage medium storing computer instructions for executing the phase-tunable clock signal generation method disclosed in the first aspect of the present invention when the computer instructions are called.

Compared with the prior art, the embodiment of the invention has the following beneficial effects:

the embodiment of the invention discloses a phase-adjustable clock signal generation method and a phase-adjustable clock signal generation device, the method determines a first target clock signal input into a second multi-stage signal delay unit from a plurality of first clock signals output by a first multi-stage signal delay unit and having phase delay precision of 1/N reference clock cycles, further determines a second target clock signal from a plurality of second clock signals output by the second multi-stage signal delay unit and having phase delay precision of 1/M reference clock cycles, and determines the second target clock signal as a target output clock signal having phase delay precision of 1/(N M) reference clock cycles, wherein M is (N +/-1), and M and N are positive integers. Therefore, the embodiment of the invention realizes the effect of delaying the phase of the signal with higher precision by cascading and selecting the delayed clock signals with specific mathematical relation output by the two multi-stage signal delay units, and compared with the existing method of directly delaying the signal by the multi-stage signal delay units, the embodiment of the invention can achieve the same precision requirement under the conditions that the number of stages of the delay units is less and the circuit area and the power consumption are both effectively reduced, and avoids the problem that the output phase precision is greatly changed along with external factors caused by the signal delay realized by the existing phase interpolation circuit.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic flowchart of a phase-adjustable clock signal generation method according to an embodiment of the present invention;

FIG. 2 is a flow chart illustrating another method for generating a phase-tunable clock signal according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a phase-adjustable clock signal generating apparatus according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of another phase-tunable clock signal generator according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of another phase-adjustable clock signal generating apparatus according to an embodiment of the disclosure;

FIG. 6 is a schematic structural diagram of another phase-adjustable clock signal generating apparatus according to an embodiment of the disclosure;

FIG. 7 is a schematic structural diagram of another phase-adjustable clock signal generating apparatus according to an embodiment of the disclosure;

FIG. 8 is a schematic structural diagram of another phase-adjustable clock signal generating apparatus according to an embodiment of the disclosure;

FIG. 9 is a schematic structural diagram of another phase-adjustable clock signal generating apparatus according to an embodiment of the disclosure;

FIG. 10 is a circuit diagram of a phase adjustable clock signal generating circuit according to an embodiment of the present invention;

fig. 11 is a selection logic diagram of a signal selector of a phase-adjustable clock signal generation circuit according to an embodiment of the disclosure.

Fig. 12 is a timing logic diagram of clock signal delay control of a phase-adjustable clock signal generating circuit according to an embodiment of the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "first," "second," and the like in the description and claims of the present invention and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product, or apparatus that comprises a list of steps or elements is not limited to those listed but may alternatively include other steps or elements not listed or inherent to such process, method, product, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

The invention discloses a method and a device for generating a clock signal with adjustable phase, which realize the effect of delaying the phase of a signal with higher precision by cascading and selecting delay clock signals with specific mathematical relations output by two multi-stage signal delay units. The following are detailed below.

Example one

Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a phase-adjustable clock signal generating method according to an embodiment of the present invention. The phase-adjustable clock signal generation method described in fig. 1 is applied to a signal processing system/a signal processing device/a signal processing server (where the signal processing server includes a local signal processing server or a cloud signal processing server). As shown in fig. 1, the phase-tunable clock signal generating method may include the following operations:

101. a plurality of first clock signals output by the first multi-stage signal delay unit are acquired, and a first target clock signal is determined from the plurality of first clock signals.

In an embodiment of the present invention, the first target clock signal is used to be input to the second multi-stage signal delay unit, and optionally, the phase delay precision between the first clock signal and the reference clock signal input to the first multi-stage signal delay unit is 1/N reference clock cycles, where the reference clock cycle is a clock cycle of the reference clock signal, and N is a positive integer.

In the embodiment of the present invention, the multi-stage signal delay manner of the first multi-stage signal delay unit includes, but is not limited to, multi-stage signal delay using PPL ring oscillator technology, multi-stage signal delay using injection locked ring oscillator technology, multi-stage signal delay using DLL locked delay chain technology, multi-stage signal delay using digital delay chain technology, or multi-stage signal delay using phase interpolation technology, and any circuit structure or algorithm that can perform multi-stage delay with a certain precision on the phase of the clock signal should be considered to be included in the protection scope of the present invention.

102. And acquiring a plurality of second clock signals output by the second multi-stage signal delay unit, determining a second target clock signal from the plurality of second clock signals according to the phase delay between the target output clock signal and the reference clock signal and the phase delay between the first target clock signal and the reference clock signal, and determining the second target clock signal as the target output clock signal.

In an embodiment of the present invention, the phase delay precision of the second clock signal and the reference clock signal is 1/M reference clock cycles, and specifically, the phase delay precision of the final target output clock signal and the reference clock signal is 1/(N × M) reference clock cycles, where M is (N ± 1), and M and N are positive integers. Specifically, when the first multi-stage signal delay unit and the second multi-stage signal delay unit delay signals, the clock period of the clock signal is not changed, but only the phase is delayed, so that the phase delay precision of the second clock signal output by the second multi-stage signal delay unit still takes the reference clock period of the reference clock signal as a unit, and those skilled in the art can understand the principle, and details are not described herein.

Optionally, in an embodiment of the present invention, the multi-stage signal delay manner of the second multi-stage signal delay unit is to perform multi-stage signal delay by using a PPL ring oscillator technology, perform multi-stage signal delay by using an injection locked ring oscillator technology, perform multi-stage signal delay by using a DLL locked delay chain technology, perform multi-stage signal delay by using a digital delay chain technology, or perform multi-stage signal delay by using a phase interpolation technology, and any circuit structure or algorithm capable of performing multi-stage delay with a certain precision on the phase of the clock signal should be considered to be included in the protection scope of the present invention.

Specifically, in the embodiment of the present invention, the first multi-stage signal delay unit with the phase delay accuracy of 1/N reference clock cycles and the second multi-stage signal delay unit with the phase delay accuracy of 1/M reference clock cycles are subjected to signal selection and cascade connection, so that the principle of the target output clock signal with the phase delay accuracy of 1/(N × M) reference clock cycles can be finally obtained, and the following is demonstrated:

first, it should be noted that in the expression of the phase delay mentioned in the present invention being a/B clock cycles, it is clear to those skilled in the art that a ≦ B, and a and B are both positive integers, which is a necessary limitation of this expression of phase delay and a sufficient requirement to prove that this optional phase delay exists.

In the technical solution of the present invention, if M ═ N ± 1, the phase delay precision of the second multi-stage signal delay unit is 1/(N ± 1) reference clock cycles, and the phase delay precision of the target output clock signal is 1/(N × (N ± 1)) reference clock cycles, in this case, to obtain the final target output clock signal, the phase delay of the final target clock output signal may be set to T/[ N (N ± 1) ] reference clock cycles, where T ≦ N (N ± 1), and discussion is performed according to two cases, i.e., (N +1) and M ═ N-1, respectively:

(1) when M is (N +1), the phase delay of the target clock output signal may be divided into [ T/N-T/(N +1) ] reference clock cycles, and then the first multi-stage signal delay unit and the second multi-stage signal delay unit may be selected to superimpose the delays of the two multi-stage signal delay units, so that the phase signal delay of the first multi-stage signal delay unit should be T/N reference clock cycles, and the phase signal delay of the second multi-stage signal delay unit should be-T/(N +1) reference clock cycles, and based on the principle that the clock signal phase is returned to the original phase after being delayed by one reference clock cycle, the phase signal delay of the first multi-stage signal delay unit may be converted into (T-WN)/N reference clock cycles The phase signal delay of the second multi-stage signal delay unit is scaled to [ V (N +1) -T ]/(N +1) reference clock cycles, where W and V are positive integers.

From the above reasoning, as long as N is a positive integer, in the case that T ≦ N, the phase signal delay of the first multi-stage signal delay unit is T/N reference clock cycles, and the phase signal delay of the second multi-stage signal delay unit is [ (N +1) -T ]/(N +1) reference clock cycles, i.e. when V is 1, 1< (N +1) -T ≦ N +1, so that the phase signal delays can all be solved positively, and 1/(N +1)) reference clock cycles with phase delay accuracy can be output.

And in the case of T > N, since W is a positive integer, that is, W is greater than or equal to 1, then T > WN at this time, the phase signal delay of the first multi-stage signal delay unit may be selected to be (T-WN)/N reference clock cycles, at this time 0< (T-WN), and in the case where T is less than or equal to N (N +1), T-WN is less than or equal to N (N +1) -WN is greater than or equal to N (N +1-W), then when W is greater than or equal to N, N (N +1-W) is less than or equal to N, that is, T-WN is less than or equal to N (N +1-W) is less than or equal to N. And the phase signal delay of the second multistage signal delay unit is [ V (N +1) -T ]/(N +1) reference clock cycles, at this time [ V (N +1) -T ] > [ V (N +1) -N ], since V is not less than 1, [ V (N +1) -T ] > [ V (N +1) -N ] > 1, and in the case where T is not more than N +1, [ V (N +1) -T ≦ V (N +1) -N (N +1) ] (V-N) × (N +1) ], at this time, it is possible to achieve [ (V-N) × (N +1) ] ≦ N +1, at this time, [ V (N +1) -T ≦ V-N) × (N +1) ] ≦ (N +1) ] (N + 1). The phase signal delays can all be solved positively, and the phase delay precision can be output to be 1/(N × N +1)) reference clock cycles.

(2) If M is (N-1), then N is M +1, then all N in the above argument in (1) is replaced by M, and M is guaranteed to be a positive integer, and a conclusion that the argument passes can be obtained as well.

As can be seen from the above discussion, the embodiments of the present invention can select and cascade signals of the first multi-stage signal delay unit with a phase delay accuracy of 1/N reference clock cycles and the second multi-stage signal delay unit with a phase delay accuracy of 1/M reference clock cycles, so as to finally obtain the target output clock signal with a phase delay accuracy of 1/(N × M) reference clock cycles, and when achieving the effect of high-accuracy clock signal phase delay of 1/(N × M) reference clock cycles, only two multi-stage signal delay units with a total number of stages N + M are needed, whereas the existing scheme of directly performing signal delay through the multi-stage signal delay units needs N × M stages of multi-stage signal delay units, so the scheme in the embodiments of the present invention obviously needs fewer circuit elements, fewer circuit areas, and lower circuit power consumption, compared with the existing scheme using the phase interpolation circuit, the method has higher precision and cannot be influenced by external factors.

It can be seen that, in the above embodiments of the present invention, the delayed clock signals having a specific mathematical relationship and output by the two multi-stage signal delay units are cascaded and selected, so as to achieve an effect of delaying the phase of the signal with higher accuracy.

As an alternative implementation, the determining the second target clock signal from the plurality of second clock signals according to the phase delay between the target output clock signal and the reference clock signal and the phase delay between the first target clock signal and the reference clock signal in step 102 includes:

determining a phase delay between the target output clock signal and the reference clock signal to be K/(N M) reference clock cycles, wherein K is less than or equal to (N M), and K is a positive integer;

determining a phase delay between the first target clock signal and the reference clock signal to be J/N reference clock cycles; wherein J is not more than N, and J is a positive integer;

and screening a second clock signal with a phase delay of L/M reference clock cycles from the reference clock signal from the plurality of second clock signals, and determining the screened second clock signal as a second target clock signal, wherein L satisfies:

l is (K-JM)/N, L is less than or equal to M, and L is a positive integer;

and/or L ═ K + (N-J) × M ]/N, and L ≦ M, L being a positive integer.

In this alternative embodiment, the satisfaction condition of L is derived by:

first, the phase delay between the target output clock signal and the reference clock signal is determined to be K/(N × M) reference clock cycles, and the phase delay between the first target clock signal and the reference clock signal is determined to be J/N reference clock cycles when the first target clock signal is received, then, as can be seen from the above explanation of the basic principle of the embodiment of the present invention, the relationship between the phase delay of the second target clock signal and the above phase delays is: L/M + J/N ═ K/(N × M), and/or L/M + J/N ═ K + (N × M) ]/(N × M).

Of the above two relations, the latter relation is a result of adding one clock cycle to the phase delay of the target output clock signal based on the principle that the phase of the clock signal is returned to the original phase after being delayed by one reference clock cycle, and the maximum value of L/M + J/N is 2(N × M)/(N × M) in the case where L is equal to or less than M and J is equal to or less than N, so that it is not necessary to consider a result of adding two or more clock cycles to the phase delay of the target output clock signal.

From the two relations above, it can be directly deduced that L should satisfy the following condition:

l is (K-JM)/N, L is less than or equal to M, and L is a positive integer;

and/or L ═ K + (N-J) × M ]/N, and L ≦ M, L being a positive integer.

In order to make the solution in the present embodiment more clear to those skilled in the art, the solution is first illustrated with reference to fig. 10-12:

taking the implementation of a clock signal generation circuit with a phase delay precision of 1/30 clock cycles as an example, the scheme in this embodiment is implemented by using a circuit structure of a phase-adjustable clock signal generation circuit as shown in fig. 11, where the circuit structure includes two multi-stage signal delay units D1 and D2 and two signal selectors M1 and M2. As shown in fig. 11, the multi-stage signal delay unit D1 is a 6-stage ring oscillator with a phase delay accuracy of 1/6 clock cycles, outa1 to outa6 are delay signal output terminals of D1, adjacent phase differences of the output delay signals are 1/6 t period, that is, outa1 to outa6 respectively output clock signals with a phase delay accuracy of 1/6, 2/6, 3/6, 4/6, 5/6, 6/6 clock cycles, the multi-stage signal delay unit D2 is a lock delay chain with a phase delay accuracy of 1/5 clock cycles, outb1 to outb5 are delay signal output terminals of D2, adjacent phase differences of the output delay signals are 1/5 t period, that is, outb1 to outb5 respectively output clock signals with a phase delay accuracy of 1/5, 2/5, 3/5, 4/5, 5/5 clock cycles, tperiod is the clock signal period of outa and outb. Specifically, the signal selector M1 selects outa1 to outa6 with a phase interval of 1/6 × Tperiod output from the 6-stage ring oscillator D1 to obtain an input ckint _ a of the lock delay chain D2 corresponding to outb, the lock delay chain D2 generates outb1 to outb5 with a phase interval of 1/5 × Tperiod, and finally, the signal selector M2 selects outb1 to outb5 to obtain a final ckout output. By properly designing the input selection signals clka _ sel and clkb _ sel of M1 and M2, the phase adjustment accuracy of the ckout output to 1/30 × Tperiod can be ensured.

Based on the selection logic of the second target clock signal described in the above embodiment, it can be obtained that the selection signal generation logic of M1 and M2 in this example is as shown in fig. 11, and then signal selection is finally performed according to the logic of fig. 11, so as to implement a timing logic diagram of phase delay precision control, as can be seen from fig. 12, and as can be seen from fig. 10 to 12, when M1 selects outa5, and M2 selects outb1, the delay of ckout with respect to outa6 is (1/5+5/6) × Tperiod ═ 31/30 × Tperiod ═ 1/30 tpriod, and the delay of 1/30 × Tperiod is implemented; when M1 selects outa4 and M2 selects outb2, the delay of ckout with respect to outa6 is (2/5+4/6) × Tperiod ═ 32/30 ═ 2/30 ═ Tperiod, and the delay of 2/30 × Tperiod is realized; by analogy, when M1 selects outa1 and M2 selects outb4, the delay of ckout with respect to outa6 is (4/5+1/6) × Tperiod 29/30 × Tperiod; when M1 selects outa6 and M2 selects outb5, ckout is just one period relative to the delay of outa6, i.e., 30/30 Tperiod. So far, delays from 1/30 by Tperiod to 30/30 by Tperiod have been generated, and all the delays are generated by accurate delay units through selection, without any interpolation or approximation, and the same accuracy and stability as the original delay units can be achieved.

Example two

Referring to fig. 2, fig. 2 is a schematic flow chart illustrating another phase-adjustable clock signal generating method according to an embodiment of the invention. The phase-adjustable clock signal generation method described in fig. 2 is applied to a signal processing system/a signal processing device/a signal processing server (where the signal processing server includes a local signal processing server or a cloud signal processing server). As shown in fig. 2, the phase-tunable clock signal generating method may include the following operations:

201. the method comprises the steps of obtaining a plurality of first sub-clock signals output by a first sub-multi-level signal delay unit, and determining a first sub-target clock signal from the plurality of first sub-clock signals.

In the embodiment of the invention, the first sub-target clock signal is used for being input to the second sub-multilevel signal delay unit; the phase delay precision of the first sub-clock signal and the reference clock signal input to the first sub-multi-stage signal delay unit is 1/H reference clock cycles.

202. And acquiring a plurality of second sub-clock signals output by the second sub-multi-stage signal delay unit, determining a second sub-target clock signal from the plurality of second sub-clock signals according to the phase delay between the first clock signal and the reference clock signal and the phase delay between the first sub-target clock signal and the reference clock signal, and determining the second sub-target clock signal as the first clock signal.

In the embodiment of the invention, the phase delay precision of the second sub-clock signal and the reference clock signal is 1/I reference clock period; wherein, H is a positive integer, and I ═ H +/-1, H ═ I ═ N.

In an embodiment of the present invention, the first multi-stage signal delay unit includes the first sub multi-stage signal delay unit and the second sub multi-stage signal delay unit.

203. A plurality of first clock signals output by the first multi-stage signal delay unit are acquired, and a first target clock signal is determined from the plurality of first clock signals.

206. And acquiring a plurality of second clock signals output by the second multi-stage signal delay unit, determining a second target clock signal from the plurality of second clock signals according to the phase delay between the target output clock signal and the reference clock signal and the phase delay between the first target clock signal and the reference clock signal, and determining the second target clock signal as the target output clock signal.

In the embodiment of the present invention, please refer to the detailed description of steps 101 to 102 in the first embodiment for the related description of

steps

203 and 206, which is not repeated herein.

Optionally, in an embodiment of the present invention, the multi-stage signal delay manner of the first sub-multi-stage signal delay unit is to perform multi-stage signal delay by using a PPL ring oscillator technology, perform multi-stage signal delay by using an injection locked ring oscillator technology, perform multi-stage signal delay by using a DLL locked delay chain technology, perform multi-stage signal delay by using a digital delay chain technology, or perform multi-stage signal delay by using a phase interpolation technology, and any circuit structure or algorithm capable of performing multi-stage delay with a certain precision on the phase of the clock signal should be considered to be included in the protection scope of the present invention. Optionally, the multi-stage signal delay manner of the second sub-multi-stage signal delay unit is to perform multi-stage signal delay by using a PPL ring oscillator technology, perform multi-stage signal delay by using an injection locked ring oscillator technology, perform multi-stage signal delay by using a DLL locked delay chain technology, perform multi-stage signal delay by using a digital delay chain technology, or perform multi-stage signal delay by using a phase interpolation technology, and any circuit structure or algorithm capable of performing multi-stage delay with a certain precision on the phase of the clock signal should be considered to be included in the protection scope of the present invention.

It can be seen that, in the embodiment of the present invention, the first multi-stage signal delay unit described in the first embodiment is expanded, signal selection logics of the first sub multi-stage signal delay unit and the second sub multi-stage signal delay unit included in the first multi-stage signal delay unit are expressed, and a principle of generating a sum of the signal selection logics of the first sub multi-stage signal delay unit and the second sub multi-stage signal delay unit may refer to the expression of the principle of the first multi-stage signal delay unit and the second multi-stage signal delay unit in the first embodiment, which is similar in principle and effect, and is not described herein again.

With reference to the discussion of the first embodiment, it can be seen that, in the embodiments of the present invention, by performing signal selection and cascade connection on the first multi-stage signal delay unit including the first sub-multi-stage signal delay unit with the phase delay accuracy of 1/H reference clock cycles and the second multi-stage signal delay unit with the phase delay accuracy of 1/M reference clock cycles, the target output clock signal with the phase delay accuracy of 1/(H × I × M) reference clock cycles can be finally obtained, and when the effect of phase delay of the high-precision clock signal with 1/(H × I × M) reference clock cycles is achieved, only three multi-stage signal delay units with the total number of stages of H + I + M are needed, whereas the existing scheme of directly performing signal delay through the multi-stage signal delay units needs H × M The multi-stage signal delay unit of the stage, therefore, the scheme in the embodiment of the invention obviously needs less circuit elements, less circuit area and lower circuit power consumption, and compared with the existing scheme using the phase interpolation circuit, the scheme has higher precision and is not influenced by external factors.

As an alternative implementation, the determining the second sub-target clock signal from the plurality of second sub-clock signals according to the phase delay between the first clock signal and the reference clock signal and the phase delay between the first sub-target clock signal and the reference clock signal in step 202 includes:

determining a phase delay between the first clock signal and the reference clock signal as R/(H I) reference clock cycles, wherein R ≦ (H I), and R is a positive integer;

determining a phase delay between the first sub-target clock signal and the reference clock signal to be S/H reference clock cycles; wherein S is less than or equal to H and is a positive integer;

and screening a second sub-clock signal with the phase delay of T/I reference clock cycles from the reference clock signals in the plurality of second sub-clock signals, and determining the screened second sub-clock signal as a second sub-target clock signal, wherein T satisfies the following condition:

t is (R-SI)/H, and T is less than or equal to I, and T is a positive integer;

and/or T ═ R + (H-S) × I ]/H, and T ≦ I, T being a positive integer.

In this optional embodiment, for deriving the phase delay of the second sub-target clock signal, reference may be made to the derivation process of L in the phase delay of the second target clock signal in the first embodiment, and the principle is similar, which is not described herein again.

As an alternative implementation, the second multi-stage signal delay unit includes a third sub multi-stage signal delay unit and a fourth sub multi-stage signal delay unit, as shown in fig. 2, before performing step 206, the method further includes:

204. and acquiring a plurality of third sub-clock signals output by the third sub-multi-stage signal delay unit, and determining a third sub-target clock signal from the plurality of third sub-clock signals.

In the embodiment of the present invention, the third sub-target clock signal is used to be input to the fourth sub-multi-stage signal delay unit, and optionally, the phase delay precision between the third sub-clock signal and the first target clock signal input to the third sub-multi-stage signal delay unit is 1/Q reference clock cycles.

205. And obtaining a plurality of fourth sub-clock signals output by the fourth sub-multi-stage signal delay unit, determining a fourth sub-target clock signal from the plurality of fourth sub-clock signals according to the phase delay between the second clock signal and the first target clock signal and the phase delay between the third sub-target clock signal and the first target clock signal, and determining the fourth sub-target clock signal as the second clock signal.

In the embodiment of the invention, the phase delay precision of the fourth sub-clock signal and the reference clock signal is 1/P reference clock cycles; wherein Q and P are positive integers, and P ═ Q ± M (Q ± 1).

Optionally, in an embodiment of the present invention, the multi-stage signal delay manner of the third sub-multi-stage signal delay unit is to perform multi-stage signal delay by using a PPL ring oscillator technology, perform multi-stage signal delay by using an injection locked ring oscillator technology, perform multi-stage signal delay by using a DLL locked delay chain technology, perform multi-stage signal delay by using a digital delay chain technology, or perform multi-stage signal delay by using a phase interpolation technology, and any circuit structure or algorithm capable of performing multi-stage delay with a certain precision on the phase of the clock signal should be considered to be included in the protection scope of the present invention. Optionally, the multi-stage signal delay manner of the fourth sub-multi-stage signal delay unit is to perform multi-stage signal delay by using a PPL ring oscillator technology, perform multi-stage signal delay by using an injection locked ring oscillator technology, perform multi-stage signal delay by using a DLL locked delay chain technology, perform multi-stage signal delay by using a digital delay chain technology, or perform multi-stage signal delay by using a phase interpolation technology, and any circuit structure or algorithm that can perform multi-stage delay with a certain precision on the phase of the clock signal should be considered to be included in the protection scope of the present invention.

It can be seen that, in the embodiment of the present invention, the second multi-stage signal delay unit described in the first embodiment is expanded, signal selection logics of a third sub multi-stage signal delay unit and a fourth sub multi-stage signal delay unit included in the second multi-stage signal delay unit are expressed, and a principle of generating a sum of signal selection logics of the third sub multi-stage signal delay unit and the fourth sub multi-stage signal delay unit may refer to the expression of the principle of the first multi-stage signal delay unit and the principle of generating a sum of signal selection logics of the fourth sub multi-stage signal delay unit, which are similar to each other in principle and effect, and are not described herein again.

With reference to the discussion of the first embodiment, it can be seen that, according to the embodiments of the present invention, by selecting and cascading the first multi-stage signal delay unit with the phase delay accuracy of 1/N reference clock cycles, and the second multi-stage signal delay unit including the third sub-multi-stage signal delay unit with the phase delay accuracy of 1/P reference clock cycles and the fourth sub-multi-stage signal delay unit with the phase delay accuracy of 1/Q reference clock cycles, the target output clock signal with the phase delay accuracy of 1/(N + P + Q) reference clock cycles can be finally obtained, and when the effect of delaying the high-accuracy clock signal with 1/(N + P + Q) reference clock cycles is achieved, only three multi-stage signal delay units with the total number of stages N + P + Q are needed, whereas the existing scheme of directly delaying the signal through the multi-stage signal delay units needs the multi-stage signal with N + P stages Q The delay unit, therefore, the solution in the embodiment of the present invention obviously requires less circuit elements and less circuit area and lower circuit power consumption, and compared with the existing solution using the phase interpolation circuit, the solution has higher precision and is not influenced by external factors.

As an alternative implementation, the determining the fourth sub-target clock signal from the plurality of fourth sub-clock signals according to the phase delay between the second clock signal and the first target clock signal and the phase delay between the third sub-target clock signal and the first target clock signal in step 205 includes:

determining a phase delay between the second clock signal and the first target clock signal as X/(QP) reference clock cycles, wherein X is ≦ (QP), and X is a positive integer;

determining a phase delay between the third sub-target clock signal and the first target clock signal to be Y/Q reference clock cycles; wherein Y is less than or equal to Q and is a positive integer;

screening out a fourth sub-clock signal with the phase delay of Z/P reference clock cycles from the plurality of fourth sub-clock signals, and determining the screened out fourth sub-clock signal as a fourth sub-target clock signal, wherein Z satisfies:

z is (X-YP)/Q, and Z is less than or equal to P and is a positive integer;

and/or, Z ═ X + (Q-Y) P/Q, and Z ≦ P, Z being a positive integer.

EXAMPLE III

Referring to fig. 3, fig. 3 is a schematic structural diagram of a phase-adjustable clock signal generating device according to an embodiment of the present invention. The phase-adjustable clock signal generating apparatus depicted in fig. 3 is applied to a signal processing system/signal processing device/signal processing server (where the signal processing server includes a local signal processing server or a cloud signal processing server). As shown in fig. 3, the phase-adjustable clock signal generating apparatus may include a first multi-stage signal delay unit 301, a first signal selection unit 302, a second multi-stage signal delay unit 303, and a second signal selection unit 304, wherein an output terminal of the first multi-stage signal delay unit 301 is connected to an input terminal of the first signal selection unit 302. An output terminal of the first signal selection unit 302 is connected to an input terminal of the second multi-stage signal delay unit 303. An output terminal of the second multi-stage signal delay unit 303 is connected to an input terminal of the second signal selection unit 304.

Specifically, the first signal selection unit 302 is configured to obtain a plurality of first clock signals output by the first multi-stage signal delay unit 301, determine a first target clock signal from the plurality of first clock signals, and input the first target clock signal to the second multi-stage signal delay unit 303. The phase delay precision of the first clock signal and the reference clock signal input to the first multi-stage signal delay unit 301 is 1/N reference clock cycles. The reference clock period is a clock period of the reference clock signal.

The second signal selecting unit 304 is configured to acquire the plurality of second clock signals output by the second multi-stage signal delaying unit 303, determine a second target clock signal from the plurality of second clock signals according to the phase delay between the target output clock signal and the reference clock signal and the phase delay between the first target clock signal and the reference clock signal, and determine the second target clock signal as the target output clock signal. The phase delay precision of the second clock signal and the reference clock signal is 1/M reference clock cycles. The phase delay precision of the target output clock signal and the reference clock signal is 1/(N × M) reference clock cycles, where M ═ N ± 1, and M and N are positive integers.

As an alternative implementation, the specific manner in which the second signal selection unit 304 determines the second target clock signal from the plurality of second clock signals according to the phase delay between the target output clock signal and the reference clock signal and the phase delay between the first target clock signal and the reference clock signal includes:

determining a phase delay between the target output clock signal and the reference clock signal to be K/(N M) reference clock cycles, wherein K is less than or equal to (N M), and K is a positive integer.

The phase delay between the first target clock signal and the reference clock signal is determined to be J/N reference clock cycles. Wherein J is less than or equal to N, and J is a positive integer.

and L is (K-JM)/N, and is less than or equal to M, and L is a positive integer.

And/or L ═ K + (N-J) × M ]/N, and L ≦ M, L being a positive integer.

As an alternative embodiment, as shown in fig. 4, the first multi-stage signal delay unit 301 includes a first sub-multi-stage signal delay unit 3011, a second sub-multi-stage signal delay unit 3012, a first sub-signal selection unit 3021, and a second sub-signal selection unit 3022. An output terminal of the first sub-multi-stage signal delay unit 3011 is connected to an input terminal of the first sub-signal selection unit 3021. An output terminal of the first sub-signal selecting unit 3021 is connected to an input terminal of the second sub-multi-stage signal delay unit 3012. An output terminal of the second sub-multi-stage signal delay unit 3012 is connected to an input terminal of the second sub-signal selection unit 3022.

The first sub-signal selecting unit 3021 is configured to obtain a plurality of first sub-clock signals output by the first sub-multi-level signal delay unit 3011, determine a first sub-target clock signal from the plurality of first sub-clock signals, and input the first sub-target clock signal to the second sub-multi-level signal delay unit 3012. The phase delay precision of the first sub-clock signal and the reference clock signal input to the first sub-multi-stage signal delay unit 3011 is 1/H reference clock period.

The second sub-signal selecting unit 3022 is configured to obtain a plurality of second sub-clock signals output by the second sub-multi-level signal delaying unit 3012, determine a second sub-target clock signal from the plurality of second sub-clock signals according to a phase delay between the first clock signal and the reference clock signal and a phase delay between the first sub-target clock signal and the reference clock signal, and determine the second sub-target clock signal as the first clock signal. The phase delay precision of the second sub-clock signal and the reference clock signal is 1/I reference clock period. Wherein, H is a positive integer, and I ═ H +/-1, H ═ I ═ N.

It can be seen that, the embodiment of the present invention can finally obtain the target output clock signal with the phase delay accuracy of 1/(H × I) reference clock cycles by selecting and cascading the first multi-stage signal delay unit including the first sub-multi-stage signal delay unit with the phase delay accuracy of 1/H reference clock cycles and the second multi-stage signal delay unit with the phase delay accuracy of 1/M reference clock cycles, and thus when the effect of high-precision clock signal phase delay of 1/(H × I × M) reference clock cycles is achieved, only three multi-stage signal delay units with the total stage number of H + I + M are needed, while the existing scheme of directly performing signal delay through the multi-stage signal delay units needs H × I × M multi-stage signal delay units, therefore, the scheme in the embodiment of the invention obviously requires less circuit elements, less circuit area and lower circuit power consumption, and compared with the existing scheme utilizing the phase interpolation circuit, the scheme has higher precision and is not influenced by external factors.

As an alternative embodiment, the specific manner in which the second sub-signal selecting unit 3022 determines the second sub-target clock signal from the plurality of second sub-clock signals according to the phase delay between the first clock signal and the reference clock signal and the phase delay between the first sub-target clock signal and the reference clock signal includes:

t is (R-SI)/H, and T is less than or equal to I, and T is a positive integer;

and/or T ═ R + (H-S) × I ]/H, and T ≦ I, T being a positive integer.

As an alternative embodiment, as shown in fig. 5, the second multi-stage signal delay unit 303 includes a third sub-multi-stage signal delay unit 3031, a fourth sub-multi-stage signal delay unit 3032, a third sub-signal selection unit 3041, and a fourth sub-signal selection unit 3042. An output terminal of the third sub-multi-level signal delay unit 3031 is connected to an input terminal of the third sub-signal selection unit 3041. An output terminal of the third sub signal selection unit 3041 is connected to an input terminal of the fourth sub multi-stage signal delay unit 3032. An output terminal of the fourth sub-multi-level signal delay unit 3032 is connected to an input terminal of the fourth sub-signal selection unit 3042.

The third sub-signal selecting unit 3041 is configured to acquire a plurality of third sub-clock signals output by the third sub-multi-level signal delay unit 3031, determine a third sub-target clock signal from the plurality of third sub-clock signals, and input the third sub-target clock signal to the fourth sub-multi-level signal delay unit 3032. The phase delay precision of the third sub-clock signal and the first target clock signal input to the third sub-multi-stage signal delay unit 3031 is 1/Q reference clock cycles.

The fourth sub-signal selecting unit 3042 is configured to acquire a plurality of fourth sub-clock signals output by the fourth sub-multi-level signal delaying unit 3032, determine a fourth sub-target clock signal from the plurality of fourth sub-clock signals according to a phase delay between the second clock signal and the first target clock signal and a phase delay between the third sub-target clock signal and the first target clock signal, and determine the fourth sub-target clock signal as the second clock signal. The phase delay precision of the fourth sub-clock signal and the first target clock signal is 1/P reference clock cycles. Wherein Q and P are positive integers, and P ═ Q ± M (Q ± 1).

As an alternative embodiment, the specific manner in which the fourth sub-signal selecting unit 3042 determines the fourth sub-target clock signal from the plurality of fourth sub-clock signals according to the phase delay between the second clock signal and the first target clock signal and the phase delay between the third sub-target clock signal and the first target clock signal includes:

z is (X-YP)/Q, and Z is less than or equal to P and is a positive integer;

and/or, Z ═ X + (Q-Y) P/Q, and Z ≦ P, Z being a positive integer.

As an optional implementation manner, in the embodiment of the present invention, the multi-stage signal delay manner of the first multi-stage signal delay unit 301 is to perform multi-stage signal delay by using a PPL ring oscillator technology, perform multi-stage signal delay by using an injection locked ring oscillator technology, perform multi-stage signal delay by using a DLL locked delay chain technology, perform multi-stage signal delay by using a digital delay chain technology, or perform multi-stage signal delay by using a phase interpolation technology.

Optionally, the multi-stage signal delay manner of the first sub-multi-stage signal delay unit 3011 is to perform multi-stage signal delay by using a PPL ring oscillator technology, perform multi-stage signal delay by using an injection locked ring oscillator technology, perform multi-stage signal delay by using a DLL locked delay chain technology, perform multi-stage signal delay by using a digital delay chain technology, or perform multi-stage signal delay by using a phase interpolation technology.

Optionally, the multi-stage signal delay manner of the second sub-multi-stage signal delay unit 3012 is to perform multi-stage signal delay by using a PPL ring oscillator technology, perform multi-stage signal delay by using an injection locked ring oscillator technology, perform multi-stage signal delay by using a DLL locked delay chain technology, perform multi-stage signal delay by using a digital delay chain technology, or perform multi-stage signal delay by using a phase interpolation technology.

Optionally, the multi-stage signal delay manner of the second multi-stage signal delay unit 303 is to perform multi-stage signal delay by using a PPL ring oscillator technology, perform multi-stage signal delay by using an injection locked ring oscillator technology, perform multi-stage signal delay by using a DLL locked delay chain technology, perform multi-stage signal delay by using a digital delay chain technology, or perform multi-stage signal delay by using a phase interpolation technology.

Optionally, the multi-stage signal delay manner of the third sub multi-stage signal delay unit 3031 is to perform multi-stage signal delay by using a PPL ring oscillator technology, perform multi-stage signal delay by using an injection locked ring oscillator technology, perform multi-stage signal delay by using a DLL locked delay chain technology, perform multi-stage signal delay by using a digital delay chain technology, or perform multi-stage signal delay by using a phase interpolation technology.

Optionally, the fourth sub-multi-stage signal delay unit 3032 performs multi-stage signal delay by using a PPL ring oscillator technology, multi-stage signal delay by using an injection locked ring oscillator technology, multi-stage signal delay by using a DLL locked delay chain technology, multi-stage signal delay by using a digital delay chain technology, or multi-stage signal delay by using a phase interpolation technology.

Optionally, in this embodiment, the first signal selecting unit 302, the second signal selecting unit 304, the first sub-signal selecting unit 3021, the second sub-signal selecting unit 3022, the third sub-signal selecting unit 3041, and the fourth sub-signal selecting unit 3042 may be data selectors preset with signal selecting logic, such as multiplexers controlled by a control chip, or signal selecting electronic elements implementing the signal selecting logic through circuit design, and specific details of the circuit design and the logic table of the multi-stage signal delaying unit and the signal selecting unit in this embodiment may refer to the examples shown in fig. 10 to 12 in the first embodiment, and are not described herein again.

Example four

Referring to fig. 6, fig. 6 is a schematic diagram illustrating another phase-adjustable clock signal generating apparatus according to an embodiment of the present invention. The phase-adjustable clock signal generating apparatus depicted in fig. 6 is applied to a signal processing system/signal processing device/signal processing server (where the signal processing server includes a local signal processing server or a cloud signal processing server). As shown in fig. 7, the phase-tunable clock signal generating apparatus may include:

the first determining module 401 is configured to obtain a plurality of first clock signals output by the first multi-stage signal delay unit, and determine a first target clock signal from the plurality of first clock signals.

A second determining module 402, configured to obtain a plurality of second clock signals output by the second multi-stage signal delay unit, determine a second target clock signal from the plurality of second clock signals according to a phase delay between the target output clock signal and the reference clock signal and a phase delay between the first target clock signal and the reference clock signal, and determine the second target clock signal as the target output clock signal.

As an alternative implementation, the specific manner in which the second determining module 402 determines the second target clock signal from the plurality of second clock signals according to the phase delay between the target output clock signal and the reference clock signal and the phase delay between the first target clock signal and the reference clock signal includes:

l is (K-JM)/N, L is less than or equal to M, and L is a positive integer;

and/or L ═ K + (N-J) × M ]/N, and L ≦ M, L being a positive integer.

As an alternative embodiment, the first multi-stage signal delay unit includes a first sub multi-stage signal delay unit and a second sub multi-stage signal delay unit. As shown in fig. 7, the phase-tunable clock signal generating apparatus further includes:

the third determining module 403 is configured to obtain a plurality of first sub-clock signals output by the first sub-multi-stage signal delay unit, and determine a first sub-target clock signal from the plurality of first sub-clock signals.

The fourth determining module 404 is configured to obtain a plurality of second sub-clock signals output by the second sub-multi-stage signal delay unit, determine a second sub-target clock signal from the plurality of second sub-clock signals according to a phase delay between the first clock signal and the reference clock signal and a phase delay between the first sub-target clock signal and the reference clock signal, and determine the second sub-target clock signal as the first clock signal.

As an alternative implementation, the specific manner in which the fourth determining module 404 determines the second sub-target clock signal from the plurality of second sub-clock signals according to the phase delay between the first clock signal and the reference clock signal and the phase delay between the first sub-target clock signal and the reference clock signal includes:

t is (R-SI)/H, and T is less than or equal to I, and T is a positive integer;

and/or T ═ R + (H-S) × I ]/H, and T ≦ I, T being a positive integer.

As an alternative implementation, the second multi-stage signal delay unit includes a third sub-multi-stage signal delay unit and a fourth sub-multi-stage signal delay unit, and as shown in fig. 8, the phase-adjustable clock signal generating apparatus further includes:

a fifth determining module 405, configured to obtain a plurality of third sub-clock signals output by the third sub-multi-stage signal delay unit, and determine a third sub-target clock signal from the plurality of third sub-clock signals.

A sixth determining module 406, configured to obtain a plurality of fourth sub-clock signals output by the fourth sub-multi-stage signal delay unit, determine a fourth sub-target clock signal from the plurality of fourth sub-clock signals according to a phase delay between the second clock signal and the first target clock signal and a phase delay between the third sub-target clock signal and the first target clock signal, and determine the fourth sub-target clock signal as the second clock signal.

It can be seen that, the embodiment of the present invention can finally obtain the target output clock signal with the phase delay accuracy of 1/(N × Q) reference clock cycles by selecting and cascading the first multi-stage signal delay unit with the phase delay accuracy of 1/N reference clock cycles, and the second multi-stage signal delay unit including the third sub-multi-stage signal delay unit with the phase delay accuracy of 1/P reference clock cycles and the fourth sub-multi-stage signal delay unit with the phase delay accuracy of 1/Q reference clock cycles, so that when the effect of high-accuracy clock signal phase delay of 1/(N × P × Q) reference clock cycles is achieved, only three multi-stage signal delay units with the total number of stages N + P + Q are needed, and the existing scheme of directly performing signal delay through the multi-stage signal delay units needs the multi-stage signal delay units with the number of N × P stages, therefore, the scheme in the embodiment of the invention obviously requires less circuit elements, less circuit area and lower circuit power consumption, and compared with the existing scheme utilizing the phase interpolation circuit, the scheme has higher precision and is not influenced by external factors.

As an optional implementation manner, the specific manner in which the sixth determining module 406 determines the fourth sub-target clock signal from the plurality of fourth sub-clock signals according to the phase delay between the second clock signal and the first target clock signal and the phase delay between the third sub-target clock signal and the first target clock signal includes:

z is (X-YP)/Q, and Z is less than or equal to P and is a positive integer;

and/or, Z ═ X + (Q-Y) P/Q, and Z ≦ P, Z being a positive integer.

EXAMPLE five

Referring to fig. 9, fig. 9 is a schematic diagram illustrating another phase-adjustable clock signal generating apparatus according to an embodiment of the present invention. The phase-adjustable clock signal generating apparatus depicted in fig. 9 is applied to a signal processing system/signal processing device/signal processing server (where the signal processing server includes a local signal processing server or a cloud signal processing server). As shown in fig. 9, the phase-adjustable clock signal generating apparatus may include:

a memory 501 in which executable program code is stored;

a processor 502 coupled to a memory 501;

the processor 502 calls the executable program code stored in the memory 501 for executing the steps of the phase-tunable clock signal generation method described in the first embodiment or the second embodiment.

EXAMPLE six

The embodiment of the invention discloses a computer-readable storage medium which stores a computer program for electronic data exchange, wherein the computer program enables a computer to execute the steps of the phase-adjustable clock signal generation method described in the first embodiment or the second embodiment.

EXAMPLE seven

An embodiment of the present invention discloses a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute the steps of the phase-tunable clock signal generation method described in the first embodiment or the second embodiment.

The above-described embodiments of the apparatus are merely illustrative, and the modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

Through the above detailed description of the embodiments, those skilled in the art will clearly understand that the embodiments may be implemented by software plus a necessary general hardware platform, and may also be implemented by hardware. With this understanding in mind, the above-described technical solutions and/or portions thereof that contribute to the prior art may be embodied in the form of software products, the computer software product may be stored in a computer-readable storage medium, which may include Read-only memory (ROM), Random Access Memory (RAM), programmable Read-only memory (PROM), erasable programmable Read-only memory (EPROM), One-time programmable Read-only memory (OTPROM), Electrically erasable rewritable Read-only memory (EEPROM), compact disc Read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage, tape storage, or any other medium readable by a computer that can be used to carry or store data.

Finally, it should be noted that: the method and apparatus for generating a clock signal with adjustable phase according to the embodiments of the present invention are disclosed in the preferred embodiments of the present invention, which are only used for illustrating the technical solutions of the present invention, and are not limited thereto; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art; the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for generating a phase adjustable clock signal, the method comprising:

2. The method of claim 1, wherein determining a second target clock signal from the plurality of second clock signals based on a phase delay between a target output clock signal and the reference clock signal and a phase delay between the first target clock signal and the reference clock signal comprises:

determining a phase delay between a target output clock signal and the reference clock signal as K/(N M) of the reference clock cycles, wherein K ≦ (N M), K being a positive integer;

screening out a second clock signal with a phase delay of L/M reference clock cycles from the plurality of second clock signals, and determining the screened out second clock signal as a second target clock signal, wherein L satisfies:

l is (K-JM)/N, L is less than or equal to M, and L is a positive integer;

and/or L ═ K + (N-J) × M ]/N, and L ≦ M, L being a positive integer.

3. The method of claim 1, wherein the first multi-stage signal delay unit comprises a first sub-multi-stage signal delay unit and a second sub-multi-stage signal delay unit, and wherein the method further comprises, before obtaining the plurality of first clock signals output by the first multi-stage signal delay unit:

acquiring a plurality of first sub-clock signals output by a first sub-multi-stage signal delay unit, and determining a first sub-target clock signal from the plurality of first sub-clock signals; the first sub-target clock signal is used for being input to the second sub-multilevel signal delay unit; the phase delay precision of the first sub-clock signal and the reference clock signal input to the first sub-multi-stage signal delay unit is 1/H of the reference clock period;

acquiring a plurality of second sub-clock signals output by the second sub-multi-level signal delay unit, determining a second sub-target clock signal from the plurality of second sub-clock signals according to the phase delay between the first clock signal and the reference clock signal and the phase delay between the first sub-target clock signal and the reference clock signal, and determining the second sub-target clock signal as the first clock signal; the phase delay precision of the second sub-clock signal and the reference clock signal is 1/I of the reference clock period; wherein, H is a positive integer, and I ═ H +/-1, H ═ I ═ N.

4. The method of claim 1, wherein the second multi-stage signal delay unit comprises a third sub-multi-stage signal delay unit and a fourth sub-multi-stage signal delay unit, and wherein the method further comprises, before obtaining the plurality of second clock signals output by the second multi-stage signal delay unit:

acquiring a plurality of third sub-clock signals output by a third sub-multi-stage signal delay unit, and determining a third sub-target clock signal from the plurality of third sub-clock signals; the third sub-target clock signal is used for being input to the fourth sub-multilevel signal delay unit; the phase delay precision of the third sub-clock signal and the first target clock signal input to the third sub-multi-stage signal delay unit is 1/Q of the reference clock period;

acquiring a plurality of fourth sub-clock signals output by the fourth sub-multi-stage signal delay unit, determining a fourth sub-target clock signal from the plurality of fourth sub-clock signals according to the phase delay between the second clock signal and the first target clock signal and the phase delay between the third sub-target clock signal and the first target clock signal, and determining the fourth sub-target clock signal as the second clock signal; the phase delay precision of the fourth sub-clock signal and the first target clock signal is 1/P reference clock cycles; wherein Q and P are positive integers, and P ═ Q ± M (Q ± 1).

5. The phase tunable clock signal generation method of claim 3, wherein the first multi-stage signal delay unit performs multi-stage signal delay using a PPL ring oscillator technique, multi-stage signal delay using an injection locked ring oscillator technique, multi-stage signal delay using a DLL locked delay chain technique, multi-stage signal delay using a digital delay chain technique, or multi-stage signal delay using a phase interpolation technique;

and/or the multi-stage signal delay mode of the first sub multi-stage signal delay unit is to perform multi-stage signal delay by using a PPL ring oscillator technology, perform multi-stage signal delay by using an injection locked ring oscillator technology, perform multi-stage signal delay by using a DLL locked delay chain technology, perform multi-stage signal delay by using a digital delay chain technology or perform multi-stage signal delay by using a phase interpolation technology;

and/or the multi-stage signal delay mode of the second sub multi-stage signal delay unit is to perform multi-stage signal delay by using a PPL ring oscillator technology, perform multi-stage signal delay by using an injection locked ring oscillator technology, perform multi-stage signal delay by using a DLL locked delay chain technology, perform multi-stage signal delay by using a digital delay chain technology, or perform multi-stage signal delay by using a phase interpolation technology.

6. The phase-tunable clock signal generation method of claim 4, wherein the second multi-stage signal delay unit performs multi-stage signal delay using a PPL ring oscillator technique, multi-stage signal delay using an injection locked ring oscillator technique, multi-stage signal delay using a DLL locked delay chain technique, multi-stage signal delay using a digital delay chain technique, or multi-stage signal delay using a phase interpolation technique;

and/or the third sub-multistage signal delay unit performs multistage signal delay by using a PPL ring oscillator technology, performs multistage signal delay by using an injection locked ring oscillator technology, performs multistage signal delay by using a DLL locked delay chain technology, performs multistage signal delay by using a digital delay chain technology, or performs multistage signal delay by using a phase interpolation technology;

and/or the fourth sub-multistage signal delay unit performs multistage signal delay by using a PPL ring oscillator technology, performs multistage signal delay by using an injection locked ring oscillator technology, performs multistage signal delay by using a DLL locked delay chain technology, performs multistage signal delay by using a digital delay chain technology, or performs multistage signal delay by using a phase interpolation technology.

7. A phase-adjustable clock signal generating device is characterized by comprising a first multi-stage signal delay unit, a first signal selection unit, a second multi-stage signal delay unit and a second signal selection unit; the output end of the first multi-stage signal delay unit is connected to the input end of the first signal selection unit; the output end of the first signal selection unit is connected to the input end of the second multi-stage signal delay unit; the output end of the second multi-stage signal delay unit is connected to the input end of the second signal selection unit;

8. A phase adjustable clock signal generating apparatus, comprising:

9. A phase adjustable clock signal generating apparatus, comprising:

a memory storing executable program code;

a processor coupled with the memory;

the processor calls the executable program code stored in the memory to execute the phase-tunable clock signal generation method according to any one of claims 1 to 7.

10. A computer storage medium storing computer instructions for performing the phase tunable clock signal generation method of any one of claims 1-7 when invoked.