CN112786729A - Solar cell and cell module - Google Patents

Solar cell and cell module Download PDF

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CN112786729A
CN112786729A CN202011395240.8A CN202011395240A CN112786729A CN 112786729 A CN112786729 A CN 112786729A CN 202011395240 A CN202011395240 A CN 202011395240A CN 112786729 A CN112786729 A CN 112786729A
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layer
inversion
inversion layer
solar cell
substrate layer
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CN112786729B (en
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吴兆
徐琛
李子峰
解俊杰
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Longi Green Energy Technology Co Ltd
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Longi Green Energy Technology Co Ltd
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Priority to PCT/CN2021/133236 priority patent/WO2022116894A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
    • H01L31/0288—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
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    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

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Abstract

The invention provides a solar cell and a cell module, and relates to the technical field of photovoltaics. The solar cell comprises a PN junction; the PN junction is formed by a substrate layer and an inversion layer; room temperature TmAt least partial region of the substrate layer and the inversion layer on the backlight side forms a weak degenerate or degenerate semiconductor, and the partial region extends from the light-facing surface of the substrate layer and the inversion layer on the backlight side; the substrate layer and the inversion layer which are positioned at the light-facing side are nondegenerate semiconductors; the weakly degenerate or degenerate semiconductor is arranged such that the difference in the fermi level from the conduction band bottom of the n-type semiconductor or the valence band top of the p-type semiconductor is less than 2kB×Tm. Under the condition of applying reverse voltage, the PN junction can be used as a tunnel junction for reverse bias, tunnel current is formed in the PN junction, reverse conduction is realized, a battery string formed by the solar battery does not need to be connected with a bypass diode in parallel, the packaging loss is small,the size of the junction box is small; when the abnormity occurs, the loss current is less, the heat generation is less, and the reliability and the long-term stability are higher.

Description

Solar cell and cell module
Technical Field
The invention relates to the technical field of photovoltaics, in particular to a solar cell and a cell module.
Background
The PN junction solar cell has the characteristics of forward conduction and reverse cut-off, and when a certain PN junction solar cell is abnormal, the output current of the whole PN junction solar cell string connected with the PN junction solar cell in series is greatly influenced, and the cell module is easily damaged.
At present, the problems are solved by arranging the bypass diodes connected in parallel for the PN junction solar cell series. However, when the bypass diode is turned on, the power of the component is reduced greatly, the diode generates heat seriously, and serious potential safety hazard is easily caused.
Disclosure of Invention
The invention provides a solar cell and a cell module, and aims to solve the problems that when a bypass diode which is formed by connecting PN junction solar cells in series and in parallel is conducted, the power of the module is reduced greatly, and the diode heats seriously.
According to a first aspect of the present invention, there is provided a solar cell comprising a PN junction; the PN junction is formed by a substrate layer and an inversion layer; the doping types of the substrate layer and the inversion layer are different;
room temperature TmAt least a partial region of the substrate layer and the inversion layer on the backlight side, which extends from the light-facing surface of the substrate layer and the inversion layer on the backlight side, forms a weakly degenerate or degenerate semiconductor;
the substrate layer and the inversion layer which are positioned at the light-facing side are nondegenerate semiconductors;
the weakly degenerate or degenerate semiconductor is arranged such that the difference in the fermi level from the conduction band bottom of the n-type semiconductor or the valence band top of the p-type semiconductor is less than 2kB×Tm. The PN junction in the embodiment of the present invention exists as a general PN junction when a forward voltage is applied, and is used to separate carriers. When a reverse voltage is applied, the PN junction exists as a tunnel junction, and is reverse-biased, a tunnel current is formed in the PN junction and is reversely turned on, and when a forward voltage is applied, the PN junction returns to the normal PN junction. In the event of an abnormality, a reverse voltage is applied to the PN junction, i.e.The PN junction can be used as a tunnel junction under the abnormal condition, cannot be broken down, and cannot influence the output of the whole solar cell string connected in series with the PN junction solar cell, so that on one hand, the cell string formed by the solar cell does not need a bypass diode in parallel, the packaging loss is small, and the size of the junction box can be reduced; on the other hand, when an abnormality occurs, the other solar cells in the battery string allow normal current to pass through, only the output current of the abnormal solar cell is affected, the loss current is low, the heat generation is low, the reliability and the long-term stability are higher, and the reduction of the module power is also low. Optionally, the battery module formed by the solar battery can adopt a side junction box, and the back plate does not need to be provided with holes, so that the process is simple and the cost is low. In addition, the substrate layer and the inversion layer which are positioned at the side facing light are nondegenerate semiconductors, so that the light absorption performance is better, and the recombination is lower.
Optionally, the material of the inversion layer is selected from: at least one of a III-V compound semiconductor, an oxide semiconductor, amorphous silicon carbide, nanocrystalline silicon, and nanocrystalline silicon carbide;
the material of the substrate layer is selected from: at least one of crystalline silicon, a III-V compound semiconductor, an oxide semiconductor, amorphous silicon carbide, nanocrystalline silicon, and nanocrystalline silicon carbide.
Optionally, the inversion layer is located on the backlight side, wherein, when the following materials are used as the inversion layer,
the doping concentration of the III-V compound semiconductor is 1017cm-3-1021cm-3；
The oxide semiconductor has a donor defect or acceptor defect concentration of 1016cm-3-1021cm-3；
Under the condition that the inversion layer adopts at least one of amorphous silicon, amorphous silicon carbide, nanocrystalline silicon and nanocrystalline silicon carbide, the doping concentration of the inversion layer is 1015cm-3-1018cm-3。
Optionally, the substrate layer is located on the backlight side, wherein, when the following materials are used as the substrate layer,
crystalline siliconHas a doping concentration of 1016cm-3-1020cm-3；
The doping concentration of the III-V compound semiconductor is 1017cm-3-1021cm-3；
The oxide semiconductor has a donor defect or acceptor defect concentration of 1016cm-3-1021cm-3；
When the substrate layer is selected from at least one of amorphous silicon, amorphous silicon carbide, nanocrystalline silicon and nanocrystalline silicon carbide, the doping concentration of the substrate layer is 1015cm-3-1018cm-3。
Optionally, the inversion layer is located on the whole backlight surface of the substrate layer; the substrate layer is crystalline silicon, and the doping concentration of the crystalline silicon is 1013cm-3-1016cm-3(ii) a Or the like, or, alternatively,
the inversion layer is positioned in a local area of a backlight surface of the substrate layer, the substrate layer is crystalline silicon, and the doping concentration of the crystalline silicon is 1013cm-3-1020cm-3。
Optionally, the inversion layer is located in a local region of a backlight surface of the substrate layer, the substrate layer is crystalline silicon, and in the local region, the doping concentration of the crystalline silicon on the side close to the inversion layer is greater than that on the opposite side.
Optionally, the inversion layer is made of a III-V compound semiconductor, and a buffer layer is further disposed between the base layer and the inversion layer; the thickness of the buffer layer is 0.1-50nm, and the buffer layer is made of a material selected from the group consisting of: germanium crystal, silicon germanium compound, III-V compound.
Optionally, the inversion layer is made of an oxide semiconductor, and a silicon oxide layer is further disposed between the substrate layer and the inversion layer; the thickness of the silicon oxide layer is 0.1-10 nm.
Optionally, the material of the inversion layer is selected from: at least one of amorphous silicon, amorphous silicon carbide, nanocrystalline silicon and nanocrystalline silicon carbide, and a passivation layer is arranged between the substrate layer and the inversion layer; the thickness of the passivation layer is 0.1-10nm, and the material of the passivation layer is selected from the following materials: intrinsic amorphous silicon, nanocrystalline silicon or silicon oxide.
Optionally, the III-V compound semiconductor is selected from: at least one of GaAs, InAs, InP, GaP, AlP and AlAs;
the oxide semiconductor is selected from: a doped compound of a first material or of the first and second materials; the first material is selected from: at least one of titanium oxide, zinc oxide, tin oxide, nickel oxide, copper oxide, tungsten oxide, molybdenum oxide, and vanadium oxide; the second material is selected from: at least one of halogen elements, transition metal elements, alkali metal elements, rare earth elements, group III elements, group IV elements and group V elements.
Optionally, in a case that the inversion layer is located in a local region of the backlight surface of the base layer, a projected area of the inversion layer on the backlight surface of the base layer occupies 50% to 95% of a total area of the backlight surface of the base layer.
According to a second aspect of the present invention, there is also provided a battery assembly comprising: any of the foregoing solar cells.
The battery module has the same or similar beneficial effects as the solar battery.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without inventive exercise.
Fig. 1 shows a schematic structural diagram of a first solar cell in an embodiment of the invention;
fig. 2 shows a schematic structural diagram of a second solar cell in an embodiment of the invention;
fig. 3 shows a schematic structural view of a third solar cell in an embodiment of the invention;
fig. 4 shows a schematic structural view of a fourth solar cell in an embodiment of the invention;
fig. 5 shows a schematic structural diagram of a fifth solar cell in an embodiment of the invention;
fig. 6 is a schematic structural view showing a battery pack according to an embodiment of the present invention;
fig. 7 shows a schematic circuit diagram of a battery pack according to an embodiment of the present invention.
Description of the figure numbering:
1-a substrate layer, 2-an inversion layer, 3-a second electrode, 4-a first electrode, 5-one of a buffer layer, a first passivation layer and a second passivation layer, 6-a front surface field, 7-a back surface field, 8-a back surface passivation layer and 9-a front surface antireflection film layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
The inventor finds that in the prior art, when one PN junction solar cell is abnormal, the output current of the cell string is greatly influenced, and the reason that the cell component is easily damaged is as follows: when a PN junction solar cell is damaged and shielded, the output current and voltage of the solar cell in the string are reduced, and the other solar cells are all normally output, at this time, the abnormal solar cell is in a reverse bias state, but the current of the other solar cells in the string is not allowed to pass due to the reverse cut-off characteristic, and the abnormal solar cell needs to absorb the surplus output power of the whole string of cells. In order to solve the problem, in the prior art, the bypass diode is connected in series or in parallel with the battery, when the bypass diode is in a reverse cut-off state during normal operation, the bypass diode is in forward bias conduction when an abnormality occurs, and the battery string where the abnormal solar battery is located is short-circuited, so that the damaged solar battery is protected. However, when the bypass diode is forward biased and conducted, the output power of the cell string in which the abnormal solar cell is located is limited, the output power of the cell string in which the abnormal solar cell is located is not used as the output power of the cell module, and the conducted bypass diode generates heat seriously, which is easy to cause serious electrical safety hazard, even fire.
In the embodiment of the present invention, referring to fig. 1, fig. 1 shows a schematic structural diagram of a first solar cell in the embodiment of the present invention. The solar cell includes: a PN junction. The PN junction is composed of a body layer 1 and an inversion layer 2, the doping types of the body layer 1 and the inversion layer 2 are different, that is, the doping type of one of the body layer 1 and the inversion layer 2 is P type, the doping type of the other is N type, and there is no specific limitation as to which of the two is P type. For example, if the doping type of the body layer 1 in fig. 1 is N-type, the doping type of the inversion layer 2 is P-type. An inversion layer 2 is arranged on the backlight or light facing side of the matrix layer 1. As shown in fig. 1, an inversion layer 2 is provided on the backlight side of the matrix layer 1. Referring to fig. 2, fig. 2 is a schematic structural view of a second solar cell according to an embodiment of the present invention. In fig. 2, an inversion layer 2 is provided at the light-facing side of the matrix layer 1.
TmCharacterization of Room temperature, Room temperature TmNext, at least a part of the region of the base layer 1 and the inversion layer 2 on the backlight side forms a weakly degenerate or degenerate semiconductor. That is, room temperature TmIn this case, at least a partial region of one of the base layer 1 and the inversion layer 2 on the backlight side is doped with a high concentration to form a weakly degenerate or degenerate semiconductor. The size of at least a part of the region is not particularly limited. Specifically, a weak degenerate or degenerate semiconductor is formed in a region close to a PN junction in one of the substrate layer 1 and the inversion layer 2 on the backlight side, and both the substrate layer 1 and the inversion layer 2 can form a tunnel junction. The light-facing surface of one of the base layer 1 and the inversion layer 2 on the backlight side is the interface with the other of the base layer 1 and the inversion layer 2 on the backlight side. Part of the region is in the light-facing surface of the backlight side of the substrate layer 1 and the inversion layer 2The extension is not particularly limited in depth.
The substrate layer 1 and the inversion layer 2 are doped to a lower concentration toward the light side and are nondegenerate semiconductors. The doping concentration of the substrate layer 1 and the inversion layer 2 on the side facing light is low, the light absorption performance is good, and the recombination is low.
The base layer 1 and the inversion layer 2 on the backlight side are formed by a weakly degenerated or degenerated semiconductor such that the energy difference between the Fermi level and the conduction band bottom of the n-type semiconductor or the valence band top of the p-type semiconductor is less than 2kB×TmIn the formula kBBoltzmann constant, kBValue of 1.380649 × 10-23J/K. The PN junction formed by the base layer 1 and the inversion layer 2 is present as a general PN junction for separating carriers when a forward voltage is applied. Under the condition of applying reverse voltage, the PN junction can be used as a tunnel junction and can be reversely biased, tunnel current is formed in the PN junction and is reversely conducted without reverse breakdown, and under the condition of applying forward voltage, the PN junction is restored to be the common PN junction. Under the abnormal condition, reverse voltage is applied to the PN junction, namely, the PN junction exists as a tunnel junction and cannot be broken down under the abnormal condition, the output of the whole solar cell string connected with the PN junction solar cell in series is not influenced, and on one hand, the cell string formed by the solar cell does not need a bypass diode connected in parallel, so that the packaging loss is small, and the size of the junction box can be reduced; on the other hand, when an abnormality occurs, the other solar cells in the battery string allow normal current to pass through, only the output current of the abnormal solar cell is affected, the loss current is low, the heat generation is low, the reliability and the long-term stability are higher, and the reduction of the module power is also low.
For example, if the battery module includes 3 battery strings formed of 60 solar cells, 20 solar cells are connected in series in each battery string. If any one of the solar cells in the 1 cell string is abnormal, the abnormal solar cell is in a reverse bias state in the prior art, the current of the other solar cells in the cell string where the abnormal solar cell is located is not allowed to pass, and the output power loss is about 1/3. In the present application, when the solar cell is abnormal, the PN junction in the solar cell exists as a tunnel junction, and is reverse-biased and then reversely turned on, tunnel current is formed in the PN junction, and current of another solar cell connected in series with the solar cell can pass through the solar cell, and the solar cell exists only as a resistor in a cell string, and the output power loss is about 1/60.
As shown with reference to fig. 1, an inversion layer 2 is provided on the backlight side of the base layer 1. At least a part of the region in the inversion layer 2 is doped with a higher concentration, forming a weakly degenerate or degenerate semiconductor. The regions of the inversion layer 2 in which the weakly degenerate or degenerate semiconductor is formed extend from the light-facing surface of the inversion layer 2 into the layer. Of both the matrix layer 1 and the inversion layer 2, the matrix layer 1 is located on the light-facing side. The base layer 1 has a low doping concentration and is a non-degenerate semiconductor. A region in the inversion layer 2 forming a weakly degenerate or degenerate semiconductor with a fermi level that differs by less than 2k from the conduction band bottom of the n-type semiconductor or the valence band top of the p-type semiconductorB×Tm。
For another example, referring to fig. 2, an inversion layer 2 is provided on the light-facing surface of the base layer 1. At least a part of the region in the base layer 1 is doped with a high concentration to form a weakly degenerate or degenerate semiconductor. The regions of the base layer 1 in which the weakly degenerate or degenerate semiconductor is formed extend from within the light-facing layer of the base layer 1. The inversion layer 2 is doped with a low concentration and is a non-degenerate semiconductor. A region forming a weakly degenerate or degenerate semiconductor in the counter substrate layer 1, the difference in energy level between the Fermi level and the conduction band bottom of the n-type semiconductor or the valence band top of the p-type semiconductor being less than 2kB×Tm。
Optionally, the material of the inversion layer 2 is selected from: at least one of a III-V compound semiconductor, an oxide semiconductor, amorphous silicon carbide, nanocrystalline silicon, and nanocrystalline silicon carbide. The material of the substrate layer 1 is selected from: at least one of crystalline silicon, a III-V compound semiconductor, an oxide semiconductor, amorphous silicon carbide, nanocrystalline silicon, and nanocrystalline silicon carbide. The III-V compound semiconductor, the oxide semiconductor, the amorphous silicon carbide, the nanocrystalline silicon and the nanocrystalline silicon carbide are all direct band gap semiconductors with high tunneling efficiency, and further, when a PN junction formed by the materials exists as a tunnel junction, higher photoelectric conversion efficiency and larger reverse tunnel current can be realized.
Alternatively, in the case where the inversion layer 2 is located on the backlight side of the body layer 1, and in the case where the material of the inversion layer 2 is selected from III-V compound semiconductors, the III-V compound semiconductor has a doping concentration of 1017cm-3-1021cm-3I.e. close to the degenerate state. In the case where the material of the inversion layer 2 is selected from an oxide semiconductor, the oxide semiconductor has a donor defect or acceptor defect concentration of 1016cm-3-1021cm-3. In the case where the material of the inversion layer 2 is at least one selected from amorphous silicon, amorphous silicon carbide, nanocrystalline silicon carbide, the inversion layer 2 has a doping concentration of 1015cm-3-1018cm-3. The inversion layer 2 made of the material is easy to conduct reversely under the condition that reverse voltage is applied to the PN junction, and the tunneling efficiency is high.
Optionally, the substrate layer 1 is located on the backlight side, i.e. in case the inversion layer 2 is located on the light facing side of the substrate layer 1, in case the material of the substrate layer 1 is selected from crystalline silicon, which has a doping concentration of 1016cm-3-1020cm-3Close to the degenerate state. In the case where the material of the base layer 1 is selected from III-V compound semiconductors, the doping concentration of the III-V compound semiconductor is 1017cm-3-1021cm-3. In the case where the material of the base layer 1 is selected from oxide semiconductors, the oxide semiconductor has a donor defect or acceptor defect concentration of 1016cm-3-1021cm-3. When the material of the base layer 1 is at least one selected from amorphous silicon, amorphous silicon carbide, nanocrystalline silicon and nanocrystalline silicon carbide, the doping concentration of the base layer 1 is 1015cm-3-1018cm-3The substrate layer 1 and the inversion layer 2 made of the materials are easy to conduct reversely under the condition that reverse voltage is applied to a PN junction, and the tunneling efficiency is high.
According to the PN junction in the embodiment of the invention, when the solar cell is abnormal, through testing, the PN junction in the solar cell can exist as a tunnel junction, and can be reversely biased and further reversely conducted, tunnel current is formed in the PN junction, the self photoproduction current is reduced, the current of other solar cells connected in series with the solar cell can pass through the solar cell, the solar cell only exists in a cell string as a resistor, the heating power of the solar cell is very weak compared with the prior art, a bypass diode is not required to be connected in parallel, the packaging loss is small, and the size of a junction box can be reduced; meanwhile, when abnormality occurs, the other solar cells in the cell string allow normal current to pass, only the output current of the abnormal solar cell is affected, the loss current is low, the heat generation is low, the reliability and the long-term stability are higher, and the power reduction of the module is also low. When the reverse voltage continues to increase, the tunnel current can be continuously increased, the PN junction is not broken down, and when the reverse bias state is removed, namely the solar cell recovers to the normal operation state, the PN junction can recover to the normal working state, namely the PN junction is recovered to the existence of the general PN junction. Moreover, the PN junction reduces body recombination and parasitic absorption, and the extended space charge region expands the forbidden bandwidth of the interface region and inhibits spontaneous interface tunneling recombination under normal conditions. Meanwhile, the III-V compound semiconductor, the oxide semiconductor, the amorphous silicon carbide, the nanocrystalline silicon and the nanocrystalline silicon carbide are all direct band gap semiconductors with high tunneling efficiency, and further, when a PN junction formed by the materials exists as a tunnel junction, higher photoelectric conversion efficiency and larger reverse tunnel current can be realized.
Alternatively, the III-V compound semiconductor is selected from: GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), GaP (gallium phosphide), AlP (aluminum phosphide), AlAs (aluminum arsenide).
Optionally, the oxide semiconductor specifically refers to a transition metal oxide semiconductor, specifically selected from: a doped compound of a first material or the first material and a second material. The first material is selected from: at least one of titanium oxide, zinc oxide, tin oxide, nickel oxide, copper oxide, tungsten oxide, molybdenum oxide, and vanadium oxide. The second material is selected from: at least one of halogen elements, transition metal elements, alkali metal elements, rare earth elements, group III elements, group IV elements and group V elements.
Optionally, the inversion layer 2 is disposed on the backlight surface or the light-facing surface of the substrate layer 1 by one of epitaxy, deposition, and doping. The inversion layer 2 obtained by epitaxial growth has a steep doped element diffusion interface at the interface to reduce the width of one side of the space charge region and improve the tunneling recombination probability in a reverse state, and the epitaxial interface has fewer defects, so that the steep space charge region and energy band change response at the epitaxial side are ensured, and the lower reverse on-resistance is ensured, therefore, the epitaxial growth can be an optimal process. Besides epitaxy, precise doping processes such as ion implantation or rapid thermal diffusion, and post-deposition crystallization processes can also be used.
Alternatively, referring to fig. 1, the inversion layer 2 is disposed on the entire backlight surface of the matrix layer 1, so as to facilitate the transmission and collection of minority carriers. In the case where the inversion layer 2 is provided on the entire back side of the substrate layer 1 and the material of the substrate layer 1 is selected from crystalline silicon, the doping concentration of the crystalline silicon is 1013cm-3-1016cm-3Can reduce body recombination and parasitic absorption. The first electrode 4 is arranged on the backlight surface of the inversion layer 2, and the second electrode 3 is arranged on the light-facing surface of the base layer 1.
Alternatively, as shown in fig. 2, in the case where the inversion layer 2 is provided on the entire light-facing surface of the base layer 1, the first electrode 4 is provided on the backlight surface of the base layer 1, and the second electrode 3 is provided on the light-facing surface of the inversion layer 2.
Alternatively, referring to fig. 3, fig. 3 is a schematic structural diagram of a third solar cell according to an embodiment of the present invention. The inversion layer 2 is located in a local region of the backlight of the substrate layer 1, i.e. the inversion layer 2 does not cover the entire backlight of the substrate layer 1, and the material of the substrate layer 1 is selected from crystalline silicon, which has a doping concentration of 1013cm-3-1020cm-3. The solar cell further includes: a first electrode 4 and a second electrode 3, wherein the first electrode 4 is arranged on the backlight surface of the inversion layer 2, the second electrode 3 is arranged in the region outside the inversion layer 2 in the backlight surface of the substrate layer 1, and the electrodes do not shield the backlight surface completely, thereby being beneficial to improving the output of the solar cellAnd (6) outputting power.
Alternatively, referring to fig. 3, the inversion layer 2 is located in a local area of the backlight surface of the substrate layer 1, the substrate layer 1 is crystalline silicon, and the doping concentration of the crystalline silicon in the local area of the substrate layer 1 is greater on the side close to the inversion layer 2 than on the opposite side. That is, the inversion layer 2 is located in the local area of the backlight surface of the substrate layer 1, the substrate layer 1 is crystalline silicon, and the doping concentration of the crystalline silicon in the local area of the substrate layer 1, which is close to the inversion layer 2, is greater than that of the crystalline silicon which is far away from the inversion layer 2, so that the incident quantity of light can be ensured.
It should be noted that, after the PN junction is formed, the subsequent process temperature needs to be controlled, and an excessively high subsequent process temperature may cause element diffusion or interface layer cracking at the PN junction interface, damage the PN junction interface, and decrease the efficiency.
Optionally, as shown in fig. 3, in a case where the inversion layer 2 is disposed in a local region of the backlight surface of the base layer 1, a projected area of the inversion layer 2 on the backlight surface of the base layer 1 occupies 50% to 95% of a total area of the backlight surface of the base layer 1, and the transportation and collection effects of minority carriers and majority carriers are good.
Alternatively, the inversion layer 2 may be provided in a localized area of the light-facing surface of the matrix layer 1, i.e. the inversion layer 2 does not cover the entire light-facing surface of the matrix layer 1.
Fig. 4 shows a schematic structural diagram of a fourth solar cell in the embodiment of the present invention. Alternatively, referring to fig. 2 or fig. 4, the material in the inversion layer 2 is selected from: a buffer layer 5 is further provided between the III-V compound semiconductor, the inversion layer 2 and the base layer 1. That is, the buffer layer 5 may be provided between the inversion layer 2 and the base layer 1, regardless of whether the inversion layer 2 is provided on the light-facing surface of the base layer 1 or the inversion layer 2 is provided on the backlight surface of the base layer 1. The buffer layer 5 may function to buffer lattice mismatch, passivate interface defects, and the like. The thickness d1 of the buffer layer 5 is 0.1-50nm, and the buffer layer 5 with the thickness range has good lattice adaptation effect and good passivation performance.
Optionally, the material of the buffer layer 5 is selected from: germanium crystal, silicon germanium compound, III-V compound. The III-V compound in the buffer layer 5 may be: InPSb (indium phosphorus antimony), GaInP (gallium indium phosphorus), and the like. The buffer layer 5 made of the material has good lattice adaptation effect and passivation performance.
Optionally, the materials of the inversion layer 2 are: the oxide semiconductor is characterized in that a silicon oxide layer is further arranged between the substrate layer 1 and the inversion layer 2, namely, no matter the inversion layer 2 is arranged on the light facing surface of the substrate layer 1 or the inversion layer 2 is arranged on the backlight surface of the substrate layer 1, the silicon oxide layer can be arranged between the inversion layer 2 and the substrate layer 1, the silicon oxide layer has the functions of blocking mutual diffusion of doping elements of the substrate layer 1 and passivating interface defects, the preparation process can be realized by using the existing preparation process of the solar cell, and the preparation efficiency is high. The thickness of the silicon oxide layer is 0.1-10 nm.
Optionally, the material in the inversion layer 2 is selected from: at least one of amorphous silicon, amorphous silicon carbide, nanocrystalline silicon carbide still is provided with the passivation layer between base member layer and the inversion layer, promptly, no matter be inversion layer 2 and set up the plane of light facing at base member layer 1, still the inversion layer 2 sets up the backlight face at base member layer 1, all can be provided with the passivation layer between inversion layer 2 and the base member layer 1, the passivation layer plays and stops doping element interdiffusion between them, and the function of passivation interface defect. The thickness of the passivation layer is 0.1-10 nm.
Optionally, the material of the passivation layer is selected from: the intrinsic amorphous silicon, the nanocrystalline silicon or the silicon oxide has good diffusion blocking and passivation effects, and the preparation process only needs the existing preparation process of the solar cell, so that the preparation efficiency is high.
Fig. 5 shows a schematic structural diagram of a fifth solar cell in the embodiment of the present invention. Optionally, as shown in fig. 4 and 5, in the case that the inversion layer 2 is located on the backlight side of the matrix layer 1, the solar cell further includes a front surface field 6 located on the light-facing side of the matrix layer 1, the doping type of the front surface field 6 is the same as that of the matrix layer 1, and the doping concentration of the front surface field 6 is greater than that of the matrix layer 1. The front surface field 6 and the substrate layer 1 form a concentration gradient difference, which is beneficial to improving the photoelectric conversion efficiency.
Optionally, referring to fig. 2, in the case that the inversion layer 2 is located on the light-facing side of the base layer 1, the solar cell further includes a back surface field 7 located on the backlight side of the base layer 1, the doping type of the back surface field 7 is the same as that of the base layer 1, and the doping concentration of the back surface field 7 is greater than that of the base layer 1. The back surface field 7 and the substrate layer 1 form a concentration gradient difference, which is beneficial to improving the photoelectric conversion efficiency.
Optionally, referring to fig. 3, in the case that the inversion layer 2 is located in a local region of the backlight surface of the body layer 1, the solar cell further includes a back surface field 7 located in the backlight surface of the body layer 1 outside the inversion layer 2, the doping type of the back surface field 7 is the same as that of the body layer 1, and the doping concentration of the back surface field 7 is greater than that of the body layer 1. The back surface field 7 and the substrate layer 1 form a concentration gradient difference, which is beneficial to improving the photoelectric conversion efficiency.
Optionally, the backlight surface of the matrix layer 1 is of a planar structure or a light trapping structure, and/or the light-facing surface of the matrix layer 1 is of a planar structure or a light trapping structure, and the inversion layer 2 in contact with the planar structure or the light trapping structure adapts to the surface structure of the matrix layer 1.
Optionally, at least one of a front passivation layer, a front antireflection film layer, a scattering structure layer and a light-gathering structure layer is arranged on a light-facing surface of the PN junction; and/or at least one of a back passivation layer, a back antireflection film layer, a scattering structure layer and a light condensation structure layer is arranged on the backlight surface of the PN junction. For example, in fig. 2, 3 to 5, 9 may be a front anti-reflection thin film layer, and 8 may be a back passivation layer.
An embodiment of the present invention also provides a battery pack including: any of the foregoing solar cells. Fig. 6 is a schematic structural view showing a battery pack according to an embodiment of the present invention. Fig. 6 may be a top view looking from the light-facing side to the backlight side of the battery assembly. Fig. 7 shows a schematic circuit diagram of a battery pack according to an embodiment of the present invention. As shown with reference to fig. 7, a shunt diode is not required in each string of cells. The solar cell in the module can specifically refer to the above related descriptions, and can achieve the same or similar beneficial effects, and the details are not repeated herein for avoiding repetition.
The invention is further illustrated by the following specific examples.
Example 1
With reference to FIG. 4The substrate layer 1 is n-type monocrystalline silicon, the light facing surface of the substrate layer 1 is of a suede structure, the backlight surface is of a polishing structure, and the doping concentration of the substrate layer 1 is 1013cm-3-1016cm-3. The light facing surface of the matrix layer 1 is provided with a front surface field 6, the front surface field 6 is a heavily doped layer, the doping type is the same as that of the matrix layer 1, and the doping concentration is higher than that of the matrix layer 1. At least some regions of the inversion layer 2 form a weakly degenerate or degenerate semiconductor, and the base layer 1 is a non-degenerate semiconductor.
The light-facing surface of the base layer 1 includes a front antireflection film layer 9. The inversion layer 2 is located on the entire backlight surface side of the substrate layer 1 and is obtained by epitaxial growth. The inversion layer 2 is GaAs and is doped p-type (doped with Al) with a doping concentration of 1018cm-3-1020cm-3. The inversion layer 2 is in a nearly degenerate or degenerate state. A buffer layer 5 exists between the inversion layer 2 and the substrate layer 1, the buffer layer 5 is a SiGe buffer layer, the thickness of the buffer layer is 2-50nm, and the buffer layer is obtained by adopting an epitaxial growth mode. The back surface side of the inversion layer 2 is provided with a back passivation layer 8.
And printing the second electrode 3 on the light-facing surface of the device, drying and sintering the second electrode, printing the first electrode 4 on the backlight surface of the device, drying and sintering the first electrode, wherein the sintering temperature is not more than 700 ℃ so as to protect the tunnel junction interface and reduce interface diffusion.
Example 2
Referring to FIG. 4, the substrate layer 1 is n-type monocrystalline silicon, the light facing surface of the substrate layer 1 is of a textured structure, the back light surface is of a polished structure, and the doping concentration 10 of the substrate layer 115cm-3-1016cm-3. The light facing surface of the matrix layer 1 is provided with a front surface field 6, the front surface field 6 is a heavily doped layer, the doping type is the same as that of the matrix layer 1, and the doping concentration is higher than that of the matrix layer 1. At least some regions of the inversion layer 2 form a weakly degenerate or degenerate semiconductor, and the base layer 1 is a non-degenerate semiconductor.
The light-facing surface of the base layer 1 includes a front antireflection film layer 9. The inversion layer 2 is located on the whole backlight surface side of the substrate layer 1 and is obtained by adopting a vapor deposition method. The inversion layer 2 is aluminum-doped zinc oxide and is p-type doped. A silicon oxide layer 5 exists between the inversion layer 2 and the substrate layer 1, the silicon oxide layer 5 is a silicon oxide layer with the thickness of 1nm, and the silicon oxide layer is obtained by adopting a mode of annealing after deposition and oxidation. The back surface side of the inversion layer 2 is provided with a back passivation layer 8.
And printing the second electrode 3 on the light-facing surface of the device, drying and sintering the second electrode, printing the first electrode 4 on the backlight surface of the device, drying and sintering the first electrode, wherein the sintering temperature is not more than 700 ℃ so as to protect the tunnel junction interface and prevent the oxide layer from cracking to generate interface defects.
Example 3
Referring to FIG. 4, the substrate layer 1 is n-type monocrystalline silicon, the light facing surface of the substrate layer 1 is of a textured structure, the back light surface is of a polished structure, and the doping concentration 10 of the substrate layer 115cm-3-1016cm-3. The light facing surface of the matrix layer 1 is provided with a front surface field 6, the front surface field 6 is a heavily doped layer, the doping type is the same as that of the matrix layer 1, and the doping concentration is higher than that of the matrix layer 1. At least some regions of the inversion layer 2 form a weakly degenerate or degenerate semiconductor, and the base layer 1 is a non-degenerate semiconductor.
The light-facing surface of the base layer 1 includes a front antireflection film layer 9. The inversion layer 2 is located on the whole backlight surface side of the substrate layer 1 and is obtained by adopting a vapor deposition method. The inversion layer 2 is amorphous silicon and doped p-type with a doping concentration of 1015cm-3-1018cm-3. A passivation layer 5 is arranged between the inversion layer 2 and the substrate layer 1, the passivation layer 5 is an intrinsic amorphous silicon layer, the thickness of the passivation layer is 2nm, and the passivation layer is obtained by adopting a vapor deposition mode. The back surface side of the inversion layer 2 is provided with a back passivation layer 8.
And printing the second electrode 3 on the light-facing surface of the device, drying and sintering, printing the first electrode 4 on the backlight surface of the device, drying and sintering, wherein the sintering temperature is not more than 250 ℃ so as to protect a tunnel junction interface and prevent passivation and tunnel junction performance reduction caused by amorphous silicon crystallization.
Example 4
Referring to FIG. 2, the substrate layer 1 is n-type monocrystalline silicon, the back light surface of the substrate layer 1 is a textured structure, the light facing surface is a polished structure, and the doping concentration 10 of the substrate layer 116cm-3-1019cm-3. At least a part of the region in the base layer 1 forms a weakly degenerate or degenerate semiconductor, and the inversion layer 2 is a non-degenerate semiconductor. The backlight surface of the substrate layer 1 is provided with a back surface field 7, and the back surface field 7 is heavyAnd the doping type of the doping layer is the same as that of the base layer 1, and the doping concentration of the doping layer is higher than that of the base layer 1. The back surface field 7 may be a complete layer or in a local area located in the back side of the matrix layer 1, e.g. only in the vicinity of the electrode locations in the back side of the matrix layer 1. The base layer 1 is provided with a back passivation layer 8 on the back light side.
The inversion layer 2 is located on the whole light-facing side of the substrate layer 1 and is obtained by an epitaxial method. The inversion layer 2 is GaAs and is doped p-type (doped with Al) with a doping concentration of 1015cm-3-1017cm-3. A buffer layer 5 is arranged between the inversion layer 2 and the substrate layer 1, the buffer layer 5 is a GaAs buffer layer, the thickness of the buffer layer is 2-50nm, and the buffer layer is obtained in an epitaxial mode. The light-facing surface of the inversion layer 2 is provided with a front-facing antireflection film layer 9.
And printing the second electrode 3 on the light-facing surface of the device, drying and sintering the second electrode, printing the first electrode 4 on the backlight surface of the device, drying and sintering the first electrode, wherein the sintering temperature is not more than 700 ℃ so as to protect the tunnel junction interface and reduce interface diffusion.
Example 5
Referring to FIG. 2, the substrate layer 1 is n-type monocrystalline silicon, the back light surface of the substrate layer 1 is a textured structure, the light facing surface is a polished structure, and the doping concentration 10 of the substrate layer 116cm-3-1019cm-3. At least a part of the region in the base layer 1 forms a weakly degenerate or degenerate semiconductor, and the inversion layer 2 is a non-degenerate semiconductor. The backlight surface of the matrix layer 1 is provided with a back surface field 7, the back surface field 7 is a heavily doped layer, the doping type is the same as that of the matrix layer 1, and the doping concentration is higher than that of the matrix layer 1. The back surface field 7 may be a complete layer or in a local area located in the back side of the matrix layer 1, e.g. only in the vicinity of the electrode locations in the back side of the matrix layer 1. The base layer 1 is provided with a back passivation layer 8 on the back light side.
The inversion layer 2 is positioned on the whole light-facing side of the substrate layer 1 and is obtained by adopting a chemical vapor deposition method. The inversion layer 2 is molybdenum oxide and is doped p-type. A silicon oxide layer 5 exists between the inversion layer 2 and the substrate layer 1, the silicon oxide layer 5 is a silicon oxide layer with the thickness of 1nm, and the silicon oxide layer is obtained by adopting a mode of annealing after molybdenum oxide is deposited. The light-facing surface of the inversion layer 2 is provided with a front-facing antireflection film layer 9.
And printing the second electrode 3 on the light-facing surface of the device, drying and sintering the second electrode, printing the first electrode 4 on the backlight surface of the device, drying and sintering the first electrode, wherein the sintering temperature is not more than 700 ℃ so as to protect the tunnel junction interface and reduce interface diffusion.
Example 6
Referring to FIG. 2, the substrate layer 1 is n-type monocrystalline silicon, the back light surface of the substrate layer 1 is a textured structure, the light facing surface is a polished structure, and the doping concentration 10 of the substrate layer 116cm-3-1019cm-3. At least a part of the region in the base layer 1 forms a weakly degenerate or degenerate semiconductor, and the inversion layer 2 is a non-degenerate semiconductor. The backlight surface of the matrix layer 1 is provided with a back surface field 7, the back surface field 7 is a heavily doped layer, the doping type is the same as that of the matrix layer 1, and the doping concentration is higher than that of the matrix layer 1. The back surface field 7 may be a complete layer or in a local area located in the back side of the matrix layer 1, e.g. only in the vicinity of the electrode locations in the back side of the matrix layer 1. The base layer 1 is provided with a back passivation layer 8 on the back light side.
The inversion layer 2 is positioned on the whole light-facing side of the substrate layer 1 and is obtained by adopting a chemical vapor deposition method. The inversion layer 2 is made of hydrogen-containing amorphous silicon and is doped p-type with the doping concentration of 1013cm-3-1018cm-3. A passivation layer 5 is arranged between the inversion layer 2 and the substrate layer 1, the passivation layer 5 is an intrinsic hydrogen-containing amorphous silicon layer, the thickness of the passivation layer is 2nm, and the passivation layer is obtained by adopting a chemical vapor deposition mode. The light-facing surface of the inversion layer 2 is provided with a front-facing antireflection film layer 9.
And printing the second electrode 3 on the light-facing surface of the device, drying and sintering, printing the first electrode 4 on the backlight surface of the device, drying and sintering, wherein the sintering temperature is not more than 250 ℃, and the interface passivation failure caused by amorphous silicon crystallization is prevented.
Example 7
Referring to FIG. 3, the substrate layer 1 is n-type monocrystalline silicon, the light facing surface of the substrate layer 1 is of a textured structure, the back light surface is of a polished structure, and the doping concentration 10 of the substrate layer 113cm-3-1020cm-3And is conventional doping. At least some regions of the inversion layer 2 form a weakly degenerate or degenerate semiconductor, and the base layer 1 is a non-degenerate semiconductor. More preferably, the doping concentration is 1013cm-3-1016cm-3. The light facing surface of the matrix layer 1 is provided with a front surface field 6, the front surface field 6 is a heavily doped layer, the doping type is the same as that of the matrix layer 1, and the doping concentration is higher than that of the matrix layer 1.
The light-facing surface of the base layer 1 includes a front antireflection film layer 9. The inversion layer 2 is located in a local area of the backlight surface of the substrate layer 1, the projection of the inversion layer 2 on the backlight surface of the substrate layer 1 accounts for 50-95% of the backlight surface of the substrate layer 1, and the inversion layer 2 is obtained by adopting a vapor deposition method. The inversion layer 2 is amorphous silicon and doped p-type with a doping concentration of 1015cm-3-1018cm-3. The backlight surface of the matrix layer 1 is provided with a back surface field 7, the back surface field 7 is a heavily doped layer, the doping type is the same as that of the matrix layer 1, and the doping concentration is higher than that of the matrix layer 1. The back surface side of the inversion layer 2 is provided with a back passivation layer 8.
And printing a second electrode 3 on the region of the backlight surface of the device opposite to the inversion layer 2, printing a first electrode 4 on the rest region of the backlight surface of the device, drying and sintering, printing the first electrode 4 on the backlight surface of the device, drying and sintering, wherein the sintering temperature is not more than 250 ℃ so as to protect a tunnel junction interface and prevent passivation and tunnel junction performance reduction caused by amorphous silicon crystallization.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative rather than restrictive, and it will be apparent to those skilled in the art that many more modifications and variations can be made without departing from the spirit of the invention and the scope of the appended claims.

Claims (12)

1. A solar cell, comprising a PN junction; the PN junction is formed by a substrate layer and an inversion layer; the doping types of the substrate layer and the inversion layer are different;
room temperature TmAt least a partial region of the substrate layer and the inversion layer on the backlight side forms a weakly degenerate or degenerate semiconductor, and the partial region is formed from the substrate layer and the inversion layerA light-facing surface of the layer on one side of the backlight extends into the layer;
the substrate layer and the inversion layer which are positioned at the light-facing side are nondegenerate semiconductors;
the weakly degenerate or degenerate semiconductor is arranged such that the difference in the fermi level from the conduction band bottom of the n-type semiconductor or the valence band top of the p-type semiconductor is less than 2kB×Tm。
2. The solar cell of claim 1, wherein the inversion layer is made of a material selected from the group consisting of: at least one of a III-V compound semiconductor, an oxide semiconductor, amorphous silicon carbide, nanocrystalline silicon, and nanocrystalline silicon carbide;
the material of the substrate layer is selected from: at least one of crystalline silicon, a III-V compound semiconductor, an oxide semiconductor, amorphous silicon carbide, nanocrystalline silicon, and nanocrystalline silicon carbide.
3. The solar cell according to claim 2, wherein the inversion layer is located on a backlight side, and wherein, when the following material is used as the inversion layer,
the doping concentration of the III-V compound semiconductor is 1017cm-3-1021cm-3；
The oxide semiconductor has a donor defect or acceptor defect concentration of 1016cm-3-1021cm-3；
Under the condition that the inversion layer adopts at least one of amorphous silicon, amorphous silicon carbide, nanocrystalline silicon and nanocrystalline silicon carbide, the doping concentration of the inversion layer is 1015cm-3-1018cm-3。
4. The solar cell according to claim 2, wherein the base layer is located on a backlight side, and wherein, when the following materials are used as the base layer,
the doping concentration of crystalline silicon is 1016cm-3-1020cm-3；
III-V conversionThe compound semiconductor has a doping concentration of 1017cm-3-1021cm-3；
The oxide semiconductor has a donor defect or acceptor defect concentration of 1016cm-3-1021cm-3；
When the substrate layer is selected from at least one of amorphous silicon, amorphous silicon carbide, nanocrystalline silicon and nanocrystalline silicon carbide, the doping concentration of the substrate layer is 1015cm-3-1018cm-3。
5. The solar cell of any of claims 1-4, wherein the inversion layer is located across the back side of the matrix layer; the substrate layer is crystalline silicon, and the doping concentration of the crystalline silicon is 1013cm-3-1016cm-3(ii) a Or the like, or, alternatively,
the inversion layer is positioned in a local area of a backlight surface of the substrate layer, the substrate layer is crystalline silicon, and the doping concentration of the crystalline silicon is 1013cm-3-1020cm-3。
6. The solar cell of claim 5, wherein the inversion layer is located in a localized region of a back-side surface of the substrate layer, and the substrate layer is crystalline silicon, wherein a doping concentration of the crystalline silicon is greater in the localized region on a side of the crystalline silicon adjacent to the inversion layer than on an opposite side.
7. The solar cell according to any of claims 1 to 4, wherein the material of the inversion layer is selected from the group consisting of III-V compound semiconductors, and a buffer layer is further provided between the base layer and the inversion layer; the thickness of the buffer layer is 0.1-50nm, and the buffer layer is made of a material selected from the group consisting of: germanium crystal, silicon germanium compound, III-V compound.
8. The solar cell according to any one of claims 1 to 4, wherein the inversion layer is made of an oxide semiconductor, and a silicon oxide layer is further provided between the base layer and the inversion layer; the thickness of the silicon oxide layer is 0.1-10 nm.
9. The solar cell according to any of claims 1-4, the inversion layer being of a material selected from the group consisting of: at least one of amorphous silicon, amorphous silicon carbide, nanocrystalline silicon and nanocrystalline silicon carbide, and a passivation layer is arranged between the substrate layer and the inversion layer; the thickness of the passivation layer is 0.1-10nm, and the material of the passivation layer is selected from the following materials: intrinsic amorphous silicon, nanocrystalline silicon or silicon oxide.
10. A solar cell according to any of claims 2-4, characterized in that the III-V compound semiconductor is selected from: at least one of GaAs, InAs, InP, GaP, AlP and AlAs;
the oxide semiconductor is selected from: a doped compound of a first material or of the first and second materials; the first material is selected from: at least one of titanium oxide, zinc oxide, tin oxide, nickel oxide, copper oxide, tungsten oxide, molybdenum oxide, and vanadium oxide; the second material is selected from: at least one of halogen elements, transition metal elements, alkali metal elements, rare earth elements, group III elements, group IV elements and group V elements.
11. The solar cell according to any of claims 1-4, wherein in the case where the inversion layer is located in a local region of the backlight surface of the base layer, a projected area of the inversion layer on the backlight surface of the base layer is 50% to 95% of a total area of the backlight surface of the base layer.
12. A battery assembly, comprising: the solar cell of any one of claims 1 to 11.
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