CN112784971A - Neural network operation circuit based on digital-analog hybrid neurons - Google Patents
Neural network operation circuit based on digital-analog hybrid neurons Download PDFInfo
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Abstract
The invention discloses a neural network operation circuit based on a digital-analog mixed neuron, and relates to the technical field of neural networks. The multiplication circuit is used for multiplying the quantization weight and the fixed point quantization activation value, the multiplication circuit is realized by N shift registers, each shift register shifts and outputs m bits, the addition circuit sequentially carries out wide vector summation operation on the m bits output by the shift registers by adopting an analog circuit, the AD conversion circuit is used for converting a wide vector summation result output by the convolution circuit into a digital signal, and the quantization weight is 2 raised to the power of 2 or 0. The method is suitable for mobile terminals and portable equipment, improves the precision of the neural network model, improves the accuracy of the output result of the neural network model, reduces the chip area, enables the neural network model to be deployed on a terminal, ensures the operation precision, and overcomes the problems of high power consumption and hard hardware realization of the high-precision neural network while meeting the requirement of precision improvement.
Description
Technical Field
The invention relates to the technical field of neural networks, in particular to a neural network operation circuit based on digital-analog hybrid neurons.
Background
At present, with the development of neural network technology, in the fields of image processing, voice recognition and the like, a deep neural network obtains a good result at a cloud end. Based on the requirements of delay, bandwidth, privacy and the like, the neural network needs to be pushed to the terminal from the cloud, and inference applications such as keyword detection, face recognition, image classification and the like are carried out on the terminal. However, along with the improvement of the precision, the depth and the parameter of the neural network are also increased sharply, and the problem that the high-precision neural network is difficult to deploy on a mobile terminal and a portable device due to the fact that the prior art cannot overcome the problem that the power consumption of the neural network is large and hardware is difficult to implement under the condition of meeting the improvement of the precision is solved.
Disclosure of Invention
The invention aims to solve the technical problem of the prior art and provides a neural network operation circuit, a module, a terminal and a system based on a digital-analog mixed neuron.
The technical scheme for solving the technical problems is as follows:
a neural network operation circuit based on digital-analog hybrid neurons comprises: the convolution circuit comprises a multiplication circuit and an addition circuit, wherein the multiplication circuit is used for performing multiplication operation on quantization weight and fixed point quantization activation value, the multiplication circuit is realized by N shift registers, the bit width of each shift register is P + Q, each shift register is used for performing shift operation on the fixed point quantization activation value of each dimension of N dimensions of input data, and each shift register shifts and outputs m bits each time;
the addition operation circuit adopts an analog circuit to successively carry out wide vector summation operation on the m bits output by the shift register, and the AD conversion circuit is used for converting the wide vector summation result output by the convolution circuit into a digital signal;
wherein, P is the bit width of the fixed point quantization activation value, Q is the bit width of the shift operation, m is the preset shift output bit width, and the quantization weight is the exponential power of 2 or 0.
Another technical solution of the present invention for solving the above technical problems is as follows:
a neural network operation module based on digital-analog mixed neurons comprises: the device comprises a packaging shell, wherein an input pin and an output pin are arranged outside the packaging shell, a convolution circuit and an AD conversion circuit are arranged in the packaging shell, the convolution circuit comprises a multiplication circuit and an addition circuit, the multiplication circuit is connected with the input pin and is used for obtaining quantization weight and a fixed point quantization activation value through the input pin and carrying out multiplication operation, the multiplication circuit is realized by adopting N shift registers, the bit width of each shift register is P + Q, each shift register is used for carrying out shift operation on the fixed point quantization activation value of each dimension of N dimensions of input data, and each shift register shifts and outputs m bits each time;
the addition operation circuit adopts an analog circuit to carry out wide vector summation operation on the m bits output by the shift register in a shifting way, and the AD conversion circuit is connected with the output pin and is used for converting the wide vector summation result output by the convolution circuit into a digital signal and outputting the digital signal through the output pin;
wherein, P is the bit width of the fixed point quantization activation value, Q is the bit width of the shift operation, m is the preset shift output bit width, and the quantization weight is the exponential power of 2 or 0.
Another technical solution of the present invention for solving the above technical problems is as follows:
a terminal comprises the neural network operation circuit based on the digital-analog mixed neuron.
Another technical solution of the present invention for solving the above technical problems is as follows:
a neural network operation system based on digital-analog hybrid neurons comprises the neural network operation circuit based on the digital-analog hybrid neurons according to the technical scheme.
The invention has the beneficial effects that: the neural network operation circuit provided by the invention is suitable for mobile terminals and portable equipment, fixed point quantization of set bits is carried out on a neural network activation value, 2 exponential power or 0 quantization is carried out on weights, the precision of a neural network model is improved, the accuracy of an output result of the neural network model is improved, convolution operation is realized through a multiplication operation circuit and an addition operation circuit, multiplication operation is realized through a shift register, a plurality of bits of a multiplication operation circuit output signal in the neural network model are replaced by capacitors with different sizes, resource consumption and chip area are reduced through a successive accumulation method, the neural network operation circuit can be deployed on a terminal, the operation precision is ensured, and the problems of high power consumption and hard realization of high-precision neural network are solved while the precision improvement is met. In addition, the calculation precision can be dynamically adjusted according to the application scene, and in the case of high precision, the calculation precision is improved by increasing the iteration times; and when the power consumption is low, the precision requirement is not high, the iteration times can be reduced, and the power consumption is reduced.
Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a block diagram of a neural network circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an addition circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a latch circuit according to an embodiment of the neural network operation circuit of the present invention.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth to illustrate, but are not to be construed to limit the scope of the invention.
The neural network quantization algorithm provides great convenience for the terminal implementation of the network. However, if the weighting and the activation value of the network are both quantized by 1bit, the accuracy of the network is greatly lost; if the weight and the activation value of the network are quantized by multiple bits at the same time, the multiply-add operation is increased sharply. A convolutional neural network contains millions or even hundreds of millions of MAC operations, and conventional digital circuits consume very much power to perform such MAC operations.
Therefore, there is a need for improvement in the implementation of neural networks in algorithms and hardware to meet the requirement for improving network accuracy, and facilitate deployment on mobile terminals and portable devices.
As shown in fig. 1, a schematic diagram of a structural framework provided for an embodiment of a neural network operation circuit of the present invention is implemented based on a digital-analog hybrid neuron, and the neural network operation circuit can be deployed in terminals such as a mobile phone, a computer, and a notebook computer, and includes: the convolution circuit comprises a multiplication circuit 1 and an addition circuit 2, the multiplication circuit 1 is used for carrying out multiplication operation on quantization weight and fixed point quantization activation values, the multiplication circuit 1 is realized by N shift registers, the bit width of each shift register is P + Q, each shift register is used for carrying out shift operation on the fixed point quantization activation value of each dimension of N dimensions of input data, and each shift register shifts and outputs m bits each time;
the addition operation circuit 2 adopts an analog circuit to successively perform wide vector summation operation on the m bits output by the shift of each shift register, and the AD conversion circuit 3 is used for converting the wide vector summation result output by the convolution circuit into a digital signal;
wherein, P is the bit width of the fixed point quantization activation value, Q is the bit width of the shift operation, m is the preset shift output bit width, and the quantization weight is the exponential power of 2 or 0.
Specifically, the shift operation method comprises the following steps: the bit width of the fixed point quantization activation value is P, and the weight quantization result is { +/-2Q1,···,±2Q20, Q1 and Q2 are integers, Q2 ≦ Q1, Q ≦ max (abs (Q1), abs (Q2)), and if the weight quantization result is 0, the shift register output is 0; if the weight quantization result is 1, the shift register is kept unchanged; if the weight quantization result is other numbers, the shift register performs Q shift operations, wherein abs represents the absolute value.
For example, assuming that Q1 is 4 and Q2 is 1, the weight quantization result is { ±)/21,±22,±23,±24,0}。
It should be understood that N fixed point quantization activation values XijAnd quantization weight value WijThe multiplication is performed, and the multiplication output can be a positive number, a negative number or 0.
It should be noted that the function of the addition circuit 2 can be implemented by using the existing circuit structures, such as an adder, and these structures are the prior art and will not be described again.
After the convolution operation is completed, the AD conversion circuit 3 converts and quantizes the convolution circuit output result into a digital signal through an analog-digital circuit, and writes the digital signal into a memory as an input of a next layer of the neural network.
The neural network operation circuit provided by the embodiment is suitable for mobile terminals and portable equipment, fixed point quantization of set bits is carried out on a neural network activation value, 2-exponential power or 0 quantization is carried out on weights, the precision of a neural network model is improved, the accuracy of an output result of the neural network model is improved, convolution operation is realized through the multiplication circuit 1 and the addition circuit 2, multiplication operation is realized through a shift register, multiple bits of an output signal of the multiplication circuit 1 in the neural network model are replaced by capacitors with different sizes, resource consumption and chip area are reduced through a successive accumulation method, the neural network operation circuit can be deployed on a terminal, the operation precision is guaranteed, the problems that the high-precision neural network is large in power consumption and hardware is difficult to realize are solved while the precision is improved.
In addition, the calculation precision can be dynamically adjusted according to the application scene, and in the case of high precision, the calculation precision is improved by increasing the iteration times; and when the power consumption is low, the precision requirement is not high, the iteration times can be reduced, and the power consumption is reduced.
Optionally, in some possible implementations, as shown in fig. 1, the addition operation circuit 2 includes: a switched capacitor neuron circuit 21 and a latch circuit 22, wherein a shift register in the multiplication circuit 1 shifts and outputs an m-bit signal in the P + Q-bit output signal each time;
the switched capacitor neuron circuit 21 is used for dividing the m-bit signal to obtain an analog voltage value;
the latch circuit 22 is used for storing the analog voltage value output by the switched capacitor neuron circuit 21;
the switched capacitor neuron circuit 21 is further configured to perform addition calculation on a first analog voltage value obtained by current voltage division and a second analog voltage value obtained by last voltage division and stored in the latch circuit 22 until a preset condition is ended, and output a wide vector summation result;
where m is a preset value, m may be 4, and the P + Q bit output signal is any value stored in the corresponding shift register.
As shown in fig. 3, an exemplary structural diagram of the latch circuit 22 is shown, and the latch circuit 22 includes: switch S and capacitor CHAnd a differential amplifier a. The control signal controls the switch S, and when S is closed, the analog signal V is applied to the capacitor CHCharging is carried out, and the voltage of the capacitor changes along with the voltage of the analog signal V; when S is disconnected, the capacitor voltage is the analog voltage at the moment of disconnection of the switch, and the analog voltage can be latched by using the circuit.
Optionally, in some possible implementations, the switched-capacitor neuron circuit 21 includes: the wide vector summation circuit comprises a switched capacitor array and a differential operational amplifier, wherein the switched capacitor array is used for dividing an input signal and providing divided voltage for the differential operational amplifier, and the differential operational amplifier is used for performing addition calculation on a first analog voltage value provided by the switched capacitor array and a second analog voltage value obtained by last divided voltage stored by a latch circuit 22 until a preset condition is met, and outputting a wide vector summation result.
It should be noted that, taking multiplexing 4-bit multiplication circuit 1 output signal as an example, when voltage division is started, the switched capacitor array divides the voltage of the 4-bit output signal output by the shift register in the multiplication circuit 1 for the first time to obtain a first analog voltage value, the differential operational amplifier adds the first analog voltage value and a preset initial analog voltage value to obtain a second analog voltage value, the latch circuit 22 stores the second analog voltage value, and the multiplexing switched capacitor array divides the voltage of the 4-bit multiplication circuit 1 output signal output by the k-th shift to obtain an analog voltageValue VkWherein, in the step (A),
then the differential operational amplifier is used for simulating the voltage value VkAnd the analog voltage value latched at the (k-1) th time is added to obtain a target analog voltage value until the target analog voltage value is obtained
Then, the target analog voltage value is output, i.e., the wide vector sum of the output signals of the multiplication circuit 1.
Multiplication operation is realized by using the shift operation of the shift register, multi-bit positions of output signals of the multiplication circuit 1 in the neural network model are replaced by capacitors with different sizes, and a switched capacitor neuron multiplexing technology is adopted, so that the number of switched capacitors is further reduced, the resource loss and the chip area are reduced, and the integration on a terminal is facilitated.
Optionally, in some possible implementations, the preset condition is: when in use
And outputting a wide vector summation result, wherein k is the voltage division times of the switched capacitor array on the same signal.
Optionally, in some possible implementations, the switched capacitor array includes: a positive array and a negative array, wherein:
the positive array is connected with the positive input end of the differential operational amplifier and comprises: the first switches are used for controlling the connection states of all the first capacitors according to the obtained two non-overlapping clock signals;
the negative array is connected with the negative input end of the differential operational amplifier and comprises: and all the second switches are used for controlling the connection state of all the second capacitors according to the obtained two non-overlapping clock signals.
As shown in fig. 2, taking m-4 as an example, an example of adding the 4-bit quantization weight and the 4-bit fixed point quantization activation value to the N-dimensional data of the neuron is given, and an output signal of the multiplication circuit 1 of the 4-bit quantization weight and the 4-bit fixed point quantization activation value is 8 bits. The switched capacitor array comprises 2N × 4 capacitors with set sizes and 4N × 4 switches, and is divided into a positive part and a negative part, wherein each part comprises N × 4 capacitors with set sizes and 2N × 4 switches;
as shown in fig. 2, two switches are connected in parallel and then connected in series with a capacitor to form a capacitor control structure, 4 capacitor control structures are divided into a group, that is, a portion circled by a dotted line in fig. 2, the capacitor control structure group connected in parallel with the positive input end of the differential amplifier D is a positive array, the capacitor control structure group connected in parallel with the negative input end of the differential amplifier D is a negative array, the positive array and the negative array respectively include N capacitor control structure groups, and the switches control the connection state of 2N × 4 capacitors with set sizes in the switched capacitor array based on the obtained two non-overlapping clock signals.
Wherein Cs and Cf are preset capacitances.
For example, when the binomial non-overlapping clock signal is Φ 1, that is, before the wide vector summation operation, two plates of 2N × 4 capacitors with set sizes in the switched capacitor array are shorted, that is, two plates of each capacitor are shorted, and the capacitors are cleared;
when the two-term non-overlapping clock signal is phi 2, based on the obtained output signal of each shift register, the upper plates of 2N × 4 capacitors with set sizes in the switched capacitor array are connected with a reference power supply or a reference ground, the lower plate of the capacitor in the positive array is connected with the positive input end of the operational amplifier and used for providing positive voltage division, and the lower plate of the capacitor in the negative array is connected with the negative input end of the operational amplifier and used for providing negative voltage division.
Wherein, based on the obtained output signals of each shift register, the upper polar plates of 2N × 4 capacitors with set sizes in the switched capacitor array are connected with a reference power supply or a reference ground, and the method comprises the following steps:
when the output signal of the shift register is zero during the period that the two-phase non-overlapping clock signal is phi 2, the upper polar plates of the corresponding capacitor units in the positive array and the negative array are grounded;
when the output signal of the shift register is positive, the output signal drives the capacitor unit corresponding to the positive array to enable the upper electrode plate of the capacitor unit corresponding to the negative array to be connected with a reference power supply or a reference ground through a switch, and the upper electrode plate of the capacitor unit corresponding to the positive array is connected with the reference ground through the switch;
when the output signal of the shift register is negative, the absolute value of the output signal drives the capacitor unit corresponding to the negative array, so that the upper electrode plate of the capacitor unit corresponding to the positive array is connected with a reference power supply or a reference ground through a switch, and the upper electrode plate of the capacitor unit corresponding to the negative array is connected with the reference ground through the switch.
Wherein, the method is that the upper pole plate is connected with a reference power supply or a reference ground through a switch:
if a bit signal of the driving capacitor unit is 1, the upper electrode plate of the corresponding capacitor is connected with a reference power supply through a switch;
if a bit signal of the driving capacitor unit is 0, the upper plate of the corresponding capacitor is connected with the reference ground through the switch.
The driven capacitor unit adopts different capacitance values to replace multiple bits of a multiplication result, the capacitance value of the switch capacitor of the high bit is double of that of the second high bit, and the capacitance value of the switch capacitor of the lowest bit is the unit capacitor C.
Preferably, the driving capacitor unit can adopt different capacitance values to replace 4 bits selected by the multiplication result, and the capacitance values of the driving capacitor unit are C and 2 in sequence1C、22C、23C。
Specifically, each shift register output signal is respectively connected with a capacitor unit in the positive switch capacitor array and the negative switch capacitor array, and the capacitor units correspond to 4 bits selected by the output signals.
Firstly, when the output of the shift register is zero, the shift register shifts the lower 4bit of the output signal, and the upper electrode plates of the capacitor units corresponding to the positive array and the negative array are grounded.
When the output of the shift register is positive, the shift register shifts the lower 4 bits of the output signal, the output signal drives the capacitor unit corresponding to the positive array, if a bit driving signal of the capacitor unit is 1, the upper plate of the corresponding capacitor is connected with a reference power supply, if a bit driving signal of the capacitor unit is 0, the upper plate of the corresponding capacitor is connected with a reference ground, and the upper plate of the capacitor unit corresponding to the negative array is connected with the reference ground.
When the output of the shift register is negative, the shift register shifts the lower 4 bits of the output signal, the absolute value of the output signal drives the capacitor unit corresponding to the negative array, if a bit driving signal of the capacitor unit is 1, the upper plate of the corresponding capacitor is connected with a reference power supply, if a bit driving signal of the capacitor unit is 0, the upper plate of the corresponding capacitor is connected with a reference ground, and the upper plate of the capacitor unit corresponding to the positive array is connected with the reference ground.
The low 4bit of the shift output signal of the shift register is divided by the switch capacitor array to obtain the analog voltage Vtp_1、Vtn_1。Vtp_1、Vtn_1And initializing an analog voltage Vtp_0＝0V、Vtn_00V, V is still obtained through a differential operational amplifiertp_1、Vtn_1The latch circuit 23 stores Vtp_1、Vtn_1。
Then, a switched-capacitor neuron multiplexing technique is employed, namely: when the output of the shift register is zero, the shift register shifts to output 4 bits of signals, and the upper electrode plates of the capacitor units corresponding to the positive array and the negative array are grounded.
When the output of the shift register is positive, the shift register shifts the high 4-bit of the output signal, the output signal drives the capacitor unit corresponding to the positive array, if a bit driving signal of the capacitor unit is 1, the upper plate of the corresponding capacitor is connected with a reference power supply, if a bit driving signal of the capacitor unit is 0, the upper plate of the corresponding capacitor is connected with a reference ground, and the upper plate of the capacitor unit corresponding to the negative array is connected with the reference ground.
When the output of the shift register is negative, the shift register shifts the high 4-bit of the output signal, the absolute value of the output signal drives the capacitor unit corresponding to the negative array, if a bit driving signal of the capacitor unit is 1, the upper plate of the corresponding capacitor is connected with a reference power supply, if a bit driving signal of the capacitor unit is 0, the upper plate of the corresponding capacitor is connected with a reference ground, and the upper plate of the capacitor unit corresponding to the positive array is connected with the reference ground.
The high 4bit of the shift output signal of the shift register is divided by the switch capacitor array to obtain the analog voltage Vtp_2、Vtn_2。Vtp_2、Vtn_2And V stored by the latch circuit 23tp_1、Vtn_1Obtaining the final analog output voltage V through a differential operational amplifierop、Von。
Differential operational amplifier output voltage Vop、VonAnd an input voltage Vtp_1、Vtn_1、Vtp_2、Vtn_2The relationship of (a) is shown as follows:
alternatively, in the addition circuit 2, as shown in fig. 2, a bias circuit b may be connected in parallel between the latch circuit 22 and the switched capacitor array to correct the divided voltage of the switched capacitor array.
The difference operational amplifier can realize the summation operation of the positive number and the negative number of the output signal of the multiplication circuit 1, and the difference structure can reduce noise interference and ensure the stability and reliability of the signal.
Optionally, in some possible implementations, the capacitor may be an MOM finger capacitor.
It will be appreciated that all or part of the various embodiments described above may be included in some possible implementations.
In another embodiment of the present invention, a neural network operation module based on a digital-analog hybrid neuron is further provided, including: the device comprises a packaging shell, wherein an input pin and an output pin are arranged outside the packaging shell, a convolution circuit and an AD conversion circuit 3 are arranged in the packaging shell, the convolution circuit comprises a multiplication circuit 1 and an addition circuit 2, the multiplication circuit 1 is connected with the input pin and is used for obtaining quantization weight and fixed point quantization activation values through the input pin and carrying out multiplication operation, the multiplication circuit 1 is realized by adopting N shift registers, the bit width of each shift register is P + Q, each shift register is used for carrying out shift operation on the fixed point quantization activation value of each dimension of N dimensions of input data, and each shift register shifts and outputs m bits each time;
the addition operation circuit 2 adopts an analog circuit to successively carry out wide vector summation operation on the m bits output by the shift of each shift register, and the AD conversion circuit 3 is connected with an output pin and is used for converting the wide vector summation result output by the convolution circuit into a digital signal and outputting the digital signal through the output pin;
wherein, P is the bit width of the fixed point quantization activation value, Q is the bit width of the shift operation, m is the preset shift output bit width, and the quantization weight is the exponential power of 2 or 0.
In another embodiment of the present invention, a terminal is further provided, which includes a neural network operation circuit based on a digital-analog hybrid neuron as disclosed in any of the above embodiments.
In another embodiment of the present invention, a digital-analog hybrid neuron-based neural network operation system is further provided, including the digital-analog hybrid neuron-based neural network operation circuit disclosed in any of the above embodiments.
The reader should understand that in the description of this specification, reference to the description of the terms "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described method embodiments are merely illustrative, and for example, the division of steps into only one logical functional division may be implemented in practice in another way, for example, multiple steps may be combined or integrated into another step, or some features may be omitted, or not implemented.
The above method, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. A neural network operation circuit based on digital-analog hybrid neurons is characterized by comprising: the convolution circuit comprises a multiplication circuit and an addition circuit, wherein the multiplication circuit is used for performing multiplication operation on quantization weight and fixed point quantization activation value, the multiplication circuit is realized by N shift registers, the bit width of each shift register is P + Q, each shift register is used for performing shift operation on the fixed point quantization activation value of each dimension of N dimensions of input data, and each shift register shifts and outputs m bits each time;
the addition operation circuit adopts an analog circuit to successively carry out wide vector summation operation on the m bits output by the shift register, and the AD conversion circuit is used for converting the wide vector summation result output by the convolution circuit into a digital signal;
wherein, P is the bit width of the fixed point quantization activation value, Q is the bit width of the shift operation, m is the preset shift output bit width, and the quantization weight is the exponential power of 2 or 0.
2. The digital-analog hybrid neuron-based neural network operation circuit of claim 1, wherein the addition operation circuit comprises: the circuit comprises a switched capacitor neuron circuit and a latch circuit, wherein a shift register in the multiplication circuit shifts and outputs m-bit signals in P + Q-bit output signals each time;
the switched capacitor neuron circuit is used for successively dividing the m-bit signal to obtain an analog voltage value;
the latch circuit is used for storing the analog voltage value output by the switched capacitor neuron circuit;
the switched capacitor neuron circuit is also used for carrying out addition calculation on a first analog voltage value obtained by current voltage division and a second analog voltage value obtained by last voltage division and stored in the latch circuit until a preset condition is finished and outputting a wide vector summation result;
the P + Q bit output signal is any value stored in the corresponding shift register.
3. The digital-analog hybrid neuron-based neural network operation circuit of claim 2, wherein the switched-capacitor neuron circuit comprises: the wide vector summation circuit comprises a switched capacitor array and a differential operational amplifier, wherein the switched capacitor array is used for dividing an input signal and providing divided voltage for the differential operational amplifier, and the differential operational amplifier is used for performing addition calculation on a first analog voltage value provided by the switched capacitor array and a second analog voltage value obtained by last divided voltage stored by a latch circuit until a preset condition is met and outputting a wide vector summation result.
4. The digital-analog hybrid neuron-based neural network operation circuit according to claim 3, wherein the preset condition is that: when in use
And outputting a wide vector summation result, wherein k is the voltage division times of the switched capacitor array on the same signal.
5. The digital-analog hybrid neuron-based neural network operation circuit of claim 3, wherein the switched capacitor array comprises: a positive array and a negative array, wherein:
the positive array is connected to the positive input of the differential operational amplifier, and includes: the circuit comprises N × m first capacitors and 2N × m first switches, wherein all the first switches are used for controlling the connection states of all the first capacitors according to the obtained two non-overlapping clock signals;
the negative array is connected to the negative input of the differential operational amplifier, and includes: and all the second switches are used for controlling the connection state of all the second capacitors according to the obtained two non-overlapping clock signals.
6. A neural network operation module based on digital-analog mixed neurons is characterized by comprising: the device comprises a packaging shell, wherein an input pin and an output pin are arranged outside the packaging shell, a convolution circuit and an AD conversion circuit are arranged in the packaging shell, the convolution circuit comprises a multiplication circuit and an addition circuit, the multiplication circuit is connected with the input pin and is used for obtaining quantization weight and a fixed point quantization activation value through the input pin and carrying out multiplication operation, the multiplication circuit is realized by adopting N shift registers, the bit width of each shift register is P + Q, each shift register is used for carrying out shift operation on the fixed point quantization activation value of each dimension of N dimensions of input data, and each shift register shifts and outputs m bits each time;
the addition operation circuit adopts an analog circuit to carry out wide vector summation operation on the m bits output by the shift register in a shifting way, and the AD conversion circuit is connected with the output pin and is used for converting the wide vector summation result output by the convolution circuit into a digital signal and outputting the digital signal through the output pin;
wherein, P is the bit width of the fixed point quantization activation value, Q is the bit width of the shift operation, m is the preset shift output bit width, and the quantization weight is the exponential power of 2 or 0.
7. A terminal, comprising a digital-to-analog hybrid neuron based neural network operation circuit as claimed in any one of claims 1 to 5.
8. A digital-analog hybrid neuron-based neural network operation system, comprising the digital-analog hybrid neuron-based neural network operation circuit according to any one of claims 1 to 5.
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