CN112784616B - I with data link layer protocol2C interface card reader - Google Patents
I with data link layer protocol2C interface card reader Download PDFInfo
- Publication number
- CN112784616B CN112784616B CN202110080640.8A CN202110080640A CN112784616B CN 112784616 B CN112784616 B CN 112784616B CN 202110080640 A CN202110080640 A CN 202110080640A CN 112784616 B CN112784616 B CN 112784616B
- Authority
- CN
- China
- Prior art keywords
- block
- main control
- control chip
- data
- received
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000003993 interaction Effects 0.000 claims abstract description 18
- 230000005540 biological transmission Effects 0.000 claims abstract description 14
- 230000004044 response Effects 0.000 claims description 89
- 238000000034 method Methods 0.000 claims description 23
- 230000008569 process Effects 0.000 claims description 21
- 238000012545 processing Methods 0.000 claims description 11
- 230000000977 initiatory effect Effects 0.000 claims description 3
- 230000002159 abnormal effect Effects 0.000 claims description 2
- 238000012937 correction Methods 0.000 abstract description 8
- BAWFJGJZGIEFAR-NNYOXOHSSA-O NAD(+) Chemical compound NC(=O)C1=CC=C[N+]([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=C1 BAWFJGJZGIEFAR-NNYOXOHSSA-O 0.000 description 12
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 230000004927 fusion Effects 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
- G06K7/0013—Methods or arrangements for sensing record carriers, e.g. for reading patterns by galvanic contacts, e.g. card connectors for ISO-7816 compliant smart cards or memory cards, e.g. SD card readers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Artificial Intelligence (AREA)
- Computer Vision & Pattern Recognition (AREA)
- General Engineering & Computer Science (AREA)
- Communication Control (AREA)
Abstract
The invention discloses an I 2 C interface card reader with a data link layer protocol, which comprises: the main control chip is provided with an I 2 C interface and a USB interface, and is connected with the SE equipment through the I 2 C interface, wherein the I 2 C interface comprises an SDA data pin, an SCL clock pin and an SCT control pin, the SCT control pin is used for receiving a notification sent by the SE equipment, and whether data can be received or sent is determined according to the notification. The physical layer transport protocol of the I 2 C interface includes a data link layer protocol. The invention adds SCT control pin in the original I 2 C interface double-line protocol, which is used for SE device to inform the card reader whether to receive or send data, and adds data link layer protocol in the original physical layer transmission protocol, and can realize the functions of card reader, intelligent card, SE instruction interaction, integrity check and transmission error correction.
Description
Technical Field
The invention relates to a card reader in the field of smart cards, in particular to an I 2 C interface card reader with a data link layer protocol.
Background
With the development of intelligent network-connected automobiles, the field increasingly uses intelligent cards and Secure Elements (SE), and in order to enable communication protocols of the traditional automobile industry to be compatible with the intelligent cards and the SE better, and meanwhile, considering the difference of I 2 C interface functions of different MCUs, the invention provides a data link layer protocol which is used for completing the fusion of I 2 C interface application and intelligent card application instructions of the traditional automobile industry, so that the modification of the original mechanism of the intelligent card and the Secure Element can be reduced, and the product fusion is promoted.
In order to facilitate verification, production, development and debugging of the smart card and SE, the invention designs a card reader with a standard I 2 C interface and embedded with the data link layer protocol, which can communicate with the smart card and SE through the I 2 C interface and analyze the link layer protocol in the process of data interaction, thereby completing the functions of interaction of data blocks, integrity verification, error correction and the like.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention aims to provide the I 2 C interface card reader with the data link layer protocol, which can realize the functions of instruction interaction, integrity check, transmission error correction and the like of the card reader with a smart card and SE.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
An I 2 C interface card reader having a data link layer protocol, the card reader comprising: the main control chip is connected with the SE equipment through the I 2 C interface, the I 2 C interface comprises an SDA data pin, an SCL clock pin and an SCT control pin, the SCT control pin is used for receiving a notification sent by the SE equipment, and determining whether data can be received or sent according to the notification;
The physical layer transmission protocol of the I 2 C interface comprises a Data link layer protocol, wherein a Data frame of the Data link layer protocol comprises an NAD field, a PCB field, a Len field, a Data field and a CRC field which are sequentially arranged, the length of the NAD field and the length of the PCB field are one byte, and the length of the Len field and the length of the CRC field are two bytes; the NAD field is used for identifying a transceiver of the data; the Len field is used for identifying the length of the Data field; the CRC field is used for calculating all Data of the NAD field, the PCB field, the Len field and the Data field;
The data link layer protocol includes three data blocks: the Data processing device comprises an I block, an R block and an S block, wherein the three Data blocks comprise a PCB field, a Len field, a Data field and a CRC field which are sequentially arranged; the I block is used for actually sending data, and the block number of the I block is 0 or 1 and is sequentially and circularly used; the R block is used for notifying the opposite side when the data is abnormal, and the block number of the R block is 0 or 1 and is recycled in sequence; the S block is used for protocol control.
Further, as described above, the S block includes a timeout waiting S block and a protocol synchronization S block, where the timeout waiting S block is configured to send, during execution of the SE device, the timeout waiting S block to the main control chip within a preset waiting time, and notify the main control chip end to continue waiting; the protocol synchronization S block is used for initiating a protocol synchronization function at the main control chip end.
Further, as described above, the main control chip sending data means that the main control chip sends an APDU command to the SE device, and the main control chip receiving data means that the SE device returns an APDU response to the main control chip;
The data receiving process of the main control chip comprises the following steps: the main control chip uses a first read instruction to read the data length expected to be returned to the main control chip by the SE equipment, and uses a second read instruction to read the data with the corresponding length from the SE equipment based on the data length.
Further, as described above, the data flow control process of the master control chip terminal includes: the main control chip is used for controlling the main control chip,
(1.1) Confirming that APDU command can be transmitted when the SCT control pin of the self is detected to be high level;
(1.2) upon detecting that its own SCT control pin is low, acknowledging that a response returned by the SE device can be received;
(1.3) when an APDU command needs to be sent and the own SCT control pin is detected to be at a low level, reporting errors and resetting the SE equipment;
(1.4) after the APDU command is sent, if the preset waiting time is exceeded and any response of the SE device is not received, performing error reporting and performing a reset operation on the SE device.
Further, as described above, the data flow control process of the master control chip further includes: the main control chip is used for controlling the main control chip,
(1.5) Initially setting the current block number to 0 and the current state to be the state to be transmitted;
(1.6) after sending an I block to the SE device and correctly receiving an I block response returned by the SE device, flipping the current block number;
(1.7) after sending the protocol sync S block to the SE device,
(1.7.1) If a protocol synchronization S block response returned by the SE equipment is received, setting the current block number to 0, and setting the current state to be a state to be transmitted;
And (1.7.2) retransmitting the protocol synchronization S block in the step (1.7) if the protocol synchronization S block response returned by the SE equipment is not received, and if the retransmission times reach the preset times and the correct protocol synchronization S block response is not received, reporting an error and resetting the SE equipment.
Further, as described above, the data flow control process of the master control chip further includes: the main control chip is used for controlling the main control chip,
(1.8) After the APDU command is transmitted, within the preset waiting time,
(1.8.1) Before receiving a timeout waiting S block response returned by the SE device, if the next APDU command is continuously sent, the SE device returns an R (N) block response; n is 0 or 1;
(1.8.2) before receiving the timeout waiting S block response returned by the SE equipment, if the R (N) block response returned by the SE equipment is received, judging whether the block number of the received R (N) block response is consistent with the current block number, if so, retransmitting an instruction, otherwise, transmitting an R (N) block to the SE equipment;
(1.8.3) after receiving a correct timeout waiting S block response returned by the SE device, resetting the preset waiting time, continuing waiting, and if receiving an incorrect timeout waiting S block response, sending an R (N) block to the SE device, and requesting the SE device to retransmit;
(1.8.4) if a correct I block response returned by the SE equipment is received and the block number is consistent with the current block number, ending the interaction of the APDU instruction, turning over the current block number and preparing to send the next instruction;
(1.8.5) if other blocks are received or an error occurs, sending an R (N) block to the SE device, and requesting the SE device to retransmit.
Further, as described above, the data flow control process of the SE device side includes: the SE-equipment is provided with a control unit,
(2.1) When the main control chip powers on the SE equipment, setting an SCT control pin of the main control chip to be high level;
(2.2) after receiving and processing the APDU command sent by the main control chip, returning an APDU response to the main control chip, and setting an SCT control pin of the main control chip to be at a low level;
And (2.3) after the main control chip completely reads the data expected to be returned by the SE equipment, setting an SCT control pin of the main control chip to be high level, and waiting for receiving the next instruction.
Further, as described above, the data flow control process of the SE device side further includes: the SE-equipment is provided with a control unit,
(2.4) Initially setting the current reception block number to 0, the current transmission block number to 1, and the current state to the reception state;
(2.5) at initial power-up,
(2.5.1) If the I block sent by the main control chip is received, setting the time of the timeout waiting S block timer as the preset time, and transferring to the subsequent instruction processing;
(2.5.2) if the protocol synchronization S block sent by the main control chip is received, returning a protocol synchronization S block response, and recovering to an initial state;
(2.5.3) if other blocks are received or an error occurs, returning an R (N) block response notification error.
Further, as described above, the data flow control process of the SE device side further includes: the SE-equipment is provided with a control unit,
(2.6) If the correct I block sent by the main control chip is received and the block number is consistent with the current receiving block number, indicating successful receiving, and turning over the current receiving block number and the current sending block number;
(2.7) after receiving the correct I block sent by the main control chip, setting the time-out waiting S block timer time as the preset time, transferring to the subsequent instruction processing, at this time,
(2.7.1) If the instruction execution is completed, pulling down an SCT control pin of the main control chip, and preparing to send an I block;
(2.7.2) if the R (N) block sent by the main control chip is received, returning an R (N) block response notification error;
(2.7.3) if the S block sent by the main control chip is received, returning an R (N) block response notification error;
(2.7.4) if the I block sent by the main control chip is received, returning an R (N) block response notification error;
(2.7.5) if the preset time is reached, pulling down an SCT control pin of the main control chip, returning a timeout waiting S block response, and informing the main control chip to continue waiting;
(2.8) after a timeout wait S block response is returned to the master chip,
(2.8.1) If the instruction execution is completed, pulling down an SCT control pin of the main control chip, and preparing to send an I block;
(2.8.2) if the R (N) block sent by the main control chip is received and the block number is consistent with the current sending block number, retransmitting the timeout in the step (2.7.5) to wait for the S block response;
(2.8.3) if other blocks are received or an error occurs, an R (N) block response notification error is returned.
Further, as described above, the data flow control process of the SE device side further includes: the SE-equipment is provided with a control unit,
(2.9) After transmitting the I block to the main control chip,
(2.9.1) If the I block sent by the main control chip is received, judging whether the block number of the received I block is consistent with the current received block number, if not, returning an R (N) block response notification error, and if so, turning over the current received block number;
(2.9.2) if the R (N) block sent by the main control chip is received, judging whether the block number of the received R (N) block is consistent with the current sending block number, retransmitting the I block in the step (2.9) if the block number is consistent with the current sending block number, and returning an R (N) block response notification error if the block number is inconsistent with the current sending block number;
(2.9.3) if other blocks are received or an error occurs, returning an R (N) block response notification error;
and (2.9.4) if the protocol synchronization S block sent by the main control chip is received, returning a protocol synchronization S block response, and recovering to an initial state.
The invention has the beneficial effects that: the invention adds SCT control pin in the original I 2 C interface double-line protocol, which is used for SE device to inform the card reader whether to receive or send data, and adds data link layer protocol in the original physical layer transmission protocol, and can realize the functions of card reader, intelligent card, SE instruction interaction, integrity check and transmission error correction.
Drawings
Fig. 1 is a schematic structural diagram of connection between an I 2 C interface card reader with a data link layer protocol and a SE device according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of an I 2 C interface card reader with data link layer protocol according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating interaction between a USB interface and an upper computer according to an embodiment of the present invention;
FIG. 4 is a flow chart of interaction between an I 2 C interface reader and a SE provided in an embodiment of the present invention.
Detailed Description
In order to make the technical problems solved, the technical scheme adopted and the technical effects achieved by the invention more clear, the technical scheme of the embodiment of the invention will be further described in detail with reference to the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, are intended to fall within the scope of the present invention.
1. Hardware circuit of I 2 C interface card reader
In order to reduce power consumption, increase flexibility and expansibility, in consideration of MCU difference which may occur, we add SCT control pins in the original I 2 C double-wire protocol for SE equipment to inform a card reader whether to receive or send data at the moment. When the main device detects that the SCT pin is at a high level, a data sending operation may be performed, and when the SCT pin is detected to be at a low level, a data receiving operation may be performed, where the connection is shown in fig. 1, in this embodiment, the card reader hardware part uses an MCU chip with an I 2 C interface as a main control chip (any MCU with an I 2 C interface and a USB interface may be used) for providing a hardware implementation of a USB physical interface and an I 2 C physical interface, and uses a GPIO interface of the main control chip as an SCT signal. The circuit uses the pin array to lead out the pin of the main control chip, can be connected to a smart card or SE through the adapter plate, and a part of protection circuit is added in the circuit, and the schematic diagram is shown in figure 2.
Based on the hardware circuit design and the circuit schematic diagram, as shown in fig. 1, an embodiment of the present invention provides an I 2 C interface card reader with a data link layer protocol, including: the main control chip is provided with an I 2 C interface and a USB interface, and is connected with the SE equipment through the I 2 C interface, wherein the I 2 C interface comprises an SDA data pin, an SCL clock pin and an SCT control pin, the SCT control pin is used for receiving a notification sent by the SE equipment, and whether data can be received or sent is determined according to the notification. In this embodiment, the physical layer transport protocol of the I 2 C interface includes a data link layer protocol, and the specific design is as follows.
2. Data link layer protocol
1. Data format
In this embodiment, the Data frame of the Data link layer protocol includes an NAD field, a PCB field, a Len field, a Data field, and a CRC field that are sequentially arranged, where the lengths of the NAD field and the PCB field are one byte, and the lengths of the Len field and the CRC field are two bytes; one byte stores 8-bit unsigned numbers, and the stored values range from 0 to 255. The NAD field is used for identifying a transceiver of data, wherein the NAD field of a data block sent by a host (a main control chip) to a slave (SE equipment) is identified as 0x5A, and the NAD field of a data block returned by the slave is identified as 0xA5; the Len field is used for identifying the length of the Data field; the CRC field is used to calculate all Data for the NAD field, the PCB field, the Len field and the Data field, i.e., all Data for NAD+PCB+Len+Data, using the polynomial x 16+x12+x5 +1, x being any 16-ary number and the initial vector being all zeros. Because the original I 2 C protocol receiver can only know whether the receiving is completed or not through the ACK signal, the problem of integrity and consistency check in the data transmission process can be solved by adding the CRC field.
The data link layer protocol includes three data blocks: i block, R block and S block, three kinds of Data blocks all include PCB field, len field, data field and CRC field that arrange in proper order, and three kinds of Data blocks distinguish through PCB field, and the following table shows:
List one
| B8 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | Description of the invention |
| 0 | 0 | x | x | x | x | x | x | I block |
| 1 | 0 | x | x | x | x | x | x | R block |
| 1 | 1 | x | x | x | x | x | x | S block |
The I block is used for actually transmitting data, the fifth bit of the PCB field of the I block is used for identifying a block number, which is 0 or 1 and is sequentially recycled, and the classification thereof is as follows:
watch II
| B8 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | Description of the invention |
| 0 | 0 | x | 0 | x | x | x | x | I (0) block with block number 0 |
| 0 | 0 | x | 1 | x | x | x | x | I (1) block with block number 1 |
The fifth bit of the PCB field of the R block is used for identifying the block number, the block number is 0 or1 and is used circularly in turn, and the Len field of the R block is 0x0000, and the classification is as shown in the following table:
Watch III
| B8 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | Description of the invention |
| 1 | 0 | x | 0 | x | x | x | x | R (0) block with block number 0 |
| 1 | 0 | x | 1 | x | x | x | x | R (1) block with block number 1 |
The S block is used for protocol control, and the Len field of the S block is 0x0000, and the classification is as follows:
Table four
| B8 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | Description of the invention |
| 1 | 1 | x | x | x | x | 0 | 1 | S (bwt) block, timeout waiting |
| 1 | 1 | x | x | x | x | 1 | 0 | S (resynth) block, protocol synchronization |
The S block comprises an S (bwt) block and an S (resynth) block, wherein the S (bwt) block is used for sending the S (resynth) block to the main control chip in a preset waiting time in the execution process of the SE equipment, informing the main control chip end to continue waiting, and the S (resynth) block is used for initiating a protocol synchronization function by the main control chip end.
2. Data transceiving scheme
The main control chip sends data to the SE equipment, the main control chip sends an APDU instruction, and the main control chip receives data to the SE equipment returns an APDU response to the main control chip. The data receiving process of the main control chip comprises the following steps: the main control chip uses a first read instruction to read the data length expected to be returned to the main control chip by the SE equipment, and uses a second read instruction to read the data with the corresponding length from the SE equipment based on the data length.
The format of the data sent by the main control chip end is as follows:
TABLE five
| S | Device address +0 | A | NAD | A | PCB | A | Len | A | Data | A | CRC | A | P |
Wherein, len length is 2 bytes, its value is the length of the following data field, and the high byte is sent first and then the low byte is sent. For example, the main control chip sends data (00 a4040008a 000000333010101), and the data flow is as follows:
S+0x26(0x13+0)+A+
0x5A+A+0x00+A+
0x00+A+0x0D+A+
0x00+A+0xA4+A+0x04+A+0x00+A+0x08+A+A0+A+0x00+A+0x00+A+0x03+A+0x33+A+
0x01+A+0x01+A+0x01+A+CrcH+A+CrcL+A+P
The main control chip end receives data in two modes, and the two modes are selected according to the software and hardware functions of the MCU end.
First mode: the data receiving consists of an I 2 C read instruction, is suitable for the MCU which can receive data and analyze at the same time, and the format of the received data is as follows:
TABLE six
| S | Device address +1 | A | NAD | A | PCB | A | Len | A | Data | A | CRC | A/～A | P |
Wherein, len length is 2 bytes, its value is the length of the following data field, and the high byte is sent first and then the low byte is sent. For the APDU command sent by the main control chip, the smart card or SE returns data (Len byte data 6F4a84 … 9000,9000). The main control chip end sends a reading instruction, and the data flow is as follows:
S+0x27(0x13+1)+A+
0xA5+A+0x00+A+
LenH+A+LenL+A+
0x6F+A+0x4A+A+0x84+A+…+0x90+A+0x00+A+CrcH+A+CrcL+～A+P
Second mode: the data reception consists of two I 2 C read commands, and is applicable to MCU which must know the length to receive data, and the card reader in this embodiment adopts this mode. The MCU receives the lengths of two bytes from the SE by using the first read instruction to obtain the data length expected to be returned to the MCU by the subsequent SE, and then the MCU sends the second read instruction to read the data with the corresponding length. The format of the received data is as follows:
Watch seven
| S | Device address +1 | A | NAD | A | PCB | A | Len | A/～A | P |
Table eight
| S | Device address +1 | A | Data | A | CRC | A/～A | P |
Wherein, len length is 2 bytes, its value is the length of the following data field, and the high byte is sent first and then the low byte is sent. The MCU needs to send two read instructions, wherein the first read instruction is used for reading the length of data to be returned, and the second read instruction is used for reading the data with the corresponding length. For the APDU command sent by the main control chip, the smart card or SE returns data (Len byte data 6F4a84 … 9000,9000). The main control chip end sends a first reading instruction, and the data flow is as follows:
S+0x27(0x13+1)+A+
0xA5+A+0x00+A+
LenH+A+LenL+～A+P
The main control chip end continues to send a second reading instruction, and the data flow is as follows:
S+0x27(0x13+1)+A+
0x6F+A+0x4A+A+0x84+A+…+0x90+A+0x00+A+CrcH+A+CrcL+～A+P
3. Transmit-receive data flow control
(1) The data flow control receiving and transmitting process of the main control chip end comprises the following steps: a main control chip is arranged on the main control chip,
(1.1) Confirming that APDU command can be transmitted when the SCT control pin of the self is detected to be high level;
(1.2) upon detecting that its SCT control pin is low, acknowledging that a response returned by the SE device can be received;
(1.3) when an APDU instruction needs to be sent and the SCT control pin of the APDU instruction is detected to be at a low level, reporting errors and resetting the SE equipment;
(1.4) after the APDU command is sent, if the preset waiting time is exceeded and any response of the SE device is not received, performing error reporting and resetting operation on the SE device.
(1.5) Initially setting the current block number to 0 and the current state to be the state to be transmitted;
(1.6) after sending the I block to the SE equipment and correctly receiving the I block response returned by the SE equipment, turning over the current block number;
(1.7) after transmitting the S (resynth) block to the SE device,
(1.7.1) If an S (resynth) block response returned by the SE equipment is received, setting the current block number to 0, and setting the current state to be a state to be transmitted;
And (1.7.2) retransmitting the S (resynth) block in the step (1.7) if the S (resynth) block response returned by the SE equipment is not received, and reporting an error and resetting the SE equipment if the retransmission times reach the preset times and correct S (resynth) block responses are not received.
(1.8) After the APDU command is transmitted, within a preset waiting time,
(1.8.1) Before receiving the S (bbwt) block response returned by the SE device, if the next APDU command is continuously sent, the SE device returns an R (N) block response;
(1.8.2) before receiving the S (bwt) block response returned by the SE equipment, if the R (N) block response returned by the SE equipment is received, judging whether the block number of the received R (N) block response is consistent with the current block number, if so, retransmitting an instruction, otherwise, transmitting the R (N) block to the SE equipment;
(1.8.3) after receiving the correct S (bwt) block response returned by the SE equipment, resetting the preset waiting time, continuing waiting, and if receiving the wrong S (bwt) block response, sending an R (N) block to the SE equipment, and requesting the SE equipment to retransmit;
(1.8.4) if a correct I block response returned by the SE equipment is received and the block number is consistent with the current block number, ending the interaction of the APDU instruction, turning over the current block number and preparing to send the next instruction;
(1.8.5) if other blocks are received or an error occurs, sending an R (N) block to the SE device, requiring retransmission by the SE device. The error refers to an error such as CRC or NAD.
(2) The data flow control receiving and transmitting process of the SE equipment end comprises the following steps: the SE device(s) is/are,
(2.1) When the main control chip powers on the SE equipment, setting an SCT control pin of the main control chip to be high level;
(2.2) after receiving and processing the APDU command sent by the main control chip, returning an APDU response to the main control chip, and setting the SCT control pin of the main control chip to be at a low level;
And (2.3) after the main control chip completely reads the data expected to be returned by the SE equipment, setting the SCT control pin of the main control chip to be high level, and waiting for receiving the next instruction.
(2.4) Initially setting the current reception block number to 0, the current transmission block number to 1, and the current state to the reception state;
(2.5) at initial power-up,
(2.5.1) If the I block sent by the main control chip is received, setting the S (bwt) block timer time as preset time, and transferring to subsequent instruction processing;
(2.5.2) if the S (resynth) block sent by the main control chip is received, returning to the S (resynth) block response, and recovering to an initial state;
(2.5.3) if other blocks are received or an error occurs, returning an R (N) block response notification error.
(2.6) If the correct I block sent by the main control chip is received and the block number is consistent with the current receiving block number, indicating successful receiving, and turning over the current receiving block number and the current sending block number;
(2.7) after receiving the correct I block sent by the main control chip, setting the S (bwt) block timer time as the preset time, transferring to the subsequent instruction processing, at this time,
(2.7.1) If the instruction execution is completed, pulling down an SCT control pin of the main control chip, and preparing to send an I block;
(2.7.2) if the R (N) block sent by the main control chip is received, returning an R (N) block response notification error;
(2.7.3) if the S block sent by the main control chip is received, returning an R (N) block response notification error;
(2.7.4) if the I block sent by the main control chip is received, returning an R (N) block response notification error;
(2.7.5) if the preset time is reached, pulling down the SCT control pin of the main control chip, returning an S (bwt) block response, and informing the main control chip to continue waiting;
(2.8) after returning the S (bbw) block response to the main control chip,
(2.8.1) If the instruction execution is completed, pulling down an SCT control pin of the main control chip, and preparing to send an I block;
(2.8.2) if the R (N) block sent by the main control chip is received and the block number is consistent with the current sending block number, retransmitting the S (bwt) block response in the step (2.7.5);
(2.8.3) if other blocks are received or an error occurs, returning an R (N) block response notification error;
(2.9) after transmitting the I block to the main control chip,
(2.9.1) If the I block sent by the main control chip is received, judging whether the block number of the received I block is consistent with the current received block number, if not, returning an R (N) block response notification error, and if so, turning over the current received block number;
(2.9.2) if the R (N) block sent by the main control chip is received, judging whether the block number of the received R (N) block is consistent with the current sending block number, retransmitting the I block in the step (2.9) if the block number is consistent with the current sending block number, and returning an R (N) block response notification error if the block number is not consistent with the current sending block number;
(2.9.3) if other blocks are received or an error occurs, returning an R (N) block response notification error;
And (2.9.4) if the S (resynth) block sent by the main control chip is received, returning to the S (resynth) block response, and recovering to the initial state.
(3) In the data flow control process of the main control chip end and the SE equipment end,
(3.1) When an error occurs, the trial test of transmitting R (N) for error correction is three times, and after all fail:
1) The MCU main control chip should report errors and reset the SE equipment;
2) The SE device maintains the current state and no longer responds to the R block; if the correct I block is received, the SE device should respond.
(3.2) An S (resynth) block can only be initiated by the MCU end, the S (resynth) block is recovered after the SE end correctly receives the S (resynth) block, the synchronization times of the MCU end are three times, and the SE equipment is required to be reset after the failure.
The default time for sending the S block by the SE device is set to be 0.8 seconds, and the default timeout time for the MCU side to wait for response of the SE device is set to be 1 second. Regarding the maximum length of transmission data in one frame, customization can be negotiated according to different items.
3. I 2 C interface card reader software implementation
The card reader software mainly comprises two parts of interaction between a USB interface and an upper computer and interaction between a card reader I 2 C interface and SE. The USB interface and upper computer interaction part is used for realizing the functions of receiving an instruction issued by an upper computer, issuing the instruction and uploading an execution result, and the card reader I 2 C interface and SE interaction part is used for realizing the functions of I 2 C interface drive calling of the card reader, data link layer protocol rotation, instruction interaction, integrity check, error correction and the like.
Fig. 3 shows a code flow of the interaction part of the USB interface and the upper computer, and the command received by the card reader from the upper computer is analyzed and processed correspondingly, such as resetting SE, configuring card reader parameters, moving APDU command to the data transmission buffer, etc. And informs the main program whether the next action is to send an APDU command or directly return the operation result to the upper computer through the configuration return data n.
Fig. 4 shows that the interaction part of the interface of the card reader I 2 C and the SE mainly realizes the APDU interaction flow, converts the APDU command received by the card reader from the upper computer into an I block and sends the I block to the SE, and the operations of error correction, protocol adjustment, retransmission and the like are all completed by the program. The card reader I 2 C interface sends the I block to the SE, receives the data block returned by the SE, and judges the type of the data block: if the data block returned by the SE is the correct I block, storing the data and returning 1 to the main flow, informing the main flow to upload the returned data to the upper computer, and ending; if the data block returned by the SE is the R block, judging whether the block number is changed, if not, retransmitting the I block and then continuously receiving the data block returned by the SE, and if so, transmitting the R block to the SE and then continuously receiving the data block returned by the SE; if the data block returned by the SE is the S block, judging whether the type is correct, if not, sending the R block to the SE and then continuously receiving the data block returned by the SE, and if so, continuously receiving the data block returned by the SE, wherein the correct S block can only be S (bwt); if other blocks are received or CRC errors occur, R blocks are sent, SE retransmission is waited, and if the number of times of retransmission is exceeded, ERR is returned to the main flow; if the S block request is sent, judging whether the received instruction is an S block response, if yes, returning to 0, informing the main flow to restore the initial state and resend the instruction, if not resending the S block, and if the resending times are exceeded, returning ERR to SE.
The invention provides a complete set of data link layer protocol based on the reference of the prior I 2 C interface standard, solves the problems that the I 2 C interface protocol cannot carry out data integrity check, data error correction and data retransmission, and simultaneously, as the bottom layer protocol is close to the interface application in the traditional industrial manufacturing field, the data link layer protocol is close to the traditional safety chip application transmission protocol, the technical scheme can lead the two parties to be fused under the condition of only slightly modifying the original mechanism of the two parties, so that the fusion of two traditional industries is easier. The I 2 C interface card reader compatible with the data link layer protocol can effectively improve the testing, program development and production efficiency of the intelligent card or SE with the I 2 C interface and supporting the data link layer protocol, and provides assistance for the application of the chip in the industrial field. In terms of hardware, the I 2 C interface card reader can be replaced by any system with a main control chip MCU, such as a vehicle-mounted circuit board, intelligent card production equipment, FT test equipment and the like, and can provide I 2 C interface communication, and has wide application space in the fields of industrial production, automobile electronic equipment and the like.
It is to be added that, besides the mode of using a card reader, the technical scheme can be realized by directly connecting the MCU and the SE in the circuit board.
It will be appreciated by persons skilled in the art that the systems and methods of the present invention are not limited to the examples described in the detailed description, which are provided for the purpose of illustrating the invention only and are not intended to limit the invention. Other embodiments will occur to those skilled in the art from a consideration of the specification and practice of the invention as claimed and as claimed in the claims and their equivalents.
Claims (10)
1. An I 2 C interface card reader having a data link layer protocol, the card reader comprising: the main control chip is provided with an I 2 C interface and a USB interface, and is connected with SE equipment through the I 2 C interface, wherein the I 2 C interface comprises an SDA data pin, an SCL clock pin and an SCT control pin, the SCT control pin is used for receiving a notification sent by the SE equipment, and determining whether data can be received or sent according to the notification;
The physical layer transmission protocol of the I 2 C interface comprises a Data link layer protocol, wherein a Data frame of the Data link layer protocol comprises an NAD field, a PCB field, a Len field, a Data field and a CRC field which are sequentially arranged, the length of the NAD field and the length of the PCB field are one byte, and the length of the Len field and the length of the CRC field are two bytes; the NAD field is used for identifying a transceiver of the data; the Len field is used for identifying the length of the Data field; the CRC field is used for calculating all Data of the NAD field, the PCB field, the Len field and the Data field;
The data link layer protocol includes three data blocks: the Data processing device comprises an I block, an R block and an S block, wherein the three Data blocks comprise a PCB field, a Len field, a Data field and a CRC field which are sequentially arranged; the I block is used for actually sending data, and the block number of the I block is 0 or 1 and is sequentially and circularly used; the R block is used for notifying the opposite side when the data is abnormal, and the block number of the R block is 0 or 1 and is recycled in sequence; the S block is used for protocol control.
2. The card reader of claim 1 wherein the S block comprises a timeout waiting S block and a protocol synchronization S block, the timeout waiting S block being configured to send the timeout waiting S block to the main control chip within a preset waiting time during execution of the SE device, and notify the main control chip to continue waiting; the protocol synchronization S block is used for initiating a protocol synchronization function at the main control chip end.
3. The card reader of claim 2 wherein the main control chip sending data means that the main control chip sends an APDU command to the SE device, and the main control chip receiving data means that the SE device returns an APDU response to the main control chip;
The data receiving process of the main control chip comprises the following steps: the main control chip uses a first read instruction to read the data length expected to be returned to the main control chip by the SE equipment, and uses a second read instruction to read the data with the corresponding length from the SE equipment based on the data length.
4. The card reader of claim 3 wherein the data flow control process of the master control chip terminal comprises: the main control chip is used for controlling the main control chip,
(1.1) Confirming that APDU command can be transmitted when the SCT control pin of the self is detected to be high level;
(1.2) upon detecting that its own SCT control pin is low, acknowledging that a response returned by the SE device can be received;
(1.3) when an APDU command needs to be sent and the own SCT control pin is detected to be at a low level, reporting errors and resetting the SE equipment;
(1.4) after the APDU command is sent, if the preset waiting time is exceeded and any response of the SE device is not received, performing error reporting and performing a reset operation on the SE device.
5. The card reader of claim 4 wherein the data flow control process of the master control chip further comprises: the main control chip is used for controlling the main control chip,
(1.5) Initially setting the current block number to 0 and the current state to be the state to be transmitted;
(1.6) after sending an I block to the SE device and correctly receiving an I block response returned by the SE device, flipping the current block number;
(1.7) after sending the protocol sync S block to the SE device,
(1.7.1) If a protocol synchronization S block response returned by the SE equipment is received, setting the current block number to 0, and setting the current state to be a state to be transmitted;
And (1.7.2) retransmitting the protocol synchronization S block in the step (1.7) if the protocol synchronization S block response returned by the SE equipment is not received, and if the retransmission times reach the preset times and the correct protocol synchronization S block response is not received, reporting an error and resetting the SE equipment.
6. The card reader of claim 5 wherein the data flow control process of the master control chip further comprises: the main control chip is used for controlling the main control chip,
(1.8) After the APDU command is transmitted, within the preset waiting time,
(1.8.1) Before receiving a timeout waiting S block response returned by the SE device, if the next APDU command is continuously sent, the SE device returns an R (N) block response; n is 0 or 1;
(1.8.2) before receiving the timeout waiting S block response returned by the SE equipment, if the R (N) block response returned by the SE equipment is received, judging whether the block number of the received R (N) block response is consistent with the current block number, if so, retransmitting an instruction, otherwise, transmitting an R (N) block to the SE equipment;
(1.8.3) after receiving a correct timeout waiting S block response returned by the SE device, resetting the preset waiting time, continuing waiting, and if receiving an incorrect timeout waiting S block response, sending an R (N) block to the SE device, and requesting the SE device to retransmit;
(1.8.4) if a correct I block response returned by the SE equipment is received and the block number is consistent with the current block number, ending the interaction of the APDU instruction, turning over the current block number and preparing to send the next instruction;
(1.8.5) if other blocks are received or an error occurs, sending an R (N) block to the SE device, and requesting the SE device to retransmit.
7. The card reader of claim 6 wherein the SE device side transceiving data flow control procedure comprises: the SE-equipment is provided with a control unit,
(2.1) When the main control chip powers on the SE equipment, setting an SCT control pin of the main control chip to be high level;
(2.2) after receiving and processing the APDU command sent by the main control chip, returning an APDU response to the main control chip, and setting an SCT control pin of the main control chip to be at a low level;
And (2.3) after the main control chip completely reads the data expected to be returned by the SE equipment, setting an SCT control pin of the main control chip to be high level, and waiting for receiving the next instruction.
8. The card reader of claim 7 wherein the SE device side transceiving data flow control process further comprises: the SE-equipment is provided with a control unit,
(2.4) Initially setting the current reception block number to 0, the current transmission block number to 1, and the current state to the reception state;
(2.5) at initial power-up,
(2.5.1) If the I block sent by the main control chip is received, setting the time of the timeout waiting S block timer as the preset time, and transferring to the subsequent instruction processing;
(2.5.2) if the protocol synchronization S block sent by the main control chip is received, returning a protocol synchronization S block response, and recovering to an initial state;
(2.5.3) if other blocks are received or an error occurs, returning an R (N) block response notification error.
9. The card reader of claim 8 wherein the SE device side transceiving data flow control process further comprises: the SE-equipment is provided with a control unit,
(2.6) If the correct I block sent by the main control chip is received and the block number is consistent with the current receiving block number, indicating successful receiving, and turning over the current receiving block number and the current sending block number;
(2.7) after receiving the correct I block sent by the main control chip, setting the time-out waiting S block timer time as the preset time, transferring to the subsequent instruction processing, at this time,
(2.7.1) If the instruction execution is completed, pulling down an SCT control pin of the main control chip, and preparing to send an I block;
(2.7.2) if the R (N) block sent by the main control chip is received, returning an R (N) block response notification error;
(2.7.3) if the S block sent by the main control chip is received, returning an R (N) block response notification error;
(2.7.4) if the I block sent by the main control chip is received, returning an R (N) block response notification error;
(2.7.5) if the preset time is reached, pulling down an SCT control pin of the main control chip, returning a timeout waiting S block response, and informing the main control chip to continue waiting;
(2.8) after a timeout wait S block response is returned to the master chip,
(2.8.1) If the instruction execution is completed, pulling down an SCT control pin of the main control chip, and preparing to send an I block;
(2.8.2) if the R (N) block sent by the main control chip is received and the block number is consistent with the current sending block number, retransmitting the timeout in the step (2.7.5) to wait for the S block response;
(2.8.3) if other blocks are received or an error occurs, an R (N) block response notification error is returned.
10. The card reader of claim 9 wherein the SE device side transceiving data flow control process further comprises: the SE-equipment is provided with a control unit,
(2.9) After transmitting the I block to the main control chip,
(2.9.1) If the I block sent by the main control chip is received, judging whether the block number of the received I block is consistent with the current received block number, if not, returning an R (N) block response notification error, and if so, turning over the current received block number;
(2.9.2) if the R (N) block sent by the main control chip is received, judging whether the block number of the received R (N) block is consistent with the current sending block number, retransmitting the I block in the step (2.9) if the block number is consistent with the current sending block number, and returning an R (N) block response notification error if the block number is inconsistent with the current sending block number;
(2.9.3) if other blocks are received or an error occurs, returning an R (N) block response notification error;
and (2.9.4) if the protocol synchronization S block sent by the main control chip is received, returning a protocol synchronization S block response, and recovering to an initial state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110080640.8A CN112784616B (en) | 2021-01-21 | 2021-01-21 | I with data link layer protocol2C interface card reader |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110080640.8A CN112784616B (en) | 2021-01-21 | 2021-01-21 | I with data link layer protocol2C interface card reader |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112784616A CN112784616A (en) | 2021-05-11 |
| CN112784616B true CN112784616B (en) | 2024-05-24 |
Family
ID=75757713
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110080640.8A Active CN112784616B (en) | 2021-01-21 | 2021-01-21 | I with data link layer protocol2C interface card reader |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112784616B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004114628A1 (en) * | 2003-06-26 | 2004-12-29 | Nokia Corporation | Method and system for establishing a data link layer protocol on a 12c physical layer connection |
| EP1671467A1 (en) * | 2003-09-10 | 2006-06-21 | Nokia Corporation | Method and system for establishing a data link layer protocol on a physical layer port connection |
| CN102508812A (en) * | 2011-11-30 | 2012-06-20 | 上海大学 | Dual-processor communication method based on SPI (serial peripheral interface) bus |
| JP2018088156A (en) * | 2016-11-29 | 2018-06-07 | 大日本印刷株式会社 | Electronic information storage device, data processing method, and data processing program |
| CN110297800A (en) * | 2019-06-29 | 2019-10-01 | 飞天诚信科技股份有限公司 | The realization method and system of stabilized communication between a kind of main control chip and safety chip |
| CN111008172A (en) * | 2019-12-09 | 2020-04-14 | 东信和平科技股份有限公司 | Interface communication protocol stack |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102880842B (en) * | 2012-08-16 | 2015-09-23 | 飞天诚信科技股份有限公司 | A kind of method strengthening non-contact card and card reader communication robust |
| US20180114007A1 (en) * | 2016-10-21 | 2018-04-26 | Samsung Electronics Co., Ltd. | Secure element (se), a method of operating the se, and an electronic device including the se |
| US11971841B2 (en) * | 2020-05-21 | 2024-04-30 | Intel Corporation | Link layer-PHY interface adapter |
-
2021
- 2021-01-21 CN CN202110080640.8A patent/CN112784616B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004114628A1 (en) * | 2003-06-26 | 2004-12-29 | Nokia Corporation | Method and system for establishing a data link layer protocol on a 12c physical layer connection |
| CN1813456A (en) * | 2003-06-26 | 2006-08-02 | 诺基亚有限公司 | Method and system for establishing a data link layer protocol on a i2c physical layer connection |
| EP1671467A1 (en) * | 2003-09-10 | 2006-06-21 | Nokia Corporation | Method and system for establishing a data link layer protocol on a physical layer port connection |
| CN102508812A (en) * | 2011-11-30 | 2012-06-20 | 上海大学 | Dual-processor communication method based on SPI (serial peripheral interface) bus |
| JP2018088156A (en) * | 2016-11-29 | 2018-06-07 | 大日本印刷株式会社 | Electronic information storage device, data processing method, and data processing program |
| CN110297800A (en) * | 2019-06-29 | 2019-10-01 | 飞天诚信科技股份有限公司 | The realization method and system of stabilized communication between a kind of main control chip and safety chip |
| CN111008172A (en) * | 2019-12-09 | 2020-04-14 | 东信和平科技股份有限公司 | Interface communication protocol stack |
Non-Patent Citations (1)
| Title |
|---|
| I2C总线详解;jiangchao3392;https://blog.csdn.net/jiangchao3392/article/details/103899380;20200108;第1-17页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112784616A (en) | 2021-05-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1681814B1 (en) | Wireless identification protocol with confirmation of successful transmission | |
| CN100366029C (en) | Communication controller, host-side controller, communication equipment, communication system and method | |
| CN102546784B (en) | Method for conducting batch upgrading for device firmware based on controller area network (CAN) bus | |
| US20160299753A1 (en) | Firmware upgrading method for bluetooth electronic scales | |
| CN108337120A (en) | A kind of remote upgrade method of internet-of-things terminal equipment | |
| CN1245620A (en) | Method for conveying control commands for SIM card from external apparatus to SIM card | |
| EP2797026B1 (en) | Portable electronic device | |
| CN107832250A (en) | A kind of master-slave communication timing method and method for reliable transmission based on SPI | |
| CN109450912B (en) | Data transmission method, device and equipment | |
| CN104883611B (en) | The adjustment method and system of TV screen | |
| CN112784616B (en) | I with data link layer protocol2C interface card reader | |
| WO2017049557A1 (en) | Adapter upgrade method, mobile terminal, and adapter | |
| CN107852275B (en) | Data transmission device, data transmission method, reception device, and reception method | |
| EP2851839B1 (en) | Portable electronic device and IC card processing device | |
| CN116578521A (en) | Single-bus communication method, device, system and equipment | |
| CN111241172B (en) | Data storage method, device, terminal and computer readable medium | |
| CN116579365A (en) | Antenna detection device, method and equipment of RFID (radio frequency identification) tag used by power grid | |
| CN113904723B (en) | Infrared communication method and device, storage medium and electronic device | |
| CN113452603A (en) | Data transmission method and related device | |
| US10162570B2 (en) | Methods and apparatuses of compensating for delays caused by an extension line of a storage device | |
| JPH09179947A (en) | Ic card | |
| CN113760577B (en) | Dynamic connection answering device, processing method, control device and storage medium | |
| KR20070076747A (en) | Apparatus of data processing and method of setting program data thereof | |
| CN104038309A (en) | Simulation system communication method and simulation system | |
| CN109962828B (en) | Device and method for secure communication |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |