CN112783472B

CN112783472B - Multi-value logic wide-bit high-speed adder

Info

Publication number: CN112783472B
Application number: CN201911105173.9A
Authority: CN
Inventors: 何群
Original assignee: Individual
Current assignee: Individual
Priority date: 2019-11-05
Filing date: 2019-11-05
Publication date: 2023-12-12
Anticipated expiration: 2039-11-05
Also published as: CN112783472A

Abstract

A multi-value logic wide-bit high-speed adder. The voltage values are divided into different levels by using a wide voltage space and a lower threshold value of the CMOS logic circuit so that one site can represent various values. The invention describes the principle of 4-level 4-ary addition operation by dividing the voltage value. The improved schmitt gate is adopted to carry out voltage comparison to determine the value range of the variable so as to carry out fidelity registering and total input and output; the state logic simplification is adopted to convert the multi-value into the weighted binary logic to realize the two-site full adder, 4 full adders are divided into 1 group, the 16 groups are used to form the 64-site (equivalent to 128 bits of binary) wide-bit adder, the single-chain gating carry mode is adopted in the group, and the single-chain logic push-pull carry mode is adopted between the groups. Compared with a corresponding CMOS adder, the CMOS adder has the following characteristics: each site can represent 4 numerical values, and compared with two-value logic, the bit length can be doubled and the bus and storage space can be reduced by one time; the carry delay of each group is only 1 BJT tube, so that the carry delay of 4 CMOS tubes can be reduced; one-line single-chain carry linkage between groups is easy to linearly expand.

Description

Multi-value logic wide-bit high-speed adder

Technical Field

Computer arithmetic operation unit, in particular adder. Belonging to the integrated circuit design.

Background

The adder is a core component of the computer system, and the execution speed of the adder is proportional to word length, time delay (time delay) of a logic device and a carry mode, and the three are keys for solving the execution speed of the adder.

For word length and time delay problems, various CMOS devices with VDD in the range of 1.0 to 18.0V have been widely used in recent years, and devices employing several power supplies (VCC) with different voltage values in the same chip have been rapidly developed to accommodate such situations, and it is apparent that logic 0 and 1 can be distinguished in the case where VCC is low due to the decrease of the turn-on voltage VT of the CMOS device. Based on the principle, if VCC is widened, a voltage space with a wide VCC range can be defined as a plurality of logic values, the voltage values are used for representing the numerical values based on the multi-value logic principle, 1-bit variable can be used for representing not only 0 and 1 but a plurality of values, namely, the potential in a logic circuit is divided into a plurality of grades, and each grade represents one numerical value, so that a multi-value logic relation is obtained, and therefore, an adder with 4, 6 and … systems can be realized at 1 bit, the length of an operation word length can be effectively increased, and the operation speed can be increased;

for the carry mode of the adder, the multi-chain carry adder structure represented by carry-ahead is layered by grouping. Each group characterizes the carry state of the group by a carry transfer function (P) and a carry generation function (G), and hierarchical uploading of the groups is judged to give the carry state of each group. With the increase of the word width and the increase of the hierarchy of the adder, the number of devices is increased, the number of connecting lines is increased, and the problem of obviously decreasing carry speed is caused; a single-chain carry adder structure represented by Manchester chain is controlled by P signal to increase carry speed by bypass mode. Because each bypass node is realized by a multi-way switch or a transmission gate step, when the word width is increased, the delay step of the multi-way switch is obviously increased, and the transmission gate is limited by the number of nodes, so that high-speed transmission of the carry state is difficult to realize. By combining the characteristics of the two, n loci are divided into m groups, single-chain gating carry is carried out in the groups by pi and gi characteristics, and the arithmetic speed of the adder can be greatly improved by adopting single-chain logic push-pull carry under the condition of P, G (which is a function of pi and gi) among the groups.

Disclosure of Invention

Aiming at the problems of the background technology, a multi-value access and single-chain carry wide-bit high-speed adder is provided.

The invention uses four-value logic to illustrate the principle that the logic variable a can be one of four values of 0, 1, 2 and 3, and the corresponding voltages are 0-1V, 1-2V, 3-4V and 4-5V;

before addition operation, converting the multi-value variable into corresponding weighted binary logic value, wherein the weight corresponds to the numerical value, and the method is realized by an improved schmitt gate based on a multi-value logic threshold operation principle. Using 2.0V as demarcation voltage, using one voltage-controlled Schmidt gate to divide a into two parts of (3, 2) and (1, 0), using y=logic 1 to show a= (3, 2) and logic 0 to show a= (0, 1), using two asymmetric Schmidt gates to respectively distinguish two extreme values 3 and 0 from a, and comparing with demarcation logic y to determine weight logic values L0, L1, L2, L3 of a to respectively represent values 0, 1, 2, 3;

according to the characteristic of definite value of the weighted binary logic value, a state logic simplification is adopted to realize a two-variable full adder, namely, a high-resistance state is taken as a logic 0 state to participate in single-tube AND and single-line OR operation, and finally, an active Schmitt gate is used for converting the high-resistance state into logic 0;

the 4 full adders are used as a unit group, single-chain selected carry is adopted in the group, and single-chain logic push-pull carry is adopted between groups. The gating carry in the group adopts a 4-pipe gating gate, and has the gating effects of mutual exclusion of the carry in the home position and the forward transmission in the rear position; the inter-group single-chain logic push-pull carry is composed of 4 BJT transistors and 1 tristate gate, the carry state of opening/closing the home position is realized by using the two transistors to enter a carry chain, and the push-pull uploading carry signal is realized by using a pair of BJT transistors (BiCMOS). Thus, the extreme value speed of carry can be achieved;

the access and transmission of the variable are realized by adopting the multi-value fidelity logic, the corresponding weighted binary logic value fields 0, 1, 2 and 3 are obtained for the input multi-value variable a according to the variable conversion method, the corresponding standard voltage is driven by the value field intensity, and the multi-value variable register or the memory with voltage fidelity is formed by the multi-value variable a and the three transmission gates. The variable can be stored, fetched and transmitted by orderly controlling the on/off of the transmission gate.

Drawings

FIG. 1 conversion of a multivalued variable to a weighted logic value

(a) The method comprises the following steps A voltage-controlled asymmetric schmitt gate logic diagram, wherein a multi-value variable a is resolved into a logic diagram of two parts of (0, 1) and (2, 3), y=0 represents a=2 or 3, and y=1 represents a=0 or 1;

(b) The method comprises the following steps The upper asymmetric schmitt gate logic diagram resolves a=3 to L3, if a=3, l3=1 and conversely l3=0;

(c) The method comprises the following steps The lower asymmetric schmitt gate logic map resolves a=0 to L0, l0=1 if a=0 and l0=0 otherwise.

FIG. 2 state addition logic carry transfer function (P) and carry generation function (G)

(a) The method comprises the following steps A state logic specification legend;

(b) The method comprises the following steps Adding logic diagrams with sum of 0 and 1 values and corresponding carry g1 (1), wherein c is the carry state of the rear site to the present site;

(c) The method comprises the following steps The addition of the present bit points adds the logic diagrams with the sum of 1 and 2 values and generates corresponding carry g1 (2).

FIG. 3 carry function and AND generating logic and two-site full adder diagram

(a) The method comprises the following steps The addition of the position points is that the sum is a logic diagram with 2 and 3 values and corresponding carry G1 (3), and the carry generated by the addition of the two values generates a function G;

(b) The method comprises the following steps The addition of the present bit points is carried out on a logic diagram with the sum of 3 and 0 values and a carry transfer function P generated by adding the two values;

(c) The method comprises the following steps Generating a binary-added full-addition sum variable S;

(d) The method comprises the following steps The two-site full adder general diagram, wherein ci-1 is the carry state of the rear site to the present site.

FIG. 4 select gate, pass gate and description

(a) The method comprises the following steps A selection gate; (b): a gate; (c): a bit carry principle description.

FIG. 54 bit point adder

Including 4-bit adders for intra-group and inter-group carry.

Figure 664 locus adder

A 64-bit adder (equivalent to a binary 128-bit adder), c, co are abbreviations for c in, cout, respectively.

FIG. 7 multiple-value access logic and bus transfer

(a) The method comprises the following steps Multi-value comparison and fidelity logic;

(b) The method comprises the following steps A multi-value register and bus access logic, wherein elements 1, 2,3 are transmission gates.

FIG. 8 example 1 uses a 32-bit adder (equivalent to a binary 64-bit adder)

Detailed Description

1. Multi-value logic definition

Since CMOS devices can operate under a wide range of voltages and have excellent symmetry, n potentials V1, V2, …, vn having a multi-valued logic relationship can be provided, each potential representing a logic value to 0 potential (ground), one of which can be taken by a 1-site logic variable representing its range of values. The present invention illustrates its principles in four-value logic.

Let the value of a four-valued logic system be i: 0. 1, 2,3, the logical variables of which are a, b, the invention relates to the following multi-valued logical operations (denoted "not" sign):

and (5) inverting operation: -a= (3-a); threshold operation: a, a ⁱ =3 (if a=i), a ⁱ =0 (if a+.i);

the four-value logic system represents the value range by voltage as shown in table 1.

Table 1 four-value logic definition

2. Conversion of multi-valued variables into weighted binary logic

For addition calculation, a multi-value variable a belonging to four value ranges is resolved into corresponding values, and the conversion of the multi-value variable into the authorized two-value logic (L3, L2, L1 and L0) can be realized by adopting an improved Schmitt device according to the multi-value logic threshold operation principle. The logic diagram is shown in fig. 1 (in which the logic gate diagrams correspond to the respective virtual box parts, which are also part of the multi-valued variable register, see description of 6 later).

Let the multi-value variable be a and the turn-on voltage VT of the M-tube be approximately 1V, divide the a logic value into two parts a= (3, 2) and a= (0, 1) with fig. 1 (a); fig. 1 (b) resolves a=3 to L3; fig. 1 (c) resolves a=0 to L0.

The front end of fig. 1 (a) is a schmitt gate with asymmetric voltage control, and when a= (3, 2), the fidelity voltage is (4.8V, 3.8V), as shown in fig. 6, since the drain of M1 is V2 (=4v), M1 cannot be turned on; when M2 and M4 are on, x=0 turns on M6, V1L turns on M7, and y=0, which means that a is in the range of 3 and 2; when a=0, 1, the voltage is between 0 and 2V, M1 is turned on, M3 is turned on from positive feedback, M2 is turned on, x=v2, M6 is turned on, and M7 is turned off (because x voltage > V1L), and x=v2 is shaped to y=v3 (logic 1), and there is

When a= (3, 2), y=0; when a= (0, 1), y=1 (1)

Fig. 1 (b) is an upper asymmetric schmitt gate for resolving a=3, with a fidelity voltage of 4.8V, as follows:

when a=0, 1, 2, M1 is turned on, positive feedback is caused by the voltage increase of the point a to the point B to turn on M3, M3 is turned on and M2 is turned off, and the output l3=v3 (logic 1) indicates that a is not in the value range of 3;

when a=3, stopping M1, without causing positive feedback, the point a is 0V, i.e., output l3=0v (logical 0), indicating that a is within the value range of 3. Has the following components

When a= (0, 1, 2), -l3=1; when a=3, l3=0 (2)

Fig. 1 (c) is an asymmetric schmitt gate for resolving a=0, with a fidelity voltage of 0.2V, as follows:

when a=3, 2, 1, m4 is turned on, positive feedback is caused by the voltage increase of the point F to the point G to turn on m2, m2 is turned on and m3 is turned off, and the output l0=0v (logic 0) indicates that a is not in the value range of 0;

when a=0, let m4 end, and cause no positive feedback, the G point is V3, i.e., output l0=v3 (logical 1), indicating that a is within the value range of 0. Has the following components

When a= (0, 1, 2), l0=0; when a=3, l0=1 (3)

From formulas (1), (2) and (3), directly derive L3, L0 and derive the logic formulas for L1 and L2:

l2= -y. -L3; l1= y. to L0, see fig. 1.

3. Two-variable addition operation

The addition operation is to obtain S ("sum") and P and G1 by adding arithmetic formula to the weighted binary logic values L3-0, i 3-0 converted by the multi-value variables a, b. See truth table 2 below, which in fact forms a 4-ary full adder. In the table, N represents the value sequence number, a (L3-0) and b (i 3-0) represent the weight values thereof, H represents the sum of the addition arithmetic values, P represents the carry transfer function, G1 (carry generation function) represents the forward carry of 1, S represent the addition "sum" of the present position point respectively, c represents the carry value of the following position point to the present position point, S is the "sum" without adding c, and S is the "sum" with adding c.

Table 2 addition truth table

Table 2 is divided into 4 parts (separated by a double line in the table) by the truth table by s-increasing values (0.fwdarw.1.fwdarw.2.fwdarw.3).

Because only one true value appears in the table 2 in one operation, the state logic simplification is adopted, and the method is to realize the AND operation by a single tube and the OR operation by a single wire on the premise of ensuring that the input (grid) of each CMOS tube has a certain logic value; the high resistance (corresponding to logic "0") is present as a logic state, and is converted to logic 0 by an active threshold operation at the logic termination point of the state.

The and operation is realized by a single tube, see fig. 2 (a):

lio=li·ik (lio=1 when li=1 and ik=1; otherwise lio=z (high resistance);

ljo =lj·ik (Ljo =1 when lj=1 and ik=0, otherwise Ljo =z.

The OR operation is implemented in a single line, see FIG. 2 (a):

in the figure, point a=l1·i3+l2·i2 (when one of the two and formulas (at most 1) is 1, a=1, otherwise a=z (high resistance)), m is a demarcation tube in the figure, the state of point a is transferred to point B, and the state logic combination of point B will not change the state of point a, and the output of the tube is the output of the or gate.

The termination point uses the active schmitt gate to resolve the high resistance to a logic 0 operation, see fig. 2 (a) below:

x=z, m1, m2 output is Z, m3, m4 are on under V1L action, y=0. Wherein V1L is the logic potential of V1, see FIG. 1 (a);

x=1, m1 and m2 are turned on under the action of V1L, m2 is turned on to stop m3, m1 is turned on, and x is turned on to pass through m1, so that y=x=1.

The implementation of the addition operation is performed,

the arithmetic represented by numbers 1, 8, 11, 14 (first part) is expressed as:

if (1+3) or (2+2) or (3+1) =1, then a carry will be generated, i.e. g1 (1) =1. And the home sum is:

((0+0) or (1+3) or (2+2) or (3+1)) and (c=0) s0=1, showing the sum being 0;

s1=1 when (0+0) or (1+3) or (2+2) or (3+1)) and (c=1), the sum is shown as 1.

The corresponding logic expression is:

g1＝L1·i3+L2·i2+L3·i1；

s0＝(L0·i0+L1·i3+L2·i2+L3·i1)·～c；

s1＝(L0·i0+L1·i3+L2·i2+L3·i1)·c。

fig. 2 (b) is a logic diagram thereof.

The logical expressions shown by the numbers 2, 5, 12, 15 (second part) are (fig. 2 (c) is a logical diagram thereof):

g1(2)＝L2·i3+L3·i2；

s1＝(L0·i1+L1·i0+L2·i3+L3·i2)·～c；

s2＝(L0·i1+L1·i0+L2·i3+L3·i2)·c。

the logical expressions shown by the numbers 3, 6, 9, 16 (third part) are (fig. 3 (a) is a logical diagram thereof):

g1(3)＝L3·i3；

s1＝(L0·i2+L1·i1+L2·i0+L3·i3)·～c；

s2＝(L0·i2+L1·i1+L2·i0+L3·i3)·c。

the logical expressions shown by the numbers 4, 7, 10, 13 (fourth part) are (the logical diagram of which is left in fig. 3 b):

s3＝(L0·i3+L1·i2+L2·i1+L3·i0)·～c；

s0＝(L0·i3+L1·i2+L2·i1+L3·i0)·c；

p＝L0·i3+L1·i2+L2·i1+L3·i0。

fig. 3 (b) shows the right side of the graph for generating a logic diagram for G (and P), g=1 when any bit of the outputs G1 (1), G1 (2), G1 (3) is 1 (at most, only 1 bit), showing that the carry forward state is 1; on the contrary, if the outputs of G1 (1), G1 (2) and G1 (3) are all Z (high resistance), g=0 is obtained through the active schmitt logic gate, and the forward carry state is 0.P is implemented in the same principle as G.

The resulting si (i=3, 2, 1, 0) of these four parts is subjected to active schmitt logic gate to find the corresponding logic value (0 or 1), see fig. 2 (a), by which the gates of the cmos transistors (1, 2,3, 4) are controlled, while the drains are at the voltages of the corresponding standard, the local multi-value logic "and" S "of the variable a+b will be produced, see fig. 3 (c). The result is a two-variable multi-value full adder, called 1-site full adder, whose general profile is fig. 3 (d), where ci-1 is the carry value of the post-site to the present site.

4.4 bit-point adder

The four full adders are divided into 1 group, the group is carried out with pi and gi as conditions, and single-chain push-pull carry is adopted between groups with Pj and Gj as conditions.

Basic components: two-pipe select gate (tri-state), see fig. 4 (a).

ck is a selection signal, di is input data, do is output data, the realization logic is shown in table 3, and the right graph is a simplified graph.

Table 3 select gate specification

Ck	～Ck	di	TP	TN	do
						0	1	1	Stop for vehicle	Stop for vehicle	High resistance
0	1	0	Stop for vehicle	Stop for vehicle	High resistance
						1	0	1	General purpose medicine	Stop for vehicle	1
1	0	0	Stop for vehicle	General purpose medicine	0

Four-pipe gate (tri-state) is composed of two selection gates, see fig. 4 (b) (the right drawing is a simplified drawing).

When (ck=1, -ck=0) the upper select gate is gated and the lower select gate is stopped. In the mode of operation of fig. 4 (a), D1 is passed to D; when (ck=0, -ck=1) the lower select gate is gated and the upper select gate is stopped, D2 passes to D.

1 bit full adder carry principle:

see fig. 4 (c), where the lower graph is its corresponding full adder, when pi=1, the lower select gate is opened, passing the carry state ci-1 of the latter bit to the forward bit, where ci=ci-1; when pi=0, the select gate is turned on, passing the present bit carry state gi to the forward bit, where ci=gi.

4-site adder and carry principle:

the 4-bit full adder was connected as described above for carry to get a 4-bit single-chain carry adder and inter-group carry line, see figure 5. Wherein a 4-1 and b 4-1 are addend and summand, and S4-1 is addition sum; cin (c 0) is the carry state of the back group to the group, c 3-1 is the carry state generated in the group, and cout is the carry state of the group to the front group.

The logical formula of the carry among groups is given by the carry logical formula of 4 sites in the group, and the group generates P and G among groups, wherein the logical formula is as follows:

P＝p4·p3·p2·p1；

G＝g4+g3·p4+g2·p4·p3+g1·p4·p3·p2。

to increase the parallel operation speed, the bin signal is used to control the BJT (BiCMOS) to realize the logical push-pull carry, see fig. 5, top left.

When p=1, the group does not generate a carry state, and the tri-state gate (original No. 1) is controlled to be closed (output is high resistance) G and does not enter the carry chain. At the same time, P controls T1 and T2 to turn on, if cin=1, T3 is turned on, T4 is turned off, and the T3 emitter outputs V3 to cout, cout=1. When cin is 0, the sum output of T3 and T4 is 0, T3T4 forms a logic push-pull carry, and the time delay of 1 BJT tube when 0 and 1 are switched and transferred. So that cin completes the forward group carry-out, i.e., cout=cin.

When p=0, the group of bits can receive the carry state of the latter bit, while the forward carry state of the group is determined by G. P controls T1 and T2, then T3 and T4 are stopped, and the emitter of T3 and the collector output of T4 are both high-resistance. At this point the tri-state gate (original No. 1) is open, delivering the G input link then cout=g to the front group.

Because carry and addition operation are simultaneously realized in parallel in each group, and inter-group carry is realized in series, the carry mode is critical to the operation speed of the whole adder, and the logic push-pull carry solves two key problems, namely, the speed is increased to reach the extreme speed, namely, the time delay of 1 BTJ tube is not compared with that of other methods; the output of each stage is a standard logic value provided by T1 or T2, and the logic swing is not reduced, no matter how many groups are connected in series. The logic swing is decreased and distorted when the number of groups is increased by adopting the logic switch, the transmission gate and other elements.

In the case of low speed requirements, another parallel carry mode may be used, i.e. 1 tri-state gate is used instead of T1, T2, T3, T4.Cin is connected to the input of the gate, the output of the gate is connected to Cout, and P is connected to the control of the gate. The structure is simple, but the carry speed is far lower than that of the former.

5.64 site adder

The 4-site adder composed of FIG. 5 is taken as a unit, and 16 units are connected in series to obtain the 64-site adder, which is equivalent to a 128-bit binary adder, as shown in FIG. 6. Similarly, adders with wider bits can be formed by the concatenation method. The working procedure is described in example 1.

6. Access and transmission of multiple-valued variables

The logic circuit in fig. 1 is simplified correspondingly to obtain a fidelity logic circuit of the multi-valued variable, see fig. 7 (a) (the lower right is a simplified diagram). Wherein the original numbers 1 and 3 are shown in fig. 1 (b) and (c), the original number 2 is shown in fig. 1 (a), the principle thereof is shown in the relevant description of fig. 1, and only the driving part will be described herein.

When di=2, 3, point B is 0 (b=0), and c=0. C=0 makes m6 stop its output high-impedance, with no effect on do. And b=0 makes m5 have a high resistance, and does not act on do even if two driving pipes m6 and m5 have no output.

In this case, if di=3, point a is 0 (a=0), and m1 is given the general rule of do=v3, which is the range of the multi-value logic 3. Meanwhile, the point E of the m2 stop is high-resistance, so that the driving of m3 by B=0 has no effect; conversely, if di=2, a=1, m1 is stopped, m2 is on, point E is V2, b=0 drives m3 to do=v2, if a=3, do=v3, and if a=2, do=v2.

When di=1, 0, point B is 1 (b=1), and a=1. A=1 indicates that the output is high-impedance, and b=0 indicates that the output is high-impedance, and does not affect do even if the two driving pipes m1 and m3 do not output.

At this time, if di=0, c=1, and m6 is set to do=0v, which is the range of the multi-value logical 0. Meanwhile, C=1 makes m4 stop point F be high resistance, so that B=1 drives m5 to have no effect; conversely, if di=1, c=0, m6 is stopped, m4 is on, F is V1, b=1 drives m5 to do=v1, if a=0, do=0v, and if a=1, do=v1.

In accordance with the above, table 4 is presented wherein the critical tube, italic for driving standard voltage, is turned on, "Z on" shows that the tube is turned on but its drain is high-resistance, and is not actually turned on.

TABLE 4 Voltage fidelity logic specification

The function of the fidelity circuit is to make the deviation of the variable in the register and the standard voltage value be about 0.2V (saturation voltage drop of one tube), so that the variable transmission and resolution are accurate. And the voltage fidelity logic is used for realizing the storage, the fetch and the transmission of the multi-valued variable. Fig. 7 (b) (below is a simplified diagram) shows a schematic diagram, in which elements 1, 2, and 3 are transmission gates, and the working process is shown in table 5.

TABLE 5 Access to multiple-valued variables

(symbol)

Cpi

Cpo

1

2

3

a

Input (open)

H

L

Opening device

Switch for closing

dio- & gt a (storing)

Input (final)

L

Switch for closing

Opening device

Switch for closing

Hold a

Output (Start)

L

H

Switch for closing

Opening device

a- & gt dio (taking out)

Output (final)

L

Switch for closing

Opening device

Switch for closing

Hold a

TABLE 5

It is essentially a multi-value register comprising bus inputs, outputs, from which the aforementioned multi-value variables a, b are taken, and into which the sum S obtained by addition is stored. The corresponding large-capacity memory unit (RAM) can be designed according to its principle. 4-ary adder implementing example 132 site

Mainly for the purpose of illustrating the principle, a 32-bit (4-ary) adder is used as an implementation example, and the computing power of the adder is the same as that of a 64-bit 2-ary adder. The unit logic diagram is i block in fig. 6, and the 16 unit logic diagrams are connected in series to obtain a total logic diagram, see fig. 8. Is provided with

a＝(30101113123112131231031223203220) _{Fourth, fourth} ；

b＝(03232220211111032120212110230122) _{Fourth, fourth} ;

c0 =1 (binary "1").

The calculation steps of the examples are shown in Table 6.

Table 6 calculation procedure

i	z8	32	31	30	29	z7	28	27	26	25	z6	24	23	22	21	z5	20	19	18	17
																						ai		3	0	1	0		1	1	1	3		1	2	3	1		1	2	1	3
bi		0	3	2	3		2	2	2	0		2	1	1	1		1	1	0	3
																						Pi	1	1	1	1	1	1	1	1	1	1	0	1	1	0	0	0	0	1	0	0
Gi	1←	*	*	*	*	*	*	*	*	*	1	*	*	1	0	0	0	*	0	1
																						Si		0	0	0	0		0	0	0	0		0	0	0	2		2	3	2	3
i	z4	16	15	14	13	z3	12	11	10	9	z2	8	7	6	5	z1	4	3	2	1	c0
																						ai		1	2	3	1		0	3	1	2		2	3	2	0		3	2	2	0
bi		2	1	2	0		2	1	2	1		1	0	2	3		0	1	2	2
																						Pi	0	1	1	0	0	0	0	0	1	1	0	1	1	0	1	0	1	1	0	0
Gi	1	*	*	1	0	0	0	1	*	*	1	*	*	1	*	1	*	*	1	0	1
																						Si		0	0	1	1		3	1	0	0		0	0	1	0		0	0	0	3

In table 6, i represents the site number (32, 31, …,2, 1) and the group number (z 8, z7, …, z 1) of the packet, pi, gi respectively represent the transfer function (P), the carry generation function (G), the site represented by the corresponding sequence number is the Pi, gi state of the site, and the corresponding group number is the P, G state of the group; ai. bi and Si are summands, summands and sums respectively and correspond to sequence numbers one by one. To distinguish the carry state, the carry state of the post-position is symbolized as forward position.

The inter-group generation demarcation is determined by Pi (Pi equals p1.p2.p3.p4) corresponding to zi (i=1 to 8), pi=0 (z 1 to 6) will generate 1 carry demarcation point, and the forward group carry is determined by the Gi state of the group; pi=1 (z 7, z 8) does not generate a carry demarcation point and the Gi state of the back group continues to be forwarded. Gi is x denotes that the carry state of the post-site (or post-group) continues to be forwarded.

The actual sum arithmetic logic formula may be defined as si= ((ai+bi) MOD (4) +g (i-1)) MOD (4) (implemented by hardware logic, see fig. 2,3 for implementation principles), where 1 st MOD (4) represents the carry-out (the carry-out has been given by the line), and 2 nd MOD (4) represents the sum-out and the remainder-only (the remainder is given by the line).

For example, 1:

a17 =3, b17=3, (a17+b17) MOD (4) =6mod (4) =2, g17=1 (carry in this position),

s17= ((a17+b17) MOD (4) +g16=2+ +) MOD (4), where (G16) is the carry generated by G14 (with value 1) and is further uploaded to the carry chain after the group carry z4 is entered, so s17= (2+1) MOD (4) =3.

For example 2:

a29 =0, b29=3, (a29+b29) MOD (4) =3mod (4) =3, p29=1, g29= (the carry state of G28 is passed to G30),

s29= ((a29+b29) MOD (4) +g28) MOD (4) = (3+) MOD (4) = (4) MOD (4) = 0, where the carry state generated by G22 (value 1) is passed into the carry chain by group carry z6 and then further up-loaded by group carry z 7.

For example 3:

pi= (p32.p31.p30.p29) =1 for z8, indicating that the present group p=1, gi= (1≡) indicates that the value generated by z6 is 1 and proceeds to the front, i.e. the highest carry C64 (binary logic "1") of the present calculation is obtained.

Referring to the calculation process of table 6, the calculated value at this time is:

S＝(10000 0000 0002 2323 0011 3100 0010 0003) _{fourth, fourth} 。

Performance comparison

The main data of the present invention and a typical chip (CD 40181) are shown in Table 7.

TABLE 7 Main Properties

Critical delay (time delay to generate G and into the carry chain),

the invention comprises the following steps:

gi for one site is the maximum 3 pipe delay required to generate L and i from FIG. 1 (y, L3, L0 from register extraction); g1 (1), g1 (2) and g1 (3) are respectively generated in parallel by L and i (fig. 2 (b) and fig. 3 (a)), and 3 pipe delays are respectively generated in parallel (only one logic formula is needed to be calculated); 2 pipe delays are needed for generating the original position G (shown in fig. 2 (a) and 3 (b)) by G1 (1), G1 (2) and G1 (3) in parallel respectively;

the four bits within the group produce a group carry (carry part of fig. 5) G for a total of 5 pipe delays.

Inter-group carry delay;

inter-group carry delay (upper left of fig. 5) 1 BJT tube delay.

The total of 14 pipe delays.

Typical application:

4-bit addition generation5 pipe delays are required;

4+3=7 tube delays are required to produce g=g4+g3.p4+g2.p4.p3+g1.p4.p3.p2;

the inter-group carry of two groups (8 bits) requires 2 to be implemented with 2 entries and 2×2=4 pipe delays.

The total of 16 pipe delays is described above.

Table 8 was compared according to the parameters described above and in table 7.

Table 8 comparison conclusion

As shown in Table 8, the present invention has a slightly smaller logic swing when the power source type is used for the multi-purpose 2 kinds of the power source type, the transmission and addition operation is preceded by the resolution, and the parameters of the power source type, such as the amount of the power source used, the carry delay in the group, the carry delay between groups, the number of bits of the 128 bit (binary) adder, etc. are all better than those of the typical application, especially the latter two, the present invention has the advantages that the number of bits is reduced by 1 time compared with the typical application, the corresponding bus, the control and the memory are also reduced by 1 time, and the carry speed is improved by at least 4 times (the delay difference between the BJT tube and the MOS tube is not counted). In addition, the carry mode of the invention can be linearly connected in series, and the carry delay of only 1 BJT tube is increased when an 8-bit (binary meter) adder is added.

Claims

1. The method is characterized in that the method for generating the multi-value logic, accessing and converting the voltage value in a fidelity way and the method for simplifying the state logic based on the addition of 4 sites into 1 group and realizing the wide-bit high-speed adder formed by 16 groups of push-pull carry are described based on four-value logic: wherein,

the voltage value of a site is divided into different grades of V0 domains, V1 domains, V2 domains, V3 domains, … domains and Vn domains by utilizing a wide voltage space and a low threshold in a CMOS circuit, the voltage value can be correspondingly expressed as different values of 0, 1, 2,3, … and n, the variable of the voltage value is accessed in a potential mode in a fidelity way, the voltage value conversion is realized by directly converting the variable of the voltage value into a right two-value logic value through a fidelity resolution circuit, the voltage value fidelity access and conversion are respectively realized by adopting an improved schmitt circuit, and the voltage value domain can be correspondingly expanded and reduced according to a range given by a power supply to carry out voltage value fidelity access and conversion so as to realize multi-value logic processing of different value domain ranges;

the state logic simplification of the 4-locus addition 1 group takes high resistance as a logic state to participate in simplification and transfer, and the high resistance is converted into logic 0 by using active threshold operation only at a state logic terminal point, so that AND operation can be realized by using a single tube, OR operation can be realized by using a single tube, the method can be commonly used in MOS logic circuits according to the state logic simplification principle, a single-chain gating carry is adopted in a wide-bit high-speed adder group consisting of 16 groups of push-pull carry, and single-chain logic push-pull carry is adopted among groups, so that the adder circuit is concise and easy to linearly expand bits and high speed.

2. The multi-value logic wide-bit high-speed adder according to claim 1, wherein a plurality of values are expressed by using a voltage space, and the voltage values are divided into different grades Vi, wherein v0=0 to 1V, v1=1 to 2V, v2=3 to 5V, v3=4 to 5V, and one bit voltage value variable a can be a value range of one of the voltage values, and is denoted as a= (0, 1, 2, 3).

3. The multi-value logic wide-bit high-speed adder according to claim 1, wherein the threshold value is symmetrically set by utilizing the symmetrical relation of the CMOS to ensure accurate resolution, one bit voltage value variable a is set, the demarcation between (3, 2) and (0, 1) is realized by using a voltage-controlled schmitt gate pair a with the VDD of 4V, the accurate resolution of a=3 and a=0 is respectively realized by using two asymmetrical schmitt gates, the corresponding standard voltage is driven by the resolution value, and a voltage fidelity access circuit is formed together with a transmission gate, so that the registering of the value a and the bus input and output are realized.

4. The multi-value logic wide-bit high-speed adder according to claim 1, wherein the direct conversion voltage value variable is not needed to be decoded, a bit voltage value variable a is set, and the corresponding weighted binary logic value Li of a can be directly converted into the corresponding weighted binary logic value Li of a because the corresponding fidelity resolution logic circuit exists in the register of the register a, the subscript indicates the weight of the value, and each weighted value is represented by 0, 1 binary logic and has become a direct logic value relation (0, 1, 2, 3).

5. The multi-value logic wide-bit high-speed adder according to claim 1, wherein the high-resistance participation logic reduction and transfer make logic circuits compact and low in power consumption, two bit point voltage value variables a and b are set, a weighted binary logic value Li is converted from a register thereof, a truth table is listed corresponding to an addition formula of L3-0, pi, gi and addition and si are obtained by state logic reduction, logic ' AND ' in the state logic reduction is realized by a single CMOS tube, logic ' or ' single line ' is realized, the high-resistance is used as a logic state participation reduction, and the high-resistance is converted into logic ' 0 ' by an active schmitt gate only at a logic formula end point, thereby obtaining a full adder a+b of one site.

6. The multi-value logic wide-bit high-speed adder according to claim 1, wherein the logic circuit is simple, the carry value switching time delay is small, 8 bit voltage value variables ai+bi are set, wherein full adders of i=1, 2,3 and 4 are divided into 1 group, and according to pi and gi of the bit, a single-chain carry in the group is realized by adopting a gate; the Pi and Gi of the group adopt BICMOS to realize inter-group single-chain logic push-pull carry, i.e. 1 BJT transistor delay is used to forward the carry of the following group to the preceding group.

7. The multi-value logic wide-bit high-speed adder according to claim 1, wherein the linear expansion bit width and high-speed carry are carried by taking 4-bit adders as 1 unit, 8 and 16 … units are connected in series, wherein only one carry chain is used for obtaining the 32-64 … -bit wide-bit adder, which is equivalent to a binary 64-128 … -bit adder, and each time the 4-bit adder is added, which is equivalent to a binary 8-bit adder, the carry delay of only 1 BJT tube is added.