CN112782559A - AD chip testing device and testing method thereof - Google Patents
AD chip testing device and testing method thereof Download PDFInfo
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- CN112782559A CN112782559A CN202011638687.3A CN202011638687A CN112782559A CN 112782559 A CN112782559 A CN 112782559A CN 202011638687 A CN202011638687 A CN 202011638687A CN 112782559 A CN112782559 A CN 112782559A
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- 238000012360 testing method Methods 0.000 title claims abstract description 95
- 238000005259 measurement Methods 0.000 claims abstract description 78
- 238000012216 screening Methods 0.000 claims abstract description 23
- 238000006243 chemical reaction Methods 0.000 claims abstract description 20
- 238000005070 sampling Methods 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 12
- 238000003466 welding Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/01—Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass production; Testing objects at points as they pass through a testing station
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Abstract
The invention discloses an AD chip testing device and a testing method thereof, and aims to solve the technical problems that an AD chip in the prior art is low in testing efficiency, difficult to disassemble and assemble and easy to repeatedly test. It includes: outputting analog quantity signals with different frequencies and different amplitudes according to the control signals; controlling an AD chip to perform data conversion on the analog quantity signal to obtain a measurement analog quantity, and controlling the AD chip to obtain a null shift signal; and calculating chip measurement error and null shift value according to the analog quantity signal, the measurement analog quantity and the null shift signal, and screening the fault AD chip. The invention can automatically test the AD chip, has high test efficiency and high speed, and realizes the rapid and accurate screening of the AD chip.
Description
Technical Field
The invention relates to an AD chip testing device and a testing method thereof, belonging to the technical field of chip testing.
Background
AD7606 is an 8-channel synchronous AD chip, which has the advantages of low price, excellent performance, etc., and thus is widely used in the field of power applications. At present, a plurality of domestic manufacturers have produced AD chips which are completely compatible with AD7606 and can be used as a substitute for AD7606, but the domestic AD chips and the AD7606 have certain gap, and the performance parameter difference between different individuals is large, so that the AD chips must be screened to find the chips with relatively excellent performance. In addition, because the analog quantity acquisition function is very important, and the abnormal protection function can be caused by the occurrence of problems, the AD chip needs to be subjected to various tests before being used in batch, and the performance of the chip can meet the performance requirements of protection and automation devices.
The existing AD chip test system is to weld the AD chip on the PCB, and then directly test whether the performance of the device using the AD chip can meet the requirements of test specifications, and the test system has the following problems: 1. generally, each PCB can test a small number of AD chips, and the chip testing efficiency is low; 2. the chip is difficult to install and replace, the welding temperature of the chip is difficult to accurately control, poor welding or chip damage caused by overhigh temperature is easy to occur, the chip needs to be replaced after the test is finished, the replacement process is complex, and electrostatic damage can be caused in the replacement process; 3. the existing test mode is generally a whole-board test, once an AD chip is found to be unqualified, a failed AD needs to be taken down from a board, a new AD is replaced, then the whole board is tested again, repeated tests exist, time and labor are consumed, and the qualified chip is possibly abnormal due to multiple high-low temperature tests.
Disclosure of Invention
In order to solve the problems of low test efficiency, difficult chip disassembly and assembly and easy repeated test of the AD chip in the prior art, the invention provides the AD chip test device and the test method thereof.
In order to solve the technical problems, the invention adopts the following technical means:
in a first aspect, the present invention provides an AD chip testing apparatus, including a tester, a control terminal, a chip screening module, and at least one chip testing module, wherein:
the control terminal is used for outputting a control signal to the tester through the network port on one hand, and is used for collecting measurement data of the chip testing module through the switch on the other hand;
the tester is used for outputting analog quantity signals with different frequencies and different amplitudes according to the control signals;
the chip testing module is used for controlling the AD chip to perform data conversion on the analog quantity signal to obtain a measurement analog quantity and controlling the AD chip to obtain a null shift signal;
and the chip screening module is used for calculating chip measurement errors and zero drift values according to the analog quantity signals, the measurement analog quantity signals and the zero drift signals and screening the fault AD chips.
With reference to the first aspect, further, the chip testing module includes an IC socket, a chip controller, and a testing board, where the testing board is connected to the tester through a data line, the IC socket is mounted on the testing board, and an insertion opening of the IC socket is connected to the chip controller in parallel through the data line; the socket on the IC socket is used for installing an AD chip, and the chip controller is used for controlling the AD chip on the IC socket to perform data conversion, obtaining measurement analog quantity and controlling the AD chip to obtain a null shift signal.
With reference to the first aspect, further, a single-pole double-throw switch is disposed on the test board, a stationary end of the single-pole double-throw switch is connected to the IC socket, and a movable end of the single-pole double-throw switch is connected to the tester and the ground, respectively.
With reference to the first aspect, further, the chip controller employs a CPU or an FPGA.
With reference to the first aspect, further, the apparatus further includes an address configuration module, where the address configuration module is configured to set an internet access address of the chip testing module.
With reference to the first aspect, further, the method for screening the failed AD chip by the chip screening module includes:
taking the percentage of the difference value of the analog quantity signal and the measurement analog quantity in the analog quantity signal as the chip measurement error of the AD chip;
comparing the chip measurement error with an error threshold condition, and judging the AD chip as a fault chip when the chip measurement error does not meet the error threshold condition;
counting sampling points according to the zero drift signals to obtain a measurement histogram, and obtaining the zero drift value of each AD chip according to the measurement histogram;
and comparing the zero drift value with a zero drift threshold condition, and judging the AD chip as a fault chip when the zero drift value does not meet the zero drift threshold condition.
In a second aspect, the present invention provides an AD chip testing method, including the following steps:
generating analog quantity signals with different frequencies and different amplitudes according to the control signals;
respectively carrying out analog-to-digital conversion on the analog quantity signals by utilizing a plurality of AD chips to obtain the measurement analog quantity of each AD chip and obtain a null shift signal of each AD chip;
counting sampling points based on the measurement analog quantity, and carrying out Fourier transform on the sampling points to obtain a measurement effective value of each AD chip;
calculating the chip measurement error of each AD chip according to the analog quantity signal and the measurement effective value;
counting sampling points based on the zero drift signals to obtain a measurement histogram, and obtaining the zero drift value of each AD chip according to the measurement histogram;
and analyzing the chip measurement error and the null shift value according to a preset threshold condition, and screening the fault AD chip.
With reference to the second aspect, further, the method for obtaining the measurement analog quantity of the AD chip includes:
a plurality of AD chips are connected in parallel through an IC socket, and analog quantity signals are input to AIN pins of each AD chip;
outputting a conversion signal to the AD chips by using a chip controller, and controlling each AD chip to perform analog-to-digital conversion;
the BUSY signal of each AD chip is monitored in real time by the chip controller, and when the BUSY signal of the AD chip is converted from a high level to a low level, the chip controller reads the measurement analog quantity on the data line of the AD chip through a clock signal or a chip selection signal.
With reference to the second aspect, further, the chip measurement error is: the difference between the analog signal and the measured effective value is a percentage of the analog signal.
With reference to the second aspect, further, the preset threshold condition includes an error threshold condition and a null shift threshold condition;
the error threshold condition is: the measurement error of the chip is less than or equal to 0.1%;
the zero drift threshold condition is as follows: the number of sampling points of the zero drift signal is not less than 2000, the fluctuation value of the measured histogram is within plus or minus 5 codes, and the difference between the number of the sampling points with the sampling point values greater than 0 and the number of the sampling points with the sampling point values less than 0 is less than 50.
The following advantages can be obtained by adopting the technical means:
the invention provides an AD chip testing device and a testing method thereof.A tester is controlled by a control terminal to output analog quantity signals with different frequencies and amplitudes according to the precision requirements of different applications on an AD chip, so that the performance of the AD chip in a certain frequency and amplitude interval is tested in a targeted manner, the AD chip is rapidly screened according to the test result, the screened AD chip can meet the requirements of specific applications, and the measurement is more targeted.
In addition, the AD chip is directly inserted on the IC socket, so that the operations such as welding and the like are not needed, the AD chip is more convenient to disassemble and assemble, and the AD chip is not easy to damage in the disassembling and assembling process. The AD chip is connected to the chip controller through the data line, one line corresponds to one chip, and the control terminal can be directly positioned to the AD chip with a fault according to the line in the test process without repeatedly measuring the AD chip on the whole board.
Drawings
FIG. 1 is a schematic structural diagram of an AD chip testing device according to the present invention;
FIG. 2 is a block diagram of an AD chip testing apparatus according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating steps of an AD chip testing method according to the present invention.
In the figure, 1 is a tester, 2 is a control terminal, 3 is a chip screening module, 4 is a chip testing module, and 5 is an address configuration module.
Detailed Description
The technical scheme of the invention is further explained by combining the accompanying drawings as follows:
the invention provides an AD chip testing device, which mainly comprises a tester 1, a control terminal 2, a chip screening module 3 and at least one chip testing module 4, wherein one end of the tester and the output end of the chip testing module are respectively connected with the control terminal, the other end of the tester is connected with the input end of the chip testing module, and the control terminal is also connected with the chip testing module, as shown in figures 1 and 2.
The control terminal (such as PC) can generate a control signal according to the test requirement and output the control signal to the tester through the network port, the tester outputs analog quantity signals with different frequencies and different amplitudes to the chip test module according to the control signal, the chip test module is connected with a plurality of AD chips in parallel, the chip test module can add the analog quantity signals to the AD chips on one hand and control the AD chips to carry out data conversion on the analog quantity signals to obtain measurement analog quantity on the other hand, the chip test module can also control the AD chips to be grounded to further obtain a null shift signal, the control terminal collects the measurement data (the measurement analog quantity and the null shift signal) of the chip test module through the switch and outputs the measurement data to the chip screening module, the chip screening module calculates the measurement error and the null shift value of the chip according to the analog quantity signals, the measurement analog quantity and the null shift signal, and screening fault AD chips.
The chip testing module mainly comprises an IC socket, a chip controller and a testing board, wherein the IC socket adopts a 64-pin IC socket, and the chip controller can adopt a CPU or an FPGA. The IC socket is arranged on the test board and is electrically connected with the test board, and the socket on the IC socket is connected to the chip controller in parallel through a data line; the test board is provided with a single-pole double-throw switch, the immovable end of the single-pole double-throw switch is connected with the IC socket, the movable end of the single-pole double-throw switch is respectively connected with the tester and the ground through a data line, and the input of the chip test module can be changed by using the single-pole double-throw switch.
The socket on the IC socket is used for mounting the AD chip, and the AD chip is not directly welded on the bottom plate, so that the plugging and the replacement of the chip are more convenient and quicker, the mounting operation of the AD chip is simplified, and the AD chip is not easily damaged. The chip controller is used for controlling an AD chip on the IC socket to perform data conversion through various control signals to obtain measurement analog quantity, and controlling the AD chip to obtain a null shift signal, wherein the control signals comprise a conversion signal, a serial clock signal, a serial data signal, a BUSY signal (an AD chip BUSY signal), a chip selection signal and the like.
The working principle of the chip testing module is as follows: connecting a plurality of AD chips in parallel by using an IC socket, adding analog quantity signals with different frequencies and different amplitudes on an AIN pin of the AD chip through a single-pole double-throw switch, outputting a conversion signal by using a chip controller, setting a BUSY signal of the AD chip to be high level, starting to convert the analog quantity signals by the AD chip, monitoring the BUSY signal in real time by using the chip controller, indicating that the data conversion of the AD chip is finished when the BUSY signal is converted to be low level, outputting a serial clock signal or a chip selection signal by using the chip controller, reading a serial data signal on a data pin of the AD chip, and obtaining the measurement analog quantity of the AD chip; the AD chip is grounded by the single-pole double-throw switch, and the chip controller is used for controlling the AD chip to obtain a zero-drift signal. In addition, the chip controller can realize different sampling intervals by controlling the intervals of the conversion signals, thereby obtaining the measured values of a plurality of AD chips on the same analog quantity signal in a targeted manner, and facilitating the subsequent comparison of the performances of the AD chips.
The device also comprises an address configuration module 5, when a plurality of chip test modules exist in the device, the network port address of each chip test module can be set through the address configuration module, the chip test modules are distinguished through the network port addresses, and the parallel test of the plurality of chip test modules is realized.
In the embodiment of the invention, the method for screening the fault AD chip by the chip screening module comprises the following steps:
the percentage of the difference between the analog signal and the measured analog signal in the analog signal is used as the chip measurement error of the AD chip, i.e., = | analog signal-measured analog amount |/analog signal 100%.
Comparing the chip measurement error with an error threshold condition, and judging the AD chip as a fault chip when the chip measurement error does not meet the error threshold condition; the error threshold condition of the power application is generally as follows: the chip measurement error is less than or equal to 0.1%, and if the peculiar application is involved, the threshold condition can be adjusted according to the actual situation.
And counting 2000 sampling points according to the null shift signal to obtain a measurement histogram, checking the fluctuation value of the measurement histogram, and obtaining the null shift value of each AD chip according to the measurement histogram, namely the value of each AD chip sampling points in 2000 sampling.
Comparing the zero drift value with a zero drift threshold condition, and judging the AD chip as a fault chip when the zero drift value does not meet the zero drift threshold condition; wherein, the zero drift threshold condition is as follows: the fluctuation value of the measurement histogram is within plus or minus 5 codes, and the difference between the number of sampling points with the sampling point value greater than 0 and the number of sampling points with the sampling point value less than 0 is less than 50.
The invention also provides an AD chip testing method, as shown in FIG. 3, which mainly comprises the following steps:
step 1, generating analog quantity signals with different frequencies and different amplitudes according to the control signals, wherein the control terminal can generate different control signals according to the precision requirements of different applications/scenes on the AD chip, and then controlling the tester to generate different analog quantity signals by using the control signals.
Step 2, respectively carrying out analog-to-digital conversion on the analog quantity signals by utilizing a plurality of AD chips to obtain the measurement analog quantity of each AD chip and obtain a null shift signal of each AD chip, wherein the specific operation is as follows:
step 201, connecting a plurality of AD chips in parallel through an IC socket, and inputting an analog quantity signal for an AIN pin of each AD chip;
step 202, outputting a conversion signal to the AD chips by using a chip controller, and controlling each AD chip to perform analog-to-digital conversion on the analog quantity signal;
step 203, monitoring the BUSY signal of each AD chip in real time by using a chip controller, and reading the measurement analog quantity on the data line of the AD chip by the chip controller through a clock signal or a chip selection signal when the BUSY signal of the AD chip is converted from a high level to a low level;
and step 204, grounding the input of the AD chips on the IC socket by using the single-pole double-throw switch, and obtaining a zero-drift signal of each AD chip.
And 3, counting sampling points based on the measurement analog quantity, and carrying out Fourier transform on the sampling points to obtain a measurement effective value of each AD chip.
And 4, calculating the chip measurement error of each AD chip according to the analog quantity signal and the measurement effective value, namely calculating the percentage of the difference value of the analog quantity signal and the measurement effective value in the analog quantity signal.
And 5, counting sampling points based on the null shift signals to obtain a measurement histogram, and obtaining the null shift value of each AD chip according to the measurement histogram.
And 6, analyzing chip measurement errors and a zero drift value according to a preset threshold condition, and screening the fault AD chip.
And when the chip measurement error or the zero drift value does not meet the threshold condition, determining that the AD chip is in fault or unqualified. The threshold condition comprises an error threshold condition and a zero drift threshold condition, wherein the error threshold condition is as follows: the measurement error of the chip is less than or equal to 0.1%; the zero drift threshold condition is as follows: the number of sampling points of the zero drift signal is not less than 2000, the fluctuation value of the measured histogram is within plus or minus 5 codes, and the difference between the number of the sampling points with the sampling point values greater than 0 and the number of the sampling points with the sampling point values less than 0 is less than 50.
Compared with the prior art, the invention can test a large number of AD chips at the same time, has high test efficiency and high speed, can generate analog quantity signals according to specific requirements in the test process, and further pointedly test the performance of the AD chips in a certain frequency and amplitude interval, can directly position the specific chips after the test, thereby realizing the rapid chip screening, and can conveniently take down the fault chips after the fault chips are found because the AD chips are connected with the test board through the IC socket. The invention provides automatic testing and screening functions of the AD chip.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. The utility model provides a AD chip testing arrangement which characterized in that, includes tester, control terminal, chip screening module and at least one chip test module, wherein:
the control terminal is used for outputting a control signal to the tester through the network port on one hand, and is used for collecting measurement data of the chip testing module through the switch on the other hand;
the tester is used for outputting analog quantity signals with different frequencies and different amplitudes according to the control signals;
the chip testing module is used for controlling the AD chip to perform data conversion on the analog quantity signal to obtain a measurement analog quantity and controlling the AD chip to obtain a null shift signal;
and the chip screening module is used for calculating chip measurement errors and zero drift values according to the analog quantity signals, the measurement analog quantity signals and the zero drift signals and screening the fault AD chips.
2. The AD chip testing device of claim 1, wherein the chip testing module comprises an IC socket, a chip controller and a testing board, the testing board is connected with the tester through a data line, the IC socket is mounted on the testing board, and a socket on the IC socket is connected to the chip controller in parallel through the data line; the socket on the IC socket is used for installing an AD chip, and the chip controller is used for controlling the AD chip on the IC socket to perform data conversion, obtaining measurement analog quantity and controlling the AD chip to obtain a null shift signal.
3. The device for testing the AD chip of claim 2, wherein a single-pole double-throw switch is arranged on the test board, the fixed end of the single-pole double-throw switch is connected with an IC socket, and the movable end of the single-pole double-throw switch is respectively connected with the tester and the ground.
4. The AD chip testing device of claim 2, wherein the chip controller is a CPU or an FPGA.
5. The device of claim 1, further comprising an address configuration module, wherein the address configuration module is configured to set an internet access address of the chip testing module.
6. The AD chip testing device of claim 1, wherein the method for the chip screening module to screen the fault AD chip is as follows:
taking the percentage of the difference value of the analog quantity signal and the measurement analog quantity in the analog quantity signal as the chip measurement error of the AD chip;
comparing the chip measurement error with an error threshold condition, and judging the AD chip as a fault chip when the chip measurement error does not meet the error threshold condition;
counting sampling points according to the zero drift signals to obtain a measurement histogram, and obtaining the zero drift value of each AD chip according to the measurement histogram;
and comparing the zero drift value with a zero drift threshold condition, and judging the AD chip as a fault chip when the zero drift value does not meet the zero drift threshold condition.
7. An AD chip testing method is characterized by comprising the following steps:
generating analog quantity signals with different frequencies and different amplitudes according to the control signals;
respectively carrying out analog-to-digital conversion on the analog quantity signals by utilizing a plurality of AD chips to obtain the measurement analog quantity of each AD chip and obtain a null shift signal of each AD chip;
counting sampling points based on the measurement analog quantity, and carrying out Fourier transform on the sampling points to obtain a measurement effective value of each AD chip;
calculating the chip measurement error of each AD chip according to the analog quantity signal and the measurement effective value;
counting sampling points based on the zero drift signals to obtain a measurement histogram, and obtaining the zero drift value of each AD chip according to the measurement histogram;
and analyzing the chip measurement error and the null shift value according to a preset threshold condition, and screening the fault AD chip.
8. The method for testing the AD chip as claimed in claim 7, wherein the method for obtaining the measurement analog quantity of the AD chip comprises:
a plurality of AD chips are connected in parallel through an IC socket, and analog quantity signals are input to AIN pins of each AD chip;
outputting a conversion signal to the AD chips by using a chip controller, and controlling each AD chip to perform analog-to-digital conversion;
the BUSY signal of each AD chip is monitored in real time by the chip controller, and when the BUSY signal of the AD chip is converted from a high level to a low level, the chip controller reads the measurement analog quantity on the data line of the AD chip through a clock signal or a chip selection signal.
9. The AD chip testing method of claim 7, wherein the chip measurement error is: the difference between the analog signal and the measured effective value is a percentage of the analog signal.
10. The method according to claim 7, wherein the predetermined threshold condition comprises an error threshold condition and a null shift threshold condition;
the error threshold condition is: the measurement error of the chip is less than or equal to 0.1%;
the zero drift threshold condition is as follows: the number of sampling points of the zero drift signal is not less than 2000, the fluctuation value of the measured histogram is within plus or minus 5 codes, and the difference between the number of the sampling points with the sampling point values greater than 0 and the number of the sampling points with the sampling point values less than 0 is less than 50.
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| CN114791557A (en) * | 2022-04-21 | 2022-07-26 | 杭州三海电子有限公司 | High and low temperature test method for integrated circuit |
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Application publication date: 20210511 |