CN112771546A - 运算加速器和压缩方法 - Google Patents

运算加速器和压缩方法 Download PDF

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CN112771546A
CN112771546A CN201880098124.4A CN201880098124A CN112771546A CN 112771546 A CN112771546 A CN 112771546A CN 201880098124 A CN201880098124 A CN 201880098124A CN 112771546 A CN112771546 A CN 112771546A
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calculation result
compression
accelerator
data
control instruction
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CN201880098124.4A
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刘保庆
刘虎
陈清龙
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/60—General implementation details not specific to a particular type of compression
    • H03M7/6047—Power optimization with respect to the encoder, decoder, storage or transmission
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3059—Digital compression and data reduction techniques where the original information is represented by a subset or similar information, e.g. lossy compression
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/60—General implementation details not specific to a particular type of compression
    • H03M7/6017—Methods or arrangements to increase the throughput
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/048—Activation functions
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/70—Type of the data to be coded, other than image and sound

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
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  • Computational Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
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  • General Health & Medical Sciences (AREA)
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  • Computational Linguistics (AREA)
  • Artificial Intelligence (AREA)
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Abstract

本申请公开了一种运算加速器,该运算加速器包括：第一缓存，用于存储第一输入数据；第二缓存，用于存储权重数据；与该输入缓存和该权重缓存连接的运算电路，用于对第一输入数据和该权重数据进行矩阵乘运算以得到计算结果；压缩模块，用于对该计算结果进行压缩以得到压缩数据；与该压缩模块连接的直接存储器访问控制器DMAC，用于将该压缩数据存入到该运算加速器之外的存储器。由于在该运算加速器中增加了压缩模块，降低了从该运算加速器中搬运计算结果到存储器的数据量，节省该运算加速器的I/O带宽，提升该运算加速器的计算性能。

Description

PCT国内申请，说明书已公开。

Claims (24)

  1. PCT国内申请，权利要求书已公开。
CN201880098124.4A 2018-09-30 2018-09-30 运算加速器和压缩方法 Pending CN112771546A (zh)

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PCT/CN2018/109117 WO2020062252A1 (zh) 2018-09-30 2018-09-30 运算加速器和压缩方法

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CN112771546A true CN112771546A (zh) 2021-05-07

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US (1) US11960421B2 (zh)
EP (1) EP3852015A4 (zh)
CN (1) CN112771546A (zh)
WO (1) WO2020062252A1 (zh)

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US11507831B2 (en) * 2020-02-24 2022-11-22 Stmicroelectronics International N.V. Pooling unit for deep learning acceleration
KR102383962B1 (ko) * 2020-11-19 2022-04-07 한국전자기술연구원 가변 데이터 압축/복원기를 포함하는 딥러닝 가속 장치
CN112559043A (zh) * 2020-12-23 2021-03-26 苏州易行电子科技有限公司 一种轻量级人工智能加速模块

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DE102004004796B4 (de) * 2004-01-30 2007-11-29 Infineon Technologies Ag Vorrichtung zur Datenübertragung zwischen Speichern
JP2007226615A (ja) * 2006-02-24 2007-09-06 Matsushita Electric Ind Co Ltd 情報処理装置、圧縮プログラム生成方法及び情報処理システム
US9153230B2 (en) * 2012-10-23 2015-10-06 Google Inc. Mobile speech recognition hardware accelerator
US10540588B2 (en) * 2015-06-29 2020-01-21 Microsoft Technology Licensing, Llc Deep neural network processing on hardware accelerators with stacked memory
CN106954002B (zh) * 2016-01-07 2019-03-26 深圳市汇顶科技股份有限公司 一种指纹数据的压缩方法及装置
US10733505B2 (en) * 2016-11-10 2020-08-04 Google Llc Performing kernel striding in hardware
US10096134B2 (en) * 2017-02-01 2018-10-09 Nvidia Corporation Data compaction and memory bandwidth reduction for sparse neural networks
CN107341544B (zh) * 2017-06-30 2020-04-10 清华大学 一种基于可分割阵列的可重构加速器及其实现方法
US20190228037A1 (en) * 2017-08-19 2019-07-25 Wave Computing, Inc. Checkpointing data flow graph computation for machine learning
CN108416434B (zh) * 2018-02-07 2021-06-04 复旦大学 针对神经网络的卷积层与全连接层进行加速的电路结构
US10846363B2 (en) * 2018-11-19 2020-11-24 Microsoft Technology Licensing, Llc Compression-encoding scheduled inputs for matrix computations

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WO2020062252A1 (zh) 2020-04-02
US20210216483A1 (en) 2021-07-15
US11960421B2 (en) 2024-04-16
EP3852015A4 (en) 2021-09-01
EP3852015A1 (en) 2021-07-21

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