CN112768419A - Semiconductor device package - Google Patents

Semiconductor device package Download PDF

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Publication number
CN112768419A
CN112768419A CN202110122303.0A CN202110122303A CN112768419A CN 112768419 A CN112768419 A CN 112768419A CN 202110122303 A CN202110122303 A CN 202110122303A CN 112768419 A CN112768419 A CN 112768419A
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CN
China
Prior art keywords
layer
substrate
nitride semiconductor
device package
semiconductor device
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Pending
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CN202110122303.0A
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Chinese (zh)
Inventor
沈竞宇
赵起越
周春华
杨超
高吴昊
石瑜
魏宝利
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Innoscience Suzhou Semiconductor Co Ltd
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Innoscience Suzhou Semiconductor Co Ltd
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Priority to CN202110122303.0A priority Critical patent/CN112768419A/en
Publication of CN112768419A publication Critical patent/CN112768419A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3738—Semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate, a heat conduction structure, a first nitride semiconductor layer, and a second nitride semiconductor layer. The substrate has a first surface and a second surface opposite to the first surface. The heat conducting structure is disposed on the second surface of the substrate, wherein the heat conducting structure has a plurality of fins, each of the plurality of fins extending from the second surface of the substrate toward the first surface. The first nitride semiconductor layer is disposed on the heat conductive structure. The second nitride semiconductor layer is provided on the first nitride semiconductor layer and has a band gap larger than that of the first nitride semiconductor layer.

Description

Semiconductor device package
Technical Field
The present disclosure relates to a semiconductor device package, and more particularly, to a semiconductor device package including two-dimensional material (two-dimensional material).
Background
Components comprising direct gap semiconductors, such as semiconductor components comprising III-V materials or III-V compounds (class: III-V compounds), may operate or operate under various conditions or in various environments (e.g., at different voltages and frequencies).
The semiconductor device may include a Heterojunction Bipolar Transistor (HBT), a Heterojunction Field Effect Transistor (HFET), a high-electron-mobility transistor (HEMT), a modulation-doped field effect transistor (MODFET), and the like.
Disclosure of Invention
According to some embodiments of the present disclosure, a semiconductor device package includes a substrate, a heat conduction structure, a first nitride semiconductor layer, and a second nitride semiconductor layer. The substrate has a first surface and a second surface opposite to the first surface. The heat conducting structure is disposed on the second surface of the substrate, wherein the heat conducting structure has a plurality of fins, each of the plurality of fins extending from the second surface of the substrate toward the first surface. The first nitride semiconductor layer is disposed on the heat conductive structure. The second nitride semiconductor layer is provided on the first nitride semiconductor layer and has a band gap larger than that of the first nitride semiconductor layer.
According to some embodiments of the present disclosure, a semiconductor device package includes a substrate, a heat conduction structure, a first nitride semiconductor layer, and a second nitride semiconductor layer. The substrate has a first surface and a second surface opposite to the first surface. A thermally conductive structure is disposed on the second surface of the substrate. The heat conduction structure is provided with a main body part and at least one protruding part. The protruding portion penetrates through the substrate. The first nitride semiconductor layer is disposed on the main body portion of the heat conduction structure. The second nitride semiconductor layer is provided on the first nitride semiconductor layer and has a band gap larger than that of the first nitride semiconductor layer.
According to some embodiments of the present disclosure, a semiconductor device package includes a substrate, a heat conduction structure, a first nitride semiconductor layer, a second nitride semiconductor layer, and a two-dimensional material layer. The substrate has a first surface and a second surface opposite to the first surface. The heat conducting structure is disposed on the second surface of the substrate. The heat conduction structure is provided with at least one protruding part which penetrates through the substrate. The first nitride semiconductor layer is disposed on the heat conductive structure. The second nitride semiconductor layer is provided on the first nitride semiconductor layer and has a band gap larger than that of the first nitride semiconductor layer. The two-dimensional material layer is disposed on the first surface of the substrate. The two-dimensional material layer is in contact with the protruding portion of the heat conducting structure.
Drawings
Aspects of the present disclosure may be readily understood by the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.
Fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, and 2H illustrate various stages of a method for fabricating a semiconductor device package, according to some embodiments of the present disclosure.
Common reference numerals are used throughout the drawings and the detailed description to refer to the same or like components. The present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In the present disclosure, a reference to forming or disposing a first feature on or over a second feature may encompass embodiments in which the first and second features are formed or disposed in direct contact, and may also encompass embodiments in which additional features may be formed or disposed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Embodiments of the present disclosure are discussed in detail below. However, it should be appreciated that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.
The present disclosure provides a semiconductor device package. The semiconductor device package may include a two-dimensional material. The semiconductor device package may include a thermally conductive structure. The heat dissipation efficiency of the semiconductor device package of the present disclosure is relatively better than that of the previous semiconductor device package. The semiconductor device package of the present disclosure may be applied to, but is not limited to, HEMT devices, particularly low-voltage HEMT devices, high-voltage HEMT devices, and Radio Frequency (RF) HEMT devices.
Fig. 1 is a cross-sectional view of a semiconductor device package 1a according to some embodiments of the present disclosure.
The semiconductor device package 1a may include a substrate 100, a thermal conduction structure 110, a nitride semiconductor layer 120, a nitride semiconductor layer 130, a gate electrode 141, an electrode 142, an electrode 143, a dielectric layer 150, a conductive layer 161, a via 162, a passivation layer 170, a pad 180, a bump 190, a thermal conduction layer 200, and a thermal conduction layer 210.
Substrate 100 may include, but is not limited to, silicon (Si), doped Si, silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs), or other semiconductor materials. Substrate 100 may include, but is not limited to, sapphire, Silicon On Insulator (SOI), or other suitable material. The thickness of the substrate 100 may range from about 200 μm to about 400 μm, such as 220 μm, 240 μm, 260 μm, 280 μm, 300 μm, 320 μm, 340 μm, 360 μm, or 380 μm.
The substrate 100 may have a surface 100s1 and a surface 100s 2. The surface 100s2 may be opposite to the surface 100s 1. The surface 100s1 may be adjacent to the back surface (back surface) of the semiconductor device package 1 a. The surface 100s2 is closer to the active surface (active surface) of the semiconductor device package 1a than the surface 100s 1. In the present disclosure, the active surface may be defined closer to the metal layer than the back surface, such as the surface of the first metal layer (M1 layer), the second metal layer (M2 layer). The substrate 100 may include a plurality of openings. From a top view (not shown), the opening may have a circular, quadrilateral or other suitable profile. The width (or pore size) of the opening can be in the range of about 10 μm to about 100 μm, such as 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, or 90 μm.
The heat conduction structure 110 may be disposed on the surface 100s2 of the substrate 100. The heat conduction structure 110 may be in contact with the substrate 100. The thermally conductive structure 110 may comprise a thermally conductive material. The thermal conductivity of the thermal conduction structure 110 may be greater than that of the nitride semiconductor layer 120. The thermal conductivity of the thermally conductive structure 110 may be greater than the thermal conductivity of the substrate 100. The heat conductive structure 110 may include aluminum nitride (AlN). The heat conductive structure 110 may comprise aluminum gallium nitride (AlGaN). The heat conduction structure 110 may include aluminum indium gallium nitride (InAlGaN).
The heat conduction structure 110 may include a body portion 111 and a fin (or protrusion) 112. The material of the body portion 111 may be the same as that of the fin 112. The material of the body portion 111 may be different from that of the fin 112. The body portion 111 may cover the fin 112. The body portion 111 may completely cover the fin 112. The body portion 111 may serve as a buffer layer. The body portion 111 may be provided to reduce defects caused by lattice mismatch (lattice mismatch) between the substrate 100 and the nitride semiconductor layer 120. The body portion 111 may be located on the surface 100s 2. The body portion 111 may cover the surface 100s 2. The body portion 111 may completely cover the surface 100s 2. The thickness of the body portion 111 may range from about 10 μm to about 100 μm, such as 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, or 90 μm.
The heat conducting structure 110 may include at least one fin 112. The heat conducting structure 110 may include a plurality of fins 112. The fin 112 may extend from the surface 100s2 of the substrate 100 toward the surface 100s 1. The fin 112 may extend from the body portion 111 toward the surface 100s1 of the substrate 100. The fin 112 may fill the opening of the substrate 100. The fin 112 may be embedded in the substrate 100. The fin 112 may extend through the substrate 100. The thickness H of the fin 112 may range from about 200 μm to about 400 μm, such as 220 μm, 240 μm, 260 μm, 280 μm, 300 μm, 320 μm, 340 μm, 360 μm, or 380 μm. The cross-section of the fin 112 may be rectangular, trapezoidal, or other suitable profile. The width W (or diameter) of the fin 112 may range from about 10 μm to about 100 μm, such as 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, or 90 μm. The aspect ratio (e.g., the ratio of the thickness H to the width W of the fin 112) of the fin 112 may range from about 2 to about 10, such as 3, 4, 5, 6, 7, 8, or 9. The width (or diameter) of the fin 112 at the surface 100s2 may be substantially equal to the width (or diameter) at the surface 100s 1. The width (or diameter) of the fin 112 at the surface 100s2 may be greater than the width (or diameter) at the surface 100s 1. When the thickness H, width W (or diameter), or aspect ratio of the thermal conduction structure 110 is in the above range, the substrate 100 can bear the stress applied by the components above it (such as the dielectric layer 150 and the passivation layer 170) without cracking or generating cracks. When the thickness H, width W (or diameter) or aspect ratio of the thermal conduction structure 110 is in the above range, it has relatively better thermal conduction effect.
The nitride semiconductor layer 120 (or channel layer) may be disposed on the heat conduction structure 110. The nitride semiconductor layer 120 may be disposed on the body portion 111 of the thermal conduction structure 110. The nitride semiconductor layer 120 may include a group III-V layer. The nitride semiconductor layer 120 may include, but is not limited to, a group III nitride, such as compound InaAlbGa1-a-bN, where a + b ≦ 1. The group III nitride further includes, but is not limited to, for example, the compound AlaGa(1-a)N, where a ≦ 1. The nitride semiconductor layer 120 may include a gallium nitride (GaN) layer. The energy gap of GaN is about 3.4 eV. The thickness of the nitride semiconductor layer 120 may range from, but is not limited to, about 0.1 μm to about 1 μm.
The nitride semiconductor layer 130 (or the barrier layer) may be disposed on the nitride semiconductor layer 120. The nitride semiconductor layer 130 may include a group III-V layer. The nitride semiconductor layer 130 may include, but is not limited to, a group III nitride, such as compound InaAlbGa1-a-bN, where a + b ≦ 1. The group III nitride may further include, but is not limited to, for example, the compound AlaGa(1-a)N, where a ≦ 1. The energy gap of the nitride semiconductor layer 130 may be greater than that of the nitride semiconductor layer 120. The nitride semiconductor layer 130 may include an aluminum gallium nitride (AlGaN) layer. The energy gap of AlGaN is about 4.0 eV. The thickness of the nitride semiconductor layer 130 may range from, but is not limited to, about 10nm to about 100 nm.
A heterojunction is formed between the nitride semiconductor layer 130 and the nitride semiconductor layer 120, and polarization of the heterojunction forms a two-dimensional electron gas (2 DEG) region in the nitride semiconductor layer 120.
The gate electrode 141 may be disposed on the nitride semiconductor layer 130. The gate electrode 141 may be disposed between the electrode 142 and the electrode 143. The gate electrode 141 may include a gate metal. The gate metal may include titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), lead (Pb), molybdenum (Mo) and compounds thereof (such as, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), other conductive nitrides or conductive oxides), metal alloys (such as aluminum copper alloy (Al-Cu)), or other suitable materials. The gate electrode 141 may be electrically isolated from the thermally conductive layer 200. The gate 141 may be electrically isolated from the thermally conductive layer 210.
The electrode 142 (or source electrode) may be disposed on the nitride semiconductor layer 130. The electrode 142 may be in contact with the nitride semiconductor layer 130. The electrode 142 may comprise, for example, but not limited to, a conductive material. The conductive material may comprise a metal, alloy, doped semiconductive material (e.g., doped crystalline silicon), or other suitable conductive material, such as Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN, or other suitable material. The electrode 142 may comprise a multi-layer structure. For example, electrode 142 may comprise a structure of two layers of different materials. The electrode 142 may comprise a three-layer structure, with two adjacent layers made of different materials. The electrode 142 may be electrically connected to ground. The electrode 142 may be electrically connected to a virtual ground. The electrode 142 may be electrically connected to actual ground. The electrode 142 may be electrically isolated from the thermally conductive layer 200. The electrode 142 may be electrically isolated from the thermally conductive layer 210.
The electrode 143 (or the drain electrode) may be disposed on the nitride semiconductor layer 130. The electrode 143 may be in contact with the nitride semiconductor layer 130. Electrode 143 may comprise, for example, but is not limited to, a conductive material. The conductive material may comprise a metal, alloy, doped semiconductive material (e.g., doped crystalline silicon), or other suitable conductive material, such as Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN, or other suitable material. The structure of electrode 143 may be similar or identical to the structure of electrode 142. The electrode 143 may be electrically isolated from the thermally conductive layer 200. The electrode 143 may be electrically isolated from the thermally conductive layer 210.
The semiconductor device package 1a may further include a nitride semiconductor layer 144 (or depletion layer). The nitride semiconductor layer 144 may be disposed on the nitride semiconductor layer 130. The nitride semiconductor layer 144 may be in direct contact with the nitride semiconductor layer 130. The nitride semiconductor layer 144 may be disposed between the gate electrode 141 and the nitride semiconductor layer 130. The nitride semiconductor layer 144 may be doped with impurities. The nitride semiconductor layer 144 may contain p-type dopants. The nitride semiconductor layer 144 may include a p-doped GaN layer, a p-doped AlGaN layer, a p-doped AlN layer, or other suitable III-V layer. The p-type dopant may include magnesium (Mg), beryllium (Be), zinc (Zn), and cadmium (Cd).
The nitride semiconductor layer 144 may be configured to control the concentration of 2DEG in the nitride semiconductor layer 120. The nitride semiconductor layer 144 may be used to deplete the 2DEG directly under the nitride semiconductor layer 144.
The dielectric layer 150 may be disposed on the nitride semiconductor layer 130. The dielectric layer 150 may cover the gate 141. Dielectric layer 150 may cover electrode 142. Dielectric layer 150 may cover electrode 143. The dielectric layer 150 may comprise a high dielectric (high k) constant dielectric material. The high-k dielectric material may have a k value greater than about 5. The dielectric layer 150 may comprise a low-k dielectric material. The low-k dielectric material may have a k value of less than about 5. The dielectric layer 150 may comprise an oxide, nitride, oxynitride or other suitable material. Dielectric layer 150 may include multiple dielectric sublayers. The materials of the dielectric sublayers described above may be partially the same. The materials of the dielectric sublayers described above may be partially different. The adjacent dielectric sublayers may have incomplete boundaries (e.g., a portion of the boundary may be confirmed by Scanning Electron Microscope (SEM), and another portion of the boundary may not be observed by SEM). There may be substantially no boundaries between adjacent dielectric sublayers.
Conductive layer 161 may be disposed within dielectric layer 150. Conductive layer 161 may be embedded within dielectric layer 150. The conductive layer 161 may include a first metal layer (M1), a second metal layer (M2), or more metal layers.
Vias 162(via) may be disposed between two adjacent conductive elements (such as, but not limited to, between M1 and M2 or between M1 and electrode 142) to electrically connect the two adjacent conductive elements.
A passivation layer 170 is disposed on the dielectric layer 150. The passivation layer 170 may comprise a dielectric material. The passivation layer 170 may comprise an oxide, nitride, or other suitable material. The passivation layer 170 may include a resin.
The liner 180 is disposed on the dielectric layer 150. The liner 180 may penetrate the passivation layer 170. The pad 180 may be electrically connected to the conductive layer 161. The pad 180 may be electrically connected to the via 162. The pads 180 may serve as Under Bump Metallurgy (UBM).
The bump 190 may be disposed on the gasket 180. The bump 190 may be electrically connected to the pad 180. The pads 180 may include, but are not limited to, solder balls.
The heat conductive layer 200 may be disposed on the surface 100s1 of the substrate 100. The heat conductive layer 200 may directly contact the substrate 100. The thermally conductive layer 200 may have a surface that is coplanar with the surface 100s1 of the substrate 100. The heat conductive layer 200 may have a surface that is coplanar with the surface of the fin 112. The heat conductive layer 200 may directly contact the heat conductive structure 110. The heat conductive layer 200 may directly contact the fins 112 of the heat conductive structure 110. The thermal conductive layer 200 may comprise a two-dimensional material (two-dimensional material). As disclosed herein, a two-dimensional material may include a single layer of material, which is a crystalline material composed of a layer of atoms. The heat conductive layer 200 may include graphene. The heat conductive layer 200 may comprise molybdenum disulfide. The heat conductive layer 200 may comprise hexagonal boron nitride. The thermally conductive layer 200 can comprise a layer of two-dimensional material. The thermal conductive layer 200 can include multiple layers of two-dimensional materials. The thermal conductivity of the two-dimensional material in the transverse direction (e.g., a direction parallel to the surface 100s1 of the substrate 100) may be greater than the thermal conductivity in the longitudinal direction (e.g., a direction perpendicular to the surface 100s1 of the substrate 100). The thickness of the thermal conductive layer 200 may be in a range from about 0.3nm to about 1.0nm, such as 0.4nm, 0.5nm, 0.6nm, 0.7nm, 0.8nm, or 0.9 nm. The thermal conductive layer 200 is configured to rapidly and laterally transfer heat from the fins 112 such that the heat is substantially uniformly distributed throughout the thermal conductive layer 200, and thus the thickness of the thermal conductive layer 200 does not need to be too thick within the above range. Also, since the efficiency of the longitudinal thermal conductivity of the thermal conductive layer 200 is relatively less excellent than the lateral thermal conductivity, if the thickness of the thermal conductive layer 200 is too small, the thermal conductivity may be reduced. The thermal conductivity of the thermal conductive layer 200 may be greater than the thermal conductivity of the thermal conductive structure 110.
The heat conductive layer 210 may be disposed on the heat conductive layer 200. The thickness of the thermal conductive layer 210 may be greater than the thickness of the thermal conductive layer 200. The material of the thermal conductive layer 210 may be different from the material of the thermal conductive layer 200. The thermally conductive layer 210 may comprise materials other than two-dimensional materials. The thermally conductive layer 210 may comprise a metal. The thermally conductive layer 210 may comprise copper, gold, silver, aluminum, or other suitable materials.
When the semiconductor device package 1a is in operation, heat generated by active elements (active elements) may be transferred to the thermal conductive layer 200 through the one or more fins 112. The thermal conductive layer 200 can rapidly transfer heat laterally to the entire surface of the thermal conductive layer 200, and then to the thermal conductive layer 210. The present disclosure utilizes the characteristic of the heat conductive layer 200 having excellent lateral heat conductivity to further improve the heat dissipation efficiency. Since the lateral thermal conductivity of the thermal conductive layer 210 is relatively poor, without the thermal conductive layer 200, most of the heat is conducted in the longitudinal direction to the portion of the thermal conductive layer 210 that overlaps the fin 112 in the longitudinal direction. The heat conductive layer 210 does not overlap the fins 112 in the longitudinal direction, and thus contributes to heat dissipation to a relatively small degree. The heat conductive layer 200 of the present disclosure helps to increase the contribution of heat dissipation in the portion of the heat conductive layer 210 that does not overlap with the fins 112 in the longitudinal direction, thereby increasing the heat dissipation efficiency.
Fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, and 2H illustrate various stages of a method for fabricating a semiconductor device package, according to some embodiments of the present disclosure.
Referring to fig. 2A, a substrate 100 is provided. And a plurality of openings 100h are formed on the substrate 100.
Referring to FIG. 2B, a thermally conductive material 110' is deposited on the surface 100s2 of the substrate 100. The thermally conductive material 110' may fill the opening 100h of the substrate 100. Thermally conductive material 110' may cover surface 100s 2. The thickness of thermally conductive material 110' may range from about 200 μm to about 400 μm. After deposition of the thermally conductive material 110', an annealing technique may be performed in a nitrogen ambient.
Referring to fig. 2C, a portion of the thermally conductive material 110' is removed to form a thermally conductive structure 110 including a body portion 111 and a fin 112. The thermally conductive material 110' may be removed by chemical mechanical polishing techniques or other suitable techniques.
Referring to fig. 2D, a nitride semiconductor layer 120, a nitride semiconductor layer 130, a gate electrode 141, an electrode 142, an electrode 143, a dielectric layer 150, a conductive layer 161, a via 162, and a passivation layer 170 are formed on the thermal conduction structure 110. The above-described elements may be formed by one or more deposition techniques, photolithography techniques and etching techniques.
Referring to fig. 2E, a portion of the substrate 100 is removed such that the fins 112 of the thermal conduction structure 110 are exposed from the surface 100s1 of the substrate 100. A chemical mechanical polishing technique or other suitable technique may be performed on the surface 100s1 of the substrate 100 to remove a portion of the substrate 100.
Referring to fig. 2F, a heat conductive layer 200 is formed on the surface 100s1 of the substrate 100. The two-dimensional material solution can be prepared first, and the two-dimensional material solution is coated on a carrier plate to form a two-dimensional material film. Then, the two-dimensional material film is transferred from the carrier plate to the surface 100s1 of the substrate 100 to form the heat conductive layer 200.
Referring to fig. 2G, a thermal conductive layer 210 is formed on the thermal conductive layer 200. The heat conductive layer 210 may be formed by sputtering, physical vapor deposition, or other suitable techniques.
Referring to fig. 2H, the pads 180 and the bumps 190 are formed to obtain a semiconductor device package identical or similar to the semiconductor device package 1a described and shown in fig. 1.
Spatially relative terms, such as "under," "below," "lower," "above," "upper," "lower," "left," "right," and the like, as used herein may be used for ease of description to describe one component or feature's relationship to another component or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 80 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present.
As used herein, the terms "about," "substantially," and "about" are used to describe and explain minor variations. When used in conjunction with an event or circumstance, the terms may refer to the exact instance in which the event or circumstance occurs, as well as the instance in which the event or circumstance occurs in close proximity. As used herein with respect to a given value or range, the term "about" generally means within ± 10%, ± 5%, ± 1%, or ± 0.5% of the given value or range. Ranges may be expressed herein as from one end point to another end point or between two end points. All ranges disclosed herein are inclusive of the endpoints unless otherwise specified. The term "substantially coplanar" may refer to two surfaces positioned along the same plane with a positional difference within a few microns (μm), such as within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm. When numerical values or characteristics are said to be "substantially" the same, the term can refer to values that are within ± 10%, ± 5%, ± 1% or ± 0.5% of the mean of the values.
The foregoing has outlined features of several embodiments and detailed aspects of the present disclosure. The embodiments described in this disclosure may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or achieving the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations may be made therein without departing from the spirit and scope of the present disclosure.

Claims (20)

1. A semiconductor device package, comprising:
the device comprises a substrate, a first electrode, a second electrode and a first electrode, wherein the substrate is provided with a first surface and a second surface opposite to the first surface;
a thermally conductive structure disposed on the second surface of the substrate, wherein the thermally conductive structure has a plurality of fins, each of the plurality of fins extending from the second surface of the substrate toward the first surface;
a first nitride semiconductor layer disposed on the heat conductive structure; and
a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer.
2. The semiconductor device package of claim 1, further comprising:
a first thermally conductive layer disposed on the first surface of the substrate.
3. The semiconductor device package of claim 2, wherein the first thermally conductive layer comprises a two-dimensional material.
4. The semiconductor device package of claim 3, wherein the first thermally conductive layer comprises graphene.
5. The semiconductor device package of claim 2, wherein a thickness of the first thermally conductive layer is between 0.3nm-1.0 nm.
6. The semiconductor device package of claim 2, wherein the first thermally conductive layer is in contact with the plurality of fins.
7. The semiconductor device package of claim 2, further comprising:
and the second heat conduction layer is arranged on the first heat conduction layer, wherein the material of the second heat conduction layer is different from that of the first heat conduction layer.
8. The semiconductor device package of claim 7, wherein the second thermally conductive layer comprises a metal.
9. A semiconductor device package, comprising:
the device comprises a substrate, a first electrode, a second electrode and a first electrode, wherein the substrate is provided with a first surface and a second surface opposite to the first surface;
a heat conduction structure disposed on the second surface of the substrate, wherein the heat conduction structure has a main body portion and at least one protrusion portion, and the protrusion portion penetrates through the substrate;
a first nitride semiconductor layer disposed on the main body portion of the thermal conduction structure; and
a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer.
10. The semiconductor device package of claim 9, further comprising:
a first thermally conductive layer disposed on the first surface of the substrate.
11. The semiconductor device package of claim 10, wherein the first thermally conductive layer comprises a two-dimensional material.
12. The semiconductor device package of claim 11, wherein the first thermally conductive layer comprises graphene.
13. The semiconductor device package of claim 10, further comprising:
and the second heat conduction layer is arranged on the first heat conduction layer, wherein the material of the second heat conduction layer is different from that of the first heat conduction layer.
14. The semiconductor device package of claim 13, further comprising:
a gate disposed on the second nitride semiconductor layer, wherein the gate is electrically isolated from the second thermally conductive layer.
15. The semiconductor device package of claim 14, further comprising:
a first electrode disposed on the second nitride semiconductor layer; and
a second electrode disposed on the second nitride semiconductor layer, wherein the first electrode and the second electrode are electrically isolated from the second thermally conductive layer.
16. A semiconductor device package, comprising:
the device comprises a substrate, a first electrode, a second electrode and a first electrode, wherein the substrate is provided with a first surface and a second surface opposite to the first surface;
a heat conducting structure disposed on the second surface of the substrate, wherein the heat conducting structure has at least one protrusion extending through the substrate;
a first nitride semiconductor layer disposed on the heat conductive structure;
a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; and
a two-dimensional material layer disposed on the first surface of the substrate, wherein the two-dimensional material layer is in contact with the protrusions of the heat conducting structure.
17. The semiconductor device package of claim 16, wherein the two-dimensional layer of material comprises graphene.
18. The semiconductor device package of claim 16, further comprising:
a heat conductive layer disposed on the two-dimensional material layer, wherein a thickness of the heat conductive layer is greater than a thickness of the two-dimensional material layer.
19. The semiconductor device package of claim 16, wherein a surface of the heat conducting structure is coplanar with the first surface of the substrate.
20. The semiconductor device package according to claim 16, wherein a thermal conductivity of the heat conduction structure is greater than a thermal conductivity of the first nitride semiconductor layer.
CN202110122303.0A 2021-01-28 2021-01-28 Semiconductor device package Pending CN112768419A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114038750A (en) * 2021-11-05 2022-02-11 西安电子科技大学芜湖研究院 Preparation method of gallium nitride power device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114038750A (en) * 2021-11-05 2022-02-11 西安电子科技大学芜湖研究院 Preparation method of gallium nitride power device
CN114038750B (en) * 2021-11-05 2022-12-02 西安电子科技大学芜湖研究院 Preparation method of gallium nitride power device

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