CN112767985A - Circuit for realizing storage and analog computation based on SRAM (static random Access memory) and storage and analog computation system - Google Patents

Circuit for realizing storage and analog computation based on SRAM (static random Access memory) and storage and analog computation system Download PDF

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CN112767985A
CN112767985A CN202110054161.9A CN202110054161A CN112767985A CN 112767985 A CN112767985 A CN 112767985A CN 202110054161 A CN202110054161 A CN 202110054161A CN 112767985 A CN112767985 A CN 112767985A
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output
transmission gate
cmos transmission
voltage value
sram
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朱贤桢
梁龙飞
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Shanghai New Helium Brain Intelligence Technology Co ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Abstract

The circuit for realizing storage and analog computation based on the SRAM and the storage and analog computation system solve the problem that the SRAM is generally only applied to an operation storage unit in the prior art, the SRAM can not be used as a basic analog operation unit, and further the use efficiency is reduced. The invention fully utilizes the characteristics of the SRAM, enables the SRAM to have the storage capacity and the calculation capacity, and endows the SRAM with the capacity of multiplication and addition operation by externally connecting 6 switches to each unit, thereby greatly improving the use efficiency.

Description

Circuit for realizing storage and analog computation based on SRAM (static random Access memory) and storage and analog computation system
Technical Field
The invention relates to the field of data processing, in particular to a circuit for realizing storage and analog computation based on an SRAM (static random access memory) and a storage and analog computation system.
Background
In recent years, rapid development of AI-related technologies has made our lives more beautiful, and at the same time, has made increasing demands on computing power in various application scenarios. Analog Computing (Analog Computing) saves the loss in time and power consumption caused by data transfer; and the method is suitable for low-power consumption and high-efficiency scenes. In the prior art, the SRAM is generally only applied to the operation memory cell, but the SRAM cannot be used as the basic analog operation unit, and the utilization efficiency is reduced.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a circuit and a storage and analog computing system for implementing storage and analog computation based on SRAM, which solve the problem that the utilization efficiency is reduced because the SRAM is generally only applied to the operation storage unit, and the SRAM cannot be used as the basic analog operation unit.
In order to achieve the above and other related objects, the present invention provides a circuit for implementing storage and analog computation based on SRAM, for performing analog computation and/or storage process, the circuit comprising: at least one 6T SRAM cell, each having input/output terminals Q1 and Q2 for simultaneously inputting/outputting data; the NMOS transistor comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor; the six CMOS transmission gates are sequentially marked as P1-P6; a first capacitor and a second capacitor with one end grounded; the input and output end Q1 of the 6T SRAM cell is respectively connected with the end of a bit line BL1 and the gate of the second NMOS transistor, and the input and output end Q2 of the 6T SRAM cell is respectively connected with the end of a bit line BL2 and the gate of the third NMOS transistor; the drain electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the drain electrode of the fourth NMOS tube is connected with the drain electrode of the third NMOS tube, the source electrode of the first NMOS tube is connected with the other end of the first capacitor, and the source electrode of the fourth NMOS tube is connected with the other end of the second capacitor; the other end of the first capacitor is also connected with a CMOS transmission gate P1, a CMOS transmission gate P2 and a CMOS transmission gate P3 respectively; the other end of the second capacitor is respectively connected with a CMOS transmission gate P4, a CMOS transmission gate P5 and a CMOS transmission gate P6; an output terminal GRBL connected to the CMOS transmission gate P3 and the CMOS transmission gate P6; a read word line RWL is respectively connected with the grid electrode of the second NMOS tube, the grid electrode of the fourth NMOS tube, the other end of the first capacitor, the other end of the second capacitor, a bit line BL1 end and a bit line BL2 end; the word line control end WL and the enabling control end EN are respectively connected to corresponding levels of the circuit; the forward average voltage output terminal Pavg and the reverse average voltage output terminal Navg are respectively connected with the CMOS transmission gate P1, the CMOS transmission gate P2, the CMOS transmission gate P4 and the CMOS transmission gate P5 in the forward direction and in the reverse direction.
In an embodiment of the invention, the CMOS transmission gate P1, the CMOS transmission gate P2, the CMOS transmission gate P4, and the CMOS transmission gate P5 are used for turning on a switch when a forward average voltage value and/or a reverse average voltage value needs to be calculated in the analog calculation process; and/or the CMOS transmission gate P3 and the CMOS transmission gate P6 are used for opening a switch when multiplication calculation is needed in the analog calculation flow.
In an embodiment of the present invention, the simulation calculation process includes: a charging step and a calculating step within one clock signal.
In an embodiment of the present invention, the charging step includes: the charging step includes: when the outputs of the read word line RWL, the word line control end WL and the enable control end EN are at a high level, and the outputs of the CMOS transmission gate P3 and the CMOS transmission gate P6 are at a low level, the first capacitor and the second capacitor are sequentially charged to the voltages of the input and output ends Q1 and Q2, which are stored in the SRAM cell in advance, respectively; when the read word line RWL, the word line control end WL and the enable control end EN output are at a low level, the CMOS transmission gate P3 and the CMOS transmission gate P6 output are at a high level, and the first capacitor and the second capacitor are discharged to the same voltage as the GRBL voltage, so as to complete the multiplication.
In an embodiment of the present invention, the calculating step includes: the calculating step includes: when the output end GRBL outputs a positive voltage, the CMOS transmission gate P1 and the CMOS transmission gate P4 are turned on, the CMOS transmission gate P2 and the CMOS transmission gate P5 are turned off, and an output voltage value is obtained by subtracting a forward average voltage value output by the forward average voltage value output terminal Pavg from a reverse average voltage value output by the reverse average voltage value output terminal Navg; when the output of the output end GRBL is negative voltage, the CMOS transmission gate P2 and the CMOS transmission gate P5 are switched on, the CMOS transmission gate P1 and the CMOS transmission gate P4 are switched off, and the output voltage value is obtained by multiplying the output of the output end Q2 and the output voltage value of the output end GRBL.
In an embodiment of the invention, when the output terminal GRBL outputs a positive voltage, the CMOS transmission gate P1 and the CMOS transmission gate P4 are turned on, the CMOS transmission gate P2 and the CMOS transmission gate P5 are turned off, and the manner of obtaining the output voltage value by subtracting the forward average voltage value output by the forward average voltage value output terminal Pavg from the reverse average voltage value output by the reverse average voltage value output terminal Navg includes: when the output of the output terminal GRBL is a positive voltage, the output of the input/output terminal Q1 of the 6T SRAM cell is 1, the output of the input/output terminal Q2 is 0, the first NMOS transistor is powered on, the output terminal RWL is at a high level, the second NMOS transistor is powered on, the voltage VPavg output by the forward average voltage value output terminal Pavg is 0, the output voltage VNavg of the reverse average voltage value output terminal Navg is equal to the output voltage VGRBL of the output terminal GRBL, and then the output voltage V is: V-VPavg-VNavg-0-VGRBL.
In an embodiment of the invention, when the output of the output terminal GRBL is a negative voltage, the CMOS transmission gate P2 and the CMOS transmission gate P5 are turned on, the CMOS transmission gate P1 and the CMOS transmission gate P4 are turned off, and the way of obtaining the output voltage value by multiplying the output of the output terminal Q2 and the output voltage value of the output terminal GRBL includes: when the output end GRBL outputs negative voltage, the output end Q1 of the 6T SRAM unit outputs 0, the output value Q2 of the input end Q2 is 1, and the output voltage value V of the other end of the second capacitorGRBLThen, the output voltage value V: q2 x VGRBL＝VGRBL。
In an embodiment of the present invention, the storing process includes: a write flow and a read flow; wherein the writing process comprises: when the word line control terminal WL and the enable control terminal EN are simultaneously outputted as high level, the input and output terminals Q1 and Q2 of the 6T SRAM cell are written with data; the readout flow includes: when the enable control terminal EN output is high, the input and output terminals Q1 and Q2 of the 6T SRAM cell read data.
To achieve the above and other related objects, the present invention provides a storage and emulation computing system, comprising: the SRAM array is formed by a plurality of circuits which realize storage and analog computation based on the SRAM; and the calculation module is connected with the SRAM array and used for carrying out analog calculation on the output voltage value of the SRAM array based on an analog calculation formula.
In an embodiment of the present invention, the simulation calculation formula includes:
Figure BDA0002900287180000031
Figure BDA0002900287180000032
wherein k is a circuit of a k-th row in the SRAM array, i is a circuit of an i-th column in the SRAM array, and VYTo be the output voltage value, VPavgIs the forward average voltage value output by the forward average voltage value output terminal Pavg of the SRAM array, the VNavgOutputting a voltage value for a reverse average voltage value output terminal Navg of the SRAM array, the VY，kIs the average value of the output voltage values of each circuit in the SRAM array, wk，iThe output value V of the input and output ends of the 6T SRAM unit corresponding to the circuit of the ith row and the ith columnGRBLiThe output voltage value of the output terminal GRBL in the circuit of the kth row and the ith column.
As described above, the circuit for implementing storage and analog computation based on SRAM and the storage and analog computation system of the present invention have the following advantages: the invention fully utilizes the characteristics of the SRAM, enables the SRAM to have the storage capacity and the calculation capacity, and endows the SRAM with the capacity of multiplication and addition operation by externally connecting 6 switches to each unit, thereby greatly improving the use efficiency.
Drawings
Fig. 1 is a schematic structural diagram of a circuit for implementing storage and analog computation based on SRAM according to an embodiment of the present invention.
FIG. 2 is a block diagram of a storage and emulation computing system according to an embodiment of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It is noted that in the following description, reference is made to the accompanying drawings which illustrate several embodiments of the present invention. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present invention. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Spatially relative terms, such as "upper," "lower," "left," "right," "lower," "below," "lower," "over," "upper," and the like, may be used herein to facilitate describing one element or feature's relationship to another element or feature as illustrated in the figures.
Throughout the specification, when a part is referred to as being "connected" to another part, this includes not only a case of being "directly connected" but also a case of being "indirectly connected" with another element interposed therebetween. In addition, when a certain part is referred to as "including" a certain component, unless otherwise stated, other components are not excluded, but it means that other components may be included.
The terms first, second, third, etc. are used herein to describe various elements, components, regions, layers and/or sections, but are not limited thereto. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of the present invention.
Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," and/or "comprising," when used in this specification, specify the presence of stated features, operations, elements, components, items, species, and/or groups, but do not preclude the presence, or addition of one or more other features, operations, elements, components, items, species, and/or groups thereof. The terms "or" and/or "as used herein are to be construed as inclusive or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a; b; c; a and B; a and C; b and C; A. b and C ". An exception to this definition will occur only when a combination of elements, functions or operations are inherently mutually exclusive in some way.
The embodiment of the invention provides a circuit for realizing storage and analog computation based on an SRAM (static random access memory), which solves the problems that in the prior art, the accuracy is low, the practical application is limited, the storage capacity is large, the power consumption is high, the computation delay is high, and the imbalance of data among categories is very sensitive when a deep learning model is adopted for face recognition. The circuit for realizing storage and analog computation based on the SRAM, which is adopted by the invention, has high accuracy, light weight attribute and is suitable for large data sets and small data sets, the model can be more flexible under the condition of ensuring certain accuracy, the circuit can be placed at the edge end to realize real-time reasoning, and the compatibility and the robustness are increased.
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings so that those skilled in the art can easily implement the embodiments of the present invention. The present invention may be embodied in many different forms and is not limited to the embodiments described herein.
Fig. 1 shows a schematic structural diagram of a circuit for implementing storage and analog computation based on SRAM in the embodiment of the present invention.
For performing analog computation and/or storage procedures, the circuit comprising:
at least one 6T SRAM cell omega0Each unit has input and output terminals Q1 and Q2 for simultaneously inputting and outputting data;
a first NMOS transistor S1, a second NMOS transistor S2, a third NMOS transistor S3 and a fourth NMOS transistor S4;
the six CMOS transmission gates are sequentially marked as P1-P6;
a first capacitor C1 and a second capacitor C2 with one end grounded;
wherein the 6T SRAM cell ω0The input end and the output end Q1 of the SRAM are respectively connected with the end of a bit line BL1 and the grid electrode of the second NMOS transistor S2, and the 6T SRAM unit omega0The input/output end Q2 of the first NMOS transistor is connected to the end of a bit line BL2 and the gate of the third NMOS transistor S3, respectively; the drain of the first NMOS transistor S1 is connected to the drain of the second NMOS transistor S2, the drain of the fourth NMOS transistor S4 is connected to the drain of the third NMOS transistor S3, the source of the first NMOS transistor S1 is connected to the other end of the first capacitor C1, and the source of the fourth NMOS transistor S4 is connected to the other end of the second capacitor C2; the other end of the first capacitor C1 is also connected with a CMOS transmission gate P1, a CMOS transmission gate P2 and a CMOS transmission gate P3 respectively; the other end of the second capacitor C2 is respectively connected with a CMOS transmission gate P4, a CMOS transmission gate P5 and a CMOS transmission gate P6; an output terminal GRBL connected to the CMOS transmission gate P3 and the CMOS transmission gate P6; a read word line RWL is respectively connected with the gate of the second NMOS transistor S2, the gate of the fourth NMOS transistor S4, the other end of the first capacitor C1, the other end of the second capacitor C2, a bit line BL1 end and a bit line BL2 end; the word line control end WL and the enabling control end EN are respectively connected to corresponding levels of the circuit; the forward average voltage output terminal Pavg and the reverse average voltage output terminal Navg are respectively connected with the CMOS transmission gate P1, the CMOS transmission gate P2, the CMOS transmission gate P4 and the CMOS transmission gate P5 in the forward direction and in the reverse direction.
It should be noted that the other end of the first capacitor C1 and the other end of the second capacitor C2 are non-grounded ends of the first capacitor C1 and the second capacitor C2, respectively.
Optionally, the CMOS transmission gate P1, the CMOS transmission gate P2, the CMOS transmission gate P4, and the CMOS transmission gate P5 are configured to open a switch when a forward average voltage value and/or a reverse average voltage value needs to be calculated in the analog calculation process; and/or the CMOS transmission gate P3 and the CMOS transmission gate P6 are used for opening a switch when multiplication calculation is needed in the analog calculation flow.
Specifically, the CMOS transmission gate P1, the CMOS transmission gate P2, the CMOS transmission gate P4, and the CMOS transmission gate P5 are used for turning on a switch when a forward average voltage value and/or a reverse average voltage value needs to be calculated, or turning off the switch when the forward average voltage value and/or the reverse average voltage value needs to be calculated; the CMOS transmission gate P3 and the CMOS transmission gate P6 are used for opening the switch when multiplication calculation is needed in the analog calculation flow, otherwise, the switch is closed.
Preferably, the CMOS transmission gate P1 is the same as the CMOS transmission gate P4, the CMOS transmission gate P2 is the same as the CMOS transmission gate P5, and the CMOS transmission gate P3 is the same as the CMOS transmission gate P6.
Optionally, the storing process includes: a write flow and a read flow; wherein the writing process comprises: when the word line control terminal WL and the enable control terminal EN are simultaneously outputted as high level, the 6T SRAM cell ω0The input and output terminals Q1 and Q2 write data; the readout flow includes: when the enable control end EN output is high level, the 6T SRAM unit omega0The input and output terminals Q1 and Q2 read out data.
Optionally, the simulation calculation process includes: a charging step and a calculating step into which one clock signal is divided.
Optionally, the charging step includes: the charging step includes: when the outputs of the read word line RWL, the word line control end WL and the enable control end EN are at a high level, and the outputs of the CMOS transmission gate P3 and the CMOS transmission gate P6 are at a low level, the first capacitor and the second capacitor are sequentially charged to the voltages of the input and output ends Q1 and Q2, which are stored in the SRAM cell in advance, respectively; when the read word line RWL, the word line control end WL and the enable control end EN output are at a low level, the CMOS transmission gate P3 and the CMOS transmission gate P6 output are at a high level, and the first capacitor and the second capacitor are discharged to the same voltage as the GRBL voltage, so as to complete the multiplication.
Optionally, the calculating step includes: when the output end GRBL outputs a positive voltage, the CMOS transmission gate P1 and the CMOS transmission gate P4 are turned on, the CMOS transmission gate P2 and the CMOS transmission gate P5 are turned off, and an output voltage value is obtained by subtracting a forward average voltage value output by the forward average voltage value output terminal Pavg from a reverse average voltage value output by the reverse average voltage value output terminal Navg; when the output of the output end GRBL is negative voltage, the CMOS transmission gate P2 and the CMOS transmission gate P5 are switched on, the CMOS transmission gate P1 and the CMOS transmission gate P4 are switched off, and the output voltage value is obtained by multiplying the output of the output end Q2 and the output voltage value of the output end GRBL.
Optionally, when the output terminal GRBL outputs a positive voltage, the CMOS transmission gate P1 and the CMOS transmission gate P4 are turned on, the CMOS transmission gate P2 and the CMOS transmission gate P5 are turned off, and a manner of obtaining an output voltage value according to a subtraction of the forward average voltage value output by the forward average voltage value output terminal Pavg and the reverse average voltage value output by the reverse average voltage value output terminal Navg includes:
when the forward average voltage value and the reverse average voltage value need to be calculated, the CMOS transmission gate P1, the CMOS transmission gate P2, the CMOS transmission gate P4 and the CMOS transmission gate P5 are opened, and the CMOS transmission gate P3 and the CMOS transmission gate P6 are closed;
when the output of the output terminal GRBL is a positive voltage, the output of the input/output terminal Q1 of the 6T SRAM cell is 1, the output of the input/output terminal Q2 is 0, the first NMOS transistor S1 is powered on, the output terminal of the read word line RWL is at a high level, the second NMOS transistor S2 is powered on, the voltage VPavg output by the forward average voltage value output terminal Pavg is 0, the output voltage value Navg of the reverse average voltage value output terminal Navg is equal to the output voltage value VGRBL of the output terminal GRBL, and an output voltage value is obtained by subtracting the forward average voltage value output by the forward average voltage value output terminal Pavg and the reverse average voltage value output by the reverse average voltage value output terminal Navg, and the output voltage value V is:
V＝VPavg-VNavg＝0-VGRBL； (1)
optionally, when the output of the output terminal GRBL is a negative voltage, the CMOS transmission gate P2 and the CMOS transmission gate P5 are turned on, the CMOS transmission gate P1 and the CMOS transmission gate P4 are turned off, and a manner of obtaining an output voltage value by performing a multiplication calculation on the output of the output terminal Q2 and the output voltage value of the output terminal GRBL includes:
when multiplication calculation is needed, the CMOS transmission gate P3 and the CMOS transmission gate P6 are opened, and the CMOS transmission gate P1, the CMOS transmission gate P2, the CMOS transmission gate P4 and the CMOS transmission gate P5 are closed;
when the output of the output terminal GRBL is a negative voltage, the output of the input/output terminal Q1 of the 6T SRAM cell is 0, the output value Q2 of the input/output terminal Q2 is 1, the third NMOS transistor S3 is powered on, the output terminal of the read word line RWL is at a low level, the fourth NMOS transistor S4 is powered on, and the output voltage value V of the other terminal of the second capacitor C2GRBLThen, the output voltage value V:
V＝Q2xVGRBL＝1xVGRBL； (2)
FIG. 2 shows a schematic diagram of a storage and emulation computing system in an embodiment of the present invention.
The system comprises:
an SRAM array 21 composed of a plurality of SRAM-based storage and analog computation-implementing circuits 211 as shown in FIG. 1;
and the calculation module 22 is connected with the SRAM array 21 and is configured to perform analog calculation on the output voltage value of the SRAM array based on an analog calculation formula.
The circuit 211 for implementing storage and analog computation based on SRAM comprises: at least one 6T SRAM cell, each having input/output terminals Q1 and Q2 for simultaneously inputting/outputting data; the NMOS transistor comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor; the six CMOS transmission gates are sequentially marked as P1-P6; it should be noted that the connection relationship of the specific components is the same as the connection manner of fig. 1, and therefore, the detailed description thereof is omitted.
Optionally, the number of the circuits 211 for implementing storage and analog computation based on SRAM is at least two, and four are taken as an example in fig. 2.
Optionally, the SRAM array 21 may copy a connection method of the circuit 211 for implementing storage and analog computation based on the SRAM, and extend to the SRAM array, and meanwhile, has read-write and operation capabilities. The extending mode may be that N lines are transversely extended in the columns, or K lines are extended in the rows, and the total number of circuits in one array is equal to N × K.
Optionally, the simulation calculation formula includes:
Figure BDA0002900287180000081
Figure BDA0002900287180000082
wherein k is a circuit of a k-th row in the SRAM array, i is a circuit of an i-th column in the SRAM array, and VYFor the output voltage value, VPavg is the forward average voltage value outputted by the forward average voltage value output terminal Pavg of the SRAM array, VNavg is the reverse average voltage value output terminal Navg of the SRAM array, and V isY，kIs the average value of the output voltage values of each circuit in the SRAM array, wk，iThe output value V of the input and output ends of the 6T SRAM unit corresponding to the circuit of the ith row and the ith columnGRBLiThe output voltage value of the output terminal GRBL in the circuit of the kth row and the ith column.
Specifically, the way for the calculation module 22 to perform analog calculation on the output voltage value of the SRAM array based on the analog calculation formula includes:
multiplying the output value of the input and output end of the 6T SRAM unit corresponding to the circuit in the ith row and the ith column with the output voltage value VGRBLi of the GRBL in the circuit in the corresponding ith row and the ith column, summing the multiplied values calculated by each circuit and dividing the summed values by the number of the circuits to obtain the average value of the output voltage values of each circuit in the SRAM array;
then the output voltage values of the circuits in the same row are summed to be equal to the subtraction value of the forward average voltage value output by the forward average voltage value output terminal Pavg and the reverse average voltage value output by the reverse average voltage value output terminal Navg.
In summary, the circuit for implementing storage and analog computation based on SRAM and the storage and analog computation system of the present invention are used to solve the problem that the utilization efficiency is reduced because the SRAM is generally only applied to the operation storage unit, and the SRAM cannot be used as the basic analog operation unit in the prior art. The invention fully utilizes the characteristics of the SRAM, enables the SRAM to have the storage capacity and the calculation capacity, and endows the SRAM with the capacity of multiplication and addition operation by externally connecting 6 switches to each unit, thereby greatly improving the use efficiency. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles of the present invention and its efficacy, and are not to be construed as limiting the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A circuit for realizing storage and analog computation based on SRAM is used for carrying out analog computation and/or storage process, and the circuit comprises:
at least one 6T SRAM cell, each having input/output terminals Q1 and Q2 for simultaneously inputting/outputting data;
the NMOS transistor comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor;
the six CMOS transmission gates are sequentially marked as P1-P6;
a first capacitor and a second capacitor with one end grounded;
the input and output end Q1 of the 6T SRAM cell is respectively connected with the end of a bit line BL1 and the gate of the second NMOS transistor, and the input and output end Q2 of the 6T SRAM cell is respectively connected with the end of a bit line BL2 and the gate of the third NMOS transistor;
the drain electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the drain electrode of the fourth NMOS tube is connected with the drain electrode of the third NMOS tube, the source electrode of the first NMOS tube is connected with the other end of the first capacitor, and the source electrode of the fourth NMOS tube is connected with the other end of the second capacitor;
the other end of the first capacitor is also connected with a CMOS transmission gate P1, a CMOS transmission gate P2 and a CMOS transmission gate P3 respectively; the other end of the second capacitor is respectively connected with a CMOS transmission gate P4, a CMOS transmission gate P5 and a CMOS transmission gate P6;
an output terminal GRBL connected to the CMOS transmission gate P3 and the CMOS transmission gate P6;
a read word line RWL is respectively connected with the grid electrode of the second NMOS tube, the grid electrode of the fourth NMOS tube, the other end of the first capacitor, the other end of the second capacitor, a bit line BL1 end and a bit line BL2 end;
the word line control end WL and the enabling control end EN are respectively connected to corresponding levels of the circuit;
the forward average voltage output terminal Pavg and the reverse average voltage output terminal Navg are respectively connected with the CMOS transmission gate P1, the CMOS transmission gate P2, the CMOS transmission gate P4 and the CMOS transmission gate P5 in the forward direction and in the reverse direction.
2. The SRAM-based storage and simulation computation circuit of claim 1, wherein the CMOS transmission gate P1, the CMOS transmission gate P2, the CMOS transmission gate P4 and the CMOS transmission gate P5 are used for opening a switch when a forward average voltage value and/or a reverse average voltage value is/are required to be computed in the simulation computation flow; and/or the CMOS transmission gate P3 and the CMOS transmission gate P6 are used for opening a switch when multiplication calculation is needed in the analog calculation flow.
3. The circuit according to claim 2, wherein the simulation calculation process comprises: a charging step and a calculating step within one clock signal.
4. The SRAM-based circuit of claim 3, wherein the charging step comprises:
when the outputs of the read word line RWL, the word line control end WL and the enable control end EN are at a high level, and the outputs of the CMOS transmission gate P3 and the CMOS transmission gate P6 are at a low level, the first capacitor and the second capacitor are sequentially charged to the voltages of the input and output ends Q1 and Q2, which are stored in the SRAM cell in advance, respectively;
when the read word line RWL, the word line control end WL and the enable control end EN output are at a low level, the CMOS transmission gate P3 and the CMOS transmission gate P6 output are at a high level, and the first capacitor and the second capacitor are discharged to the same voltage as the GRBL voltage, so as to complete the multiplication.
5. The circuit according to claim 3, wherein the calculating step comprises:
when the output end GRBL outputs a positive voltage, the CMOS transmission gate P1 and the CMOS transmission gate P4 are turned on, the CMOS transmission gate P2 and the CMOS transmission gate P5 are turned off, and an output voltage value is obtained by subtracting a forward average voltage value output by the forward average voltage value output terminal Pavg from a reverse average voltage value output by the reverse average voltage value output terminal Navg;
when the output of the output end GRBL is negative voltage, the CMOS transmission gate P2 and the CMOS transmission gate P5 are switched on, the CMOS transmission gate P1 and the CMOS transmission gate P4 are switched off, and the output voltage value is obtained by multiplying the output of the output end Q2 and the output voltage value of the output end GRBL.
6. The SRAM-based storage and analog computation circuit of claim 5, wherein when the output GRBL is positive, the CMOS transmission gate P1 and the CMOS transmission gate P4 are turned on, the CMOS transmission gate P2 and the CMOS transmission gate P5 are turned off, and the output voltage value obtained by subtracting the forward average voltage value outputted from the forward average voltage value output Pavg and the reverse average voltage value outputted from the reverse average voltage value output Navg comprises:
when the output end GRBL is positive voltage, the output end Q1 of the 6T SRAM unit is 1, the output end Q2 of the 6T SRAM unit is 0, the first NMOS tube is electrified, the output end RWL is high level, the second NMOS tube is electrified, and the voltage V output by the forward average voltage value output end Pavg isPavgIs 0, the reverse average voltage value output end Navg outputs the voltage value VNavgEqual to the output voltage value V of the GRBL at the output endGRBLThen, the output voltage value V is:
V＝VPavg-VNavg＝0-VGRBL。
7. the SRAM-based storage and analog computation circuit of claim 5, wherein when the output of the output GRBL is a negative voltage, the CMOS transmission gate P2 and the CMOS transmission gate P5 are turned on, the CMOS transmission gate P1 and the CMOS transmission gate P4 are turned off, and the output voltage value obtained by multiplying the output of the output Q2 and the output voltage value of the output GRBL comprises:
when the output end GRBL outputs negative voltage, the output end Q1 of the 6T SRAM unit outputs 0, the output value Q2 of the input end Q2 is 1, and the output voltage value V of the other end of the second capacitorGRBLThen, the output voltage value V:
V＝Q2 x VGRBL＝VGRBL。
8. the circuit according to claim 1, wherein the storing procedure comprises: a write flow and a read flow;
wherein the writing process comprises: when the word line control terminal WL and the enable control terminal EN are simultaneously outputted as high level, the input and output terminals Q1 and Q2 of the 6T SRAM cell are written with data;
the readout flow includes: when the enable control terminal EN output is high, the input and output terminals Q1 and Q2 of the 6T SRAM cell read data.
9. A storage and emulation computing system, the system comprising:
an SRAM array formed from a plurality of SRAM based circuits for performing storage and analog calculations according to any one of claims 1 to 8;
and the calculation module is connected with the SRAM array and used for carrying out analog calculation on the output voltage value of the SRAM array based on an analog calculation formula.
10. The storage and simulation computing system of claim 9, wherein the simulation calculation formula comprises:
Figure FDA0002900287170000031
Figure FDA0002900287170000032
wherein k is a circuit of a k-th row in the SRAM array, i is a circuit of an i-th column in the SRAM array, and VYTo be the output voltage value, VPavgIs the forward average voltage value output by the forward average voltage value output terminal Pavg of the SRAM array, the VNavgOutputting a voltage value for a reverse average voltage value output terminal Navg of the SRAM array, the VY，kIs the average value of the output voltage values of each circuit in the SRAM array, wk，iThe output value V of the input and output ends of the 6T SRAM unit corresponding to the circuit of the ith row and the ith columnGRBLiThe output voltage value of the output terminal GRBL in the circuit of the kth row and the ith column.
CN202110054161.9A 2021-01-15 2021-01-15 Circuit for realizing storage and analog computation based on SRAM (static random Access memory) and storage and analog computation system Pending CN112767985A (en)

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