CN112765927A - CPU module packaging method, CPU module, mainboard, server and computing equipment - Google Patents
CPU module packaging method, CPU module, mainboard, server and computing equipment Download PDFInfo
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Abstract
The application provides a CPU module packaging method, a CPU module, a mainboard, a server and an arithmetic device. The CPU module packaging method comprises the following steps: the method comprises the steps of classifying functions of a CPU bare chip, manufacturing corresponding bare chip subunits according to the types of the functions, assembling a plurality of bare chip subunits to form a 3D three-dimensional structure with openings in the bottom surface, the side surfaces and the top, and electrically connecting the bare chip subunits on the side surfaces with the bare chip subunits on the bottom surface. And signal pins are reserved on the side surface and the bottom surface of the 3D three-dimensional structure. And connecting a memory particle chip matched with the CPU bare chip on a signal pin on the side surface of the 3D three-dimensional structure. And arranging a substrate which is electrically connected with the signal pins on the bottom surface of the 3D three-dimensional structure. The packaging 3D three-dimensional structure and the memory particle chip form a CPU module, and the substrate is used as an external signal pin of the CPU module. The technical scheme of the application effectively reduces signal transmission interference between the processor and the memory and reduces the design difficulty of the mainboard.
Description
Technical Field
The application relates to the technical field of computing equipment device packaging and construction, in particular to a CPU module packaging method, a CPU module, a mainboard, a server and computing equipment.
Background
A Central Processing Unit (CPU) is a final execution unit for information processing and program operation, and serves as an operation and control core of a computer system. A Memory (Memory), also called an internal Memory and a main Memory, temporarily stores operation data in a CPU and data exchanged with an external Memory such as a hard disk.
A server is one type of computing device. The architecture of the existing server mainboard comprises a CPU, a memory bank, a peripheral bridge chip, an expansion interface chip and the like. The existing CPU and the memory are independent devices, and the CPU is in a plane packaging mode, so that when the CPU and the memory are used on a mainboard, the signal transmission distance between the CPU and the memory is relatively long, signals are easy to interfere, and the signal quality is poor.
In addition, because the speed of the data path between the CPU and the memory is very high, when designing a PCB (Printed Circuit Board), in order to ensure the integrity of high-speed signals between the CPU and the memory, impedance matching, and meanwhile signal reflection, attenuation, and distortion are also avoided, therefore, a high requirement is imposed on the PCB design, and a person skilled in the art needs to have a rich design experience when designing a PCB motherboard, and can use a complete simulation tool to check, thereby increasing the design difficulty of the motherboard.
Therefore, how to design a CPU module capable of effectively reducing signal transmission interference between a processor and a memory and reducing the difficulty in designing a motherboard becomes a hotspot of research in the industry.
Disclosure of Invention
An object of the embodiments of the present application is to provide a method for packaging a CPU module, which can effectively reduce signal transmission interference between a processor and a memory, and reduce the difficulty in designing a motherboard.
A second object of the embodiments of the present application is to provide a CPU module.
A third object of the embodiments of the present application is to provide a motherboard using the above CPU module.
A fourth object of the embodiments of the present application is to provide a server using the above motherboard.
A fifth object of the embodiments of the present application is to provide an arithmetic device using the above motherboard.
In a first aspect, a CPU module packaging method is provided, which includes the following steps:
classifying functions of the CPU bare chip, manufacturing corresponding bare chip subunits according to the function types, assembling the bare chip subunits to form a 3D (three-dimensional) structure with an opening on the bottom surface, the side surface and the top, and electrically connecting the bare chip subunits on the side surface with the bare chip subunits on the bottom surface;
reserving signal pins on the side surface and the bottom surface of the 3D three-dimensional structure;
connecting a memory particle chip matched with the CPU bare chip on a signal pin on the side face of the 3D three-dimensional structure, wherein the memory particle chip is tightly attached to the side face of the 3D three-dimensional structure;
arranging a substrate which is electrically connected with the signal pins on the bottom surface of the 3D three-dimensional structure;
the packaging 3D three-dimensional structure and the memory particle chip form a CPU module, and the substrate is used as an external signal pin of the CPU module.
In one implementable approach, a die subunit includes a base die subunit and a plurality of memory interface die subunits. The base die subunit forms the bottom surface of the 3D three-dimensional structure, and the plurality of memory interface die subunits form the side surface of the 3D three-dimensional structure.
In an implementable approach, the signal pins of the 3D solid structure are disposed on the side and bottom surfaces of the outer surface of the 3D solid structure.
According to a second aspect of the present application, there is also provided a CPU module including a CPU die, a memory particle chip, an encapsulation layer, and a substrate.
The CPU bare chip comprises a plurality of bare chip subunits, the bare chip subunits are assembled into a 3D three-dimensional structure with a bottom surface, a side surface and an opening at the top, the bare chip subunits on the side surface are electrically connected with the bare chip subunits on the bottom surface, and signal pins are reserved on the side surface and the bottom surface of the 3D three-dimensional structure. The memory particle chip is tightly attached to the side face of the 3D three-dimensional structure and is connected with the signal pin on the side face of the 3D three-dimensional structure. The packaging layer is used for packaging the CPU bare chip and the memory particle chip. The substrate is arranged on the bottom surface of the 3D three-dimensional structure, is connected with the signal pin on the bottom surface of the 3D three-dimensional structure and is used as an external signal pin of a CPU module consisting of the 3D three-dimensional structure and the memory particle chip.
In one implementable approach, the plurality of die subunits includes a base die subunit and a plurality of memory interface die subunits. The base die subunit forms the bottom surface of the 3D three-dimensional structure, and the plurality of memory interface die subunits form the side surface of the 3D three-dimensional structure.
In an implementable approach, the signal pins of the 3D solid structure are disposed on the side and bottom surfaces of the outer surface of the 3D solid structure.
In one implementation, the base die subunit is polygonal, and the number of memory interface die subunits is equal to the number of sides of the base die subunit.
According to a third aspect of the present application, there is also provided a motherboard, which is characterized by including the CPU module in the above technical solution.
According to a fourth aspect of the present application, a server is further provided, which includes the motherboard in the above technical solution.
According to a fifth aspect of the present application, there is also provided an arithmetic device, including the main board in the above technical solution.
Compared with the prior art, the beneficial effect of this application is:
1. the CPU module packaging method changes the plane structure form of the original CPU bare chip, a plurality of bare chip subunits are assembled to form a 3D three-dimensional structure with openings in the bottom surface, the side surface and the top, and the memory particle chip is tightly attached to the side surface of the 3D three-dimensional structure. The structure greatly shortens the signal transmission distance between the CPU and the memory, reduces signal interference, improves the signal transmission quality of the CPU and the memory, and realizes higher interconnection frequency between the CPU and the memory.
2. The 3D three-dimensional structure of the CPU and the memory particle chip are packaged into a device, and the substrate electrically connected with the bottom surface of the 3D three-dimensional structure is used as an external signal pin of the CPU module. When the PCB is designed, a communication circuit between the CPU and the memory is not required to be designed to ensure the quality of a high-speed signal, and the complexity of the circuit is reduced, so that the design difficulty of the PCB main board is reduced, the design success rate of the PCB main board is improved, and the design period of the PCB main board is shortened.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a flowchart illustrating a CPU module packaging method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a circuit structure of a CPU and a memory in practical application in the prior art;
FIG. 3 is a schematic diagram of a circuit structure of a CPU module obtained by the method of FIG. 1 in practical application;
FIG. 4 is a schematic structural diagram of a CPU module according to an embodiment of the present application;
FIG. 5 is an exploded view of the CPU module of FIG. 4;
FIG. 6 is a diagram illustrating a CPU die according to an embodiment of the present application;
FIG. 7 is a schematic diagram of another CPU die according to an embodiment of the present application;
FIG. 8 is a schematic view of the internal support structure of the CPU module shown in FIG. 4;
FIG. 9 is a schematic view of an alternative internal support structure for the CPU module of FIG. 4;
fig. 10 is a schematic view illustrating a heat conducting structure of a CPU module according to an embodiment of the present application.
In the figure: 10. a 3D spatial structure; 11. a die subunit; 111. a base die subunit; 112. a memory interface die subunit; 20. storing a particle chip; 30. a substrate; 40. supporting ribs; 50. a heat conductive layer; 60. a thermally conductive structure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 2 is a schematic diagram of a circuit structure of a CPU and a memory in practical application in the prior art. Because the existing CPU and memory are independent devices, when the CPU and memory are used in a circuit, the signal transmission distance between the CPU and memory is long, and signals are easy to interfere. In addition, in order to ensure the transmission rate of data signals between the CPU and the memory and ensure the integrity and accuracy of the signals, the design requirement on the PCB mainboard is higher, and the design difficulty of the PCB mainboard is increased. Therefore, on one hand, in order to effectively reduce the signal transmission interference between the CPU and the memory of the processor, the signal transmission distance between the CPU and the memory can be shortened; on the other hand, in order to reduce the design difficulty of the main board, the circuit design between the CPU and the memory needs to be simplified or even eliminated, thereby reducing the design difficulty of the PCB main board.
According to a first aspect of the present application, a CPU module packaging method is first provided. Referring to fig. 1, the method comprises the steps of:
s101: the method comprises the steps of classifying functions of a CPU bare chip, manufacturing corresponding bare chip subunits according to the types of the functions, assembling a plurality of bare chip subunits to form a 3D three-dimensional structure with openings in the bottom surface, the side surfaces and the top, and electrically connecting the bare chip subunits on the side surfaces with the bare chip subunits on the bottom surface.
S102: and signal pins are reserved on the side surface and the bottom surface of the 3D three-dimensional structure.
S103: and connecting a memory particle chip matched with the CPU bare chip on a signal pin on the side face of the 3D three-dimensional structure, wherein the memory particle chip is tightly attached to the side face of the 3D three-dimensional structure.
S104: a substrate 30 electrically connected to signal pins of the bottom surface is provided on the bottom surface of the 3D three-dimensional structure.
S105: the packaging 3D three-dimensional structure and the memory particle chip form a CPU module, and the substrate is used as an external signal pin of the CPU module.
It should be noted that some steps may be performed in an interchangeable order or synchronously in actual operation. For example, steps S103 and S104 may be in an interchangeable order, steps S103 and S104 may be performed in synchronization, and steps S102 and S101 may be performed in synchronization.
Fig. 3 is a schematic circuit diagram of a CPU module in practical application according to an embodiment of the present application. Compared with the prior art shown in fig. 2, in the technical scheme of the application, the CPU and the memory form a whole CPU module device, the signal transmission distance is shortened, and in the practical circuit application, only the connection circuit between the whole CPU module device and other circuits (a power circuit, a switch circuit and the like) needs to be designed, and the circuit between the CPU and the memory does not need to be designed, so that the design of the PCB main board is simplified, and the design difficulty of the PCB main board is reduced.
Specifically, the CPU module packaging method classifies functions of the CPU bare chips, manufactures corresponding bare chip subunits according to the function types, assembles the bare chip subunits to form a 3D three-dimensional structure with openings in the bottom surface, the side surfaces and the top, and then closely attaches the memory particle chips to the side surfaces of the 3D three-dimensional structure and is electrically connected with the side surfaces. The structure changes the plane structure form of the original CPU bare chip, greatly shortens the signal transmission distance between the CPU and the internal memory, reduces the signal interference, improves the signal transmission quality of the CPU and the internal memory, and realizes higher interconnection frequency between the CPU and the internal memory.
The CPU module packaging method further packages the 3D three-dimensional structure of the CPU and the memory particle chip into a device, and uses the substrate electrically connected with the bottom surface of the 3D three-dimensional structure as an external signal pin of the CPU module. The CPU and the memory are completely packaged into a device instead of independent devices, so that a communication circuit between the CPU and the memory is not required to be designed to ensure the quality of a high-speed signal when the PCB is designed, the complexity of the circuit is reduced, the design difficulty of the PCB main board is reduced, the design success rate of the PCB main board is improved, and the design period of the PCB main board is shortened.
In one embodiment, a die subunit includes: a base die subunit and a plurality of memory interface die subunits. The base die subunit forms the bottom surface of the 3D three-dimensional structure, and the plurality of memory interface die subunits form the side surface of the 3D three-dimensional structure.
In one embodiment, the signal pins of the 3D volume structure are disposed on the sides and bottom of the outer surface of the 3D volume structure. The arrangement on the outer surface can facilitate the connection of the substrate and the memory particle chip with the 3D three-dimensional structure.
In one embodiment, the die subunits on the side surfaces and the die subunits on the bottom surface are connected by gold wire bonding, and the memory particle chip is connected with the side surfaces of the 3D three-dimensional structure through gold wires. The gold bonding wire is used as a main connecting material of the chip and an external circuit, has good corrosion resistance and conductivity, and can achieve extremely high bonding speed.
In one embodiment, signal pins related to memory particle chip signals are led out from the side face of the 3D three-dimensional structure, and other signal pins unrelated to the memory particle chip signals are led out from the bottom face of the 3D three-dimensional structure, and the other signal pins refer to power supply pins, ground signal pins, control signal pins and the like. The three-dimensional pins of the 3D three-dimensional structure are reasonably distributed, and reasonable area distribution of the signal pins is realized, so that each bare chip subunit can respectively perform its own functions, specific functions are exerted, mutual interference among different signals is reduced, and the follow-up modularization and standardization design of the bare chip subunits is favorably realized.
In one embodiment, the substrate is made into a structure with an upper surface and a lower surface, the upper surface of the substrate is electrically connected and tightly attached with the outer surface of the bottom surface of the 3D three-dimensional structure, and the lower surface of the substrate is provided with external signal pins of the CPU module. The design of the substrate in the application enables the CPU and the memory which are packaged into one device to be flexibly connected with the peripheral circuit. The substrate may be a dielectric substrate with high frequency and low dielectric loss, such as a Polytetrafluoroethylene (PTFE) substrate, a thermosetting ppo (polyphenylene oxide), a cross-linked polybutadiene substrate, and an epoxy resin composite substrate (FR-4).
According to the second aspect of the present application, there is also provided a CPU module obtained by using the above-mentioned CPU module packaging method, referring to fig. 4 and 5, the CPU module includes a CPU die, a memory particle chip 20, a packaging layer, and a substrate 30.
The CPU bare chip comprises a plurality of bare chip subunits 11, the bare chip subunits 11 are assembled into a 3D three-dimensional structure 10 with an opening on the bottom surface, side surfaces and the top, the bare chip subunits 11 on the side surfaces are electrically connected with the bare chip subunits 11 on the bottom surface, and signal pins are reserved on the side surfaces and the bottom surface of the 3D three-dimensional structure 10. The memory particle chip 20 is closely attached to the side of the 3D three-dimensional structure 10, and is connected to a signal pin on the side of the 3D three-dimensional structure 10. The encapsulation layer is used to encapsulate the CPU die and the memory particle chip 20. The substrate 30 is disposed on the bottom surface of the 3D three-dimensional structure 10, and is connected to the signal pins on the bottom surface of the 3D three-dimensional structure 10, and is used as external signal pins of the CPU module formed by the 3D three-dimensional structure 10 and the memory particle chips 20.
In the technical scheme of the application, the plane structure form of the original CPU bare chip is changed, the signal transmission distance between the CPU and the internal memory is greatly shortened, the signal interference is reduced, the signal transmission quality of the CPU and the internal memory is improved, and the higher interconnection frequency between the CPU and the internal memory is realized. And, utilize the packaging layer to encapsulate 3D spatial structure 10 and the internal memory granule chip 20 of CPU into a device, and no longer are the independent device of each other, therefore, when carrying on PCB design, need not to design the communication circuit between CPU and the internal memory again in order to guarantee the quality of the high-speed signal, reduce the complexity of the circuit, thus reduce the design difficulty of the PCB mainboard, improve the design success rate of the PCB mainboard, shorten the design cycle of the PCB mainboard.
It should be noted that the top of the 3D three-dimensional structure 10 is open, which facilitates the heat dissipation of the CPU module. And, 3D spatial structure 10's open-top, its inside cavity can be used for placing the enhancement support, and/or fill the heat conduction material, further improves heat dissipation cooling effect.
In one embodiment, the plurality of die subunits 11 includes a base die subunit 111 and a plurality of memory interface die subunits 112. The base die subunit 111 forms a bottom surface of the 3D three-dimensional structure 10, and the plurality of memory interface die subunits 112 form a side surface of the 3D three-dimensional structure 10. The plurality of die subunits 11 include a basic die subunit 111, i.e., a die subunit 11 classified according to functions of the CPU die and fabricated according to the kinds of functions. The arrangement separates the signal pins of the memory from other signal pins, the bare chip subunits 11 on the side are only responsible for signal communication with the memory, and the bare chip subunits 11 on the bottom are responsible for power connection with a main board circuit, control signal communication and the like, so that each bare chip subunit 11 can respectively perform its own function, perform its specific function and reduce mutual interference among different signals.
In one embodiment, the signal pins of the 3D volumetric structure 10 are disposed on the sides and bottom of the outer surface of the 3D volumetric structure 10. Specifically, the memory interface die subunit 112 includes an inner surface and an outer surface, the inner surfaces of the plurality of memory interface die subunits 112 form an inner wall of the inner cavity of the 3D three-dimensional structure 10, and the outer surfaces of the plurality of memory interface die subunits 112 form peripheral side surfaces of the 3D three-dimensional structure 10. The base die subunit 111 includes a first surface and a second surface, the first surface of the base die subunit 111 is a bottom surface of the 3D three-dimensional structure 10 and is closely attached to and electrically connected to the substrate 30, and the second surface of the base die subunit 111 is gold-wire bonded to the memory interface die subunit 112.
It should be noted that the outer surface of the memory interface die subunit 112 is provided with signal pins related to signals of the memory particle chips 20, and one or more of the memory particle chips 20 are tightly attached to and electrically connected to the outer surface of the memory interface die subunit 112. According to the actual application requirements, the memory particle chip 20 may also be a memory particle or a memory chip with different capacity specifications, and the memory interface die subunit 112 with a predetermined size may also be customized according to the specification of the memory particle chip 20, and one or more memory particle chips 20 are disposed on the outer surface thereof to meet different requirements.
In one embodiment, base die subunit 11 is polygonal, and the number of memory interface die subunits 112 is equal to the number of sides of base die subunit 111. The polygon is a shape which is easy to process, the basic bare chip subunit 11 can be customized into various forms such as triangle, quadrangle and pentagon, the number of the corresponding edges of the memory interface bare chip subunit 112 and the basic bare chip subunit 11 is equal, so that various packaging specifications can be realized, and the design requirements of different PCB main boards can be met.
Referring to fig. 4, fig. 6 and fig. 7, 3 different forms of CPU die structures are respectively shown, where fig. 4 is a rectangular parallelepiped with an open top and a square bottom surface, fig. 6 is a triangular frustum with an open top and a triangular bottom surface, and fig. 7 is a pentagonal prism with an open top and a regular pentagonal bottom surface. The bottom surfaces of the 3D solid structures 10 of the CPU dies shown in fig. 4, 6 and 7 are all polygons with equal side lengths, which is beneficial for subsequent standardized production and also beneficial for forming standardized package sizes of various specifications. It should be noted that the bottom surface of the 3D three-dimensional structure 10 in the present application is not limited to the type shown in fig. 4, 6 and 7, and may be other equilateral or non-equilateral polygons. In addition, the memory interface die subunit 112 on the side surface may also be in a shape other than a rectangle or a square, and as can be seen from fig. 6, the memory interface die subunit 112 is in a trapezoidal shape and is non-perpendicularly connected to the base die subunit 111 on the bottom surface to form a certain included angle for installation, and this included angle structural form can reduce the overall height of the 3D three-dimensional structure 10, and is suitable for a scenario with a low motherboard installation height.
In one embodiment, referring to fig. 8 and 9, the CPU module further includes support ribs 40, and the support ribs 40 connect the base die subunit 111 and the memory interface die subunit 112. The support ribs 40 form a stable structural connection between the basic die subunit 111 and the memory interface die subunit 112, so that the problem of signal connection caused by bending at the circuit connection position between the basic die subunit 111 and the memory interface die subunit 112 is prevented, and the support ribs 40 play a role in reinforcing the 3D three-dimensional structure 10 and ensuring stable circuit connection. The support rib 40 may be made of the same material as the substrate 30 or the CPU die.
In one embodiment, referring to fig. 8, the number of support ribs 40 is the same as the number of memory interface die subunits 112, each support rib 40 connecting a base die subunit 111 and one memory interface die subunit 112. The above structure enables each memory interface die subunit 112 to form an effective reinforcing structure with the base die subunit 111.
In one embodiment, referring to fig. 9, a plurality of support ribs 40 are distributed across the internal cavity of the 3D three-dimensional structure 10, such that each memory interface die subunit 112 can be connected to the base die subunit 111 via the support ribs 40. The supporting rib 40 of the above structure is an intercrossed integral structure, and the integral structure reinforces and connects the memory interface die sub-units 112 and the base die sub-unit 111 together. Because the cross-distributed support ribs 40 not only connect the memory interface die subunit 112 and the base die subunit 111, but also connect a plurality of memory interface die subunits 112 to each other, the effect of using a plurality of support ribs 40 for individual reinforcement is superior.
It should be noted that the structure of the supporting rib 40 is not limited to the two structures shown in fig. 8 and fig. 9, and any structure capable of supporting the memory interface die subunit 112 falls within the scope of the present application.
In one embodiment, referring to fig. 9, the CPU module further comprises a thermally conductive layer 50, the thermally conductive layer 50 being disposed in the interior cavity of the 3D volumetric structure 10. The heat conducting layer 50 is matched with the internal cavity of the 3D three-dimensional structure 10, and specifically, the heat conducting layer 50 is coated on the inner surfaces of the memory interface die subunit 112 and the base die subunit 111 to further enlarge the heat dissipation area and improve the heat dissipation effect. The heat conduction layer 50 may be made of one of pure white heat conduction silicone grease, ceramic heat conduction silicone grease, silver-containing heat conduction silicone grease, gold-containing heat conduction silicone grease, diamond heat conduction silicone grease, liquid metal, and the like.
In one embodiment, referring to fig. 9, the CPU module further includes a heat conducting structure 60, and one end of the heat conducting structure 60 is connected to the heat conducting layer 50, and the other end is connected to the outside. The heat conduction structure 60 can fully conduct the heat of the 3D three-dimensional structure 10 to the outside, the heat conduction structure 60 can be tightly attached to the heat conduction layer and led out from the top surface of the 3D three-dimensional structure 10, and the heat conduction structure 60 is beneficial to faster and better heat dissipation. The heat conducting structure 60 may be a metal heat conducting structure such as a heat conducting copper block or a heat conducting copper pipe.
In one embodiment, the CPU module further includes an enclosure that encloses structures other than the pairs of signal pins of the substrate 30. The packaging shell structure plays a good role in protecting the whole CPU module and the internal circuit connection thereof. The packaging shell can be made of metal, ceramic, plastic and the like, and metal packaging, ceramic packaging, plastic packaging and the like are correspondingly realized.
According to a third aspect of the present application, there is also provided a main board including the CPU module in the above-described embodiments. By adopting the mainboard of the CPU module, the design difficulty is greatly reduced, the design success rate of the mainboard is improved, and the design period of the mainboard is shortened.
According to a fourth aspect of the present application, there is also provided a server including the main board in the above embodiments.
According to a fifth aspect of the present application, there is also provided an arithmetic device including the main board in the above-described embodiment.
The mainboard that computing equipment such as server adopted the CPU module preparation of this application embodiment because the mainboard need not to redesign the communication circuit between CPU and the memory when designing, reduces the complexity of circuit to reduce the design degree of difficulty of mainboard, improve the design success rate of PCB mainboard, shorten the design cycle of PCB mainboard, and then reduce the research and development cost of mainboard, thereby also can reduce the mainboard design and the cost of manufacture of computing equipment such as server. Moreover, the CPU module greatly shortens the signal transmission distance between the CPU and the internal memory, reduces signal interference, improves the signal transmission quality of the CPU and the internal memory, realizes higher interconnection frequency between the CPU and the internal memory, and further improves the performance of the operation equipment such as the server and the like.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A CPU module packaging method is characterized by comprising the following steps:
classifying functions of a CPU bare chip, manufacturing corresponding bare chip subunits according to the types of the functions, assembling a plurality of bare chip subunits to form a 3D (three-dimensional) structure with an opening on the bottom surface, the side surface and the top, and electrically connecting the bare chip subunits on the side surface with the bare chip subunits on the bottom surface;
reserving signal pins on the side surface and the bottom surface of the 3D three-dimensional structure;
connecting a memory particle chip matched with the CPU bare chip on a signal pin on the side face of the 3D three-dimensional structure, wherein the memory particle chip is tightly attached to the side face of the 3D three-dimensional structure;
arranging a substrate which is electrically connected with the signal pins on the bottom surface of the 3D three-dimensional structure;
and packaging the 3D three-dimensional structure and the memory particle chip to form a CPU module, wherein the substrate is used as an external signal pin of the CPU module.
2. The CPU module packaging method of claim 1, wherein the die subunit comprises: a base die subunit and a plurality of memory interface die subunits;
the base die subunit forms a bottom surface of the 3D volumetric structure;
the plurality of memory interface die subunits form sides of the 3D solid structure.
3. The method for packaging the CPU module according to claim 1 or 2, wherein the signal pins of the 3D solid structure are disposed on the side surface and the bottom surface of the outer surface of the 3D solid structure.
4. A CPU module, comprising:
the CPU bare chip comprises a plurality of bare chip subunits (11), wherein the bare chip subunits (11) are assembled into a 3D three-dimensional structure (10) with an opening on the bottom surface, side surfaces and a top, the bare chip subunits (11) on the side surfaces are electrically connected with the bare chip subunits (11) on the bottom surface, and signal pins are reserved on the side surfaces and the bottom surface of the 3D three-dimensional structure (10);
the memory particle chip (20) is tightly attached to the side face of the 3D three-dimensional structure (10) and is connected with the signal pin on the side face of the 3D three-dimensional structure (10);
an encapsulation layer for encapsulating the CPU die and memory particle chip (20);
and the substrate (30) is arranged on the bottom surface of the 3D three-dimensional structure (10), is connected with the signal pin on the bottom surface of the 3D three-dimensional structure (10), and is used as an external signal pin of a CPU module formed by the 3D three-dimensional structure (10) and the memory particle chip (20).
5. The CPU module according to claim 4, wherein the plurality of die subunits (11) comprises a base die subunit (111) and a plurality of memory interface die subunits (112);
the base die subunit (111) constitutes a bottom surface of the 3D volumetric structure (10);
the plurality of memory interface die subunits (112) form sides of the 3D volumetric structure (10).
6. The CPU module according to claim 4 or 5, wherein the signal pins of the 3D solid structure (10) are disposed on the side and bottom surfaces of the outer surface of the 3D solid structure (10).
7. The CPU module according to claim 5, wherein the base die subunit (11) is polygonal, and the number of the memory interface die subunits (112) is equal to the number of sides of the base die subunit (111).
8. Motherboard, characterized in that it comprises a CPU module according to any one of claims 4 to 7.
9. A server, comprising the motherboard of claim 8.
10. A computing device comprising the motherboard of claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN117313651A (en) * | 2023-11-30 | 2023-12-29 | 沐曦集成电路(上海)有限公司 | Chip function feature setting method, electronic device and medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117313651A (en) * | 2023-11-30 | 2023-12-29 | 沐曦集成电路(上海)有限公司 | Chip function feature setting method, electronic device and medium |
| CN117313651B (en) * | 2023-11-30 | 2024-02-09 | 沐曦集成电路(上海)有限公司 | Chip function feature setting method, electronic device and medium |
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