CN112765926A - Layout method and device of SRAM - Google Patents

Layout method and device of SRAM Download PDF

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Publication number
CN112765926A
CN112765926A CN202110095618.0A CN202110095618A CN112765926A CN 112765926 A CN112765926 A CN 112765926A CN 202110095618 A CN202110095618 A CN 202110095618A CN 112765926 A CN112765926 A CN 112765926A
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word line
dummy
line module
target
module
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郭燕萍
闫珍珍
许婷
卜建辉
刘海南
赵发展
罗家俊
韩郑生
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract

The invention provides a layout method and a layout device of an SRAM (static random access memory), wherein the method comprises the following steps: determining the positions of the dummy word line module, the dummy bit line module and the dummy module in the SRAM data path; determining a corresponding first layout strategy based on the target bit number and the target multiplexer number of the SRAM; determining a corresponding second layout strategy based on the number of the target words and the number of the target multiplexers; the layout of the SRAM is arranged based on a first layout arrangement strategy and a second layout arrangement strategy; therefore, when the number of words, bits and mux of the SRAM is changed, the corresponding layout strategy can be automatically determined according to the number of the words, the number of the bits and the number of the multiplexers, the SRAM memory compilers with different capacities do not need to be individually customized by manpower, the automatic splicing and expansion of the layout of the memory compiler can be efficiently realized, and the design efficiency of the memory compiler is improved.

Description

Layout method and device of SRAM
Technical Field
The invention relates to the technical field of semiconductors, in particular to a layout method and a layout device of an SRAM (static random access memory).
Background
Along with the improvement of the technology of the integrated circuit industry, the product is more and more intelligent, the internal core processing frequency is more and more high, and the functions are more and more powerful. In microprocessors and System On Chips (SOCs), the Chip area occupied by Static Random-Access memories (SRAMs) is continuously increasing, which causes the Memory delay and power consumption to increase accordingly, and high speed and low power consumption have become the development trend of future integrated circuits. Therefore, the research on the high-speed low-power consumption SRAM technology has great significance for the development of integrated circuits.
For an SRAM Memory Compiler (Memory Compiler), a user typically generates the required Memory according to a generator storing the Compiler. The area, power consumption, and speed of the resulting memory are all important to the user. To realize the SRAM with small generation area, low power consumption and high speed, the SRAM data path needs to be optimized, and then the layout method of the SRAM data path is very important.
The method adopted in the prior art generally performs layout custom design for the single-capacity SRAM, but when the number of words, bits and multiplexing mux (multiplexer) changes, the layout of the SRAM with different capacities needs to be redesigned each time, so that the layout flow is complicated, and the layout efficiency cannot be ensured.
Disclosure of Invention
Aiming at the problems in the prior art, the embodiment of the invention provides a layout method and a layout device of an SRAM (static random access memory), which are used for solving the technical problems that when the layout of the SRAMs with different capacities is required in the prior art, the SRAMs with the corresponding capacities are required to be individually customized, so that the layout flow of the SRAM is complicated, and the layout efficiency cannot be ensured.
The invention provides a layout method of an SRAM (static random access memory), which comprises the following steps:
determining the positions of the dummy word line module, the dummy bit line module and the dummy module in a data path of the SRAM;
acquiring the target bit number, the target word number and the target multiplexer number of the SRAM, and determining a corresponding first layout strategy based on the target bit number and the target multiplexer number; determining a corresponding second layout strategy based on the number of the target words and the number of the target multiplexers;
and carrying out layout on the layout of the SRAM based on the first layout strategy and the second layout strategy.
In the above scheme, the method further comprises:
when the port of the SRAM is dual-ported, determining the dummy word line module comprises: a first dummy sub-line module and a second dummy word line module; the dummy bit line module includes: a first dummy bit line module and a second dummy bit line module; the dummy module includes: a first dummy module and a second dummy module; wherein the content of the first and second substances,
the first dummy word line module and the second dummy word line module each include: a first word line module, a second word line module and a third word line module; the first word line module, the second word line module and the third word line module comprise three rows and four columns of memory cells; the word lines in the first word line module are in a connected state, the word lines of the second word line module and the third word line module are in a disconnected state, and the word line disconnection positions of the second word line module and the third word line module are different.
In the foregoing solution, the determining a corresponding first layout policy based on the target number of bits and the target number of multiplexers includes:
when the target bit number M is an even number, M/2 is an even number, and the target multiplexer number mux is 4, the layout strategy corresponding to the first dummy word line module includes: sequentially laying out M/4 first word line modules, 1 second word line module and (M/4) -1 first word line module based on the position of the first virtual word line module in the data path;
when the target bit number M is an even number, M/2 is an odd number, and mux is 4, the first layout strategy corresponding to the first dummy word line module includes: placing [ (M/2) -1]/2 first word line modules, 1 third word line module and [ (M/2) -1]/2 first word line modules in sequence based on the position of the first virtual word line module in the data path;
when the target bit number M is an odd number, (M-1)/2 is an even number, and the mux is 4, the first layout strategy corresponding to the first dummy word line module includes: sequentially laying out (M-1)/4 of the first word line modules, 1 of the third word line modules and (M-1)/4 of the first word line modules based on the position of the first dummy word line module in the data path;
when the target bit number M is even, (M-1)/2 is odd, and the mux is 4, the first layout strategy corresponding to the first dummy word line module includes: (M +1)/4 of the first word line modules, 1 of the second word line modules, and [ (M +1)/4] -1 of the first word line modules are laid out in this order based on the position of the first dummy word line module in the data path.
In the foregoing solution, determining a corresponding first layout strategy based on the target number of bits and the target number of multiplexers includes:
when the target number of bits is an even number and the target number of multiplexers mux is 8 or 16, the first version layout policy corresponding to the first dummy word line module includes: sequentially laying out (mux M)/16 first word line modules, 1 second word line module and [ (mux M)/16] -1 first word line module based on the position of the first virtual word line module in the data path;
when the target bit number M is an odd number and the mux is 8 or 16, a first layout strategy corresponding to the first dummy word line module includes: based on the location of the first dummy wordline module in the data path, [ mux (M +1) ]/16 of the first wordline modules, 1 of the second wordline modules, and [ mux (M +1)/16] -1 of the first wordline modules are laid out in sequence.
In the foregoing solution, determining a corresponding first layout strategy based on the target number of bits and the target number of multiplexers includes:
when the target number of bits M is an even number, M/2 is an even number, and the target number of multiplexers mux is 4, the first layout strategy corresponding to the second dummy word line module includes: sequentially laying out M/4 first word line modules, 1 second word line module and (M/4) -1 first word line module based on the position of a second virtual word line module in the data path;
when the target bit number M is an even number, M/2 is an odd number, and mux is 4, the first layout strategy corresponding to the second dummy word line module includes: placing [ (M/2) -1]/2 of the first word line modules, 1 of the third word line modules, and [ (M/2) -1]/2 of the first word line modules in sequence based on the position of the second dummy word line module in the data path;
when the target bit number M is an odd number, (M-1)/2 is an even number, and the mux is 4, the first layout strategy corresponding to the second dummy word line module includes: sequentially laying out (M-1)/4 of the first word line modules, 1 of the third word line modules and [ (M-1)/4] -1 of the first word line modules based on the position of the second dummy word line module in the data path;
when the target number of bits M is an odd number other than 3, (M-1)/2 is an odd number, and the mux is 4, the first version layout strategy corresponding to the second dummy word line module includes: based on the position of the second virtual word line module in the data path, sequentially laying out [ (M-1)/2) +1]/2 of the first word line modules, 1 of the second word line modules and [ (M-1)/2] - [ (M-1)/2+1) ]/2-1 of the first word line modules;
when the target bit number M is 3 and the mux is 4, the first layout strategy corresponding to the second dummy word line module includes: laying out 1 of the first word line modules based on a location of the second dummy word line module in the data path.
In the foregoing solution, determining a corresponding first layout strategy based on the target number of bits and the target number of multiplexers includes:
when the target number of bits M is an even number and the target number of multiplexers mux is 8 or 16, the first layout strategy corresponding to the second dummy word line module includes: sequentially laying out (mux M)/16 first word line modules, 1 second word line module and [ (mux M)/16] -1 first word line module based on the position of the second dummy word line module in the data path;
when the target number of bits M is an odd number other than 3 and the mux is 8 or 16, the first layout strategy corresponding to the second dummy word line module includes: sequentially laying out [ mux x (M +1) ]/16 of the first wordline modules, 1 of the second wordline modules, and mux x (M-1)/8-mux x (M +1)/16-1 of the first wordline modules based on a position of the second dummy wordline module in the data lane;
when the target number of bits M is 3 and the mux is 8 or 16, the first layout strategy corresponding to the second dummy word line module includes: sequentially laying out [ mux (M +1) ]/16 of the first wordline modules based on a location of the second dummy wordline module in the datapath.
In the foregoing solution, determining a corresponding second layout strategy based on the number of the target words and the number of the target multiplexers includes:
determining, for a first dummy bit line module and a second dummy bit line module, a number of memory cell structures included in the first dummy bit line module and the second dummy bit line module according to N/(2 × mux), the memory cell structures including: memory cells of two rows and one column;
sequentially laying out the memory cell structures according to a preset layout direction based on the positions of the first dummy bit line module and the second dummy bit line module in the data path; wherein the content of the first and second substances,
the N is the number of the target words, the mux is the number of the target multiplexers, and word lines of the first dummy bit line module and the second dummy bit line module are connected with a common ground terminal VSS; the first bit line of each memory cell in the first dummy bit line module is connected with a first dummy bit line, and the second bit line of each memory cell in the first dummy bit line module is connected with a power supply VDD; the first bit line of each memory cell in the second dummy bit line module is connected to the VDD, and the second bit line of each memory cell in the second dummy bit line module is connected to the second dummy bit line.
In the foregoing solution, determining a corresponding second layout strategy based on the number of the target words and the number of the target multiplexers includes:
determining, for a second dummy module, a number of the second dummy module from N/(2 x mux); the number of the first dummy modules comprises 1; the first dummy module comprises three rows and one column of storage units; wherein the content of the first and second substances,
n does target word quantity, the mux is target multiplexer quantity, first dummy module with first dummy word line module concatenation, the bit line connection power VDD of second dummy module.
The invention also provides a layout device of the SRAM, which comprises:
the first determining unit is used for determining the positions of the dummy word line module, the dummy bit line module and the dummy module in a data path of the SRAM;
the second determining unit is used for acquiring the target bit number, the target word number and the target multiplexer number of the SRAM and determining a corresponding first layout strategy based on the target bit number and the target multiplexer number; determining a corresponding second layout strategy based on the number of the target words and the number of the target multiplexers;
and the layout unit is used for laying out the layout of the SRAM based on the first layout strategy and the second layout strategy.
In the foregoing solution, the first determining unit is further specifically configured to:
when the port of the SRAM is dual-ported, determining the dummy word line module comprises: a first dummy word line module and a second dummy word line module; the dummy bit line module includes: a first dummy bit line module and a second dummy bit line module; the dummy module includes: a first dummy module and a second dummy module; wherein the content of the first and second substances,
the first dummy word line module and the second dummy word line module each include: a first word line module, a second word line module and a third word line module; the first word line module, the second word line module and the third word line module are memory cells in three rows and four columns; the word lines in the first word line module are in a connected state, the word lines of the second word line module and the third word line module are in a disconnected state, and the word line disconnection positions of the second word line module and the third word line module are different.
The invention provides a layout method and a device of an SRAM (static random access memory), wherein the method comprises the following steps: determining the positions of the dummy word line module, the dummy bit line module and the dummy module in the SRAM data path; acquiring the number of target bits, the number of target words and the number of target multiplexers of the SRAM, and determining a corresponding first layout strategy based on the number of the target bits and the number of the target multiplexers; determining a corresponding second layout strategy based on the number of the target words and the number of the target multiplexers; designing the layout of the SRAM based on the first layout strategy and the second layout strategy; therefore, when the number of words and bits of the SRAM and the number of muxs of the target multiplexer are changed, the corresponding layout strategy can be automatically determined according to the number of the words, the bits and the muxs, the SRAM with different capacities does not need to be customized independently by manpower, the automatic design and expansion of the layout of the SRAM can be realized efficiently, and the design efficiency of the layout of the SRAM can be improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 is a schematic flow chart of a layout method of an SRAM according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a first word line module according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a second word line module according to an embodiment of the present invention;
FIG. 4 is a block diagram of a third word line module according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a layout structure of a dual-port SRAM according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating the positions of a first dummy bit line module, a first dummy word line module, and a first dummy module according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating the positions of a second dummy bit line module, a second dummy word line module, and a second dummy module according to an embodiment of the present invention;
fig. 8 is a layout diagram of a first dummy word line module corresponding to a case where the number M of target bits is an even number, M/2 is an even number, and mux is 4 according to an embodiment of the present invention;
fig. 9 is a layout diagram corresponding to the first dummy word line module when the number M of the target bits is an even number, M/2 is an odd number, and mux is 4 according to the embodiment of the present invention;
fig. 10 is a layout diagram corresponding to the first dummy word line module when the target bit number M is an odd number, (M-1)/2 is an even number, and mux is 4 according to the embodiment of the present invention;
fig. 11 is a layout diagram corresponding to the first dummy word line module when the number M of the target bits is an odd number, (M-1)/2 is an odd number, and mux is 4 according to the embodiment of the present invention;
fig. 12 is a layout diagram corresponding to the first dummy word line module when the number M of the target bits is an even number and mux is 8 or 16 according to the embodiment of the present invention;
fig. 13 is a layout diagram corresponding to the first dummy word line module when the number M of the target bits is odd and mux is 8 or 16 according to the embodiment of the present invention;
fig. 14 is a layout diagram corresponding to the second dummy word line module when the target bit number M is an odd number, (M-1)/2 is an even number, and mux is 4 according to the embodiment of the present invention;
fig. 15 is a layout diagram corresponding to the second dummy word line module when the target bit number M is an odd number other than 3, (M-1)/2 is an odd number, and mux is 4 according to the embodiment of the present invention;
fig. 16 is a layout diagram corresponding to the second dummy word line module when the target bit number M is 3 and mux is 4 according to the embodiment of the present invention;
fig. 17 is a layout diagram corresponding to the second dummy word line module when the number M of the target bits is an even number and mux is 8 or 16 according to the embodiment of the present invention;
fig. 18 is a layout diagram corresponding to the second dummy word line module when the number M of the target bits is an odd number other than 3 and mux is 8 or 16 according to the embodiment of the present invention;
fig. 19 is a layout diagram corresponding to the second dummy word line module when the target bit number M is 3 and mux is 8 or 16 according to the embodiment of the present invention;
fig. 20 is a layout diagram corresponding to the first dummy bit line module according to the embodiment of the present invention;
fig. 21 is a layout diagram corresponding to a second dummy bit line module according to an embodiment of the present invention;
fig. 22 is a schematic layout diagram corresponding to the first dummy module and the second dummy module provided in the embodiment of the present invention;
fig. 23 is a schematic structural diagram of a layout device of an SRAM according to an embodiment of the present invention.
Detailed Description
The technical problems that in the prior art, when layout is carried out on SRAMs with different capacities, the SRAMs with corresponding capacities need to be individually customized, the layout flow of the SRAMs is complicated, and layout efficiency cannot be ensured are solved. The invention provides a layout method and a layout device of an SRAM (static random access memory).
In order to better understand the technical solutions, the technical solutions of the embodiments of the present specification are described in detail below with reference to the drawings and specific embodiments, and it should be understood that the specific features of the embodiments and embodiments of the present specification are detailed descriptions of the technical solutions of the embodiments of the present specification, and are not limitations of the technical solutions of the present specification, and the technical features of the embodiments and embodiments of the present specification may be combined with each other without conflict.
The embodiment provides a layout method of an SRAM, which is applied to a storage compiler, and as shown in fig. 1, the method includes:
s110, determining the positions of the dummy word line module, the dummy bit line module and the dummy module in the SRAM data path;
here, the storage compiler may be understood as an application tool for generating SRAMs of different capacities. The method provided by the embodiment of the invention can not only expand the layout of the SRAM with the existing capacity, but also carry out layout for the layout of a new SRAM independently.
Because the SRAM in this embodiment is a dual port, that is, the port is divided into two paths, before determining the positions of the dummy word line module, the dummy bit line module, and the dummy module in the SRAM data path, the method further includes:
when the SRAM is dual-ported (i.e., each memory cell is a dual-ported memory cell), determining the dummy word line module includes: a first dummy sub-line module and a second dummy word line module; the dummy bit line module includes: a first dummy bit line module and a second dummy bit line module; the dummy module includes: a first dummy module and a second dummy module; wherein, the first dummy word line module and the second dummy word line module both include: a first word line module, a second word line module and a third word line module; the first word line module, the second word line module and the third word line module comprise three rows and four columns of memory cells; the word lines in the first word line module are in a connected state, the word lines of the second word line module and the third word line module are in a disconnected state, and the word line disconnection positions of the second word line module and the third word line module are different.
It should be noted that a dummy word line block, a dummy bit line block, and a dummy block are included in each SRAM. For example, assuming that the ports include port a and port B, each SRAM includes: a word line WLA of port A, a bit line BLA of port A; word line WLB for port B, bit line BLB for port B. Since the bit lines are typically present in pairs, port A also includes bit line BLA _ corresponding to bit line BLA, and port B also includes bit line BLB _ corresponding to bit line BLB.
Specifically, the structure of the first wordline block may refer to fig. 2, the structure of the second wordline block may refer to fig. 3, and the structure of the third wordline block may refer to fig. 4. As can be seen from fig. 2, WLA of a first row of Memory cells (Memory cells) included in the first word line module is connected to a common ground VSS, and WLB is also connected to VSS; WLA and WLB of the second and third rows of memory cells are connected to VSS or to dummy bit lines, depending on the location.
As can be seen in FIG. 3, the off position of the second word line block is at row 2, column 1 and column 3, column 1; WLA of the memory cells in row 2, column 1 and row 3, column 1 is connected to a dummy word line MWLA, WLB of the memory cells in row 2, column 1 and row 3, column 1 is connected to a dummy word line MWLB; WLA and WLB of the other memory cells are connected to VSS. That is, in fig. 3, word lines of memory cells in the left portion of the off position of the second word line block are connected to corresponding dummy word lines, and the right portion serves as a load.
As can be seen in FIG. 4, the off position of the third word line block is at row 2, column 2 and row 3, column 3 positions; WLA of the memory cells of row 2, column 1, row 2, column 3, row 3, column 1, row 3, column 2, and column 3 are connected to a dummy word line MWLA, and WLB and MWLB of the memory cells of row 3, column 3 are connected; WLA and WLB of the other memory cells are connected to VSS. That is, in fig. 4, word lines of memory cells in the left portion of the off position of the third word line block are connected to the corresponding dummy word lines, and the right portion serves as a load.
Here, for an SRAM with a certain capacity, when the layout of the SRAM is expanded, in this embodiment, in order to generate an on-chip clock signal GTP by simulating an external clock, a dummy word line and a dummy bit line are expanded in an original storage array of the SRAM, and then the dummy word line includes: a first dummy word line MWLA for port A and a second dummy word line MWLB for port B; the dummy bit line includes: a first dummy bit line MBLA for port A and a second dummy bit line MBLB for port B.
The positions of the dummy word line block, the dummy bit line block, and the dummy block in the SRAM data path are then determined.
Referring to fig. 5, the layout of the dual port SRAM includes a data path layout, a clock control layout, and a decoding layout. In the embodiment, the dummy word line module, the dummy bit line module and the dummy module are all positioned in the data path layout; wherein the data path includes: a first data path DP _ XR _ RIGHT and a second data path DP _ XL _ LEFT. The first data path is located on the right side of the clocking and decoding layout and the second data path is located on the left side of the clocking and decoding layout.
Referring to fig. 6, after the SRAM layout is expanded, in the first data path, the first dummy bit line module is located on the left side of the right storage array, the first dummy word line module is located above the right storage array, the first dummy module is located on the right side of the right storage array, and the column gate, the sense amplifier, and the IO circuit are further connected below the right storage array. As can be seen from fig. 6, the first dummy bit line block, the first dummy word line block, and the first dummy block have a reference R0, which illustrates that the first dummy bit line block, the first dummy word line block, and the first dummy block do not need to be flipped in the layout.
Referring to fig. 7, after the SRAM layout is expanded, in the second data path, the second dummy bit line module is located on the right side of the left storage array, the second dummy word line module is located above the left storage array, the second dummy module is located on the left side of the left storage array, and the column gate, the sense amplifier, and the IO circuit are further connected below the left storage array. And the second dummy word line module, the second dummy bit line module and the second dummy module are arranged in the layout after being overturned along the Y axis in consideration of the integral symmetrical layout. As can be seen from fig. 7, the second dummy bit line module, the second dummy word line module, and the second dummy module have a mark MY, which indicates that the second dummy bit line module, the second dummy word line module, and the second dummy module need to be flipped along the Y-axis in the layout, so that the layout can be symmetrical in the layout, and the routing distance can be reduced.
It should be noted that the dummy word line module is located at the farthest place in the layout from the word line driving circuit, and then the feedback circuit will automatically include the influence of the metal connection line on the bit line delay, so as to implement self-timing. The self-timing strategy can more accurately cut off the gating of the word line, stop the discharge of the bit line and reduce the swing of the bit line, thereby being more beneficial to reducing the power consumption of the SRAM.
S111, acquiring the number of target bits, the number of target words and the number of target multiplexers of the SRAM, and determining a corresponding first layout strategy based on the number of the target bits and the number of the target multiplexers; determining a corresponding second layout strategy based on the number of the target words and the number of the target multiplexers;
it should be noted that the target bit number M is the number of data lanes; the relationship between the number of target bits M and the target bit line BL is: BL — M × mux, and the target bit line BL is the total number of columns of memory cells.
The relationship between the target word line WL and the target word N is: WL ═ N/mux, target word line WL is the number of rows of memory cells.
Thus, after the number of target word lines WL, target bit lines BL, and target multiplexers are determined, the target number of bits M and the target number of words N may be determined.
The layout expansion of the first virtual word line module and the second virtual word line module is influenced by a bit M and a mux, when M is an even number, the first virtual word line module and the second virtual word line module are symmetrical, and the layout mode is the same; when M is an odd number, the first virtual word line module and the second virtual word line module are asymmetric, and the layout modes are different.
Therefore, after the positions of the dummy word line module, the dummy bit line module and the dummy module in the data path of the SRAM are determined, the target bit number M, the target word number N and the target multiplexer number mux of the SRAM are obtained, and the corresponding first layout strategy, the target word number N and the target multiplexer number are determined based on the target bit number M and the target multiplexer number mux to determine the corresponding second layout strategy. It should be noted that in the embodiment of the present invention, the number M of target bits is at least 2, and the number N of target words is at least 128.
As an alternative embodiment, determining the corresponding first layout placement strategy based on the target number of bits and the target number of multiplexers includes:
when the target bit number M is an even number, M/2 is an even number, and mux is 4, the layout strategy corresponding to the first dummy word line module includes: in the front view of the layout, based on the position of the first dummy word line module in the first data path, M/4 first word line modules, 1 second word line module and (M/4) -1 first word line module are sequentially laid out from left to right. The layout in this case can be referred to fig. 8.
For example, when M is 4, the corresponding layout strategy includes: 1 first word line module and 1 second word line module are arranged from left to right in sequence.
When the target number of bits M is even, M/2 is odd, and mux is 4, the first layout strategy corresponding to the first dummy word line module includes: in the front view of the layout, based on the position of the first virtual word line module in the first data path, the [ (M/2) -1]/2 first word line modules, the 1 third word line module and the [ (M/2) -1]/2 first word line modules are arranged from left to right in sequence. The layout in this case can be referred to fig. 9.
For example, when M is 6, 1 first word line module, 1 third word line module, and 1 first word line module are laid out in order from left to right.
When the target number of bits M is odd, (M-1)/2 is even, and mux is 4, the first layout strategy corresponding to the first dummy word line module includes: sequentially laying out (M-1)/4 first word line modules, 1 third word line module and (M-1)/4 first word line modules based on the position of the first virtual word line module in the first data path; the layout in this case can be referred to fig. 10.
For example, when M is 5, 1 first word line module, 1 third word line module, and 1 first word line module are laid out in order from left to right.
When the target number of bits M is even, (M-1)/2 is odd, and mux is 4, the first layout strategy corresponding to the first dummy word line module includes: sequentially laying out (M +1)/4 first word line modules, 1 second word line module and [ (M +1)/4] -1 first word line module based on the position of the first virtual word line module in the first data path; the layout in this case can be referred to fig. 11.
For example, when M is 7, 2 first word line blocks, 1 third word line block, and 1 first word line block are laid out in order from left to right.
As an alternative embodiment, when the target bit number M is an even number and mux is 8 or 16, the first version layout strategy corresponding to the first dummy word line module includes: sequentially laying out (mux M)/16 first word line modules, 1 second word line module and [ (mux M)/16] -1 first word line module based on the position of the first virtual word line module in the first data path; the layout in this case can be referred to fig. 12.
For example, when M is 2 and mux is 8, 1 first word line block and 1 second word line block are laid out sequentially from left to right.
When the target number of bits M is an odd number and mux is 8 or 16, the first layout strategy corresponding to the first dummy word line module includes: based on the position of the first virtual word line module in the first data path, sequentially laying out [ mux (M +1) ]/16 first word line modules, 1 second word line module and [ mux (M +1)/16] -1 first word line module from left to right; the layout in this case can be referred to fig. 13.
For example, when M is 3 and mux is 8, 2 first word line blocks, 1 second word line block, and 1 first word line block are laid out in order from left to right.
Similarly, for the second dummy word line module, determining a corresponding first layout placement strategy based on the target number of bits and the target number of multiplexers includes:
when the target number of bits M is an even number, M/2 is an even number, and mux is 4, the first layout strategy corresponding to the second dummy word line module includes: based on the position of the second virtual word line module in the second data path, sequentially laying out M/4 first word line modules, 1 second word line module and (M/4) -1 first word line module from left to right; in this case, the layout mode is the same as that of the first dummy word line module, and the layout can refer to fig. 8, which is not described herein again.
When the target number M is even, M/2 is odd, and mux is 4, the first layout strategy corresponding to the second dummy word line module includes: based on the position of the second virtual word line module in the second data path, sequentially laying out [ (M/2) -1]/2 first word line modules, 1 third word line module and [ (M/2) -1]/2 first word line modules from left to right; in this case, the layout mode is the same as that of the first dummy word line module, and the layout can refer to fig. 9, which is not described herein again.
When the target number of bits M is odd, (M-1)/2 is even, and mux is 4, the first layout strategy corresponding to the second dummy word line module includes: sequentially laying out (M-1)/4 first word line modules, 1 third word line module and [ (M-1)/4] -1 first word line module from left to right based on the position of the second virtual word line module in the second data path; the layout in this case can be referred to fig. 14.
For example, when M is 5, 1 first word line module and 1 third word line module are laid out in sequence from left to right.
When the target number of bits M is an odd number other than 3, (M-1)/2 is an odd number, and mux is 4, the first layout strategy corresponding to the second dummy word line module includes: based on the position of the second virtual word line module in the second data path, sequentially laying out [ (M-1)/2) +1]/2 first word line modules, 1 second word line module and [ (M-1)/2] - [ (M-1)/2+1) ]/2-1 first word line modules; the layout in this case can be referred to fig. 15.
For example, when M is 7, 2 first word line modules and 1 second word line module are laid out in sequence from left to right.
When the target number of bits M is 3 and mux is 4, the first layout strategy corresponding to the second dummy word line module includes: laying out 1 first word line module based on the position of the second dummy word line module in the second data path; the layout in this case can be referred to fig. 16.
When mux is 8 or 16, as an alternative embodiment, determining the corresponding first version layout strategy based on the target number of bits and the target number of multiplexers includes:
when the target number M is an even number and mux is 8 or 16, the first layout strategy corresponding to the second dummy word line module includes: sequentially laying out (mux M)/16 first word line modules, 1 second word line module and [ (mux M)/16] -1 first word line module from left to right based on the position of the second dummy word line module in the second data path; the layout in this case can be referred to fig. 17.
For example, when M is 2 and mux is 8, 1 first word line block and 1 second word line block are laid out sequentially from left to right.
When the target number M is an odd number other than 3 and mux is 8 or 16, the first layout strategy corresponding to the second dummy word line module includes: sequentially laying out [ mux (M +1) ]/16 first word line modules, 1 second word line module and [ mux (M-1)/8-mux (M +1)/16-1] first word line modules based on the position of the second dummy word line module in the second data path; the layout in this case can be referred to fig. 18.
For example, when M is 5 and mux is 8, 3 first word line blocks and 1 second word line block are laid out sequentially from left to right.
When the target number of bits M is 3 and mux is 8 or 16, the first layout strategy corresponding to the second dummy word line module includes: sequentially laying out [ mux (M +1) ]/16 first wordline modules based on a position of a second dummy wordline module in a second datapath; the layout in this case can be referred to fig. 19.
After the first layout strategy corresponding to the first dummy word line module and the second dummy word line module is determined, the second layout strategy corresponding to the first dummy bit line module, the second dummy bit line module, the first dummy module and the second dummy module is also determined.
As an alternative embodiment, determining the corresponding second layout strategy based on the number of target words and the number of target multiplexers includes:
determining the number of memory cell structures contained in the first dummy bit line module and the second dummy bit line module according to N/(2 × mux), wherein the memory cell structures comprise: memory cells of two rows and one column;
sequentially laying out the memory cell structures according to a preset layout direction based on the positions of the first dummy bit line module and the second dummy bit line module in the corresponding data paths; wherein the content of the first and second substances,
word lines of the first dummy bit line module and the second dummy bit line module are connected with a common ground terminal VSS; the first bit line of each memory cell in the first dummy bit line module is connected with a first dummy bit line, and the second bit line of each memory cell in the first dummy bit line module is connected with a power supply VDD; the first bit line of each memory cell in the second dummy bit line block is coupled to VDD and the second bit line of each memory cell in the second dummy bit line block is coupled to the second dummy bit line. The word line of each memory cell in the first dummy module and the second dummy module is connected to VSS. The first bit line may be a bit line BLA of port a, and the second bit line may be a bit line BLB of port B; the first dummy bit line is MBLA and the second dummy bit line is MBLB. The layout corresponding to the first dummy bit line module may refer to fig. 20, and the layout corresponding to the second dummy bit line module may refer to fig. 21.
As an alternative embodiment, determining the corresponding second layout strategy based on the number of target words and the number of target multiplexers includes:
determining a number of second dummy modules from N/(2 x mux) for the second dummy modules; the number of the first dummy modules comprises 1; the first dummy module comprises memory cells of three rows and one column; wherein the content of the first and second substances,
the first dummy word line module is spliced with the first dummy word line module, the bit line of the second dummy word line module is connected with a power supply VDD, and the second dummy word line module is mainly used for providing a load. The layout of the first dummy module and the second dummy module can refer to fig. 22.
Thus, the layout strategies corresponding to the dummy word line module, the dummy bit line module and the dummy module can be determined.
In all the drawings in the present embodiment, the memory cell is the same. For any memory cell, if the label R0 exists, the memory cell does not need to be turned over; if the label R180 exists and if the label MX exists, the memory cell needs to be turned over along the X axis; if the mark MY exists, the memory cell needs to be flipped along the Y-axis.
And S112, designing the layout of the SRAM based on the first layout strategy and the second layout strategy.
After the layout strategies of the virtual word line module, the virtual bit line module and the dummy module are determined, the layout of the SRAM is designed based on the first layout strategy and the second layout strategy. Therefore, the corresponding layout strategy can be automatically determined according to the word line number, the bit line number and the mux number, SRAM with different capacities does not need to be individually customized by manpower, automatic splicing and expansion of layout of the storage compiler can be efficiently realized, and the design efficiency of the storage compiler can be further improved.
In addition, in this embodiment, an on-chip clock signal GTP may be generated by simulating an external clock CLK, a dummy word line signal MWL may be generated by GTP, the dummy word line signal may discharge the dummy bit line signal, and a reset signal RST may be triggered after the discharge is completed to reset the GTP signal to 0. In the whole feedback loop, the discharge process of the dummy word line to the dummy bit line can be accelerated, so that the RST signal is advanced, the word line is prompted to be turned off in advance, the discharge time and the swing amplitude on the bit line are controlled within a required range, and the power consumption is reduced.
It should be noted that the external clock includes CLKA and CLKB, in this embodiment, the external clock CLKA may be simulated to generate an on-chip clock signal GTPA, and the GTPA generates a dummy word line signal MWLA; the analog external clock CLKB generates an on-chip clock signal GTPB, and GTP B generates a dummy word line signal MWLB.
Based on the same inventive concept as the foregoing embodiment, an embodiment of the present invention further provides a layout apparatus of an SRAM, as shown in fig. 23, the layout apparatus includes:
a first determining unit 21 for determining positions of the dummy word line block, the dummy bit line block, and the dummy block in a data path of the SRAM;
a second determining unit 22, configured to obtain a target bit number, a target word number, and a target multiplexer number of the SRAM, and determine a corresponding first layout policy based on the target bit number and the target multiplexer number; determining a corresponding second layout strategy based on the number of the target words and the number of the target multiplexers;
and a layout unit 23, configured to layout the layout of the SRAM based on the first layout strategy and the second layout strategy.
The first determining unit 21 is specifically configured to:
when the port of the SRAM is dual-ported, determining the dummy word line module includes: a first dummy sub-line module and a second dummy word line module; the dummy bit line module includes: a first dummy bit line module and a second dummy bit line module; the dummy module includes: a first dummy module and a second dummy module; wherein the first dummy word line module and the second dummy word line module each include: a first word line module, a second word line module and a third word line module; the first word line module, the second word line module and the third word line module are memory units in three rows and four columns; the word lines in the first word line module are in a connected state, the word lines of the second word line module and the third word line module are in a disconnected state, and the word line disconnection positions of the second word line module and the third word line module are different.
Here, the positions of the dummy word line block, the dummy bit line block and the dummy block in the data path of the SRAM determined by the second determining unit 22 are described in detail above, and are not described again here. The third determining unit 23 is configured to obtain a target bit number, a target word number, and a target multiplexer number mux of the SRAM, and determine a corresponding first layout policy based on the target bit number and the target multiplexer number; the implementation of determining the corresponding second layout strategy based on the number of the target words and the number of the target multiplexers is also described in detail above, and is not described herein again. The layout unit 24 has been described in detail above for implementing the layout design of the SRAM based on the first layout strategy and the second layout strategy, and therefore, the detailed description thereof is omitted here.
The layout method and the layout device of the SRAM provided by the embodiment of the invention have the following beneficial effects that:
the invention provides a layout method and a device of an SRAM (static random access memory), wherein the method comprises the following steps: determining the positions of the dummy word line module, the dummy bit line module and the dummy module in a data path of the SRAM; acquiring the number of target bits, the number of target words and the number of target multiplexers of the SRAM, and determining a corresponding first layout strategy based on the number of the target bits and the number of the target multiplexers; determining a corresponding second layout strategy based on the number of the target words and the number of the target multiplexers; the layout of the SRAM is arranged based on the first layout arrangement strategy and the second layout arrangement strategy; therefore, when the number of words and bits of the SRAM and the number of muxs of the target multiplexer are changed, the corresponding layout strategy can be automatically determined according to the number of the words, the bits and the muxs, the SRAM with different capacities does not need to be individually customized manually, the automatic design and expansion of the layout of the SRAM can be efficiently realized, and the design efficiency of the layout of the SRAM can be further improved; the design efficiency of the storage compiler can be further improved, and the generation efficiency of the SRAM is also improved; in addition, the embodiment of the invention adds the virtual word line beside the memory array by copying the word line technology, matches the word line load, and combines the copying bit line technology to simulate the delay of an actual signal path, so as to ensure that the detection enable can reach when the swing of the bit line reaches an expected value, further accelerate the access process, reduce the swing of the bit line and achieve the effect of reducing the power consumption.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.

Claims (10)

1. A layout method of an SRAM (static random access memory), which is characterized by comprising the following steps:
determining the positions of the dummy word line module, the dummy bit line module and the dummy module in a Static Random Access Memory (SRAM) data path;
acquiring the target bit number, the target word number and the target multiplexer number of the SRAM, and determining a corresponding first layout strategy based on the target bit number and the target multiplexer number; determining a corresponding second layout strategy based on the number of the target words and the number of the target multiplexers;
and carrying out layout on the layout of the SRAM based on the first layout strategy and the second layout strategy.
2. The method of claim 1, wherein the method further comprises:
when the port of the SRAM is dual-ported, determining the dummy word line module comprises: a first dummy word line module and a second dummy word line module; the dummy bit line module includes: a first dummy bit line module and a second dummy bit line module; the dummy module includes: a first dummy module and a second dummy module; wherein the content of the first and second substances,
the first dummy word line module and the second dummy word line module each include: a first word line module, a second word line module and a third word line module; the first word line module, the second word line module and the third word line module comprise three rows and four columns of memory cells; the word lines in the first word line module are in a connected state, the word lines of the second word line module and the third word line module are in a disconnected state, and the word line disconnection positions of the second word line module and the third word line module are different.
3. The method of claim 1, wherein determining the corresponding first version placement policy based on the target number of bits and the target number of multiplexers comprises:
when the target bit number M is an even number, M/2 is an even number, and the target multiplexer number mux is 4, the layout strategy corresponding to the first dummy word line module includes: sequentially laying out M/4 first word line modules, 1 second word line module and (M/4) -1 first word line module based on the position of the first virtual word line module in the data path;
when the target bit number M is an even number, M/2 is an odd number, and mux is 4, the first layout strategy corresponding to the first dummy word line module includes: placing [ (M/2) -1]/2 first word line modules, 1 third word line module and [ (M/2) -1]/2 first word line modules in sequence based on the position of the first virtual word line module in the data path;
when the target bit number M is an odd number, (M-1)/2 is an even number, and the mux is 4, the first layout strategy corresponding to the first dummy word line module includes: sequentially laying out (M-1)/4 of the first word line modules, 1 of the third word line modules and (M-1)/4 of the first word line modules based on the position of the first dummy word line module in the data path;
when the target bit number M is even, (M-1)/2 is odd, and the mux is 4, the first layout strategy corresponding to the first dummy word line module includes: (M +1)/4 of the first word line modules, 1 of the second word line modules, and [ (M +1)/4] -1 of the first word line modules are laid out in this order based on the position of the first dummy word line module in the data path.
4. The method of claim 1, wherein determining a corresponding first version placement policy based on the target number of bits and the target number of multiplexers comprises:
when the target number of bits M is an even number and the target number of multiplexers mux is 8 or 16, the first version layout strategy corresponding to the first dummy word line module includes: sequentially laying out (mux M)/16 first word line modules, 1 second word line module and [ (mux M)/16] -1 first word line module based on the position of the first virtual word line module in the data path;
when the target bit number M is an odd number and the mux is 8 or 16, a first layout strategy corresponding to the first dummy word line module includes: based on the location of the first dummy wordline module in the data path, [ mux (M +1) ]/16 of the first wordline modules, 1 of the second wordline modules, and [ mux (M +1)/16] -1 of the first wordline modules are laid out in sequence.
5. The method of claim 1, wherein determining a corresponding first version placement policy based on the target number of bits and the target number of multiplexers comprises:
when the target number of bits M is an even number, M/2 is an even number, and the target number of multiplexers mux is 4, the first layout strategy corresponding to the second dummy word line module includes: sequentially laying out M/4 first word line modules, 1 second word line module and (M/4) -1 first word line module based on the position of a second virtual word line module in the data path;
when the target bit number M is an even number, M/2 is an odd number, and mux is 4, the first layout strategy corresponding to the second dummy word line module includes: placing [ (M/2) -1]/2 of the first word line modules, 1 of the third word line modules, and [ (M/2) -1]/2 of the first word line modules in sequence based on the position of the second dummy word line module in the data path;
when the target bit number M is an odd number, (M-1)/2 is an even number, and the mux is 4, the first layout strategy corresponding to the second dummy word line module includes: sequentially laying out (M-1)/4 of the first word line modules, 1 of the third word line modules and [ (M-1)/4] -1 of the first word line modules based on the position of the second dummy word line module in the data path;
when the target number of bits M is an odd number other than 3, (M-1)/2 is an odd number, and the mux is 4, the first version layout strategy corresponding to the second dummy word line module includes: based on the position of the second virtual word line module in the data path, sequentially laying out [ (M-1)/2) +1]/2 of the first word line modules, 1 of the second word line modules and [ (M-1)/2] - [ (M-1)/2+1) ]/2-1 of the first word line modules;
when the target bit number M is 3 and the mux is 4, the first layout strategy corresponding to the second dummy word line module includes: laying out 1 of the first word line modules based on a location of the second dummy word line module in the data path.
6. The method of claim 1, wherein determining a corresponding first version placement policy based on the target number of bits and the target number of multiplexers comprises:
when the target number of bits M is an even number and the target number of multiplexers mux is 8 or 16, the first layout strategy corresponding to the second dummy word line module includes: sequentially laying out (mux M)/16 first word line modules, 1 second word line module and [ (mux M)/16] -1 first word line module based on the position of the second dummy word line module in the data path;
when the target number of bits M is an odd number other than 3 and the mux is 8 or 16, the first layout strategy corresponding to the second dummy word line module includes: sequentially laying out [ mux x (M +1) ]/16 of the first wordline modules, 1 of the second wordline modules, and mux x (M-1)/8-mux x (M +1)/16-1 of the first wordline modules based on a position of the second dummy wordline module in the data lane;
when the target number of bits M is 3 and the mux is 8 or 16, the first layout strategy corresponding to the second dummy word line module includes: sequentially laying out [ mux (M +1) ]/16 of the first wordline modules based on a location of the second dummy wordline module in the datapath.
7. The method of claim 1, wherein determining a corresponding second layout strategy based on the target number of words and the target number of multiplexers comprises:
determining, for a first dummy bit line module and a second dummy bit line module, a number of memory cell structures included in the first dummy bit line module and the second dummy bit line module according to N/(2 × mux), the memory cell structures including: memory cells of two rows and one column;
sequentially laying out the memory cell structures according to a preset layout direction based on the positions of the first dummy bit line module and the second dummy bit line module in the data path; wherein the content of the first and second substances,
the N is the number of the target words, the mux is the number of the target multiplexers, and word lines of the first dummy bit line module and the second dummy bit line module are connected with a common ground terminal VSS; the first bit line of each memory cell in the first dummy bit line module is connected with a first dummy bit line, and the second bit line of each memory cell in the first dummy bit line module is connected with a power supply VDD; the first bit line of each memory cell in the second dummy bit line module is connected to the VDD, and the second bit line of each memory cell in the second dummy bit line module is connected to the second dummy bit line.
8. The method of claim 1, wherein determining a corresponding second layout strategy based on the target number of words and the target number of multiplexers comprises:
determining, for a second dummy module, a number of the second dummy module from N/(2 x mux); the number of the first dummy modules comprises 1; the first dummy module comprises three rows and one column of storage units; wherein the content of the first and second substances,
n does target word quantity, the mux is target multiplexer quantity, first dummy module with first dummy word line module concatenation, the bit line connection power VDD of second dummy module.
9. A layout device of SRAM, the device comprising:
the first determining unit is used for determining the positions of the dummy word line module, the dummy bit line module and the dummy module in a data path of the Static Random Access Memory (SRAM);
the second determining unit is used for acquiring the target bit number, the target word number and the target multiplexer number of the SRAM and determining a corresponding first layout strategy based on the target bit number and the target multiplexer number; determining a corresponding second layout strategy based on the number of the target words and the number of the target multiplexers;
and the layout unit is used for laying out the layout of the SRAM based on the first layout strategy and the second layout strategy.
10. The apparatus of claim 9, wherein the first determination unit is further to:
when the port of the SRAM is dual-ported, determining the dummy word line module comprises: a first dummy sub-line module and a second dummy word line module; the dummy bit line module includes: a first dummy bit line module and a second dummy bit line module; the dummy module includes: a first dummy module and a second dummy module; wherein the content of the first and second substances,
the first dummy word line module and the second dummy word line module each include: a first word line module, a second word line module and a third word line module; the first word line module, the second word line module and the third word line module are memory cells in three rows and four columns; the word lines in the first word line module are in a connected state, the word lines of the second word line module and the third word line module are in a disconnected state, and the word line disconnection positions of the second word line module and the third word line module are different.
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