CN112765925A

CN112765925A - Interconnected circuit system, verification system and method

Info

Publication number: CN112765925A
Application number: CN202110380287.5A
Authority: CN
Inventors: 杨兵
Original assignee: Beijing Suiyuan Intelligent Technology Co ltd
Current assignee: Beijing Suiyuan Intelligent Technology Co ltd
Priority date: 2021-04-09
Filing date: 2021-04-09
Publication date: 2021-05-07
Anticipated expiration: 2041-04-09
Also published as: CN112765925B

Abstract

The embodiment of the invention discloses an interconnected circuit system, a verification system and a method. The interconnect circuitry includes: the system comprises an interconnection bus model and a protocol transaction pool, wherein the protocol transaction pool is used for receiving a protocol transaction sent by a circuit module to be tested, storing the protocol transaction, generating a transaction to be transmitted corresponding to the protocol transaction, and sending the transaction to be transmitted to the interconnection bus model; the tested circuit module comprises a host circuit module and a slave circuit module, and the protocol transaction comprises a protocol access transaction and a protocol feedback transaction; and the interconnection bus model is used for receiving the transaction to be transmitted and realizing the transmission of the transaction to be transmitted between the host circuit module and the slave circuit module. The interconnection circuit system can provide a universal interconnection channel for various bus transmission protocols and is high in reusability.

Description

Interconnected circuit system, verification system and method

Technical Field

The embodiment of the invention relates to the technical field of integrated circuits, in particular to an interconnected circuit system, a verification system and a verification method.

Background

In chip design, especially 5G and artificial intelligence chips, large-scale interconnection of core circuit modules is essential. In early development of integrated circuits, more than 70% of the workload is in the verification phase. The method is an effective way for improving verification completeness, optimizing function and performance design and shortening verification time. In this case of no interconnect circuit, an interconnect bus model is indispensable.

At present, the existing interconnection bus model cannot provide a universal interconnection channel for various bus transmission protocols, reusability is poor, the interconnection channel can only be redeveloped for different bus transmission protocols, and labor cost is high.

Disclosure of Invention

The embodiment of the invention provides an interconnection circuit system, a verification system and a method, which are used for providing a universal interconnection channel for various bus transmission protocols and realizing the support of various bus transmission protocols.

In a first aspect, an embodiment of the present invention provides an interconnect circuit system, including:

an interconnect bus model and a pool of protocol transactions, wherein,

the protocol transaction pool is used for receiving a protocol transaction sent by a circuit module to be tested, storing the protocol transaction, generating a transaction to be transmitted corresponding to the protocol transaction, and sending the transaction to be transmitted to the interconnection bus model; the tested circuit module comprises a host circuit module and a slave circuit module, and the protocol transaction comprises a protocol access transaction and a protocol feedback transaction;

and the interconnection bus model is used for receiving the transaction to be transmitted and realizing the transmission of the transaction to be transmitted between the host circuit module and the slave circuit module.

In a second aspect, an embodiment of the present invention further provides a verification system for cooperation between integrated circuit modules, including: an excitation model, a functional simulation model, a memory model, a scoreboard, and at least one interconnect circuitry according to any embodiment of the invention, wherein,

the excitation model is used for generating an instruction set, interconnection circuit system configuration information and memory model configuration information of a circuit module to be tested, respectively sending the instruction set to a host circuit module and the function simulation model, respectively sending the memory model configuration information to the memory model and the function simulation model, and respectively sending the interconnection circuit system configuration information to an interconnection circuit system and the function simulation model;

the slave circuit module is used for working in cooperation with the master circuit module and sending the slave operation actual value to the scoring board;

the function simulation model is used for simulating functions of an integrated chip comprising the host circuit module, the slave circuit module, a memory and an interconnection circuit between the host circuit module and the slave circuit module, initiating operation according to the instruction set after configuration is completed according to the interconnection circuit system configuration information and the memory model configuration information, and sending an operation expectation value to the scoring board;

the memory model is used for realizing a data storage function according to the memory model configuration information;

and the scoring board is used for verifying the cooperative work between the host circuit module and the slave circuit module according to the operation expected value, the host operation actual value and the slave operation actual value.

In a third aspect, an embodiment of the present invention further provides a method for verifying cooperative work between integrated circuit modules, including:

generating an instruction set, interconnection circuit system configuration information and memory model configuration information of a circuit module to be tested through an excitation model, respectively sending the instruction set to a host circuit module and a function simulation model, respectively sending the memory model configuration information to a memory model and the function simulation model, and respectively sending the interconnection circuit system configuration information to an interconnection circuit system and the function simulation model;

receiving a protocol transaction sent by a circuit module to be tested through the protocol transaction pool, storing the protocol transaction, generating a transaction to be transmitted corresponding to the protocol transaction, and sending the transaction to be transmitted to an interconnection bus model;

receiving the transaction to be transmitted through the interconnection bus model, and realizing the transmission of the transaction to be transmitted between the host circuit module and the slave circuit module;

realizing a data storage function through the memory model according to the memory model configuration information;

simulating the functions of an integrated chip comprising the host circuit module, the slave circuit module, a memory and an interconnection circuit between the host circuit module and the slave circuit module through the function simulation model, initiating operation according to the instruction set after completing configuration according to the interconnection circuit system configuration information and the memory model configuration information, and sending an operation expectation value to a scoring board;

initiating operation according to the instruction set through the host circuit module, and sending a host operation actual value to the scoring board;

the slave computer circuit module and the host computer circuit module work cooperatively, and the slave computer operation actual value is sent to the scoring board;

and the score board realizes the verification of the cooperative work between the host circuit module and the slave circuit module according to the operation expected value, the host operation actual value and the slave operation actual value.

The interconnection circuit system provided by the embodiment of the invention can provide a universal interconnection channel for various bus transmission protocols, has strong reusability, can realize the support of various different bus transmission protocols, and has low labor cost.

Drawings

Fig. 1 is a schematic structural diagram of an interconnect circuit system according to a first embodiment of the present invention;

FIG. 2 is a schematic diagram of a cascade of interconnect bus models in an interconnect circuit system according to a first embodiment of the present invention;

FIG. 3 is a schematic diagram of an interconnect circuitry according to one embodiment of the present invention;

FIG. 4 is a schematic diagram of an arbitration policy of a host arbitration module according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an arbitration policy of a host arbitration module according to an embodiment of the present invention;

FIG. 6 is a schematic diagram illustrating an arbitration policy of a host arbitration module according to an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a verification system for cooperation between integrated circuit modules according to a second embodiment of the present invention;

FIG. 8 is a schematic structural diagram of a verification system for cooperation between integrated circuit modules according to a second embodiment of the present invention;

FIG. 9 is a flowchart illustrating a method for verifying interoperability between integrated circuit modules according to a third embodiment of the invention;

fig. 10 is a schematic structural diagram of a verification system for cooperation between integrated circuit modules according to a fourth embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.

Example one

Fig. 1 is a schematic structural diagram of an interconnect circuit system according to an embodiment of the present invention, which is applicable to a situation where a cooperative work capability between core function modules is verified under a condition that an interconnect circuit of the core circuit module is not completed. As shown in fig. 1, the interconnect circuit system 10 provided in the present embodiment includes: an interconnect bus model 11 and a pool of protocol transactions 12, wherein,

the protocol transaction pool 12 is configured to receive a protocol transaction sent by the circuit module 60 to be tested, store the protocol transaction, generate a transaction to be transferred corresponding to the protocol transaction, and send the transaction to be transferred to the interconnection bus model 11; the circuit module 60 to be tested comprises a host circuit module 61 and a slave circuit module 62;

and the interconnection bus model 11 is configured to receive the transaction to be transferred, and implement that the transaction to be transferred is transferred between the master circuit module 61 and the slave circuit module 62.

The tested circuit module refers to a tested circuit which needs to carry out the verification of the cooperative work among the core circuit modules. The circuit module to be tested comprises at least one host circuit module and at least one slave circuit module, wherein the host circuit module refers to a circuit initiating operation, and the slave circuit module is a circuit which is matched with the host circuit module to receive operation tasks. It should be noted that the master circuit module and the slave circuit module are only divided in view of role identity in cooperative work, and in fact, one circuit module may serve as the master circuit module in one cooperative work verification among multiple modules, and may serve as the slave circuit module in another cooperative work verification among multiple modules. When the cooperative work among the circuit modules is verified, the circuit module initiating the operation is the host circuit module, and the circuit module receiving the operation task is the slave circuit module.

Protocol transactions refer to transactions relating to the bus transfer protocol, including protocol access transactions and protocol feedback transactions. Protocol access transactions, which refer to transactions containing access parameters of a bus transfer protocol; protocol feedback transaction refers to a transaction that contains feedback parameters for the bus transfer protocol.

The transaction to be transferred refers to a transaction unrelated to the bus transmission protocol, and the transaction to be transferred corresponds to the protocol transaction and is generated according to the protocol transaction. And the transaction to be transmitted corresponding to the protocol access transaction is an access transaction to be transmitted, and the transaction to be transmitted corresponding to the protocol feedback transaction is a feedback transaction to be transmitted.

And after receiving the protocol transaction, the protocol transaction pool stores the protocol transaction and sends the generated transaction to be transmitted to the interconnection bus model according to the corresponding transaction to be transmitted which is generated by the protocol transaction and is irrelevant to the bus transmission protocol.

The interconnection bus model realizes the interconnection of the host circuit module and the slave circuit module, and after receiving the transaction to be transmitted, the transaction to be transmitted is transmitted between the host circuit module and the slave circuit module. Specifically, the interconnection bus model can transfer an access transaction to be transferred of the master circuit module and a feedback transaction to be transferred of the slave circuit module. Because the transaction to be transmitted in the interconnection bus model is irrelevant to the bus transmission protocol, the interconnection bus model can support any bus transmission protocol.

And the host circuit module sends the protocol access transaction to a protocol transaction pool, the protocol transaction pool stores the protocol access transaction after receiving the protocol access transaction, and sends the generated to-be-transmitted access transaction to the interconnection bus model according to the corresponding to-be-transmitted access transaction which is generated by the protocol access transaction and is irrelevant to the bus transmission protocol.

When the slave circuit module acquires a corresponding to-be-transmitted access transaction in the interconnection bus model, the slave circuit module acquires a protocol access transaction corresponding to the to-be-transmitted access transaction according to the to-be-transmitted access transaction access protocol transaction pool, generates a corresponding protocol feedback transaction after the protocol access transaction is completed, and sends the corresponding protocol feedback transaction to the protocol transaction pool, and after the protocol transaction pool receives the protocol feedback transaction, the slave circuit module stores the protocol feedback transaction, and sends the generated to-be-transmitted feedback transaction to the interconnection bus model according to the corresponding to-be-transmitted feedback transaction which is generated by the protocol feedback transaction and is irrelevant to a bus transmission protocol.

When the host circuit module acquires a corresponding to-be-transmitted feedback transaction in the interconnection bus model, the protocol feedback transaction corresponding to the to-be-transmitted feedback transaction is acquired according to the to-be-transmitted feedback transaction access protocol transaction pool, and then corresponding operation can be executed according to the protocol feedback transaction.

As an optional implementation manner, the protocol transaction pool is specifically configured to generate a to-be-transferred transaction corresponding to the protocol transaction according to the identifier of the circuit module under test, the access address of the protocol transaction, and the storage index.

When receiving a protocol transaction, the protocol transaction pool determines the identifier of the circuit module to be tested (i.e. the identifier of the master circuit module or the slave circuit module) which sends the protocol transaction and the access address corresponding to the protocol transaction, stores the protocol transaction, generates a storage index of the protocol transaction, and generates a to-be-transferred transaction corresponding to the protocol transaction according to the identifier of the circuit module to be tested, the access address corresponding to the protocol transaction and the storage index.

The transaction to be transmitted at least comprises the identification of the circuit module to be tested, the access address of the protocol transaction and the storage index in the protocol transaction pool. The identifier of the circuit module to be tested is used for determining the initiator of the corresponding protocol transaction; an access address of a protocol transaction for determining a receiver (or an executor) of the corresponding protocol transaction; and the storage index is used for searching the protocol transaction corresponding to the transaction to be transmitted in the protocol transaction pool.

Optionally, the storage indexes of the protocol transactions in the protocol transaction pool may be respectively generated according to the types of the protocol transactions, for example, a protocol access transaction index is generated for the protocol access transaction, that is, the storage index of the protocol access transaction in the protocol transaction pool, and a protocol feedback transaction index is generated for the protocol feedback transaction, that is, the storage index of the protocol feedback transaction in the protocol transaction pool.

Optionally, in the interconnected circuit system provided in this embodiment, the number of the interconnected bus models is one or more; and when the number of the interconnection bus models is multiple, the interconnection bus models are cascaded.

When there are a plurality of interconnect bus models included in the interconnect circuit system, after the protocol transaction pool generates a corresponding transaction to be transferred according to the protocol transaction, it may be determined that the transaction to be transferred needs to be sent to the interconnect bus model according to the topological relation among the master circuit module, the slave circuit module, and the interconnect bus model.

The interconnection circuit system shown in fig. 2 includes three interconnection bus models, which are an interconnection bus model a, an interconnection bus model B, and an interconnection bus model C, wherein the interconnection bus model a and the interconnection bus model B are directly cascaded, the interconnection bus model C and the interconnection bus model B are directly cascaded, and the interconnection bus model C and the interconnection bus model a are indirectly cascaded.

When a plurality of interconnection bus models are cascaded, two interconnection bus models which are directly cascaded are regarded as two circuit modules which are directly connected. Each interconnection bus model starts a thread to obtain a transaction to be transmitted needing to be transmitted with the interconnection bus model which is directly cascaded with the interconnection bus model. If the interconnection bus model is directly cascaded with the plurality of interconnection bus models, a plurality of parallel threads are started to respectively obtain the to-be-transmitted transactions needing to be transmitted from the plurality of interconnection bus models directly cascaded with the interconnection bus model.

Starting a thread to acquire a transaction to be transmitted from an interconnection bus model directly cascaded with the thread aiming at any target interconnection bus model, and acquiring the transaction to be transmitted from the interconnection bus model directly cascaded with the thread through the thread and sending the transaction to the target interconnection bus model for continuous transmission if the transaction to be transmitted exists in the interconnection bus model directly cascaded with the thread; if the transaction to be transmitted does not exist in the interconnection bus model directly cascaded with the thread, the thread is set to be in a block state by the interconnection bus model directly cascaded with the thread until the transaction to be transmitted exists in the interconnection bus model directly cascaded with the thread, and the block state of the thread is released by the interconnection bus model directly cascaded with the thread until the transaction to be transmitted exists in the interconnection bus model directly cascaded with the thread, so that the thread can acquire the transaction to be transmitted which needs to be transmitted by the target interconnection bus model.

Referring to fig. 2, an interconnection bus model B starts two parallel threads to read a to-be-transmitted transaction to be transmitted by the interconnection bus model B in the interconnection bus model a and the interconnection bus model C, respectively; the interconnection bus model A starts a thread to read a transaction to be transmitted needing to be transmitted by the interconnection bus model A in the interconnection bus model B; and the interconnection bus model C starts a thread to read the transaction to be transmitted needing to be transmitted by the interconnection bus model C in the interconnection bus model B.

Taking the interconnection bus model B as an example, when there is no transaction to be transferred that needs to be transferred by the interconnection bus model a in the interconnection bus model B, the thread of the interconnection bus model a is set to be in a blocking state by the interconnection bus model B. Supposing that when the master circuit module Z1 needs to access the slave circuit module C4, the master circuit module Z1 sends the protocol access transaction to the protocol transaction pool, the protocol transaction pool generates a corresponding to-be-transmitted access transaction to be sent to the interconnection bus model B, at this time, the to-be-transmitted access transaction needing to be transmitted by the interconnection bus model a exists in the interconnection bus model B, the thread of the interconnection bus model a is unblocked by the interconnection bus model B, the thread of the interconnection bus model a can obtain the to-be-transmitted access transaction in the interconnection bus model B and send the to-be-transmitted access transaction back to the interconnection bus model a, and the slave circuit module C4 waits to obtain the to-be-transmitted access transaction in the interconnection bus model a.

In the embodiment, each interconnection bus model waits in the interconnection bus model directly cascaded by one or more threads to acquire the to-be-transmitted transaction needing to be transmitted, so that the timeliness of the to-be-transmitted transaction transmitted among the interconnection bus models is improved, the threads are blocked when no to-be-transmitted transaction exists, and the system performance is not reduced.

When the interconnection circuit system comprises a plurality of interconnection bus models, the plurality of interconnection bus modules can share one same protocol transaction pool.

Optionally, in the interconnect circuit system provided in this embodiment, the number of the protocol transaction pools is one or more; when the number of the protocol transaction pools is multiple, the bus transmission protocols configured by different protocol transaction pools are different.

When the number of the protocol transaction pools in the interconnected circuit system is one, the bus transmission protocol supported by the protocol transaction pools can be changed, so that the support of various different bus transmission protocols can be realized, and an interconnected bus model does not need to be developed independently.

When the number of the protocol transaction pools in the interconnected circuit system is multiple, different bus transmission protocols can be configured for different protocol transaction pools, so that the support for multiple different bus transmission protocols can be realized at the same time, and an interconnected bus model does not need to be developed independently. The protocol transaction pool receives the protocol transaction matched with the bus transmission protocol of the protocol transaction pool and generates a corresponding transaction to be transmitted according to the protocol transaction.

As an alternative implementation, as shown in fig. 3, the interconnection bus model 11 provided in this embodiment includes: the method comprises the following steps: a master access delay module 111, a master feedback delay module 112, a slave access delay module 113, and a slave feedback delay module 114. Wherein the content of the first and second substances,

the master access delay module 111 is configured to simulate transmission delay of the master circuit module for sending the to-be-transmitted access transaction, and send the to-be-transmitted access transaction after delay processing to the matched slave access queue 115; a host feedback delay module 112, configured to simulate a transmission delay of the host circuit module receiving the feedback transaction to be transmitted; the slave access delay module 113 is configured to simulate a transmission delay of the slave circuit module receiving the access transaction to be transmitted; and the slave feedback delay module 114 is configured to simulate a transmission delay of the slave circuit module sending the to-be-transmitted feedback transaction, and send the delayed to-be-transmitted feedback transaction to the matched master feedback queue 116.

The number of the host access delay module 111, the number of the host feedback delay module 112 and the number of the host feedback queues 116 are equal; the number of the slave access delay modules 113, the slave feedback delay modules 114 and the slave access queues 115 is equal.

The master feedback queue is used for storing feedback transactions to be transmitted sent by the slave circuit module; and the slave access queue is used for storing the access transaction to be transmitted sent by the host circuit module. The number of the master feedback queues is equal to that of the master circuit modules, the master feedback queues are in one-to-one correspondence with the master circuit modules, the number of the slave access queues is equal to that of the slave circuit modules, and the slave access queues are in one-to-one correspondence with the slave circuit modules. Optionally, the master feedback queue and the slave access queue may be first-in-first-out queues.

For each host circuit module, the interconnection bus model can comprise a host access delay module, a host feedback delay module and a host feedback queue which are respectively corresponding to the host access delay module, the host feedback delay module and the host feedback queue; for each slave circuit module, a slave access delay module, a slave feedback delay module and a slave access queue which are respectively corresponding to the slave circuit module can be included in the interconnection bus model.

After the protocol access transaction sent from the master circuit module to the slave circuit module is converted from the protocol transaction pool into the to-be-transmitted access transaction and sent to the interconnection bus model, the to-be-transmitted access transaction first enters a master access delay module corresponding to the master circuit module and is used for simulating data transmission delay of the to-be-transmitted access transaction (namely simulating transmission delay of the to-be-transmitted access transaction sent by the master circuit module), then enters a slave access queue corresponding to the slave circuit module and then enters a slave access delay module corresponding to the slave circuit module and is used for simulating data transmission delay of the to-be-transmitted access transaction (namely simulating transmission delay of the to-be-transmitted access transaction received by the slave circuit module). The slave circuit module acquires the access transaction to be transmitted in the slave access delay module corresponding to the slave circuit module, acquiring a corresponding protocol access transaction in a protocol transaction pool according to the to-be-transmitted access transaction, generating a protocol feedback transaction in response to the protocol access transaction, converting the protocol feedback transaction into the to-be-transmitted feedback transaction from the protocol transaction pool, sending the to-be-transmitted feedback transaction to an interconnection bus model, firstly, the data enters a slave machine feedback delay module corresponding to the slave machine circuit module and is used for simulating the data transmission delay of the feedback transaction to be transmitted (namely simulating the transmission delay of the feedback transaction to be transmitted sent by the slave machine circuit module), and then the data enters a host feedback queue corresponding to the host circuit module, and then enters a host feedback delay module corresponding to the host circuit module, so as to simulate the data transmission delay of the feedback transaction to be transmitted (namely simulate the transmission delay of the feedback transaction to be transmitted received by the host circuit module). The host circuit module acquires the feedback transaction to be transmitted in the host feedback delay module corresponding to the host circuit module, and acquires the corresponding protocol feedback transaction in the protocol transaction pool according to the feedback transaction to be transmitted.

Further, as an optional implementation manner, as shown in fig. 3, the interconnection bus model 11 provided in this embodiment further includes: a master arbitration module 117 and a slave arbitration module 118; wherein the content of the first and second substances,

the master arbitration module 117 is connected to each master access delay module 111 and each slave access queue 115, and is configured to receive the delayed to-be-transferred access transaction sent by each master access delay module 111, and send the received to-be-transferred access transaction to the matched slave access queue 115 according to the first target arbitration policy;

and the slave arbitration module 118 is connected to each slave feedback delay module 114 and each master feedback queue 116, and is configured to receive the delayed to-be-transmitted feedback transaction sent by each slave feedback delay module 114, and send the received to-be-transmitted access transaction to the matched master feedback queue 116 according to the second target arbitration policy.

After the to-be-transmitted access transactions corresponding to different host circuit modules are subjected to delay processing through the corresponding host access delay modules, the to-be-transmitted access transactions can be transmitted to the host arbitration module, the transmission direction and the transmission sequence of each received to-be-transmitted access transaction are judged through the host arbitration module according to the first target arbitration strategy, and then the to-be-transmitted access transactions are transmitted to the corresponding slave access queues.

After the feedback transactions to be transmitted corresponding to different host circuit modules are subjected to delay processing through the corresponding slave feedback delay modules, the delayed transactions can be transmitted to the slave arbitration module, the slave arbitration module judges the transmission direction and the transmission sequence of each received feedback transaction to be transmitted according to a second target arbitration strategy, and then the transactions are transmitted to the corresponding host feedback queues.

The master arbitration module may determine, according to the identifier of the transaction to be transferred, a slave access queue corresponding to the transaction to be transferred, and the slave arbitration module may determine, according to the identifier of the transaction to be transferred, a master feedback queue corresponding to the transaction to be transferred.

Optionally, the first target arbitration policy may include: when a plurality of transactions to be transmitted arrive at the same time, if the priorities of the tested circuit modules corresponding to the transactions to be transmitted are the same, the transactions to be transmitted of the tested circuit modules are processed alternately according to a preset sequence.

As shown in fig. 4, when the to-be-transmitted access transactions of the master circuit module a and the master circuit module B reach the master arbitration module at the same time, if the priorities of the master circuit module a and the master circuit module B are the same, the to-be-transmitted access transactions of the master circuit module a and the master circuit module B can be processed in turn according to the preset sequence of the master circuit module a and the master circuit module B, for example, the to-be-transmitted access transaction 0 of the master circuit module a, the to-be-transmitted access transaction 0 of the master circuit module B, the to-be-transmitted access transaction 1 of the master circuit module a, and the to-be-transmitted access transaction 1 of the master circuit module B are processed in turn, that is, the to-be-transmitted access transaction 0 of the master circuit module a is sequentially transmitted to the slave access delay module corresponding to the to-be-transmitted access transaction, and the to-be-transmitted access transaction 0 of the master circuit module B is transmitted to the slave access delay, and transmitting the access transaction 1 to be transmitted of the host circuit module A to a slave access delay module corresponding to the access transaction to be transmitted, and transmitting the access transaction 1 to be transmitted of the host circuit module B to the slave access delay module corresponding to the access transaction to be transmitted.

Optionally, the first target arbitration policy may include: and processing the transaction to be transferred of the target circuit module under test if the priority of the target circuit module under test is higher than the priorities of other circuit modules under test.

As shown in fig. 5, when the to-be-transferred access transactions of the host circuit module a and the host circuit module B simultaneously reach the host arbitration module, if the priority of the host circuit module a is higher than that of the host circuit module B, the to-be-transferred access transaction of the host circuit module a is preferentially processed. When the to-be-transmitted access transaction 0 of the host circuit module a and the to-be-transmitted access transaction 0 of the host circuit module B reach the host arbitration module at the same time, preferentially processing the to-be-transmitted access transaction 0 of the host circuit module a, after the to-be-transmitted access transaction 0 of the host circuit module a is processed, judging whether the to-be-transmitted access transaction of the host circuit module a reaches, if so (such as the to-be-transmitted access transaction 1 of the host circuit module a), continuing processing the to-be-transmitted access transaction 1 of the host circuit module a, and processing the to-be-transmitted access transaction 0 of the host circuit module B until no to-be-transmitted access transaction of the host circuit module a reaches again.

Optionally, the first target arbitration policy may include: when the priority of the target circuit module to be tested is higher than the priorities of other circuit modules to be tested, if the count value of the transaction transmission counter does not reach the transmission threshold value, processing the transaction to be transmitted of the target circuit module to be tested, and updating the count value; and if the count value reaches the transmission threshold value, processing the corresponding to-be-transmitted transactions according to the priorities of other tested circuit modules, and resetting the count value when processing the preset number of to-be-transmitted transactions of other tested circuit modules.

In order to avoid the problem that the transaction to be transmitted of the circuit module under test with low priority is delayed for too long, a threshold value can be set as a transmission threshold value for limiting the continuous processing times of the transaction to be transmitted of the circuit module under test with the highest priority. The number of the to-be-transmitted transactions which are continuously processed by the circuit module to be tested and have the highest priority can be counted by a transaction transmission counter, and the count value of the transaction transmission counter is reset when the to-be-transmitted transactions are completed through interpolation processing. When the continuous processing times of the to-be-transmitted transactions of the tested circuit module with the highest priority reach the transmission threshold, namely the count value of the transaction transmission counter reaches the transmission threshold, the to-be-processed transactions of other tested circuit modules with lower priorities are processed in an interleaved manner. The number of to-be-processed transactions of other tested circuit modules with lower priorities, which are to be interleaved, may be preset, and when the number of other tested circuit modules with lower priorities, which are to be interleaved, is multiple, the to-be-processed transactions may be processed by interleaving according to the priority order, which is not specifically limited in this embodiment.

As shown in fig. 6, when the to-be-transmitted access transactions of the host circuit module a and the host circuit module B reach the host arbitration module at the same time, the priority of the host circuit module a is higher than that of the host circuit module B, and assuming that the transmission threshold of the host circuit module is 2 and the number of the to-be-processed transactions subjected to the interleave processing is 1, after two to-be-transmitted access transactions (to-be-transmitted access transaction 0 and to-be-transmitted access transaction 1) of the host circuit module a can be processed, one to-be-transmitted access transaction (to-be-transmitted access transaction 0) of the host circuit module B is interleaved, and after two to-be-transmitted access transactions (to-be-transmitted access transaction 2 and to-be-transmitted access transaction 3) of the host circuit module a are processed, one to-be-transmitted access transaction (to-be-transmitted access transaction 1).

Optionally, the second target arbitration policy may include: when a plurality of transactions to be transmitted arrive at the same time, if the priorities of the tested circuit modules corresponding to the transactions to be transmitted are the same, the transactions to be transmitted of the tested circuit modules are processed alternately according to a preset sequence.

Optionally, the second target arbitration policy may include: and processing the transaction to be transferred of the target circuit module under test if the priority of the target circuit module under test is higher than the priorities of other circuit modules under test.

Optionally, the second target arbitration policy may include: when the priority of the target circuit module to be tested is higher than the priorities of other circuit modules to be tested, if the count value of the transaction transmission counter does not reach the transmission threshold value, processing the transaction to be transmitted of the target circuit module to be tested, and updating the count value; and if the count value reaches the transmission threshold value, processing the corresponding to-be-transmitted transactions according to the priorities of other tested circuit modules, and resetting the count value when processing the preset number of to-be-transmitted transactions of other tested circuit modules.

For an explanation of the second target arbitration policy based on the slave arbitration module, refer to an explanation of the first target arbitration policy, which is not described herein again.

In addition to the above-mentioned arbitration policies, the first target arbitration policy and the second target arbitration policy may also be other transmission order decision policies, which is not specifically limited in this embodiment.

The interconnection circuit system provided by the embodiment of the invention can provide a universal interconnection channel for various bus transmission protocols, has strong reusability, can realize the support of various different bus transmission protocols, and has low labor cost; the influence of the time delay in the interconnected circuit on the function and the performance can be evaluated by changing the configuration of the time delay module through configuring the time delay module to simulate the time delay from the host circuit module to the interconnected bus model, the processing of the interconnected bus model and the time delay from the interconnected bus model to the slave circuit module.

Example two

Fig. 7 is a schematic structural diagram of a verification system for cooperation between integrated circuit modules according to a second embodiment of the present invention, which is applicable to a situation where cooperation between core function modules is verified under a condition that an interconnection circuit of the core circuit modules is not completed. As shown in fig. 7, the verification system for cooperation between integrated circuit modules specifically includes: an excitation model 30, a functional simulation model 20, a memory model 40, a scoreboard 50, and at least one interconnect circuitry 10 according to any embodiment of the invention. Wherein the content of the first and second substances,

and the excitation model 30 is used for generating an instruction set, interconnection circuit system configuration information and memory model configuration information of the circuit module 60 to be tested, sending the instruction set to the host circuit module 61 and the functional simulation model 20 respectively, sending the memory model configuration information to the memory model 40 and the functional simulation model 20 respectively, and sending the interconnection circuit system configuration information to the interconnection circuit system 10 and the functional simulation model 20 respectively.

The master circuit module 61 is configured to initiate an operation according to the instruction set and send a master operation actual value to the scoring board 50, and the slave circuit module 62 is configured to cooperate with the master circuit module 61 and send a slave operation actual value to the scoring board 50;

a function simulation model 20, configured to simulate a function of an integrated chip including a master circuit module, a slave circuit module, a memory, and an interconnection circuit between the master circuit module and the slave circuit module, initiate an operation according to the instruction set after completing configuration according to the interconnection circuit system configuration information and the memory model configuration information, and send an operation expectation value to the scoreboard 50;

the memory model 40 is used for realizing a data storage function according to the memory model configuration information;

and the scoring board 50 is used for verifying the cooperative work between the master circuit module 61 and the slave circuit module 62 according to the operation expected value, the master operation actual value and the slave operation actual value.

The following description will be given by taking an example that the circuit module to be tested includes a master circuit module and a slave circuit module, but of course, the verification system for the cooperative work between the integrated circuit modules provided in the embodiment of the present application may also implement the cooperative work verification between a plurality of master circuit modules and a plurality of slave circuit modules.

In an example, the master Circuit module and the slave Circuit module may be written in Verilog code, may be written in VHDL (Veri-High-Speed integrated Circuit Hardware Description Language), may be mixed in Verilog and VHDL, may be a Circuit netlist generated by Verilog or VHDL or mixed in Verilog and VHDL for simulation, may be a Circuit netlist generated by writing in other languages, or may be a Circuit netlist generated by writing in other languages with Verilog or VHDL as an intermediate product.

Specifically, the master circuit module may include at least one master interface circuit, and the slave circuit module may include at least one slave interface circuit.

The input to the circuit-under-test is a verification stimulus, which is a set of instructions that comprise the series of instructions that the circuit-under-test needs to execute. In order to efficiently implement the contents of the instructions, the chip needs to invoke as many hardware circuits as possible in a short time. Thus, in addition to the master circuit module completing the instructions, the master circuit module will distribute those instructions to the slave circuit modules for completion. Specifically, the master circuit module accesses the slave circuit module through the interconnection circuit system, and actively acquires a task completion result of the slave circuit module. The access affairs on the master circuit module and the feedback affairs on the slave circuit module are respectively used as a master operation actual value and a slave operation actual value to be sent to the score counting board.

In a specific example, the slave circuit module may also include a master interface circuit, and the master interface circuit is configured to send a result of processing the access transaction by the slave circuit module to the memory model for storage.

Typically, the master circuit module and the slave circuit module may have the same circuit structure, and each may include at least one master interface circuit and at least one slave interface circuit.

When the slave circuit module does not include the master interface circuit, the slave interface circuit cannot send the processing result of the protocol access transaction from the slave circuit module to the memory model for storage, but feeds back the processing result to the master interface circuit through a corresponding protocol feedback transaction when monitoring a relevant protocol access transaction (such as a protocol access transaction for reading the processing result) initiated by the master circuit module in the interconnected circuit system.

When the slave circuit module includes the host interface circuit, the host interface circuit may send a processing result of the access transaction from the slave circuit module to the memory model for storage, and the host circuit module may access the memory model through the host interface circuit to directly obtain a related processing result. The advantage of this arrangement is that it avoids the problem of occupying too much resources of the interconnected circuitry due to the large amount of data computation.

The method includes exciting the model, generating an instruction set for the circuit module under test, and generating memory model configuration information and interconnect circuitry configuration information. The configuration information of the interconnected circuit system refers to configuration information related to an interconnected bus model and configuration information related to a protocol transaction pool, and needs to be sent to the interconnected circuit system for configuration and to be sent to a function simulation model for configuration; the memory model configuration information refers to configuration information related to the memory model, and needs to be sent to the memory model for configuration and sent to the function simulation model for configuration. Specifically, the memory model configuration information may be a memory address space, a reserved address space, and the like, the configuration information related to the interconnect bus model in the interconnect circuit system configuration information may be a slave address space, the number of virtual hosts, and the like, the configuration information related to the protocol transaction pool in the interconnect circuit system configuration information may be bus transmission protocol information, and the like, and an instruction included in the instruction set may trigger the host circuit module to access the memory address space, the slave address space, and the reserved address space.

In one example, the Systemverilog language may provide for the generation of a constrained verification stimulus model, generating binary data in accordance with a user-customized instruction set. These instructions include, among other things, accesses to memory, slave circuit modules, and reserved address spaces. Of course, the binary data may be generated by C, C + +, Python, assembly, or the like, or may be compiled by a compiler after being written by Verilog and/or VHDL, or the like.

The function simulation model is a simulation model of the circuit to be tested, which simulates the functions of an integrated chip comprising a host circuit module, a slave circuit module, an interconnection circuit and a memory. And the functional simulation model is connected with the scoring board through a channel, generates an operation expectation value of the tested circuit module (comprising a host operation expectation value of the host circuit module and a slave operation expectation value of the slave circuit module) according to the instruction set, the memory model configuration information and the interconnected circuit system configuration information given by the excitation model, and sends the operation expectation value to the scoring board for comparison.

The interconnection circuit system is used for realizing interconnection of the host circuit module and the slave circuit module, specifically, the protocol transaction pool generates a transaction to be transmitted according to the protocol transaction, and the interconnection bus model can transmit the transaction to be transmitted which is irrelevant to a bus transmission protocol, so that the universality of the interconnection bus module is realized.

The host circuit module and the slave circuit module are matched with each other through the interconnection circuit system to complete the instruction set generated by the excitation model. Specifically, in the execution process of the instruction set, the master circuit module sends the master operation actual value to the score counting board, and the slave circuit module sends the slave operation actual value to the score counting board.

And the scoring board is used for checking whether the host operation expected value from the functional simulation model is consistent with the host operation actual value from the host circuit module or not and checking whether the slave operation expected value from the functional simulation model is consistent with the slave operation actual value from the slave circuit module or not so as to realize the verification of the cooperative work between the host circuit module and the slave circuit module. The verification specifically means that an instruction set generated by the excitation model is simultaneously sent to the circuit module to be tested and the functional simulation model, and an operation actual value from the circuit module to be tested and an operation expected value from the functional simulation model are received, so that the cooperative working capability between the master circuit module and the slave circuit module is automatically judged. In one example, the scoreboard may give a judgment result of whether the operation actual value and the operation expected value match for each set.

And the memory model sets a memory address space and a reserved address space according to the memory model configuration information generated by the excitation model, is used for storing the related operation data and responds to the access of the related operation data. In an example, the memory model may be responsive to data accesses of different data widths.

It is to be noted that any model and any module provided in the present embodiment may be implemented in software and/or hardware.

The technical scheme provided by the embodiment of the invention can finish the verification of the interconnection function and the multi-module cooperative working capability of the tested circuit with high quality under the condition of no interconnection circuit, no memory and no upper-layer integrated connecting line, so that the problem of the tested circuit can be discovered and solved earlier.

Further, on the basis of the above technical solution, the verification system for the cooperative work between the integrated circuit modules may further include: the detection model is used for detecting whether excitation signals on the signal interfaces of the host circuit module and the slave circuit module accord with a preset transmission protocol or not and/or judging whether interrupt output signals of the host circuit module and the slave circuit module accord with a preset time sequence or not.

The detection model is respectively connected with the host circuit module and the slave circuit module, can detect whether excitation signals on signal interfaces of the host circuit module and the slave circuit module conform to a preset transmission protocol or not, and can perform related error reporting or warning operation when the excitation signals do not conform to the preset transmission protocol; the detection module can also detect whether the interrupt output signals on the host circuit module and the slave circuit module accord with a preset time sequence or not, and can perform related error reporting or warning operation when the interrupt output signals do not accord with the preset time sequence.

Further, on the basis of the above technical solution, the verification system for the cooperative work between the integrated circuit modules may further include: and the function coverage rate analysis model is used for analyzing the coverage rate of the cooperative work function between the host circuit module and the slave circuit module according to the operation expected value, the host operation actual value and the slave operation actual value which are collected by the score board.

The function coverage rate analysis model is connected with the score board, can acquire an operation expected value (a host operation expected value and a slave operation expected value) from the function simulation model collected by the score board and a host operation actual value and a slave operation actual value from the tested circuit module, can analyze which cooperative work functions between the host circuit module and the slave circuit module are realized according to the comparison of the host operation expected value and the host operation actual value and the comparison of the slave operation expected value and the slave operation actual value, and further can determine the coverage rate of the cooperative work functions between the host circuit module and the slave circuit module by combining all preset cooperative functions between the host circuit module and the slave circuit module. The coverage rate display form is not particularly limited in this embodiment, and may be, for example, a numerical value and a coverage function detailed table.

Fig. 8 is a schematic structural diagram of a verification system for cooperation between integrated circuit modules according to a second embodiment of the present invention. In an example, as shown in fig. 8 (a plurality of master circuit modules and a plurality of slave circuit modules are taken as an example in fig. 8), on the basis of the foregoing technical solution, the verification system for cooperation between integrated circuit modules provided in this embodiment further includes: a master integrated circuit core 70 and a slave integrated circuit core 80, wherein,

the host integrated circuit core 70 is configured to convert a signal from the host circuit module 61 into a protocol access transaction, send the protocol access transaction to the interconnect circuit system 10, send the protocol access transaction to the score board 50 as a host operation actual value, and convert a protocol feedback transaction acquired in the interconnect circuit system 10 into a signal, and send the signal to the host circuit module 61;

slave integrated circuit core 80 is configured to translate protocol access transactions snooped in interconnect circuitry 10 into signals for transmission to slave circuitry module 62, and to translate signals from slave circuitry module 62 into protocol feedback transactions for transmission to interconnect circuitry 10 and to transmit the protocol feedback transactions as slave operational actual values to scoreboard 50.

The role of the integrated circuit core is to integrate a set of circuit designs together to form the basic unit of a chip for converting signals from the interface circuitry into packets of data suitable for transmission by the interconnect circuitry (e.g., transactions), or vice versa. In one specific example, the integrated circuit core may be an intellectual property core (VIP) of the integrated circuit, i.e., a group of circuit designs with intellectual property that are grouped together to form the basic unit of a chip. The core connected with the host circuit module is a host integrated circuit core, and the core connected with the slave circuit module is a slave integrated circuit core.

Specifically, the host integrated circuit core is connected with the score board through a channel, captures a signal of a host interface circuit in the host circuit module, converts the signal into a protocol access transaction, sends the protocol access transaction to the interconnection circuit system, and sends the protocol access transaction to the score board as a host operation actual value. At the same time, the host integrated circuit core converts protocol feedback transactions snooped in the interconnect circuitry into signals for the host interface circuitry.

The slave integrated circuit core is connected with the scoring board through a channel, converts protocol access transactions which are monitored in the interconnected circuit system and point to the slave integrated circuit core into signals for accessing the slave interface circuit in the slave circuit module, converts the signals from the slave interface circuit into protocol feedback transactions and sends the protocol feedback transactions to the interconnected circuit system, and sends the protocol feedback transactions to the scoring board as slave operation actual values.

Accordingly, the score board detects the expected host operation value and the expected slave operation value from the functional simulation model, and the actual host operation value and the actual slave operation value from the host integrated circuit core and the slave integrated circuit core, so as to realize the automatic judgment of the cooperative work capability between the host circuit module and the slave circuit module. Specifically, the score board checks whether the protocol access transaction from the function simulation model is consistent with the protocol access transaction from the master integrated circuit core, and checks whether the protocol feedback transaction from the function simulation model is consistent with the protocol feedback transaction from the slave integrated circuit core, so as to realize the verification of the multi-circuit module cooperation function.

Meanwhile, the scoreboard can also evaluate the performance of the interconnected circuit system according to the collected timing information of various protocol transactions (including protocol access transactions, protocol feedback transactions and the like).

Further, in an example, as shown in fig. 8, a host cooperative sequence processing sub-module 71 is loaded in the host integrated circuit core 70, and the host cooperative sequence processing sub-module 71 is configured to generate or obtain a protocol feedback transaction of the protocol access transaction according to an address of the protocol access transaction initiated by the host circuit module 61;

the slave integrated circuit core 80 is loaded with a slave cooperative sequence processing submodule 81, and the slave cooperative sequence processing submodule 81 is configured to monitor a protocol access transaction directed to the slave circuit module 62 in the interconnect circuit system 10, send the protocol access transaction to the slave circuit module 62, and obtain a protocol feedback transaction of the protocol access transaction from the slave circuit module 62 and send the protocol feedback transaction to the interconnect circuit system 10.

The role of the co-sequence processing sub-module is to perform a series of processing operations, such as sending protocol access transactions, snooping provide protocol feedback transactions, and so on. The integrated circuit core of the host computer is a host computer cooperative sequence processing submodule, and the integrated circuit core of the slave computer is a slave computer cooperative sequence processing submodule.

In one example, the host co-sequence processing sub-module may generate or retrieve a protocol feedback transaction in response to a protocol access transaction of the host interface circuitry, e.g., may generate a direct feedback transaction, a memory feedback transaction, a retrieve bus feedback transaction, etc., to be sent to the host integrated circuit core. The direct feedback transaction refers to a random protocol feedback transaction directly generated by the host cooperative sequence processing submodule, and specifically can be generated when the address of the access transaction of the host interface circuit is a reserved address space; the memory feedback transaction refers to a protocol feedback transaction generated by calling a memory model by the host in cooperation with the serial processing sub-module and executing memory access operation (including but not limited to write operation), and can be generated when the address of the access transaction of the host interface circuit is a memory address space; the bus feedback transaction refers to a protocol feedback transaction monitored in the interconnect circuit system when the address of the protocol access transaction of the host interface circuit is the address space of the slave circuit module.

In this embodiment, the integrated circuit core may be replaced according to a bus interface protocol of a protocol transaction pool in the interconnected circuit system, and the cooperative sequence processing sub-module may also be replaced as needed. Specifically, the feedback behavior may be adjusted according to the verification requirement to achieve recycling of the verification system for the cooperative work between the integrated circuit modules, that is, the verification system for the cooperative work between the integrated circuit modules provided in this embodiment is a reusable, portable, and hierarchical verification system.

For a detailed explanation of the interconnect circuitry, reference is made to the foregoing embodiments, which are not repeated herein.

On the basis of the foregoing technical solution, the verification system provided in this embodiment may further include: at least one virtual master model and at least one virtual slave model; wherein the content of the first and second substances,

the virtual host model is used for simulating a host circuit module to generate a protocol access transaction and sending the protocol access transaction to the interconnected circuit system; and the virtual slave machine model is used for simulating a slave machine circuit module to generate a protocol feedback transaction and sending the protocol feedback transaction to the interconnected circuit system.

The virtual host model is used for simulating other host circuit modules which are not developed and correspond to the slave circuit modules, generating protocol access transactions corresponding to the slave circuit modules, so that the verification of the cooperative working capacity between the host circuit modules and the circuit modules comprising the slave circuit modules is realized, and the performance of the interconnected circuit system is evaluated.

The virtual slave model is used for simulating other slave circuit modules which are not developed and correspond to the host circuit module, generating protocol feedback transactions corresponding to the host circuit module, so that the verification of the cooperative working capacity between the slave circuit module and the circuit modules comprising the host circuit module is realized, and the performance of the interconnected circuit system is evaluated.

Further, the scoreboard may also collect time information of transmission events of various transactions for evaluating the performance of the interconnect circuitry, wherein the time information may be recorded in the expected value of the operation and the actual value of the operation. For example, whether the arbitration module and/or the delay module in the interconnect circuitry are set properly is determined according to the time when the protocol transaction enters the interconnect circuitry, the time when the protocol transaction exits the interconnect circuitry, and the time fed back.

In a specific example, the verification system for the cooperation between the integrated circuit modules can be implemented by using a system level hardware description language SystemVerilog and/or SystemC. Specifically, the Verification system for the cooperative work between the integrated circuit modules may be implemented based on a Universal Verification Methodology (UVM).

In the technical scheme provided by the embodiment, the verification environment is established by the memory model based on the interconnected circuit system, so that the circuit to be tested only comprises a core circuit module, the problem detection and debugging are greatly simplified, and the problems of complex debugging and low verification efficiency are solved. Moreover, the circuit to be tested does not comprise interconnection circuits, memories and upper-layer circuit connecting lines, and the circuit to be tested is realized through an interconnection circuit system and a memory model, so that the compiling and simulating time of the circuit to be tested is greatly shortened, and the verification time and the verification cost are reduced.

EXAMPLE III

Fig. 9 is a flowchart of a method for verifying cooperation between integrated circuit modules according to a third embodiment of the present invention, where this embodiment is applicable to a case where the cooperation capability between core function modules is verified under a condition that an interconnection circuit of the core circuit modules is not completed. The method can be executed by the verification system provided by the embodiment of the invention, which can be implemented in a software and/or hardware manner and can be generally integrated in a computer.

As shown in fig. 3, the method for verifying the cooperative work between the integrated circuit modules in this embodiment specifically includes:

s310, generating an instruction set, interconnection circuit system configuration information and memory model configuration information of the circuit module to be tested through the excitation model, respectively sending the instruction set to the host circuit module and the function simulation model, respectively sending the memory model configuration information to the memory model and the function simulation model, and respectively sending the interconnection circuit system configuration information to the interconnection circuit system and the function simulation model.

The tested circuit module comprises a host circuit module and a slave circuit module.

Specifically, the interconnect circuitry configuration information may refer to configuration information associated with the interconnect bus model and configuration information associated with the protocol transaction pool. The configuration information related to the interconnection bus model may be slave address space, the number of virtual hosts, and the like, and the configuration information related to the protocol transaction pool may be bus transfer protocol information, and the like. The memory model configuration information may be memory address space, reserved address space, etc.; the instructions contained in the instruction set may trigger the host circuit module to access the memory address space, the slave address space, and the reserved address space.

S320, receiving the protocol transaction sent by the circuit module to be tested through the protocol transaction pool, storing the protocol transaction, generating a transaction to be transmitted corresponding to the protocol transaction, and sending the transaction to be transmitted to the interconnection bus model; and receiving the transaction to be transmitted through the interconnection bus model, and realizing the transmission of the transaction to be transmitted between the master circuit module and the slave circuit module.

Optionally, a to-be-transferred transaction corresponding to the protocol transaction is generated by the protocol transaction pool according to the identifier of the circuit module to be tested, the access address of the protocol transaction, and the storage index.

Optionally, a master access delay module in the interconnection bus model simulates transmission delay of a master circuit module for sending an access transaction to be transmitted, and sends the delayed access transaction to be transmitted to a matched slave access queue; simulating the transmission delay of the slave circuit module for receiving the access transaction to be transmitted by a slave access delay module in the interconnected bus model; simulating the transmission delay of the feedback transaction to be transmitted sent by the slave circuit module through a slave feedback delay module in the interconnected bus model, and sending the delayed feedback transaction to be transmitted to a matched host feedback queue; and simulating the transmission delay of the feedback transaction to be transmitted received by the host circuit module through a host feedback delay module in the interconnected bus model.

Optionally, the host arbitration module in the interconnected bus model receives the delayed to-be-transmitted access transaction sent by each host access delay module, and sends the received to-be-transmitted access transaction to the matched slave access queue according to the first target arbitration policy;

and receiving the delayed feedback transaction to be transmitted sent by each slave feedback delay module through a slave arbitration module in the interconnected bus model, and sending the received access transaction to be transmitted to the matched host feedback queue according to a second target arbitration strategy.

S330, realizing a data storage function through the memory model according to the memory model configuration information.

S340, simulating the functions of an integrated chip comprising a host circuit module, a slave circuit module, a memory and an interconnection circuit between the host circuit module and the slave circuit module through a function simulation model, initiating operation according to an instruction set after completing configuration according to the configuration information of the interconnection circuit system and the configuration information of the memory model, and sending an operation expectation value to a scoring board.

And S350, initiating operation according to the instruction set through the host circuit module, and sending the actual host operation value to the scoring board.

And S360, the slave computer circuit module and the host computer circuit module work cooperatively, and the slave computer operation actual value is sent to the scoring board.

And S370, verifying the cooperative work between the host circuit module and the slave circuit module through the scoring board according to the operation expected value, the host operation actual value and the slave operation actual value.

The technical scheme provided by the embodiment of the invention can finish the verification of the interconnection function and the multi-module cooperative working capability of the circuit to be tested with high quality under the condition of no interconnection circuit, no memory and no upper-layer integrated connecting line, so that the problem of the circuit to be tested can be discovered and solved earlier.

In a specific example, initiating, by the host circuit module, an operation according to the instruction set, and sending the actual value of the host operation to the score counting board may specifically be: converting the signal from the host circuit module into a protocol access transaction through a host integrated circuit core, sending the protocol access transaction to an interconnected circuit system, sending the protocol access transaction to a score board as a host operation actual value, converting the protocol feedback transaction acquired in the interconnected circuit system into a signal, and sending the signal to the host circuit module;

correspondingly, the slave computer circuit module and the host computer circuit module work cooperatively, and the slave computer operation actual value is sent to the scoring board, which may specifically be: and converting the protocol access transaction monitored in the interconnected circuit system into a signal and sending the signal to the slave circuit module through the slave integrated circuit core, converting the signal from the slave circuit module into a protocol feedback transaction and sending the protocol feedback transaction to the interconnected circuit system, and sending the protocol feedback transaction to the scoring board as a slave operation actual value.

Meanwhile, the scoreboard can also evaluate the performance of the interconnected circuit system according to the collected timing information of various transactions (including protocol access transactions, protocol feedback transactions and the like).

Further, the method further comprises: generating or acquiring a protocol feedback transaction of a protocol access transaction according to an address of the protocol access transaction initiated by the host circuit module through a host cooperative sequence processing submodule loaded in the host integrated circuit core;

and monitoring a protocol access transaction pointing to the slave circuit module in the interconnected circuit system through a slave cooperation sequence processing submodule loaded in the slave integrated circuit core, sending the protocol access transaction to the slave circuit module, acquiring a protocol feedback transaction of the protocol access transaction from the slave circuit module, and sending the protocol feedback transaction to the interconnected circuit system.

In this embodiment, the integrated circuit core may be replaced according to a bus interface protocol of a protocol transaction pool in the interconnected circuit system, and the cooperative sequence processing sub-module may also be replaced as needed. Specifically, the feedback behavior can be adjusted according to the verification requirements to realize the reuse of the verification system of the cooperative work among the integrated circuit modules.

Further, the verification method further includes: and detecting whether excitation signals on signal interfaces of the host circuit module and the slave circuit module accord with a preset transmission protocol or not through a detection model, and/or judging whether interrupt output signals of the host circuit module and the slave circuit module accord with a preset time sequence or not through the detection model.

Further, the verification method further includes: and analyzing the coverage rate of the cooperative work function between the host circuit module and the slave circuit module according to the operation expected value, the host operation actual value and the slave operation actual value which are collected by the scoring board through a function coverage rate analysis model.

In a specific verification process, the slave cooperative sequence processing submodule is started, monitors a protocol access transaction in the interconnected circuit system, and inputs verification excitation in the excitation model to the host circuit module and the function simulation model.

The function simulation model generates operation expectation values of the protocol access transaction and the protocol feedback transaction according to the input verification excitation and sends the operation expectation values to the score board.

The host circuit module generates access to the host integrated circuit core based on the input verification stimulus. The host integrated circuit core generates a protocol access transaction accordingly and sends it to the host co-sequence processing sub-module and scoreboard. The scoreboard checks whether the protocol access transaction from the functional simulation model is consistent with the protocol access transaction from the host integrated circuit core.

And the host cooperative sequence processing sub-module generates a protocol feedback transaction of the protocol access transaction according to the address of the access transaction. When the address of the protocol access transaction is not in the address space of the memory or the address space of the slave, the host cooperative sequence processing submodule randomly generates a protocol feedback transaction; when the address of the protocol access transaction is in the memory address space, the host computer cooperates with the sequence processing submodule to access the memory model to generate a protocol feedback transaction; when the address of the protocol access transaction is in the slave address space, the protocol access transaction is sent to the interconnected circuit system, and the host cooperates with the sequence processing submodule to monitor and acquire the protocol feedback transaction provided by the interconnected circuit system.

Furthermore, a protocol access transaction can be generated by simulating a host circuit module through the virtual host model, and the protocol access transaction is sent to the interconnected circuit system, so that the verification of the cooperative work between the virtual host module and other slave circuit modules is realized; and/or generating a protocol feedback transaction through the virtual slave model simulation slave circuit module, and sending the protocol feedback transaction to the interconnection circuit system to realize the verification of the cooperative work between the virtual slave module and other host circuit modules.

And the slave cooperative sequence processing submodule monitors a protocol access transaction for accessing the slave circuit module in the interconnected circuit system and sends the protocol access transaction to the slave integrated circuit core to execute access to the slave circuit module. And the slave cooperative sequence processing submodule sends the protocol feedback transaction to the interconnected circuit system. The slave integrated circuit core obtains feedback from the slave circuit module to generate a protocol feedback transaction and sends the protocol feedback transaction to the scoreboard. The scoreboard will check whether the protocol feedback transaction from the functional simulation model is consistent with the protocol feedback transaction from the slave integrated circuit core.

When the host cooperative sequence processing sub-module monitors a protocol feedback transaction in the interconnected circuit system, the protocol feedback transaction is sent to the host integrated circuit core, and the host integrated circuit core converts the protocol feedback transaction into a signal and sends the signal to the host interface circuit.

For those parts of the present embodiment that are not explained in detail, please refer to the previous embodiments, and further description is omitted here.

In the technical scheme, under the condition of no interconnection circuit, no memory and no upper-layer integrated connecting line, a verification person can finish the verification of the interconnection function and the multi-module cooperative work of the circuit to be tested with high quality, so that the problem of the circuit to be tested can be discovered and solved earlier. The compiling object does not comprise an interconnection circuit, a memory and the like, so that the compiling time of the verification system is greatly shortened, the verification cost is reduced, and meanwhile, the debugging complexity is also greatly reduced. Furthermore, the technical scheme can also realize the function of the interconnected circuit by modifying the parameters of the interconnected circuit system, thereby not only rapidly providing feedback for the design of the interconnected circuit, but also ensuring the iteration times of the optimized design of the interconnected circuit.

Example four

Fig. 10 is a schematic structural diagram of a verification system for cooperation between integrated circuit modules according to a fourth embodiment of the present invention. This example provides a specific implementation.

Referring to fig. 10, the circuit under test in this embodiment may be a CLUSTER of compute units (CLUSTERs) in an artificial intelligence chip, each CLUSTER having a master interface circuit and a slave interface circuit. The data transmission protocol may be AXI4.0 (Advanced eXtensible Interface is an on-chip Bus oriented to high performance, high bandwidth, and low latency in the AMBA-Advanced Microcontroller Bus Architecture protocol proposed by ARM corporation). Specifically, the circuit under test is an example of two CLUSTERs, C0 and C1, respectively, where C0 is used as the master circuit module and C1 is used as the slave circuit module.

First, the excitation model writes the instruction set to C0. Second, C0 executes the set of instructions and writes its computation to the memory model through its host interface circuitry, sending the set of instructions that require C1 to execute to C1 through the interconnect circuitry. Thirdly, C1 obtains and parses the instruction set through its slave interface circuitry to obtain the computation task, and C1 writes its computation result into the memory model through its host interface circuitry after completing its computation task. Finally, C0 accesses the memory model through the host interface circuitry to get the computed result of C1.

The verification system for the cooperative work among the integrated circuit modules in the embodiment mainly comprises the following parts: the simulation model comprises a stimulus model, a functional simulation model, a memory model, an interconnection circuit system (comprising a protocol transaction pool and an interconnection bus model), a virtual host model, a virtual slave model, a host VIP (integrated circuit intellectual property core), a slave VIP, a host cooperative sequence processing submodule loaded in the host VIP, a slave cooperative sequence processing submodule loaded in the slave VIP, a scoring board, a detection model and a functional coverage analysis model.

The excitation model generates configuration information and an instruction set according to the circuit to be tested and correspondingly sends the configuration information and the instruction set to the function simulation model, the memory model, the interconnection circuit system and the circuit to be tested. The configuration information refers to that the address space is divided into a memory address space according to the information of the tested circuit, the memory model and the interconnected circuit system, the address space of the slave computer is reserved, and the number of the sub-models of the virtual host computer is configured. The instruction set comprises instructions related to C0 calculation data, C0 writing data results to a memory, C0 sending calculation tasks to C1, C0 accessing the memory to obtain the calculation results of C1 and the like.

And the function simulation model is connected with the score board through a channel, simulates and completes related functions according to the instruction set and the configuration information given by the excitation model, and is specifically used for realizing the same functions as an integrated chip comprising C0, C1, a memory and an interconnection circuit. The functional simulation model generates operation expectation values of a protocol access transaction and a protocol feedback transaction according to the verification excitation of the excitation model, and the two expectation values are sent to the score board.

The interconnection circuit system comprises a protocol transaction pool and an interconnection bus model. The protocol transaction pool receives a protocol transaction sent by a circuit module to be tested, stores the protocol transaction, generates a transaction to be transmitted corresponding to the protocol transaction, and sends the transaction to be transmitted to the interconnection bus model; and the interconnection bus model receives the transaction to be transmitted and realizes the transmission of the transaction to be transmitted between the host circuit module and the slave circuit module.

Furthermore, a host access delay module, a host feedback delay module, a slave access delay module, a slave feedback delay module, a host arbitration module and a slave arbitration module can be further arranged in the interconnection bus model.

And the memory model sets the memory address space into an available address interval and a reserved address interval according to the verification excitation of the excitation model. The memory model may also be responsive to a variety of data widths, in this embodiment C0 and C1 may access the memory model using 512-bit or 1024-bit data widths, respectively.

And the score board checks whether the actual value of the access transaction of the host VIP 0/host VIP1 is consistent with the expected value from the functional simulation model, and checks whether the actual value of the feedback transaction of the slave VIP1 is consistent with the expected value from the functional simulation model to realize functional verification. In addition, the scoreboard collecting time information of transmission events in various transactions may also be used to evaluate the performance of the interconnect circuitry.

The detection model is connected with interface signals on the host interface circuit and the slave interface circuit and is used for checking whether excitation on the interfaces conforms to a transmission protocol or not; the detection model is also connected with a key signal of the circuit to be detected, and whether the key signal accords with a set time sequence is judged.

And the function coverage rate analysis model is connected with the scoring board and analyzes the function coverage rate of the cooperative work of the master circuit module and the slave circuit module according to the expected value and the actual value collected by the scoring board.

In particular, the host VIPs (including host VIP0 and host VIP 1) are coupled to the scoreboard via a path that converts signals from the host interface circuitry into protocol access transactions that are sent to the scoreboard as actual values. Protocol feedback transactions heard at the interconnect circuitry are converted to signals sent to the host interface circuitry. The host cooperation sequence processing submodule loaded by the host VIP provides a protocol feedback transaction for a protocol access transaction from the host interface circuit;

the slave VIPs (including the slave VIP 1) are connected to the scoreboard via a path, convert protocol access transactions heard in the interconnect circuitry model into signals for the slave interface circuitry, and convert signals from the slave interface circuitry into protocol feedback transactions that are sent as actual values to the scoreboard. And the cooperative sequence processing submodule loaded by the slave VIP is used for accessing the C1 slave interface circuit and obtaining a protocol feedback transaction from the C1 slave interface circuit.

The host cooperative sequence processing sub-module (comprising a host cooperative sequence processing sub-module 0 and a host cooperative sequence processing sub-module 1) is loaded in the host VIP, and generates or monitors a protocol feedback transaction to respond to a protocol access transaction of the host interface circuit. The feedback transaction comprises the following steps:

(1) when the address of the protocol access transaction is reserved address space, the host generates direct feedback in cooperation with the sequence processing submodule.

(2) And when the address of the protocol access transaction is a memory address space, the host generates memory feedback by cooperating with the sequence processing submodule. When there are different memory address space mappings for C0 and C1, the host co-sequence processing submodule performs the address mapping function. For example, the memory address space corresponding to address 0x0 of C0 is mapped to C1 as address 0x4, and when the memory address space of the access transaction received by the host cooperative sequence processing submodule 1 is address 0x4, the memory address space of the access transaction is modified to address 0x 0.

(3) When the address of the protocol access transaction is the slave address space, the host cooperates with the sequence processing submodule to generate an access transaction and send the access transaction into the interconnected circuit system, and then monitors the protocol feedback transaction from the interconnected circuit system, namely bus feedback.

And the slave cooperative sequence processing submodule is loaded in the slave VIP. And the slave cooperative sequence processing submodule monitors a protocol access transaction for accessing the slave interface circuit in the interconnected circuit system and converts the protocol access transaction into a protocol access transaction of the slave VIP to the slave interface circuit. The slave VIP accesses the slave interface circuit to obtain a protocol feedback transaction, and the slave cooperation sequence processing submodule obtains the protocol feedback transaction and sends the protocol feedback transaction into the interconnection circuit system.

Correspondingly, the flow of the verification method for the cooperative work between the integrated circuit modules provided by this embodiment includes:

the stimulus model generates configuration information and instruction sets from information of the circuit under test, the memory model, and the interconnected circuitry. The excitation model sends the configuration information to the function simulation model, and writes the memory address space, the slave address space and the reserved address space into the memory model; writing the number of the slave address space and the virtual host model/virtual slave model into the interconnection circuit system; the instruction set is sent to C0 and the functional simulation model.

The memory model configures a memory address space and a reserved address space; the interconnection circuit system configures slave address space and the number of virtual host models/virtual slave models; the functional simulation model configures a memory address space and a slave address space. And analyzing the instruction set by the functional simulation model to generate expected values of the protocol access transaction and the protocol feedback transaction, and writing the expected values into the score board.

C0 parses the instruction set, executing the following instructions: compute data, write data results to the memory model, send compute task to C1. The host VIP0 receives the access from C0, generates a protocol access transaction, and sends the protocol access transaction to the scoreboard.

The host computer cooperates with the sequence processing submodule 0 to execute the following operations: when the host interface circuit of C0 accesses the reserved address space, the host cooperation sequence processing submodule 0 randomly generates a feedback transaction according to the constraint; when the host interface circuit of C0 writes the data result to the memory model, the host cooperative sequence processing submodule 0 writes the protocol access transaction to the memory model; when the host interface circuit of C0 sends a computation task to the slave circuit module, the host cooperates with the sequence processing submodule 0 to write a protocol access transaction into the interconnect circuit system, and then listens for a protocol feedback transaction from the interconnect circuit system.

When the protocol transaction pool in the interconnection circuit system receives the protocol access transaction of the host VIP0, the corresponding to-be-transmitted access transaction is generated and sent to the interconnection bus model, and if the virtual host model also randomly generates a protocol access transaction for the C1 slave interface circuit. These protocol access transactions, along with the protocol access transactions from the host VIP0, trigger the host arbitration module of the interconnect bus model to make a determination of the timing of the processing.

The slave cooperative sequence processing submodule 1 obtains a protocol access transaction (including the computing task of C1) from the interconnection circuit system, sends the protocol access transaction to C1 through the slave VIP1, and obtains a protocol feedback transaction. The slave VIP1 feeds the protocol feedback transaction into the scoreboard as actual value. Meanwhile, the slave cooperative sequence processing submodule 1 obtains the protocol feedback transaction, sends the protocol feedback transaction into a protocol transaction pool in the interconnection circuit system, generates a corresponding feedback transaction to be transmitted through conversion of the protocol transaction pool, and sends the feedback transaction to the interconnection bus model. After obtaining the feedback transaction to be transmitted from the interconnection bus model, the host cooperative sequence processing sub-module 0 obtains the protocol feedback transaction corresponding to the feedback transaction to be transmitted from the protocol transaction pool, and then feeds the protocol feedback transaction back to the host interface circuit of the C0 through the host VIP 0.

C1 performs the computational tasks, the host interface circuitry of C1 writes the computational results to the memory model via host VIP1, and host VIP1 routes protocol access transactions to the scoreboard.

The host interface circuitry of C0 accesses the memory model to obtain the computed result of C1 and sends the protocol access transaction as actual value to the scoreboard.

The scoreboard verifies the expected value and the actual value of the protocol transaction (including the protocol access transaction and the protocol feedback transaction), and the scoreboard collects the actual value of the transaction and can be used for counting the performance information of the current interconnected circuit system design so as to provide feedback for the interconnected circuit design.

The detection model can detect whether excitation signals on signal interfaces of the master circuit module and the slave circuit module conform to a preset transmission protocol or not, and performs related error reporting or warning operation when the excitation signals do not conform to the preset transmission protocol; and whether the interrupt output signals on the master circuit module and the slave circuit module accord with a preset time sequence or not can be detected, and relevant error reporting or warning operation is carried out when the interrupt output signals do not accord with the preset time sequence.

The function coverage rate analysis model can analyze the function coverage rate of the cooperative work of the master circuit module and the slave circuit module according to the expected value and the actual value collected by the scoring board.

In the technical scheme, the verification of the tested circuit is complete and sufficient. Under the premise of no connection of a memory, an interconnection circuit and an upper circuit, the cooperative work function among the modules of the tested circuit is verified, so that the tested circuit can be released in high quality, and meanwhile, feedback can be provided for the design of the interconnection circuit earlier and faster.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in more detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An interconnect circuit system, comprising: an interconnect bus model and a pool of protocol transactions, wherein,

2. The interconnect circuitry of claim 1, wherein the protocol transaction pool is configured to generate a transaction to be transferred corresponding to the protocol transaction according to the identifier of the circuit module under test, the access address of the protocol transaction, and a storage index.

3. The interconnect circuitry of claim 1, wherein the transaction to be transferred corresponding to the protocol access transaction is a transaction to be transferred access transaction, and the transaction to be transferred corresponding to the protocol feedback transaction is a transaction to be transferred feedback;

the interconnection bus model comprises: the system comprises a host access delay module, a host feedback delay module, a slave access delay module and a slave feedback delay module;

the host access delay module is used for simulating the transmission delay of the host circuit module for sending the access transaction to be transmitted and sending the delayed access transaction to be transmitted to the matched slave access queue;

the host feedback delay module is used for simulating the transmission delay of the host circuit module for receiving the feedback transaction to be transmitted;

the slave access delay module is used for simulating the transmission delay of the slave circuit module receiving the access transaction to be transmitted;

the slave machine feedback delay module is used for simulating the transmission delay of the slave machine circuit module for sending the feedback transaction to be transmitted and sending the feedback transaction to be transmitted after delay processing to the matched host machine feedback queue;

the number of the host access delay module, the number of the host feedback delay module and the number of the host feedback queues are equal; the number of the slave access delay modules, the slave feedback delay modules and the slave access queues is equal.

4. The interconnect circuitry of claim 3, wherein said interconnect bus model further comprises: the system comprises a host arbitration module and a slave arbitration module; wherein the content of the first and second substances,

the host arbitration module is respectively connected with each host access delay module and each slave access queue, and is used for receiving the delayed to-be-transmitted access transaction sent by each host access delay module and sending the received to-be-transmitted access transaction to the matched slave access queue according to a first target arbitration strategy;

the slave machine arbitration module is respectively connected with each slave machine feedback delay module and each host machine feedback queue, and is used for receiving the delayed to-be-transmitted feedback transaction sent by each slave machine feedback delay module and sending the received to-be-transmitted access transaction to the matched host machine feedback queue according to a second target arbitration strategy.

5. Interconnect circuitry according to claim 4, wherein the first target arbitration policy or the second target arbitration policy comprises:

when a plurality of transactions to be transmitted arrive at the same time, if the priorities of the tested circuit modules corresponding to the transactions to be transmitted are the same, the transactions to be transmitted of the tested circuit modules are processed alternately according to a preset sequence; alternatively, the first and second electrodes may be,

if the priority of the target circuit module to be tested is higher than the priorities of other circuit modules to be tested, processing the transaction to be transferred of the target circuit module to be tested; alternatively, the first and second electrodes may be,

when the priority of the target circuit module to be tested is higher than the priorities of other circuit modules to be tested, if the count value of the transaction transmission counter does not reach the transmission threshold value, processing the transaction to be transmitted of the target circuit module to be tested, and updating the count value; and if the count value reaches the transmission threshold value, processing the corresponding to-be-transmitted transactions according to the priorities of other tested circuit modules, and resetting the count value when processing the preset number of to-be-transmitted transactions of other tested circuit modules.

6. The interconnect circuitry of claim 1, wherein the number of protocol transaction pools is one or more;

when the number of the protocol transaction pools is multiple, the bus transmission protocols configured by different protocol transaction pools are different.

7. The interconnect circuitry of claim 1, wherein the number of interconnect bus models is one or more;

and when the number of the interconnection bus models is multiple, the interconnection bus models are cascaded.

8. A system for verifying interoperability between integrated circuit modules, comprising: an excitation model, a functional simulation model, a memory model, a scoreboard, and at least one interconnected circuitry according to any one of claims 1-7,

9. The authentication system of claim 8, further comprising: at least one virtual master model and at least one virtual slave model; wherein the content of the first and second substances,

the virtual host model is used for simulating a host circuit module to generate a protocol access transaction and sending the protocol access transaction to the interconnected circuit system;

and the virtual slave machine model is used for simulating a slave machine circuit module to generate a protocol feedback transaction and sending the protocol feedback transaction to the interconnected circuit system.

10. A verification method for cooperation between integrated circuit modules, which is applied to the verification system as claimed in claim 8 or 9, comprising: