CN112765924A - Chip verification method, device and system - Google Patents
Chip verification method, device and system Download PDFInfo
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- CN112765924A CN112765924A CN202110121144.2A CN202110121144A CN112765924A CN 112765924 A CN112765924 A CN 112765924A CN 202110121144 A CN202110121144 A CN 202110121144A CN 112765924 A CN112765924 A CN 112765924A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/02—System on chip [SoC] design
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application provides a chip verification method, a device and a system, the method is applied to a server, the server is externally connected with a verification platform of a chip needing verification, the server comprises a control plane CP program, and the chip comprises a central processing unit CPU and a high-speed interface used for communicating with the server; the method comprises the following steps: the server loads the CP program after determining that the CPU finishes executing the initialization program for chip verification; and operating the CP program to interact with the chip through the high-speed interface to complete the functional verification of the chip. By adopting the method, when the chip is verified on the verification platform, the high-efficiency verification of the chip is realized.
Description
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a method, an apparatus, and a system for verifying a chip.
Background
In the design process of the chip, functional verification is often required, and different chip design companies may use different verification platforms to perform chip verification. However, the main frequency of the current mainstream verification platform is generally low, and is generally only tens of megabytes, and the low main frequency causes low execution efficiency during chip verification. For example, a code needs only 1 minute to run on a real chip with a main frequency of 1G, and needs at least 50 minutes to run on a simulation environment with a main frequency of 20MHz, so that the execution efficiency is extremely low, and the extremely low execution efficiency directly affects the verification efficiency of a chip prototype. Therefore, it is important to design a chip prototype verification framework suitable for multiple verification platforms to achieve efficient verification of chips.
The existing chip verification framework includes a central processing unit CPU, a main memory, a control module, and other peripheral devices, as shown in fig. 1. In the chip verification framework, a software part for chip verification mainly comprises an initialization program and a Control Plane (CP) program which are both run on a CPU core. The initialization program has the functions of completing the electrification of each module in the chip, necessary initialization and the movement of codes and data; the CP program functions to select a peripheral device according to chip verification requirements, and configure according to different functions of the peripheral device, for example, the ethernet interface selects different working modes and other functions to configure.
During the execution of the software, the code and the required data are moved from the external memory (such as Flash) to the main memory. The data loading speed is slow under the influence of the main frequency of the verification platform, so that the software in the verification platform needs to be designed to be extremely simplified, and the size of the software is limited. For the chip verification framework, the functional verification of each functional module and interface and the system-level verification of the whole SOC are mainly performed, so the CP program is particularly critical to the prototype verification system of the whole chip and the verification efficiency of the chip. The CP program needs to have a code that can select a certain peripheral or multiple peripherals for authentication, and can satisfy the situation of adjustment according to the authentication requirement, and the more functions that need to be authenticated, the larger the CP program.
Therefore, the current chip verification framework has the following disadvantages: the main frequency of the verification platform is low, so that the data loading speed is low, and the size of the CP program is limited. When a plurality of peripheral devices need to be verified, the CP program will inevitably increase, and thus the data required to be loaded will also increase, resulting in a too long loading time. Therefore, when designing a CP program, the existing chip verification framework needs to balance the verification content (i.e. the size of the CP program) and the data loading time, thereby limiting the upper limit of the verification efficiency. In addition, due to the problem that the main frequency of the verification platform is low, the existing verification platform cannot run an operating system, the CP program cannot be managed by the operating system, the whole chip verification framework cannot normally work and can only be restarted when the CP program is abnormal in the execution process, time waste can be greatly caused, and the chip verification efficiency is low.
Therefore, how to implement efficient verification of a chip when performing chip verification on a verification platform is one of the considerable technical problems.
Disclosure of Invention
In view of this, the present application provides a chip verification method, device and system, which are used to implement efficient verification of a chip when the chip is verified on a verification platform.
Specifically, the method is realized through the following technical scheme:
according to a first aspect of the present application, a chip verification method is provided, which is applied to a server, the server is externally connected to a verification platform including a verified chip, the server includes a control plane CP program, and the chip includes a central processing unit CPU and a high-speed interface for communicating with the server; the method comprises the following steps:
the server loads the CP program after determining that the CPU finishes executing the initialization program for chip verification;
and operating the CP program to interact with the chip through the high-speed interface to complete the functional verification of the chip.
Optionally, the chip further comprises a peripheral device; and
running the CP program to interact with the chip through the high-speed interface, including:
when the peripheral equipment of the chip needs to be verified, a corresponding CP program is operated, verification data is sent to the CPU through the high-speed interface, the CPU sends the verification data to the peripheral equipment, and the function verification of the peripheral equipment is completed.
Optionally, the chip further comprises a peripheral device; and
running the CP program to interact with the chip through the high-speed interface, including:
when peripheral equipment of the chip needs to be verified, if the server can directly access the peripheral equipment, verification data is sent to the peripheral equipment through a data interface exposed by the peripheral equipment so as to complete function verification of the peripheral equipment.
Optionally, the chip verification method provided by the present application further includes:
when the CP program is abnormally hung, the thread for running the CP program is forbidden;
a new thread is created and the CP program is run by the new thread.
Optionally, the high-speed interface provided by this embodiment at least includes one of the following: the interface comprises an Ethernet interface, an ILKN interface based on an inter-chip high-speed data transmission protocol ILKN and a PCIe interface based on a high-speed serial computer expansion bus standard PCIe.
According to a second aspect of the present application, a chip verification system is provided, including a server and a verification platform externally connected to the server, where the verification platform includes a chip to be verified, the server includes a control plane CP program, the chip includes a central processing unit CPU and a high-speed interface for communicating with the server, and the server loads and runs the CP program to interact with the chip through the high-speed interface, thereby completing function verification of the chip.
According to a third aspect of the present application, a chip verification apparatus is provided, which is applied to a server, the server is externally connected to a verification platform of a chip to be verified, the server includes a control plane CP program, and the chip includes a central processing unit CPU and a high-speed interface for communicating with the server; the apparatus, comprising:
the loading module is used for loading the CP program after the CPU is determined to finish executing the initialization program for chip verification;
and the running module is used for running the CP program to interact with the chip through the high-speed interface so as to complete the functional verification of the chip.
Optionally, the chip further comprises a peripheral device; then
The running module is specifically configured to run a corresponding CP program when peripheral equipment of the chip needs to be verified, send verification data to the CPU through the high-speed interface, and the CPU sends the verification data to the peripheral equipment to complete function verification of the peripheral equipment.
Optionally, the chip further comprises a peripheral device; then
The operating module is specifically configured to, when peripheral equipment of the chip needs to be verified, send verification data to the peripheral equipment through a data interface exposed by the peripheral equipment if the server can directly access the peripheral equipment, so as to complete function verification of the peripheral equipment.
Optionally, the chip verification apparatus provided in this embodiment further includes:
the disabling module is used for disabling the thread for running the CP program when the CP program is abnormally hung;
the creation module is used for creating a new thread;
the running module is further configured to run the CP program by the new thread.
According to a fourth aspect of the present application, there is provided a server comprising a processor and a machine-readable storage medium, the machine-readable storage medium storing a computer program executable by the processor, the processor being caused by the computer program to perform the method provided by the first aspect of the embodiments of the present application.
According to a fifth aspect of the present application, there is provided a machine-readable storage medium storing a computer program which, when invoked and executed by a processor, causes the processor to perform the method provided by the first aspect of the embodiments of the present application.
The beneficial effects of the embodiment of the application are as follows:
the CP program runs on the server, and then the server is connected with the chip through the high-speed interface, so that the verification of the chip is realized.
Drawings
FIG. 1 is a schematic diagram of a conventional chip verification framework;
fig. 2 is a schematic structural diagram of a chip verification system according to an embodiment of the present application;
fig. 3 is a schematic flowchart of a chip verification method according to an embodiment of the present application;
FIG. 4 is a diagram of a logical architecture for peripheral validation provided by an embodiment of the present application;
fig. 5 is a schematic structural diagram of a chip verification apparatus according to an embodiment of the present application;
fig. 6 is a schematic hardware structure diagram of a server according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with aspects such as the present application.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the corresponding listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
Before introducing the chip verification method provided by the present application, the technical terms related to the present application are introduced:
the peripheral device in the present embodiment refers to a slave CPU, a function module, an interface, or a device other than the master CPU in a System Of Chips (SOC). When the peripheral device is a slave CPU, the master CPU interacts with the server in this embodiment, and when the peripheral device is another device than the slave CPU, the CPU interacting with the server may be the master CPU or the slave CPU.
The chip verification method provided by the present application is explained in detail below.
The chip verification method provided by this embodiment is applied to a server in the chip verification system shown in fig. 2, and since there is no strong coupling relationship between a control plane CP program and an initialization program, the CP program is separately set in this application, that is, the CP program is set on the server, the chip verification system further includes a verification platform externally connected to the server, the verification platform includes a chip to be verified, the chip includes a CPU and a high-speed interface for communicating with the server, and the chip further includes various required functional modules (not shown in the figure). Specifically, when the server implements the chip verification method, the method can be implemented according to the chip verification process shown in fig. 3, and includes the following steps:
s301, after the CPU is determined to finish executing the initialization program for chip verification, loading the CP program.
Specifically, before the chip is verified, the chip needs to be initialized, that is, the CPU needs to run an initialization program to configure the relevant functional modules of the chip, for example, to complete the operations of powering on each module in the chip, necessary initialization, data transfer of codes, and the like. The server can actively acquire the initialization state information of the chip from the CPU, and if the acquired initialization state information represents that the chip initialization is completed, the chip is powered on and the initialization is completed, so that the server can start to load the CP program.
S302, operating the CP program to interact with the chip through the high-speed interface, and completing the functional verification of the chip.
Specifically, after the server loads the CP program, the server may start a thread to execute the CP program, and interact with a chip through a high-speed interface during running the CP program to complete functional verification of the chip. By running the CP program on the server, compared with the verification platform, the loading speed of the server is higher, the size of the CP program can be freely expanded without being limited by the verification platform, so that the data loading time can be greatly shortened by loading and running the CP program on the server, the main frequency of the server is much higher than that of the verification platform and is closer to that supported by a real chip, the verification speed of the chip can be greatly accelerated, and the verification efficiency of the chip is effectively improved.
Optionally, the chip further includes a control module and a main memory, as also shown in fig. 2, where the control module is configured to provide a clock, a Power supply, and other drivers for the chip, and the control module may include, but is not limited to, a Timer, a Power Management Unit (PMU), and other modules. The main memory is used for storing some data required for chip verification. The CPU is connected with the main memory through a memory bus; the CPU is connected to the control module through a system bus, as shown in fig. 2.
Optionally, the chip further comprises a peripheral device; on this basis, step S302 may be performed according to the following procedure: when the peripheral equipment of the chip needs to be verified, a corresponding CP program is operated, verification data is sent to the CPU through the high-speed interface, the CPU sends the verification data to the peripheral equipment, and the function verification of the peripheral equipment is completed.
Specifically, when the functions of the peripheral devices of the chip need to be verified, the corresponding CP program may be executed according to the functions to be tested, and then the required verification data is sent to the CPU through a high-speed interface (such as an Ethernet interface) of the chip, and then the CPU sends the verification data to the peripheral devices through a system bus, so as to complete the verification of the interaction functions with the peripheral devices, as shown in fig. 4.
Alternatively, step S302 may also be performed according to the following procedure: when peripheral equipment of the chip needs to be verified, if the server can directly access the peripheral equipment, verification data is sent to the peripheral equipment through a data interface exposed by the peripheral equipment so as to complete function verification of the peripheral equipment.
Specifically, in practical applications, some specific peripheral devices of the chip are visible to the server, and at this time, the server may send the verification data to the peripheral device through a data interface exposed to the outside by the peripheral device, thereby completing the functional verification of the peripheral device, and thus completing the functional verification of the peripheral device of the chip without the participation of the CPU.
It should be noted that the verification of the peripheral device may include, but is not limited to, verification of functions such as an interactive function, an interface function of the peripheral device, a storage function of the peripheral device, and a data processing function of the peripheral device. For example, when the verification data is used for testing the storage function of the peripheral device, the verification data may be sent to the CPU through the high-speed interface, the CPU performs parsing on the verification data, and then writes the parsed verification data into the corresponding storage space of the peripheral device, or the server sends the verification data to the peripheral device through a data interface exposed to the outside of the peripheral device, so as to store the verification data into the storage space of the peripheral device.
Alternatively, when the Peripheral device is an interface Peripheral device, the interface Peripheral device may include, but is not limited to, a PCIe interface based on a Peripheral Component Interconnect express (PCIe), an Ethernet interface, an ILKN interface based on an inter-chip high speed data transfer protocol ILKN, an ILKN _ LA interface, a serial Peripheral SPI interface, a General-Purpose Input/Output (GPIO) interface, a Joint Test Action Group (JTAG) interface, and the like.
Optionally, the peripheral device may further include a Wireless Local Area Network (WLAN), a High Definition Multimedia Interface (HDMI), a Long Term Evolution (LTE) of the universal mobile telecommunications technology, and the like.
Optionally, the chip testing method provided in this embodiment further includes:
when the CP program is abnormally hung, the thread for running the CP program is forbidden;
a new thread is created and the CP program is run by the new thread.
Specifically, when the server runs the CP program, a thread is created and then the CP program is run by the thread, and when the CP program is suspended due to an exception, the server may disable the thread for running the CP program, that is, kill the thread in which the CP program is located, then re-create a new thread, and execute the CP program by the newly created thread, so that the whole chip does not need to be restarted to continue to execute the verification work of the chip, which is not only flexible and efficient, but also improves the fault-tolerant capability of chip verification.
By implementing the chip verification method provided by the application, the CP program runs on the server, and then the connection between the server and the chip is realized through the high-speed interface, so that the verification of the chip is realized.
Based on the same inventive concept, the application also provides a chip verification device corresponding to the chip verification method. The chip verification method can be specifically implemented by referring to the above description of the chip verification method, which is not discussed herein.
Referring to fig. 5, fig. 5 is a diagram of a chip verification apparatus applied in a server, where the server is externally connected to a verification platform including a chip to be verified, the server includes a control plane CP program, and the chip includes a central processing unit CPU and a high-speed interface for communicating with the server; the apparatus, comprising:
a loading module 501, configured to load the CP program after it is determined that the CPU has executed the initialization program for chip verification;
an operation module 502, configured to operate the CP program to interact with the chip through the high-speed interface, so as to complete function verification of the chip.
Optionally, the chip further comprises a peripheral device; then
The operation module 502 is specifically configured to, when peripheral devices of the chip need to be verified, operate a corresponding CP program, send verification data to the CPU through the high-speed interface, and the CPU sends the verification data to the peripheral devices to complete function verification of the peripheral devices.
Optionally, the chip further comprises a peripheral device; then
The operation module 502 is specifically configured to, when peripheral devices of the chip need to be verified, send verification data to the peripheral devices through data interfaces exposed by the peripheral devices if the server can directly access the peripheral devices, so as to complete function verification of the peripheral devices.
Optionally, the chip verification apparatus provided in this embodiment further includes:
a disabling module (not shown in the figure) for disabling a thread for running the CP program when the CP program is abnormally suspended;
a creation module (not shown in the figure) for creating a new thread;
the running module 502 is further configured to run the CP program by the new thread.
Optionally, the high-speed interface provided by this embodiment at least includes one of the following: the interface comprises an Ethernet interface, an ILKN interface based on an inter-chip high-speed data transmission protocol ILKN and a PCIe interface based on a high-speed serial computer expansion bus standard PCIe.
Based on the same inventive concept, the embodiment of the present application provides a server, as shown in fig. 6, including a processor 601 and a machine-readable storage medium 602, where the machine-readable storage medium 602 stores a computer program capable of being executed by the processor 601, and the processor 601 is caused by the computer program to execute the chip verification method provided by the embodiment of the present application.
The computer-readable storage medium may include a RAM (Random Access Memory), a DDR SRAM (Double Data Rate Synchronous Dynamic Random Access Memory), and may also include a NVM (Non-volatile Memory), such as at least one disk Memory. Alternatively, the computer readable storage medium may be at least one memory device located remotely from the processor.
The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component.
In addition, the embodiment of the present application provides a machine-readable storage medium, which stores a computer program, and when the computer program is called and executed by a processor, the computer program causes the processor to execute the chip verification method provided by the embodiment of the present application.
For the embodiments of the server and the machine-readable storage medium, the contents of the related methods are substantially similar to those of the foregoing embodiments of the methods, so that the description is relatively simple, and for the relevant points, reference may be made to the partial description of the embodiments of the methods.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The implementation process of the functions and actions of each unit/module in the above device is specifically described in the implementation process of the corresponding step in the above method, and is not described herein again.
For the device embodiments, since they substantially correspond to the method embodiments, reference may be made to the partial description of the method embodiments for relevant points. The above-described embodiments of the apparatus are merely illustrative, wherein the units/modules described as separate parts may or may not be physically separate, and the parts displayed as units/modules may or may not be physical units/modules, may be located in one place, or may be distributed on a plurality of network units/modules. Some or all of the units/modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (10)
1. A chip verification method is characterized in that the method is applied to a server, the server is externally connected with a verification platform of a chip needing to be verified, the server comprises a control plane CP program, and the chip comprises a central processing unit CPU and a high-speed interface used for communicating with the server; the method comprises the following steps:
the server loads the CP program after determining that the CPU finishes executing the initialization program for chip verification;
and operating the CP program to interact with the chip through the high-speed interface to complete the functional verification of the chip.
2. The method of claim 1, wherein the chip further comprises a peripheral device; and
running the CP program to interact with the chip through the high-speed interface, including:
when the peripheral equipment of the chip needs to be verified, a corresponding CP program is operated, verification data is sent to the CPU through the high-speed interface, the CPU sends the verification data to the peripheral equipment, and the function verification of the peripheral equipment is completed.
3. The method of claim 1, wherein the chip further comprises a peripheral device; and
running the CP program to interact with the chip through the high-speed interface, including:
when peripheral equipment of the chip needs to be verified, if the server can directly access the peripheral equipment, verification data is sent to the peripheral equipment through a data interface exposed by the peripheral equipment so as to complete function verification of the peripheral equipment.
4. The method of claim 1, further comprising:
when the CP program is abnormally hung, the thread for running the CP program is forbidden;
a new thread is created and the CP program is run by the new thread.
5. The method of any of claims 1 to 4, wherein the high speed interface comprises at least one of: the interface comprises an Ethernet interface, an ILKN interface based on an inter-chip high-speed data transmission protocol ILKN and a PCIe interface based on a high-speed serial computer expansion bus standard PCIe.
6. A chip verification system is characterized by comprising a server and a verification platform externally connected with the server, wherein the verification platform comprises a chip needing to be verified, the server comprises a control plane CP program, the chip comprises a central processing unit CPU and a high-speed interface used for communicating with the server, and the server loads and runs the CP program so as to interact with the chip through the high-speed interface to complete the function verification of the chip.
7. A chip verification device is characterized in that the device is applied to a server, the server is externally connected with a verification platform of a chip needing to be verified, the server comprises a control plane CP program, and the chip comprises a central processing unit CPU and a high-speed interface used for communicating with the server; the apparatus, comprising:
the loading module is used for loading the CP program after the CPU is determined to finish executing the initialization program for chip verification;
and the running module is used for running the CP program to interact with the chip through the high-speed interface so as to complete the functional verification of the chip.
8. The apparatus of claim 7, wherein the chip further comprises a peripheral device; then
The running module is specifically configured to run a corresponding CP program when peripheral equipment of the chip needs to be verified, send verification data to the CPU through the high-speed interface, and the CPU sends the verification data to the peripheral equipment to complete function verification of the peripheral equipment.
9. The apparatus of claim 7, wherein the chip further comprises a peripheral device; then
The operating module is specifically configured to, when peripheral equipment of the chip needs to be verified, send verification data to the peripheral equipment through a data interface exposed by the peripheral equipment if the server can directly access the peripheral equipment, so as to complete function verification of the peripheral equipment.
10. The apparatus of claim 7, further comprising:
the disabling module is used for disabling the thread for running the CP program when the CP program is abnormally hung;
the creation module is used for creating a new thread;
the running module is further configured to run the CP program by the new thread.
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| CN103077104A (en) * | 2013-01-28 | 2013-05-01 | 北京君正集成电路股份有限公司 | Verification method, device and system for on-chip system |
| CN104881344A (en) * | 2015-05-20 | 2015-09-02 | 深圳市创维电器科技有限公司 | Automatic testing method and system for PCBA |
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| CN110442528A (en) * | 2019-08-21 | 2019-11-12 | 湖南中车时代通信信号有限公司 | A kind of system and method for the column control cross-platform operation of software based on fail-safe computer simulation software |
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